US 9,543,940 B2Grant
Switching circuits having ferrite beads
Issue Date:2017-01-10
•26 Claims
•14 Drawing Sheets
Abstract
A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead.
Metadata
Assignee
- Transphorm Inc.
Inventors
- Zhan Wang
- Yifeng Wu
- James Honea
Application Information
Application Number:US 14/323,777
Filing Date:2014-07-03
Priority Date:2014-07-03
Art Unit:2842
Classifications
IPC:
H03B1/00H03K3/00H03K17/16H01L29/20H01L29/16H03K17/10H03K17/12H03K17/687
Field of Search:
H03K 17/16H03K 3/012H01L 29/2003H01L 29/16H01L 27/0883H01L 27/088
Patent Drawings (14 sheets)
Description
Technical Field
[0001] This specification relates to stabilizing switching circuits, e.g., high speed III-N power switches, using ferrite beads.
Background
[0002] Using high-speed III-N power switches involves balancing requirements for heat transfer, ease of assembly, and high-speed, low-inductance electrical interconnection. Conventional leaded power packages, such as any of the variations of the TO-220 package, can be used with III-N power switches. The combination of a metal mounting tab and flexible copper leads permits attachment of the package to effective heat sinks in a variety of configurations. Connection to a PCB with conventional soldering techniques permits ease of manufacture.
[0003] Nonetheless, the package leads typically introduce undesirable inductance. Reduction in switching speed caused by this inductance may be an acceptable design compromise, but instability may still present a problem. Since a power switch can be a high-gain device, if allowed to operate in a linear mode, care should be taken that any oscillations due to parasitic resonances do not couple to a node where positive feedback may sustain or amplify the oscillations.
[0004] FIG. 1 is a circuit diagram of a half bridge circuit comprising a gate driver 102, a high side III-N transistor 104 coupled to a high voltage node 106, and a low side III-N transistor 108 coupled to a ground node 110. Two terminals of the gate driver 102 are coupled to respective gates of the transistors 104 and 108, and two terminals of the gate driver are coupled to respective sources of the transistors 104 and 108, such that the gate driver is able to apply voltage signals to the gates of each of transistors 104 and 108 relative to their respective sources. An inductive load 114 is coupled to the half bridge circuit at a load node 112.
[0005] In operation, the gate driver 102 can operate the transistors 104 and 108 in a constant-current mode (CCM), switching rated current at rated voltage. For example, the high voltage node can provide a voltage of 400V or 600V or greater, and the III-N transistors can be configured with a rating to withstand the resulting high currents. Due to the inductance of the load 114, current flowing through the load 114 cannot change instantaneously.
[0006] To illustrate the operation of the half bridge, consider an example scenario where the gate driver 102 turns the high side transistor 104 on and turns the low side transistor 108 off. Current flows from the high voltage node 106, through the high side transistor 104, and through the load node 112 to the load 114. When the gate driver 102 turns the high side transistor 104 off, the inductance of the load 114 drives the voltage at the load node 112 negative, which allows current to flow up through the low side transistor 108 even though it is off. If the half bridge is implemented using a conventional package, the undesirable inductance introduced by the package leads can cause significant ringing and oscillation related to transient current flowing through the circuit, which can interfere with a stable, efficient switching function.
Summary
[0007] In a first aspect, a circuit comprises an electronic component package with at least a first lead, where the electronic component package contains a III-N device with a drain, gate, and source, with the source coupled to the first lead. The circuit further comprises a gate driver with a first and second terminal, where the first terminal is coupled to the first lead, and a ferrite bead coupled between the gate of the III-N transistor and the second terminal of the gate driver.
[0008] In a second aspect, a circuit comprises a gate driver with a first and second high side output terminals and a first and second low side output terminals. The circuit further includes a high side III-N device with a high side gate coupled to the first high side output terminal of the gate driver, a high side drain coupled to a high voltage node, and a high side source coupled to a load node. The circuit also includes a low side III-N device with a low side gate coupled to the first low side output terminal of the gate driver, a low side drain coupled to the load node, and a low side source coupled to a ground node. A ferrite bead is coupled between the high side gate and the first high side output terminal of the gate driver.
[0009] In a third aspect, an electronic component comprises an electronic package with at least a first lead, a III-N switching device with a gate, wherein the III-N switching device is encased in the electronic package, and a ferrite bead encased in the electronic package, wherein the ferrite bead is coupled between the gate and the first lead.
[0010] In a fourth aspect, a circuit comprises a gate driver with high side and low side output terminals, a first electronic component, and a second electronic component. The first electronic component comprises a first electronic package, which includes a first conductive structural base, and a high side III-N device encased in the first electronic package, which includes a high side gate coupled to the high side output terminal of the gate driver by a ferrite bead encased in first electronic package, a high side source coupled to a load node, and a high side drain coupled to a high voltage node by the first conductive structural base of the first electronic package. The second electronic component comprises a second electronic package, which includes a second conductive structural base, and a low side III-N device encased in the second electronic package, which includes a low side gate coupled to the low side output terminal of the gate driver, a low side drain coupled to the load node, and a low side source coupled to a ground node by the second conductive structural base of the second electronic package.
[0011] The circuits and components described herein may each include one or more of the following. The circuit can include a gate loop formed with the second terminal of the gate driver, the ferrite bead, the III-N device, the first lead, and the first terminal, where the first lead has a parasitic inductance and the ferrite bead is configured to reduce oscillations and electromagnetic interference in the gate loop due to the parasitic inductance. The circuit can include a low side switch formed with the III-N device and the electronic component package, where the first lead is coupled to a ground node. The circuit can further include a high side switch coupled between the drain of the III-N device and a high voltage node, where the high side switch comprises a high side gate coupled to a third terminal of the gate driver. The gate driver can be configured to apply a low side control signal to the second terminal relative to the first terminal and a high side control signal to the third terminal relative to a fourth terminal of the gate driver, where the fourth terminal is coupled to a high side source of the high side switch.
[0012] The circuit can further include a processor, which is coupled to the gate driver, and memory storing executable instructions that, when executed by the processor, cause the processor to control the gate driver to operate the circuit as a half bridge. In the circuit, the voltage at the high voltage node relative to the ground node can be about 400V or higher. The gate driver can be configured to apply a control signal to the second terminal relative to the first terminal, where the control signal has a frequency between 30 kHz and 10 MHz. The circuit can be constructed such that a second ferrite bead is coupled between the high side gate and the third terminal of the gate driver. The III-N device can be an enhancement mode transistor or a hybrid device that includes a depletion mode III-N transistor and an enhancement mode silicon transistor. In the circuit, the ferrite bead can be configured to block electromagnetic interference having frequencies above 100 MHz. The circuit can be constructed such that the electronic component package further includes a second lead, where the second lead is coupled to the source and to a ground node, and the first lead is electrically connected to the first terminal of the gate driver.
[0013] During operation of the circuit, the voltage at the high node relative to the ground node can be at least 400V. The gate driver can be configured to apply control signals with a frequency between 30 kHz and 10 MHz to the first high side output terminal relative to the second high side output terminal and to the first low side output terminal relative to the second output terminal.
[0014] The III-N switching device in the electronic component can be an enhancement mode III-N transistor or a hybrid device that includes a depletion mode III-N transistor and an enhancement mode transistor, where the gate is a first gate of the enhancement mode transistor. The electronic package can include a conductive structural base, wherein the depletion mode III-N transistor is a lateral III-N transistor including a second gate, and the second gate is electrically connected to the conductive structural base of the electronic package. The electronic package can further include a conductive structural base, which the III-N switching device and the ferrite bead are both mounted on.
[0015] The electronic component can include a first wire bond between the ferrite bead and the gate and a second wire bond between the ferrite bead and the first lead. The III-N switching device can include a III-N transistor that has a source and drain coupled to second and third leads of the electronic package, wherein the electronic package includes a fourth lead coupled to the source for directly coupling of the source to a gate driver. The electronic package can include a conductive structural base, wherein the enhancement mode III-N transistor is a lateral III-N transistor, the gate is a gate of the enhancement mode III-N transistor, and a source or drain of the enhancement mode III-N transistor is electrically connected to the conductive structural base of the electronic package.
[0016] The gate driver can be configured to output respective control signals to the high side and low side terminals, where the control terminals have a frequency between 50 kHz and 1 MHz. The high side III-N device can be an enhancement mode transistor or a hybrid device that comprises a depletion mode III-N transistor and an enhancement mode transistor.
[0017] As used herein, the terms III-Nitride or III-N materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula BwAlxInyGazN, where w+x+y+z is about 1 with 0≦w≦1, 0≦x≦1, 0≦y≦1, and 0≦z≦1. III-N materials, layers, or devices, can be formed or prepared by either directly growing on a suitable substrate (e.g., by metal organic chemical vapor deposition), or growing on a suitable substrate, detaching from the originally substrate, and bonding to other substrates.
[0018] As used herein, two or more contacts or other items such as conductive channels or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, e.g., is about the same, at all times under any bias conditions.
[0019] As used herein, “blocking a voltage” refers to the ability of a transistor, device, or component to prevent significant current, such as current that is greater than 0.001 times the operating current during regular conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, while a transistor, device, or component is blocking a voltage that is applied across it, the total current passing through the transistor, device, or component will not be greater than 0.001 times the operating current during regular conduction. Devices with off-state currents which are larger than this value exhibit high loss and low efficiency, and are typically not suitable for many applications.
[0020] As used herein, a “high-voltage device”, e.g., a high-voltage switching transistor, is an electronic device which is optimized for high-voltage switching applications. That is, when the transistor is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, or about 1200V or higher, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, e.g., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block all voltages between 0V and at least Vmax, where Vmax is the maximum voltage that can be supplied by the circuit or power supply, and Vmax can for example be 300V, 600V, 1200V, or other suitable blocking voltage required by the application.
[0021] As used herein, a “III-Nitride” or “III-N device” is a device based on III-N materials. The III-N device can be designed to operate as an enhancement-mode (E-mode) transistor device, such that the threshold voltage of the device (i.e., the minimum voltage that must be applied to the gate relative to the source in order to turn the device on) is positive. Alternatively, the III-N device can be a depletion-mode (D-mode) device, having a negative threshold voltage. The III-N device can be a high-voltage device suitable for high voltage applications. In such a high-voltage device, when the device is biased off (e.g., the voltage on the gate relative to the source is less than the device threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high-voltage in the application in which the device is used, which for example may be 100V, 300V, 600V, 1200V, 1700V, or higher. When the high voltage device is biased on (e.g., the voltage on the gate relative to the source is greater than the device threshold voltage), it is able to conduct substantial current with a low on-voltage. The maximum allowable on-voltage is the maximum voltage that can be sustained in the application in which the device is used.
[0022] The details of one or more disclosed implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.
Description of Drawings
[0023] FIG. 1 is a circuit diagram of a half bridge circuit comprising a gate driver, a high side III-N transistor coupled to a high voltage node, and a low side III-N transistor coupled to a ground node.
[0024] FIG. 2 is a circuit diagram of an example switching circuit in which a portion of the circuit is implemented as an electronic module.
[0025] FIG. 3 is an illustration of a III-N transistor as an example of the switches in FIG. 2 .
[0026] FIG. 4 is a circuit schematic illustrating a hybrid device that includes a high-voltage D-mode transistor and a low-voltage E-mode transistor.
[0027] FIG. 5 is a circuit diagram of the example switching circuit where the switches are each encased in individual electronic packages.
[0028] FIG. 6 is a schematic illustration of a packaged III-N device as an example of the packaged switches in FIG. 5 .
[0029] FIG. 7 is a circuit diagram of the example switching circuit in which a portion of the circuit is implemented as an electronic module, with a second ferrite bead coupled between a third terminal of the gate driver and the gate of the high side switch.
[0030] FIG. 8 is a circuit diagram of the example switching circuit where the switches are each encased in individual electronic packages, with a second ferrite bead coupled between a third terminal of the gate driver and the gate of the high side transistor.
[0031] FIG. 9 is a schematic illustration of a switch which includes a III-N transistor encased in an electronic package.
[0032] FIG. 10 is a schematic illustration of a switch which includes a III-N transistor encased in another electronic package having four package leads.
[0033] FIG. 11 is a schematic illustration of an example low side transistor and an example high side transistor that are implemented using electronic packages and can be used for the individually packaged low side and high side switches in FIGS. 5 and 8 .
[0034] FIG. 12 is a circuit diagram of an example inverter circuit.
[0035] FIG. 13 is a circuit diagram of a switching circuit in which a portion of the circuit is implemented as an electronic module.
[0036] Like reference symbols in the various drawings indicate like elements.
Detailed Description
[0037] FIG. 2 is a circuit diagram of an example switching circuit in which a portion of the circuit is implemented as an electronic module 200. The module 200 includes a high side switch 104 connected in series with a low side switch 108 in a half bridge configuration. The module casing, indicated by dashed line 220, includes nodes 221-227. Nodes 221 and 222 are coupled (e.g., electrically connected) to the gate and source, respectively, of switch 104. Nodes 223 and 224 are coupled (e.g., electrically connected) to the gate and source, respectively, of switch 108. Node 225 is coupled (e.g., electrically connected) to the drain of switch 104. Node 226 is coupled (e.g., electrically connected) to the source of switch 108 by a connection that has a parasitic inductance 202. Output node 227 is coupled (e.g., electrically connected) to load node 112 at the output of the half bridge formed by switches 104 and 108. The circuit further includes a gate driver 102 which is connected to nodes 221-224 of the module in order to apply voltage signals to the gates of switches 104 and 108 relative to their respective sources. An inductive load 114 is coupled (e.g., electrically connected) to the module at output node 227. The electronic module can be formed as a circuit board with printed wiring connections that electrically couple the components of the module.
[0038] Switches 104 and 108 are capable of being operated at higher switching frequencies than some switches used in conventional high-voltage power switching circuits, such as switches implemented as silicon-based transistors (e.g., silicon-based MOSFETs or IGBTs). For example, switches 104 and 108 can be III-N transistors, such as the III-N transistor shown in FIG. 3 , which may be capable of being switched at higher frequencies than silicon-based MOSFETs or IGBTs without exhibiting substantial additional power loss or other instabilities during operation. As seen in FIG. 3 , a III-Nitride high electron mobility transistor (HEMT) can include a substrate 300 (e.g., a silicon substrate), a III-N buffer layer 302 formed of a III-N semiconductor material such as AlN or AlGaN, a III-N channel layer 306 formed of a III-N semiconductor material such as GaN, a III-N barrier layer 308 formed of a III-N semiconductor material (e.g., AlGaN or AlN) having a larger bandgap than that of the III-N channel layer 306, and a two-dimensional electron gas (2DEG) channel 316 formed in the III-N channel layer 306 adjacent to the III-N barrier layer 308, the 2DEG channel 316 serving as the conductive channel of the transistor. The III-N HEMT further includes source and drain contacts 310 and 312, respectively, which contact the 2DEG channel 316. A gate electrode 314, which is deposited between the source and drain contacts 310 and 312, is used to modulate the conductivity of the channel in the region directly below the gate electrode 314. Optionally, a gate insulator 320 is included between the gate electrode 314 and the underlying III-N semiconductor materials.
[0039] In many applications, it is preferable that switches 104 and 108 be enhancement-mode devices. However, switching devices formed of single high-voltage enhancement-mode transistors can be difficult to fabricate reliably. For example, due at least partially to tight process tolerances, it can be difficult to design a III-N HEMT such as the device shown in FIG. 3 such that it consistently and reliably operates as an enhancement-mode device with a positive threshold voltage. That is, even when a design is implemented for a III-N HEMT for which the resulting HEMT should be an enhancement-mode device, small variations in layer thicknesses, feature dimensions, etc., that typically occur can result in many of the devices either being depletion-mode devices or otherwise not exhibiting a high enough threshold voltage for reliable operation.
[0040] As an alternative to a single high-voltage enhancement-mode transistor, when enhancement-mode switches which can be operated at high switching frequencies are desired for switches 104 and 108, the switches can each be implemented as a hybrid device that includes a high-voltage depletion-mode (D-mode) transistor 404 and a low-voltage enhancement-mode (E-mode) transistor 402, configured as shown in FIG. 4 . The resulting hybrid device of FIG. 4 can be operated in the same way as a single high-voltage E-mode transistor, and in many cases achieves the same or similar output characteristics as a single high-voltage E-mode transistor. The source electrode 406 of the low-voltage E-mode transistor 402 and the gate electrode 408 of the high-voltage D-mode transistor 404 are both electrically connected together, for example with wire bonds, and together form the source 410 of the hybrid device. The gate electrode 412 of the low-voltage E-mode transistor 402 forms the gate 414 of the hybrid device. The drain electrode 416 of the high-voltage D-mode transistor 404 forms the drain 418 of the hybrid device. The source electrode 420 of the high-voltage D-mode transistor 404 is electrically connected to the drain electrode 422 of the low-voltage E-mode transistor 402.
[0041] In particular implementations of the hybrid device of FIG. 4 , the hybrid device is implemented as a III-N device. In this case, the D-mode transistor 404 is a high-voltage III-N D-mode transistor (e.g., capable of blocking at least 200V while biased in the OFF state), and the E-mode transistor 402 is a low-voltage silicon-based E-mode transistor (e.g., cannot reliably block voltages greater than 100V while biased in the OFF state). Although such an implementation of a III-N switch utilizes a silicon-based transistor in the switch, because the silicon-based transistor is a low-voltage device, the switch can still be capable of being operated at the higher switching frequencies.
[0042] Referring back to FIG. 2 , due to the use of III-N transistors (as in FIG. 3 ) or hybrid devices (as in FIG. 4 ), e.g., III-N hybrid devices, as switches 104 and 108, the switching circuit illustrated in FIG. 2 can be operated at higher switching frequencies than some conventional switching circuits implemented using silicon transistors. For example, the switching circuits can be operated at a switching frequency of 30 kHz or higher, 50 kHz or higher, 80 kHz or higher, or up to 1 MHz or higher (i.e., during operation of the circuit, the switches can be switches at a frequency of 30 kHz or higher, 50 kHz or higher, 80 kHz or higher, or up to 1 MHz or higher).
[0043] When a switching circuit is designed to operate at a given switching frequency, unwanted noise and oscillations will occur at an even higher frequency. For example, if the switching frequency is about 1 MHz or less, the oscillations can be between about 100 MHz and 300 MHz. Unwanted oscillations are especially prone to occur in circuits operated at higher switching frequencies, even if the individual switches are capable of operation at the higher switching frequencies.
[0044] Referring again to FIG. 2 , a ferrite bead 210 is coupled between the gate of the low side switch 108 and the second terminal 208 of the gate driver 102. A ferrite bead is a passive electric component and typically is a hollow bead or cylinder made of ferrite, a semi-magnetic substance made from iron oxide alloyed with other metals. A ferrite bead can be used to suppress noise from electromagnetic interference (EMI) in a circuit.
[0045] In the example switching circuit of FIG. 2 , in which the half bridge formed by the high side and low side switches 104 and 108 and configured to be operated at the higher frequencies is implemented as part of an electronic module 200, the ferrite bead 210 generally will not be effective in reducing noise. The current from the source of the low side switch 108 flows through the parasitic inductance and therefore does not flow through the connection 204 to the first terminal 206 of the gate driver 102. Since there is essentially no current flowing through the connection 204, the noise from the parasitic inductance 202 is decoupled from the loop formed by the gate driver 102, the low side switch 108, and the connectors between the gate driver 102 and the source and gate of the low side switch 108. The ineffectiveness of the ferrite bead 210 in this configuration suggests that the ferrite bead 210 would also not be effective in other configurations.
[0046] FIG. 5 is a circuit diagram of the example switching circuit where the switches 104 and 108 are each encased in individual electronic packages. An example of such a packaged III-N device is illustrated in FIG. 6 . The package 702 can, for example, include a metal mounting tab (not shown) which is connected to either a source 706 or a drain 710 of the III-N device 704, as well as source, gate, and drain leads 716, 718, and 720, respectively, connected to the respective source, gate, and drain of the III-N device by connections 701 (e.g., wire bonds). When the packaged III-N device of FIG. 6 is used for switch 108 in FIG. 5 , the source lead 716 of the package is connected both to the first terminal 206 of the gate driver (via connection 502) and to ground 110, the gate lead 718 is connected to the ferrite bead 210, and the drain lead 720 is connected to the source lead of the package of switch 104. As seen in FIG. 5 , in this configuration, the point at which connection 502 is connected to the switch 108 is between the ground 110 and the parasitic source inductance 202 of the switch 108. Consequently, in this configuration the parasitic inductance 202 between the source of the low side switch 108 and the ground node 110 is seen by the gate driver 102.
[0047] In this configuration, the first terminal 206 of the gate driver 102, the second terminal 208 of the gate driver 102, the ferrite bead 210, the low side switch 108, and the parasitic inductance 202 form a gate loop 504. The gate loop 504 is shown for purposes of illustration and does not indicate a physical structure. Here, the ferrite bead 210 can be effective in reducing oscillation and associated EMI or instability in the gate loop 504 due to the parasitic inductance 202. The effectiveness of the ferrite bead 210 in this configuration is unexpected in view of the ineffectiveness of the ferrite bead 210 observed in the electronic circuit for which the half bridge was implemented as part of a module 200, as illustrated in FIG. 2 .
[0048] FIG. 7 is a circuit diagram of the example switching circuit, where a portion of the circuit is again implemented as an electronic module 200, as in FIG. 2 . In the configuration of FIG. 7 , in addition to the ferrite bead 210 coupled between the gate of the low side switch 108 and the second terminal 208 of the gate driver 102, a second ferrite bead 610 is coupled between a third terminal 209 of the gate driver 102 and the gate of the high side switch 104. Here, the second ferrite bead 610 can be effective in reducing oscillations at the gate of the high side switch 104, which is unexpected in view of the ineffectiveness of the ferrite bead 210 coupled to the gate of the low side switch 108.
[0049] Although not shown in FIG. 5 , similar to FIG. 7 , a second ferrite bead 610 may also be coupled between the third terminal 209 of the gate driver 102 and the gate lead of the package of the high side switch 104 in the configuration of FIG. 5 . This configuration is shown in FIG. 8 .
[0050] The ferrite beads 210 and 610 in the circuits of FIGS. 2, 5, 7, and 8 can be selected to form a passive low pass filter configured to block oscillations having frequencies above about 100 MHz or 300 MHz and to pass switching frequencies, e.g., in the tens or hundreds of kHz or the 1 MHz range. Various ferrite beads are available and an appropriate ferrite bead can be selected for a switching circuit based on a target switching frequency.
[0051] For the configurations of FIGS. 5 and 8 , in which individually packaged transistor switches are used for switches 104 and 108, the ferrite beads 210 and 610 may alternatively be incorporated within the packages of their respective switches. FIG. 9 is a schematic illustration of a switch which includes a III-N transistor 704 encased in an electronic package 702. The transistor 704 includes a source 706, a gate 708, and a drain 710. A first connector 712, which can for example be a wire bond, electrically couples the gate 708 to a ferrite bead 714 which is also encased in and mounted directly to the package 702. A second connector 716, which can for example also be a wire bond, electrically couples the ferrite bead 714 to a package lead 718 for the gate 708. By encasing the ferrite bead directly within the package 702, an external ferrite bead is not needed to use the switch in switching circuits which utilize individually packaged switches, e.g., the switching circuits illustrated in FIGS. 5 and 8 .
[0052] FIG. 10 is a schematic illustration of a switch which includes a III-N transistor 704 encased in another electronic package 802 having four package leads 818, 820, 822, and 824. Electronic packages are commonly produced with either three leads or five leads, so the package 802 can be fabricated with four leads by taking a five lead package and either breaking off the fifth lead or simply not using the fifth lead.
[0053] The gate 708 is coupled to the gate lead 818 by the ferrite bead 714, and the drain 710 is coupled (e.g., electrically connected) to the drain lead 824 by a wire bond 812. The source 706 is coupled (e.g., electrically connected) to the source lead 820 by a wire bond 808. The source 706 is also coupled (e.g., electrically connected) to an additional package lead 822 by a wire bond 810. Other types of connectors may also be used in place of the wire bonds. Having two package leads 820 and 822 for the source 706 can allow the switch to be more easily integrated into switching circuits in configurations that can lead to improved circuit performance. For example, referring to FIGS. 5 and 8 , if the low side switch 108 and ferrite bead 210 are implemented as the device of FIG. 10 , then the first package lead 820 for the source 706 can be coupled (e.g., electrically connected) to the ground node 110, and the second package lead 822 for the source 706 can be coupled (e.g., electrically connected) to the first terminal 206 of the gate driver 102.
[0054] The packaged III-N device 704 illustrated in FIGS. 6, 9, and 10 can be a single chip enhancement mode power transistor, e.g. a single chip III-N E-mode transistor. Alternatively, the packaged III-N device 704 can be a hybrid device that includes an enhancement mode transistor and a depletion mode transistor, as was illustrated in FIG. 4 .
[0055] FIG. 11 is a schematic illustration of an example low side transistor 700 and an example high side transistor 700′ that are implemented using electronic packages and can be used for the individually packaged low side and high side switches 108 and 104, respectively, in FIGS. 5 and 8 . The transistors are lateral III-N devices. The low side transistor 700 package includes a heat sink 70, a conductive package base 71, and a case 72 that can be formed of an insulating material. Inside the package, the low side transistor 700 includes a substrate 73, a semiconductor body 74, a source electrode 75, a gate electrode 76, and a drain electrode 77. The source electrode is wire bonded to the conductive package base 71, which is in turn coupled (e.g., electrically connected) to a source package lead. The gate 76 is coupled (e.g., electrically connected) to a gate package lead and the drain 77 is coupled (e.g., electrically connected) to a drain package lead.
[0056] The high side transistor 700′ also includes a heat sink 70′, a conductive package base 71′, and a case 72′. The high side transistor 700′ includes a substrate 73′, a semiconductor body 74′, a source electrode 75′, a gate electrode 76′, and a drain electrode 77′. The drain electrode is wire bonded to the conductive package base 71′, which is in turn coupled (e.g., electrically connected) to a drain package lead. The gate 76′ is coupled (e.g., electrically connected) to a gate package lead and the source 75′ is coupled (e.g., electrically connected) to a source package lead.
[0057] The transistors 700 and 700′ can be used in a switching circuit, e.g., either of the switching circuits of FIGS. 5 and 8 . For example, referring to FIG. 8 , the low side transistor package 700 can be used as the package of the low side switch 108, and the high side transistor package 700′ can be used as the package of the high side switch 104. Using the transistors 700 and 700′ in this configuration can improve capacitive coupling in a switching circuit.
[0058] FIG. 12 is a circuit diagram of an example inverter. The inverter includes a microcontroller 902 and two half bridges comprising a first gate driver 904 and a second gate driver 906. The gate drivers 904 and 906 are coupled to respective gates of III-N devices, e.g., III-N transistors, by ferrite beads 91, 92, 93, and 94. The microcontroller 902 comprises a processor and a memory storing executable instructions that, when executed by the microcontroller, cause the microcontroller to operate each of the gate drivers 904 and 906 as gate drivers of a half bridge.
[0059] FIG. 13 is a circuit diagram of a switching circuit, where a portion of the circuit is again implemented as an electronic module 300, as in FIGS. 2 and 7 . The electronic module 300 in FIG. 13 differs from the electronic module 200 of FIG. 7 in that the high side switch is implemented as a pair of switches 104 and 104′ connected in parallel, and the low side switch is implemented as a pair of switches 108 and 108′ connected in parallel. Many applications require larger load currents than can be supported by individual switches. Connecting two switches in parallel, as in FIG. 13 , allows the maximum current that can be delivered to the load to be approximately double the current that can be delivered when a single switch is used for each of the high and low side switches, as in FIG. 7 . Although not shown in FIG. 13 , the high and low side switches can each include N switches connected in parallel, where N is an integer greater than 2. In this case, the maximum current that can be delivered to the load will be approximately N times the current that can be delivered when a single switch is used for each of the high and low side switches.
[0060] Although not shown in FIG. 13 for the sake of clarity, the gate of switch 104′ is coupled to terminal 209 of the gate driver 102, and the gate of switch 108′ is coupled to terminal 208 of the gate driver 102. This coupling may be achieved in a number of ways. For example, the gate of switch 104′ can be connected to module node 221 and the gate of switch 108′ can be connected to module node 223, such that ferrite bead 610 is shared by switches 104 and 104′, and ferrite bead 210 is shared by switches 108 and 108′. Alternatively, the gates of switches 104′ and 108′ can each be connected to their own additional ferrite beads, with the opposite ends of the additional ferrite beads connected to gate driver terminals 209 and 208, respectively.
[0061] When half bridge switches are formed with parallel devices, as in FIG. 13 , but without ferrite beads coupled to the gates of the switches, the half bridge switches tend to be very unstable during operation. Inclusion of the ferrite beads has been found to substantially increase the stability of these circuits. While providing each of the parallel devices with its own ferrite bead on its gate tends to result in more stable operation than when a single ferrite bead is shared by all the parallel devices, it is typically simpler to design and implement a module in which a single ferrite bead is shared by all the parallel devices.
[0062] As further seen in the circuit of FIG. 13 , in addition to the ferrite beads 610 and 210 coupled between the gates of the high and low side switches and their respective gate driver terminals 209 and 208, ferrite beads 910 and 510 can also be coupled between the sources of the high and low side switches and their respective gate driver terminals 207 and 206. Ferrite beads 910 and 510 can furthermore be included between the sources of the switches and their respective gate driver terminals in any of the circuits described herein. Ferrite beads 910 and 510 can further improve the stability of half bridge circuits in which the switches are configured to support large voltages and/or currents and to operate at high frequencies, in particular when the switches are implemented as parallel devices, as in FIG. 13 .
[0063] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. For example, in the circuits in which the half bridge is provided as an electronic module, the ferrite beads may be included within or as part of the module. Accordingly, other implementations are within the scope of the following claims.
Claims
What is claimed is:
1. A circuit comprising:
a first electronic component package comprising a first lead, a second lead, and a third lead;
a first III-N device encased in the first electronic component package, the first III-N device comprising a first drain, a first gate, and a first source, the first source coupled to the first lead, and the first drain coupled to the third lead;
a second electronic component package comprising a fourth lead, a fifth lead, and a sixth lead;
a second III-N device encased in the second electronic component package, the second III-N device comprising a second drain, a second gate, and a second source, the second source coupled to the fourth lead and the second drain coupled to the sixth lead, wherein the fourth lead of the second electronic component package is directly coupled to the third lead of the first electronic component package;
a gate driver comprising a first terminal and a second terminal, the first terminal being coupled to the first electronic component package at the first lead, and the second terminal being coupled to the first electronic component package at the second lead; and
a ferrite bead encased in the first electronic component package and coupled between the gate of the III-N device and the second lead.
2. The circuit of claim 1, wherein the second terminal of the gate driver, the ferrite bead, the III-N device, the first lead, and the first terminal are included in a gate loop; and wherein the first lead has a parasitic inductance and the ferrite bead is configured to reduce oscillations and electromagnetic interference in the gate loop due to the parasitic inductance.
3. The circuit of claim 1, wherein
the first III-N device encased in the first electronic component package forms a low side switch,
the first lead is coupled to a ground node,
the second III-N device encased in the second electronic component package forms a high side switch coupled to a high voltage node at the sixth lead, and
the gate driver further comprises a third terminal and a fourth terminal, the third terminal being coupled with the second electronic component package at the fifth lead.
4. The circuit of claim 3, wherein the gate driver is configured to apply a low side control signal to the second terminal relative to the first terminal, and to apply a high side control signal to the third terminal relative to the fourth terminal of the gate driver, the fourth terminal being coupled to the second electronic component package at the fourth lead.
5. The circuit of claim 3, comprising:
a processor coupled to the gate driver; and
memory storing executable instructions that, when executed by the processor, cause the processor to control the gate driver to operate the circuit as a half bridge.
6. The circuit of claim 3, wherein the voltage at the high voltage node relative to the ground node is about 400V or higher.
7. The circuit of claim 6, wherein the gate driver is configured to apply a control signal to the second terminal relative to the first terminal, the control signal having a frequency between 30 kHz and 10 MHz.
8. The circuit of claim 3, further comprising a second ferrite bead encased in the second electronic component package and coupled between the high side gate and the fifth lead.
9. The circuit of claim 1, wherein the gate driver is configured to apply a control signal to the second terminal relative to the first terminal, the control signal having a frequency between 30 kHz and 10 MHz.
10. The circuit of claim 1, wherein each of the first III-N device and the second III-N device is an enhancement mode transistor.
11. The circuit of claim 1, wherein each of the first III-N device and the second III-N device is a hybrid device comprising a depletion mode III-N transistor and an enhancement mode silicon transistor.
12. The circuit of claim 1, wherein the ferrite bead forms a passive low pass filter configured to block electromagnetic interference having frequencies above 100 MHz.
13. A circuit comprising:
a gate driver comprising first and second high side terminals and first and second low side terminals;
a first electronic component package comprising a first lead, a second lead coupled to a high voltage node, and a third lead coupled to a load node, the first high side terminal of the gate driver being coupled to the first electronic component package at the first lead, and the second high side terminal of the gate driver being coupled to the first electronic component package at the third lead;
a high side III-N device encased in the first electronic component package, the high side III-N device comprising a high side gate, a high side drain coupled to the second lead, and a high side source coupled to the third lead;
a second electronic component package comprising a fourth lead, a fifth lead coupled to the load node, and a sixth lead coupled to a ground node, the first low side terminal of the gate driver being coupled to the second electronic component package at the fourth lead, and the second low side terminal of the gate driver being coupled to the second electronic component package at the sixth lead;
a low side III-N device encased in the second electronic component package, the low side III-N device comprising a low side gate coupled to the fourth lead, a low side drain coupled to the fifth lead, and a low side source coupled to the sixth lead; and
a ferrite bead encased in the first electronic component package and coupled between the high side gate and the first lead.
14. The circuit of claim 13, comprising:
a processor coupled to the gate driver; and
memory storing executable instructions that, when executed by the processor, cause the processor to control the gate driver to operate the circuit as a half bridge.
15. The circuit of claim 13, wherein during operation of the circuit, the voltage at the high voltage node relative to the ground node is at least 400V.
16. The circuit of claim 13, wherein the gate driver is configured to apply control signals to the first high side terminal relative to the second high side terminal and to the first low side terminal relative to the second terminal, the control signals having a frequency between 30 kHz and 10 MHz.
17. The circuit of claim 13, wherein the high side III-N device comprises a III-N enhancement mode transistor.
18. The circuit of claim 13, wherein the high side III-N device is a hybrid device comprising a depletion mode III-N transistor and an enhancement mode silicon transistor.
19. The circuit of claim 13, wherein the ferrite bead forms a passive low pass filter configured to block electromagnetic interference having frequencies above 100 MHz.
20. A circuit comprising:
a gate driver comprising first and second high side terminals, and first and second low side terminals;
a first electronic component comprising:
a first electronic package comprising a first gate lead, a first drain lead and a first source lead, wherein the first drain lead is coupled to a high voltage node, and the first source lead is coupled to a load node, and wherein the first high side terminal of the gate driver is coupled to the first electronic component package at the first gate lead, and the second high side terminal of the gate driver is coupled to the first electronic component package at the first source lead;
a first ferrite bead encased in the first electronic package; and
a high side III-N device encased in the first electronic package, the high side III-N device comprising a high side gate, a high side source coupled to the first source lead, and a high side drain coupled to the drain lead, wherein the first ferrite bead is coupled between the high side gate and the first gate lead; and
a second electronic component comprising:
a second electronic package comprising a second gate lead, a second drain lead and a second source lead, wherein the second drain lead is coupled to the load node, and the second source lead is coupled to a ground node, and wherein the first low side terminal of the gate driver is coupled to the second electronic component package at the second gate lead, and the second low side terminal of the gate driver is coupled to the second electronic component package at the second source lead;
a second ferrite bead encased in the second electronic package; and
a low side III-N device encased in the second electronic package, the low side III-N device comprising a low side gate, a low side drain coupled to the second drain lead, and a low side source coupled to the second source lead, wherein the second ferrite bead is coupled between the low side gate and the second gate lead.
21. The circuit of claim 20, comprising:
a processor coupled to the gate driver; and
memory storing executable instructions that, when executed by the processor, cause the processor to control the gate driver to operate the circuit as a half bridge.
22. The circuit of claim 20, wherein the circuit is configured such that during operation, the voltage at the high voltage node relative to the ground node is about 400V or higher.
23. The circuit of claim 20, wherein the gate driver is configured to output respective control signals to the high side and low side terminals, the control signals having a frequency between 50 kHz and 1 MHz.
24. The circuit of claim 20, wherein the high side III-N device is an enhancement mode transistor.
25. The circuit of claim 20, wherein the high side III-N device is a hybrid device comprising a depletion mode III-N transistor and an enhancement mode transistor.
26. The circuit of claim 20, wherein the ferrite bead forms a passive low pass filter configured to block electromagnetic interference having frequencies above 100 MHz.
Patent Citations (191)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4321489(A) | 1982-03-01 | Higuchi et al. | Applicant |
| US4384287(A) | 1983-05-01 | Sakuma | Applicant |
| US4665508(A) | 1987-05-01 | Chang | Applicant |
| US4717863(A) | 1988-01-01 | Zeiler | Examiner |
| US4728826(A) | 1988-03-01 | Einzinger et al. | Applicant |
| US4808853(A) | 1989-02-01 | Taylor | Applicant |
| US4864479(A) | 1989-09-01 | Steigerwald et al. | Applicant |
| US5198964(A) | 1993-03-01 | Ito et al. | Applicant |
| US5379209(A) | 1995-01-01 | Goff | Applicant |
| US5493487(A) | 1996-02-01 | Close et al. | Applicant |
| US5637922(A) | 1997-06-01 | Fillion et al. | Applicant |
| US5767573(A) | 1998-06-01 | Noda et al. | Applicant |
| US5789951(A) | 1998-08-01 | Shen et al. | Applicant |
| US5952856(A) | 1999-09-01 | Horiguchi et al. | Applicant |
| US6008684(A) | 1999-12-01 | Ker et al. | Applicant |
| US6107844(A) | 2000-08-01 | Berg et al. | Applicant |
| US6130831(A) | 2000-10-01 | Matsunaga | Applicant |
| US6172550(B1) | 2001-01-01 | Gold et al. | Applicant |
| US6333617(B1) | 2001-12-01 | Itabashi et al. | Applicant |
| US6395593(B1) | 2002-05-01 | Pendharkar et al. | Applicant |
| US6455905(B1) | 2002-09-01 | Perugupalli et al. | Applicant |
| US6521940(B1) | 2003-02-01 | Vu et al. | Applicant |
| US6556053(B2) | 2003-04-01 | Stanley | Applicant |
| US6633195(B2) | 2003-10-01 | Baudelot et al. | Applicant |
| US6650169(B2) | 2003-11-01 | Faye et al. | Applicant |
| US6781423(B1) | 2004-08-01 | Knoedgen | Applicant |
| US6864131(B2) | 2005-03-01 | Thornton | Applicant |
| US6876235(B2) | 2005-04-01 | Li et al. | Applicant |
| US6900657(B2) | 2005-05-01 | Bui et al. | Applicant |
| US6975023(B2) | 2005-12-01 | Oliver et al. | Applicant |
| US7116567(B2) | 2006-10-01 | Shelton et al. | Applicant |
| US7193396(B2) | 2007-03-01 | Orr | Applicant |
| US7199636(B2) | 2007-04-01 | Oswald et al. | Applicant |
| US7199640(B2) | 2007-04-01 | De Cremoux et al. | Applicant |
| US7212063(B2) | 2007-05-01 | Münzer et al. | Applicant |
| US7227198(B2) | 2007-06-01 | Pavier et al. | Applicant |
| US7239108(B2) | 2007-07-01 | Best | Applicant |
| US7304331(B2) | 2007-12-01 | Saito et al. | Applicant |
| US7368980(B2) | 2008-05-01 | Benelbar et al. | Applicant |
| US7375407(B2) | 2008-05-01 | Yanagihara et al. | Applicant |
| US7378883(B1) | 2008-05-01 | Hsueh | Applicant |
| US7382001(B2) | 2008-06-01 | Beach | Applicant |
| US7417257(B2) | 2008-08-01 | Beach et al. | Applicant |
| US7443648(B2) | 2008-10-01 | Cutter et al. | Applicant |
| US7449730(B2) | 2008-11-01 | Kuraguchi | Applicant |
| US7453107(B1) | 2008-11-01 | Kapoor | Applicant |
| US7465997(B2) | 2008-12-01 | Kinzer et al. | Applicant |
| US7477082(B2) | 2009-01-01 | Fukazawa | Applicant |
| US7482788(B2) | 2009-01-01 | Yang | Applicant |
| US7501669(B2) | 2009-03-01 | Parikh et al. | Applicant |
| US7522435(B2) | 2009-04-01 | Kohnotoh et al. | Applicant |
| US7538366(B2) | 2009-05-01 | Saito et al. | Applicant |
| US7547964(B2) | 2009-06-01 | Pavier et al. | Applicant |
| US7548112(B2) | 2009-06-01 | Sheppard | Applicant |
| US7550781(B2) | 2009-06-01 | Kinzer et al. | Applicant |
| US7612602(B2) | 2009-11-01 | Yang et al. | Applicant |
| US7639064(B2) | 2009-12-01 | Hsiao et al. | Applicant |
| US7701009(B2) | 2010-04-01 | Koyama | Applicant |
| US7714360(B2) | 2010-05-01 | Otsuka et al. | Applicant |
| US7719055(B1) | 2010-05-01 | McNutt et al. | Applicant |
| US7745930(B2) | 2010-06-01 | Connah et al. | Applicant |
| US7746020(B2) | 2010-06-01 | Schnetzka et al. | Applicant |
| US7755108(B2) | 2010-07-01 | Kuraguchi | Applicant |
| US7782099(B2) | 2010-08-01 | Kawamura | Applicant |
| US7795642(B2) | 2010-09-01 | Suh et al. | Applicant |
| US7800215(B2) | 2010-09-01 | Satou et al. | Applicant |
| US7804328(B2) | 2010-09-01 | Pentakota et al. | Applicant |
| US7811872(B2) | 2010-10-01 | Hoshi et al. | Applicant |
| US7851825(B2) | 2010-12-01 | Suh et al. | Applicant |
| US7851909(B2) | 2010-12-01 | Mishra et al. | Applicant |
| US7852137(B2) | 2010-12-01 | Machida et al. | Applicant |
| US7855401(B2) | 2010-12-01 | Sheppard et al. | Applicant |
| US7863877(B2) | 2011-01-01 | Briere | Applicant |
| US7875907(B2) | 2011-01-01 | Honea et al. | Applicant |
| US7875914(B2) | 2011-01-01 | Sheppard | Applicant |
| US7884394(B2) | 2011-02-01 | Wu et al. | Applicant |
| US7884395(B2) | 2011-02-01 | Saito | Applicant |
| US7893676(B2) | 2011-02-01 | Hanna | Applicant |
| US7893791(B2) | 2011-02-01 | Ma et al. | Applicant |
| US7898004(B2) | 2011-03-01 | Wu et al. | Applicant |
| US7898509(B2) | 2011-03-01 | Iida et al. | Applicant |
| US7902809(B2) | 2011-03-01 | Briere et al. | Applicant |
| US7906837(B2) | 2011-03-01 | Cabahug et al. | Applicant |
| US7915643(B2) | 2011-03-01 | Suh et al. | Applicant |
| US7920013(B2) | 2011-04-01 | Sachdev et al. | Applicant |
| US7932539(B2) | 2011-04-01 | Chen et al. | Applicant |
| US7939391(B2) | 2011-05-01 | Suh et al. | Applicant |
| US7965126(B2) | 2011-06-01 | Honea et al. | Applicant |
| US7973335(B2) | 2011-07-01 | Okamoto et al. | Applicant |
| US7982242(B2) | 2011-07-01 | Goto | Applicant |
| US8013580(B2) | 2011-09-01 | Cervera et al. | Applicant |
| US8018056(B2) | 2011-09-01 | Hauenstein | Applicant |
| US8054110(B2) | 2011-11-01 | Wang et al. | Applicant |
| US8063616(B2) | 2011-11-01 | Bahramian et al. | Applicant |
| US8084783(B2) | 2011-12-01 | Zhang | Applicant |
| US8089139(B2) | 2012-01-01 | Shi et al. | Applicant |
| US8114710(B2) | 2012-02-01 | Muto et al. | Applicant |
| US8138529(B2) | 2012-03-01 | Wu | Applicant |
| US8188596(B2) | 2012-05-01 | Otremba | Applicant |
| US8193559(B2) | 2012-06-01 | Haeberlen et al. | Applicant |
| US8193562(B2) | 2012-06-01 | Suh et al. | Applicant |
| US8237198(B2) | 2012-08-01 | Wu et al. | Applicant |
| US8258622(B2) | 2012-09-01 | Lee et al. | Applicant |
| US8289065(B2) | 2012-10-01 | Honea et al. | Applicant |
| US8344424(B2) | 2013-01-01 | Suh et al. | Applicant |
| US8363437(B2) | 2013-01-01 | Wang et al. | Applicant |
| US8389977(B2) | 2013-03-01 | Chu et al. | Applicant |
| US8390000(B2) | 2013-03-01 | Chu et al. | Applicant |
| US8441128(B2) | 2013-05-01 | Domes | Applicant |
| US8455931(B2) | 2013-06-01 | Wu | Applicant |
| US8493129(B2) | 2013-07-01 | Honea et al. | Applicant |
| US8508281(B2) | 2013-08-01 | Honea et al. | Applicant |
| US8519438(B2) | 2013-08-01 | Mishra et al. | Applicant |
| US8530904(B2) | 2013-09-01 | Treu et al. | Applicant |
| US8531232(B2) | 2013-09-01 | Honea et al. | Applicant |
| US8541818(B2) | 2013-09-01 | Wu et al. | Applicant |
| US8592974(B2) | 2013-11-01 | Wu | Applicant |
| US8598937(B2) | 2013-12-01 | Lal et al. | Applicant |
| US8624662(B2) | 2014-01-01 | Parikh et al. | Applicant |
| US8633518(B2) | 2014-01-01 | Suh et al. | Applicant |
| US8643062(B2) | 2014-02-01 | Parikh et al. | Applicant |
| US8648643(B2) | 2014-02-01 | Wu | Applicant |
| US8681518(B2) | 2014-03-01 | Callanan et al. | Applicant |
| US8692294(B2) | 2014-04-01 | Chu et al. | Applicant |
| US8716141(B2) | 2014-05-01 | Dora et al. | Applicant |
| US8742459(B2) | 2014-06-01 | Mishra et al. | Applicant |
| US8742460(B2) | 2014-06-01 | Mishra et al. | Applicant |
| US8772842(B2) | 2014-07-01 | Dora | Applicant |
| US8786327(B2) | 2014-07-01 | Honea et al. | Applicant |
| US8803246(B2) | 2014-08-01 | Wu et al. | Applicant |
| US8816497(B2) | 2014-08-01 | Wu | Applicant |
| US8816751(B2) | 2014-08-01 | Honea et al. | Applicant |
| US8841702(B2) | 2014-09-01 | Mishra et al. | Applicant |
| US8860495(B2) | 2014-10-01 | Lal et al. | Applicant |
| US2002/0067139(A1) | 2002-06-01 | Sabate | Applicant |
| US2002/0190389(A1) | 2002-12-01 | Koenck | Examiner |
| US2004/0047540(A1) | 2004-03-01 | Moto | Examiner |
| US2004/0120090(A1) | 2004-06-01 | Galli et al. | Applicant |
| US2004/0240236(A1) | 2004-12-01 | Lanni | Applicant |
| US2006/0226433(A1) | 2006-10-01 | Kawano | Examiner |
| US2007/0109707(A1) | 2007-05-01 | Honda | Applicant |
| US2007/0210329(A1) | 2007-09-01 | Goto | Applicant |
| US2008/0017998(A1) | 2008-01-01 | Pavio | Applicant |
| US2008/0061876(A1) | 2008-03-01 | Kaya | Examiner |
| US2008/0248634(A1) | 2008-10-01 | Beach | Applicant |
| US2009/0050936(A1) | 2009-02-01 | Oka | Applicant |
| US2009/0072269(A1) | 2009-03-01 | Suh et al. | Applicant |
| US2009/0278513(A1) | 2009-11-01 | Bahramian et al. | Applicant |
| US2011/0169549(A1) | 2011-07-01 | Wu | Applicant |
| US2012/0001662(A1) | 2012-01-01 | Pidutti | Examiner |
| US2012/0132973(A1) | 2012-05-01 | Wu | Examiner |
| US2012/0306464(A1) | 2012-12-01 | Hirler et al. | Applicant |
| CN1921148 | 2007-02-01 | Applicant | |
| CN101978589 | 2011-02-01 | Applicant | |
| CN102165694 | 2011-08-01 | Applicant | |
| CN102308387 | 2012-01-01 | Applicant | |
| CN103477543 | 2013-12-01 | Applicant | |
| EP2188842 | 2010-05-01 | Applicant | |
| EP2243213 | 2010-10-01 | Applicant | |
| EP2394303 | 2011-12-01 | Applicant | |
| JP5-075040 | 1993-03-01 | Applicant | |
| JP6-067744 | 1994-03-01 | Applicant | |
| JP2000-101356 | 2000-04-01 | Applicant | |
| JP2000-124358 | 2000-04-01 | Applicant | |
| JP2003-244943 | 2003-08-01 | Applicant | |
| JP2003-338742 | 2003-11-01 | Applicant | |
| JP2004-281454 | 2004-10-01 | Applicant | |
| JP2006-033723 | 2006-02-01 | Applicant | |
| JP2006-173754 | 2006-06-01 | Applicant | |
| JP2007-036218 | 2007-02-01 | Applicant | |
| JP2007-215331 | 2007-08-01 | Applicant | |
| JP2007-294769 | 2007-11-01 | Applicant | |
| JP2008-199771 | 2008-08-01 | Applicant | |
| JP2010-525023 | 2010-07-01 | Applicant | |
| JP2011-512119 | 2011-04-01 | Applicant | |
| JP2012-517699 | 2012-08-01 | Applicant | |
| TW200941920 | 2009-10-01 | Applicant | |
| TW201027912 | 2010-07-01 | Applicant | |
| TW201036155 | 2010-10-01 | Applicant | |
| TW201126686 | 2011-08-01 | Applicant | |
| TW201143017 | 2011-12-01 | Applicant | |
| TW201332085 | 2013-08-01 | Applicant | |
| TW201347143 | 2013-11-01 | Applicant | |
| WO2009/036266 | 2009-03-01 | Applicant | |
| WO2009/102732 | 2009-08-01 | Applicant | |
| WO2010/039463 | 2010-04-01 | Applicant | |
| WO2010/090885 | 2010-08-01 | Applicant | |
| WO2011/053981 | 2011-05-01 | Applicant | |
| WO2011/085260 | 2011-07-01 | Applicant | |
| WO2011/097302 | 2011-08-01 | Applicant | |
| WO2013/085839 | 2013-06-01 | Applicant |
Non-Patent Literature (82)
- U.S. Appl. No. 11/856,695, filed Sep. 17, 2007, Gallium Nitride Diodes and Integrated Components.Applicant
- U.S. Appl. No. 14/108,642, filed Dec. 17, 2013, Gallium Nitride Power Devices.Applicant
- U.S. Appl. No. 60/971,721, filed Sep. 12, 2007, III-Nitride Bilateral Switches.Applicant
- U.S. Appl. No. 60/972,467, Sep. 14, 2007, Growing N-Polar III-Nitride Structures.Applicant
- U.S. Appl. No. 12/209,504, filed Sep. 12, 2008, Growing N-Polar III-Nitride Structures.Applicant
- U.S. Appl. No. 60/972,481, filed Sep. 14, 2007, III-Nitride Devices with Recessed Gates.Applicant
- U.S. Appl. No. 61/012,755, filed Dec. 10, 2007, Insulated Gate E-Mode Transistors.Applicant
- U.S. Appl. No. 61/028,133, filed Feb. 12, 2008, Bridge Circuits and their Components.Applicant
- U.S. Appl. No. 13/887,204, filed May 3, 2013, Bridge Circuits and their Components.Applicant
- U.S. Appl. No. 14/464,639, filed Aug. 20, 2014, Enhancement Mode III-N HEMTs.Applicant
- U.S. Appl. No. 61/099,451, filed Sep. 23, 2008, Inductive Load Power Switching Circuits.Applicant
- U.S. Appl. No. 14/332,967, filed Jul. 16, 2014, Inductive Load Power Switching Circuits.Applicant
- U.S. Appl. No. 13/973,890, filed Aug. 22, 2013, Semiconductor Heterostructure Diodes.Applicant
- U.S. Appl. No. 14/063,438, filed Oct. 25, 2013, Package Configurations for Low EMI Circuits.Applicant
- U.S. Appl. No. 13/756,284, filed Jan. 31, 2013, Methods of Forming Reverse Side Engineered III-Nitride Devices.Applicant
- U.S. Appl. No. 14/262,649, filed Apr. 25, 2014, High Voltage III-Nitride Semiconductor Devices.Applicant
- U.S. Appl. No. 14/178,701, filed Feb. 12, 2014, Semiconductor Devices with Field Plates.Applicant
- U.S. Appl. No. 14/336,287, filed Jul. 21, 2014, Electronic Devices and Components for High Efficiency Power Circuits.Applicant
- U.S. Appl. No. 14/058,089, filed Oct. 18, 2013, Semiconductor Electronic Components and Circuits.Applicant
- U.S. Appl. No. 14/260,808, filed Apr. 24, 2014, Transistors with Isolated Regions.Applicant
- U.S. Appl. No. 12/953,769, filed Nov. 24, 2010, Layer Structures for Controlling Stress of Heteroepitaxially Grown III-Nitride Layers.Applicant
- U.S. Appl. No. 13/226,380, filed Sep. 6, 2011, Semiconductor Devices with Guard Rings.Applicant
- U.S. Appl. No. 14/530,204, filed Oct. 31, 2014, Semiconductor Devices with Guard Rings.Applicant
- U.S. Appl. No. 14/102,750, filed Dec. 11, 2013, III-N Device Structures and Methods.Applicant
- U.S. Appl. No. 14/522,154, filed Oct. 23, 2014, III-N Device Structures and Methods.Applicant
- U.S. Appl. No. 14/288,682, filed May 28, 2014, Method for Making Semiconductor Diodes with Low Reverse Bias Currents.Applicant
- U.S. Appl. No. 14/524,299, filed Oct. 27, 2014, Semiconductor Diodes with Low Reverse Bias Currents.Applicant
- U.S. Appl. No. 14/211,104, filed Mar. 14, 2014, Electrode Configurations for Semiconductor Devices.Applicant
- U.S. Appl. No. 61/447,519, filed Feb. 28, 2011, Electronic Components with Reactive Filters.Applicant
- U.S. Appl. No. 14/307,234, filed Jun. 17, 2014, Method of Forming Electronic Components with Reactive Filters.Applicant
- U.S. Appl. No. 61/568,022, filed Dec. 7, 2011, Semiconductor Modules and Methods of Forming the Same.Applicant
- U.S. Appl. 13/690,103, filed Nov. 30, 2012, Semiconductor Modules and Methods of Forming the Same.Applicant
- U.S. Appl. No. 13/366,090, filed Feb. 3, 2012, Buffer Layer Structures Suited for III-Nitride Devices with Foreign Substrates.Applicant
- U.S. Appl. No. 14/134,878, filed Dec. 19, 2013, Semiconductor Power Modules and Devices.Applicant
- U.S. Appl. No. 61/621,956, filed Apr. 9, 2012, N-Polar III-Nitride Transistors.Applicant
- U.S. Appl. No. 13/859,635, filed Apr. 9, 2013, N-Polar III-Nitride Transistors.Applicant
- U.S. Appl. No. 61/765,635, filed Feb. 15, 2013, Electrodes for Semiconductor Devices and Methods of Forming the Same.Applicant
- U.S. Appl. No. 14/179,788, filed Feb. 13, 2014, Electrodes for Semiconductor Devices and Methods of Forming the Same.Applicant
- U.S. Appl. No. 61/791,395, filed Mar. 15, 2013, Carbon Doping Semiconductor Devices.Applicant
- U.S. Appl. No. 14/208,304, filed Mar. 13, 2014, Carbon Doping Semiconductor Devices.Applicant
- U.S. Appl. No. 13/799,989, filed Mar. 13, 2013, Enhancement-Mode III-Nitride Devices.Applicant
- U.S. Appl. No. 61/807,258, filed Apr. 1, 2013, Gate Drivers for Circuits Based on Semiconductor Devices.Applicant
- U.S. Appl. No. 14/222,992, filed Mar. 24, 2014, Gate Drivers for Circuits Based on Semiconductor Devices.Applicant
- U.S. Appl. No. 61/844,260, filed Jul. 9, 2013, Multilevel Inverters and their Components.Applicant
- U.S. Appl. No. 14/321,269, filed Jul. 1, 2014, Multilevel Inverters and their Components.Applicant
- U.S. Appl. No. 61/856,573, filed Jul. 19, 2013, III-Nitride Transistor Including a P-Type Depleting Layer.Applicant
- U.S. Appl. No. 14/327,371, filed Jul. 9, 2014, III-Nitride Transistor Including a P-Type Depleting Layer.Applicant
- U.S. Appl. No. 14/208,482, filed Mar. 13, 2014, Carbon Doping Semiconductor Devices.Applicant
- U.S. Appl. No. 13/231,308, filed Sep. 13, 2011, III-N Device Structures Having a Non-Insulating Substrate.Applicant
- U.S. Appl. No. 14/478,504, filed Sep. 5, 2014, Method of Forming Electronic Components with Increased Reliability.Applicant
- U.S. Appl. No. 13/535,094, filed Jun. 27, 2012, Semiconductor Devices with Integrated Hole Collectors.Applicant
- U.S. Appl. No. 14/311,600, filed Jun. 23, 2014, Semiconductor Electronic Components with Integrated Current Limiters.Applicant
- U.S. Appl. No. 13/551,094, filed Jul. 17, 2012, Contacts for Semiconductor Devices and Methods of Forming the Same.Applicant
- U.S. Appl. No. 61/672,723, filed Jul. 17, 2012, Devices and Components for Power Conversion Circuits.Applicant
- U.S. Appl. No. 13/803,912, filed Mar. 14, 2013, Devices and Components for Power Conversion Circuits.Applicant
- Authorized officer Sang Won Choi, International Search Report and Written Opinion in PCT/US2015/039041, mailed Oct. 14, 2015, 16 pages.Applicant
- Authorized officer Keon Hyeong Kim, International Search Report and Written Opinion in PCT/US2008/076160 mailed Mar. 18, 2009, 11 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2008/076160, mailed Mar. 25 2010, 6 pages.Applicant
- Authorized officer Jae Woo Wee, International Search Report and Written Opinion in PCT/US2009/033699, mailed Sep. 21, 2009, 11 pages.Applicant
- Authorized officer Dorothée Müllhausen, International Preliminary Report on Patentability in PCT/US2009/033699, mailed Aug. 26, 2010, 6 pages.Applicant
- Authorized officer Sung Hee Kim, International Search Report and the Written Opinion in PCT/US2009/057554, mailed May 10, 2010, 13 pages.Applicant
- Authorized Officer Gijsbertus Beijer, International Preliminary Report on Patentability in PCT/US2009/057554, mailed Mar. 29, 2011, 7 pages.Applicant
- Authorized officer Sung Chan Chung, International Search Report and Written Opinion for PCT/US2010/021824, mailed Aug. 23, 2010, 9 pages.Applicant
- Authorized officer Beate Giffo-Schmitt, International Preliminary Report on Patentability in PCT/US2010/021824, mailed Aug. 18, 2011, 6 pages.Applicant
- Authorized officer Bon Gyoung Goo, International Search Report and Written Opinion in PCT/US2010/055129, mailed Jul. 1, 2011, 11 pages.Applicant
- Authorized officer Yolaine Cussac, International Preliminary Report on Patentability in PCT/US2010/055129, mailed May 18, 2012, 6 pages.Applicant
- Authorized officer Sung Joon Lee, International Search Report and Written Opinion in PCT/US2011/020592, mailed Sep. 19, 2011, 9 pages.Applicant
- Authorized officer Philippe Bécamel, International Preliminary Report on Patentability in PCT/US2011/020592, mailed Jul. 19, 2012, 7 pages.Applicant
- Authorized officer Kee Young Park, International Search Report and Written Opinion in PCT/US2011/023485, mailed Sep. 23 2011, 10 pages.Applicant
- Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2011/023485, mailed Aug. 16, 2012, 7 pages.Applicant
- Authorized officer Kwak In Gu, International Search Report and Written Opinion in PCT/US2012/026810, mailed Jan. 23, 2013, 10 pages.Applicant
- Authorized officer Lingfei Bai, International Preliminary Report on Patentability in PCT/US2012/026810, mailed Sep. 12, 2013, 6 pages.Applicant
- Authorized officer Sung Gon Kim, International Search Report and Written Opinion in PCT/US2014/032241, mailed Aug. 11, 2014, 12 pages.Applicant
- Search Report and Action in TW Application No. 098132132, issued Dec. 6, 2012, 8 pages.Applicant
- Search Report and Action in TW Application No. 098141930, issued Jul. 10, 2014, 7 pages.Applicant
- Chinese Third Office Action in Application No. 200980110230.0, Jan. 24, 2014, 18 pages.Applicant
- Japanese Office action in Application No. 2010-546867, Sep. 24, 2013, 14 pages.Applicant
- Chen et al., “Single-Chip Boost Converter Using Monolithically Integrated AlGan/GaN Lateral Field-Effect Rectifier and Normally Off HEMT,” IEEE Electron Device Letters, May 2009, 30(5):430-432.Applicant
- Choi et al., “AN-9005 Driving and Layout Design for Fast Switching Super-junction MOSFETs,” © 2013 Fairchild Corporation, 13 pages.Applicant
- Napierala et al., “Selective GaN Epitaxy on Si(111) Substrates Using Porous Aluminum Oxide Buffer Layers,” Journal of the Electrochemical Society, 2006. 153(2):G125-G127, 4 pages.Applicant
- Rodriguez et al, “Tutorial on Multilevel Converters,” International Conference on Power Electronics and Intelligent Control for Energy Conservation, Warsaw, Poland, Oct. 17-19, 2005, 148 pages.Applicant
- Wu et al., “A 97.8% Efficient GaN HEMT Boost Converter with 300-W Output Power at 1MHz,”Electronic Device Letters, 2008, IEEE, 29(8):824-826.Applicant