DC/DC converter including a depletion mode power switch

[0001] This application claims the benefit of U.S. Provisional Application No. 60/867,437, filed Nov. 28, 2006, the entire disclosure of which is incorporated by reference herein.

[0002] This invention relates to DC/DC conversion circuits and more specifically relates to a buck converter circuit using one or more depletion mode III-nitride based switches.

[0003] The synchronous buck converter circuit is commonly used for DC/DC switching applications. Traditionally, the silicon based MOSFET is used in these circuits. III-nitride based heterojunction switches are also well known and have greater current capacity and improved voltage withstand ability than a silicon based device of the same size and have reduced parasitic capacitances. However, many III-nitride based switches suitable for power applications are normally on in the absence of a gate signal.

[0004] A circuit according to the present invention is a converter that includes a first switch, a III-nitride depletion mode switch, and an enhancement mode switch disposed in the path of conduction to the III-nitride depletion mode switch to selectively open/close the conduction path to the III-nitride depletion mode switch.

[0005] According to one aspect of the present invention, the enhancement mode switch enables the conduction of current to the III-nitride switch.

[0006] According to another aspect of the present invention, the enhancement mode switch cuts off the current to the III-nitride switch.

[0015] FIG. 1 shows a conventional buck converter circuit comprising an input d-c source 20 of voltage V_in connected in series with a control MOSFET Q₁ (Silicon-based), an output inductor L_out 30 and to an output node V_out 31. A synchronous MOSFET Q₂ (silicon based) is connected from switched node 27 between Q₁ and L_out to ground (the battery 20 return). An output capacitor C_out 32 is provided as usual. Devices Q₁ and Q₂ may have parasitic internal diodes D₁ and D₂.

[0016] A control IC (driver 21) is connected to the gates G₁ and G₂ of FETs Q₁ and Q₂ and drives the devices as shown in FIGS. 2A and 2B. A bias voltage V_DR is connected through capacitor 22 (not shown) to power the IC21. The waveforms of the various currents in the circuit are shown in FIGS. 2C to 2G. The output of Vout is measured and the timing of the voltages at G₁ and G₂ is appropriately modified to vary the duty cycle D (FIG. 2A) to maintain a predetermined fixed output voltage V_out, regardless of changes in the voltage V_in.

[0017] The synchronous buck converter of FIG. 1 is widely used as a non-isolated power conversion circuit, based on its half bridge topology. It is desirable to reduce the reactive components to a minimum for higher switching frequencies, making the dynamic behavior of the switches Q₁ and Q₂ a key factor. Thus, the silicon based MOSFETs Q₁ and Q₂ of FIG. 1 require a minimization of their parasitic capacitances, specifically the gate to drain (Miller) capacitance; and the source to drain (output) capacitance to increase the efficiency of the circuit.

[0018] Gallium Nitride (GaN) switches are known (for example III-Nitride heterojunction HEMT devices) which have certain improved switching characteristics, as compared to silicon based MOSFETs and particularly have a lower parasitic Miller and output capacitance.

[0019] It may be desirable to use a normally-on (depletion mode) III-nitride heterojunction power semiconductor device in a power converter application, such as a DC-DC converter. One such application may be a buck converter that includes at least one III-nitride depletion mode heterojunction power semiconductor device.

[0020] Thus, for example, the control switch Q₁ and synchronous switch Q₂ may be depletion mode devices (FIG. 3A), only the synchronous switch Q₂ can be a depletion mode device (FIG. 3B), or only the control switch Q₁ can be a depletion mode device (FIG. 3C).

[0021] In power converters that use at least one normally-on (depletion mode) device, there is a possibility of damage to the circuit if V_in powers up earlier than V_dr to the IC driver 21 or V_out is pre-biased thereby causing a short circuit between V_in to V_out or V_out to ground.

[0022] A circuit according to the present invention overcomes the above-mentioned problems by providing an enable switch which solves the power up sequence problem of V_in and V_dr, or a cutoff-switch to handle the pre-bias problem. These two solutions can be combined as in FIG. 16.

[0023] Referring now to FIG. 4, in which like numerals identify like features, in a circuit according to the first embodiment of the present invention, a silicon based enable switch Q₃ is series connected with a III-nitride depletion mode control switch Q₁, which is in a buck arrangement with an enhancement mode silicon synchronous switch Q₂ (e.g. a silicon based MOSFET). Enable switch Q₃ is a normally-off switch, which in the preferred embodiment may be a silicon-based power MOSFET, driven by an enable signal EN from a driver 23.

[0024] Referring to FIG. 5, in a second embodiment, a capacitor 25 is parallel connected between Vin and ground to reduce the parasitic elements induced by the insertion of the enable switch Q3. Otherwise, the arrangement is similar to the one shown in FIG. 4.

[0025] Referring now to FIG. 6, in a third embodiment according to the present invention, the enable switch Q₃ is series connected between III-nitride control switch Q₁ and switched node 27. Otherwise, the circuit shown in FIG. 6 is similar to the first embodiment as illustrated by FIG. 4.

[0026] FIG. 7 illustrates a waveform diagram for the circuits that include an enable switch Q₃. Thus, when Vin is established before the driver IC bias voltage Vdr, which is negative, the gate of the III-nitride switch will not be negatively biased to turn off. As a result, the III-nitride device is still on to let input voltage pass through Q₁ to the output. To solve the problem, the enable switch is off until the negative Vdr is established beyond the threshold voltage of the III-nitride switch (UVLO: under voltage lockout). Enable switch on/off is controlled by EN signal. The same sequence happens during power off. When Vdr drops below UVLO threshold, enable switch turns off to block the conduction by the III-nitride switch. The pulse signals of Q₁ and Q₂ represent PWM switching during the normal operation.

[0027] Referring now to FIG. 8, in a circuit according to the fourth embodiment of the present invention, synchronous switch Q₂ is a depletion mode III-nitride switch, while the control switch Q₁ is a silicon based device, for example, a silicon-based power MOSFET. To prevent damage due to the pre-biased condition (i.e. the presence of partial V_out during power up which may be discharged by the power switch Q₂), a cutoff-switch Q₄ is series connected between inductor 30 and output node 31. Cutoff-switch Q₄ is preferably a silicon-based switch, for example, a silicon-based power MOSFET which is operated by a drive signal PBEN from driver 33.

[0028] Referring now to FIG. 9, in a circuit according to the fifth embodiment, cutoff-switch Q₄ is series connected between the switched node 27 and inductor 30. Otherwise, the circuit is similar to the fourth embodiment as illustrated by FIG. 8.

[0029] Referring to FIG. 10, in a circuit according to the sixth embodiment, cutoff-switch Q₄ is series connected between synchronous switch Q₂ and switched node 27. Otherwise, the circuit is similar to the fourth embodiment.

[0030] Referring to FIG. 11, in a circuit according to the seventh embodiment, cutoff-switch Q₄ is series connected between the synchronous switch Q₂ and ground. Otherwise, the seventh embodiment is similar to the fourth embodiment of the present invention.

[0031] Referring now to FIG. 12, in a circuit according to the eighth embodiment, cutoff-switch Q₄ is connected between the ground connection of synchronous switch Q₂ and the ground connection of output capacitor 32. The eighth embodiment may further include a capacitor 25 parallel connected between V_in and Q₂ return. Capacitor 32 provides low impedance bypass for the floating power stage consisting of driver and Q₁/Q₂ because once Q₄ is off which cuts off the ground, capacitor 32 return is not the same as ground any more. Otherwise, the eighth embodiment is similar to the fourth embodiment.

[0032] Referring to FIG. 13, in a circuit according to the ninth embodiment, cutoff-switch Q₄ is series connected between output capacitor 32 and V_out node 31. Otherwise, the ninth embodiment is similar to the fourth embodiment.

[0033] Referring now to FIG. 14, in a circuit according to the tenth embodiment, capacitor 25 may be omitted from the eighth embodiment. Note that in this embodiment V_out return is not ground any more due to the presence of cutoff switch Q₄. Comparing to FIG. 12, which floats driver and Q₁/Q₂, this embodiment floats V_out. Thus, the difference is whether the V_in capacitor return is connected to Q₂ or V_out.

[0034] FIG. 15 illustrates a waveform diagram for a circuit that includes a pre-biased cutoff-switch Q₃ according to the present invention. Thus, when partial V_out is established before the driver IC bias voltage Vdr, which is negative, the gate of Q₂ will not be negatively biased to turn off. As a result, Q₂ is still on to discharge V_out, which is not allowed in many applications. To solve the problem, the cutoff switch is inserted between Q2 and V_out capacitor. Enable switch is off until the negative Vdr is established beyond the threshold voltage of the III-nitride switch (UVLO: under voltage lockout). Cutoff switch on/off is controlled by PEN signal. The same sequence happens during power off. When Vdr drops below UVLO threshold, cutoff switch turns off to block conduction by the III-nitride switch. The pulse signals of Q₁ and Q₂ represent PWM switching during normal operation.

[0035] FIG. 16 illustrates another embodiment of the present invention in which enable switch Q₃ and cutoff-switch Q₄ are implemented together, and control switch Q₁ and synchronous switch Q₂ are both depletion mode III-nitride switches. FIG. 16 is just one example of how enable and cutoff switches should be used with III-nitride switches on both high side and low side. The combinations of the embodiments of FIGS. 4-6 for high side III-nitride switches and FIGS. 8-14 for low side III-nitride switches can also be applied as in FIG. 16 to obtain further embodiments.

[0036] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.