US 7,804,328 B2Grant
Source/emitter follower buffer driving a switching load and having improved linearity
Issue Date:2010-09-28
•16 Claims
•3 Drawing Sheets
Abstract
A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a node formed by the junction of a pair of transistors forming a cascoded current source connected to the output of the buffer. The capacitor passes input signal current directly to a switching load connected to the output of the buffer, and very little signal-dependant current flows through the transistor receiving the input signal. As a result, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the transistor receiving the input signal is minimized. When incorporated in switched-capacitor analog to digital converters, the buffer facilitates generation of digital codes that represent an input signal more accurately.
Metadata
Assignee
- Texas Instruments Incorporated
Inventors
- Visvesvaraya Appala Pentakota
- Nitin Agarwal
Application Information
Application Number:US 12/199,804
Filing Date:2008-08-28
Priority Date:2008-06-23
Art Unit:2819
Classifications
IPC:
H03K17/16H03B1/00
Patent Drawings (3 sheets)
Description
Related Application
[0001] The present application claims the benefit of co-pending India non-provisional application serial number: 1531/CHE/2008, entitled: “SOURCE /EMITTER FOLLOWER BUFFER DRIVING A SWITCHING LOAD AND HAVING IMPROVED LINEARITY ”, filed on Jun. 23, 2008, naming Texas Instruments Inc. (the intended assignee) as the Applicant, and the same inventors as in the subject application as inventors, and is incorporated in its entirety herewith.
Background
[0002] 1. Field of the Invention
[0003] The present invention relates generally to buffers used in semiconductor circuits, and more specifically to a source/emitter follower buffer that drives a switching load, and has improved linearity.
[0004] 2. Related Art
[0005] Buffers are often used in a semiconductor device to isolate one portion of the device from another portion, generally to minimize the characteristics of one portion from influencing the operation of the other portion. A buffer generally contains at least one transistor and the buffer is termed as a source follower when the output is provided from a source terminal and as an emitter follower when the output is provided from an emitter terminal. In both cases, the input signal is provided to the control (gate or base) terminal of the transistor.
[0006] Buffers often drive switching loads. A switching load generally refers to a load which is electrically connected and disconnected from (a source of) a signal in different intervals of time. Examples of switching loads include switched-capacitor components such as switched-capacitor analog to digital converters (ADC), switched capacitor filters, etc. In a common configuration associated with switching loads, a buffer receives the input signal, and provides a corresponding output signal to the switching load.
[0007] It is generally desirable that an output signal of a buffer have as linear a relation as possible with an input signal, i.e., the buffer operate with a high degree of linearity to ensure that the output signal is a correct representation of the input signal.
Summary of the Invention
[0008] A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a node formed by the junction of a pair of transistors forming a cascoded current source connected to the output of the buffer. The capacitor passes input signal current directly to a switching load connected to the output of the buffer, and very little signal-dependant current flows through the transistor receiving the input signal.
[0009] As a result, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the transistor receiving the input signal is minimized.
[0010] When incorporated in switched-capacitor analog to digital converters, the buffer facilitates generation of digital codes that represent an input signal more accurately.
[0011] Several aspects of the invention are described below with reference to examples for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant arts, however, will readily recognize that the invention can be practiced without one or more of the specific details, or with other methods, etc. In other instances, well known structures or operations are not shown in detail to avoid obscuring the features of the invention.
Brief Description of the Drawings
[0012] The present invention will be described with reference to the following accompanying drawings, which are described briefly below.
[0013] FIG. 1 is a block diagram of an example circuit in which several aspects of the present invention can be implemented.
[0014] FIG. 2 is a circuit diagram illustrating the details of a prior source follower buffer.
[0015] FIG. 3 is a circuit diagram illustrating the details of another prior source follower buffer.
[0016] FIG. 4 is a circuit diagram of a source/emitter follower buffer in an embodiment of the present invention.
[0017] In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
Detailed Description of Example Embodiments
1. Example Circuit
[0018] FIG. 1 is a block diagram of an example circuit in which several aspects of the present invention can be implemented. The diagram is shown containing switched-capacitor analog to digital converter (ADC) 110 and processing unit 150. Switched-capacitor ADC 110 is, in turn, shown containing buffer 130 and conversion block 140. Each of switched-capacitor ADC 110 and processing unit 150 may be implemented in the form of either separate integrated circuits (IC) or combined in a single IC.
[0019] Processing unit 150 receives on path 115 digital codes representing the strength (magnitude) of samples of input signal 101 at corresponding time instances, and operates to process the digital codes in a desired manner. Processing unit 150 may, for example, correspond to a digital signal processor (DSP), and may execute software instructions to process the codes to implement a desired functionality.
[0020] Buffer 130 receives an input signal on path 101, and provides a buffered output signal on path 134. Conversion block 140 performs analog to digital conversion of the signal on path 134, and contains sampling circuitry to store samples of signal 134 at time instances specified by one or more sampling clocks (not shown). Specifically, the sampling circuit contains at least one sampling capacitor and a switch (driven on or off by a sampling clock) on which charge corresponding to the magnitude of signal 134 is stored. Conversion block 140 provides digital codes representing the magnitudes of signal 134 on path 115.
[0021] Buffer 130 may be implemented as a source follower or emitter follower according to several aspects of the present invention. The features of the present invention will be clearer in comparison to a prior approach, and accordingly the prior approach is described next with respect to FIGS. 2 and 3 .
2. Prior Source/Emitter Follower Buffer
[0022] FIG. 2 is a circuit diagram illustrating the details of a prior source follower buffer. A portion of the sampling circuitry which may be contained within a conversion block (such as conversion block 140 of FIG. 1 ) is also shown in the Figure. Terminals 201 and 299 represent power and ground terminals respectively (reference potentials in general). Inductor 220 represents the inductance (which may be a distributed inductance on the path, rather than the lumped inductance shown in FIG. 2 ) due to bond wire and package lead (pin) through which an input signal is provided to buffer 130.
[0023] Prior buffer 200, which may be implemented in the place of buffer 130 of FIG. 1 , is shown containing N-type metal oxide semiconductor transistor (NMOS), and current source (or current sink) 240. The source, gate and drain terminals of NMOS 230 are indicated in FIG. 2 as S, G and D respectively. Input signal 202 is provided (via inductance 220) to the gate terminal of NMOS 230, and the buffered output 234 is provided at the source terminal of NMOS 230.
[0024] Current source 240 maintains a constant current from the source terminal of NMOS 230 to ground (node 299). Buffer 200 is, therefore, provided as a source follower buffer. When a bipolar junction transistor (BJT) (not shown) is implemented in place of NMOS 230, buffer 200 may be referred to as an emitter follower buffer, in which case the output is provided at the emitter terminal of the BJT.
[0025] Output 234 is sampled by the combination of switch 260 and sampling capacitor 270. Resistor 250 may represent the resistance of switch 260. Switch 260, which may be implemented as an analog (e.g., CMOS) switch, is closed during a sampling interval, and causes sampling capacitor 270 to store a charge representative of the magnitude of signal 234.
[0026] During a subsequent conversion interval, switch 260 is opened, and the sampled charge on (or voltage across) sampling capacitor 270 is available on path 267. Conversion circuitry (such as that which would be contained in conversion block 140 of FIG. 1 ) receives the sampled voltage on path 267, and generates a corresponding digital code representing the magnitude of signal 234.
[0027] FIG. 3 illustrates the circuit details of a prior buffer 300, in which current source 240 is implemented as a cascode circuit, shown containing transistors NMOS 310 and 320. Gate terminals 305 and 315 of NMOS 310 and 320 respectively receive a bias voltage.
[0028] In both of prior buffers 200 and 300, very little (or zero) current flows into the gate terminal of NMOS 230 due to the high gate impedance of NMOS 230, thereby isolating input 202 from the switching load represented by the combination of switch 260 and sampling capacitor 270. Switching transients which would otherwise (had input 202 been directly provided on path 234, without the use of buffer 200) have resulted due to inductance 220 and the switching load are prevented. Buffers 200 and 300, thus, shield the effects of the switching load from the input signal path.
[0029] However, the relation between output 234 and input 202 may not be linear. As is well known, current through NMOS 230 (drain current Id) has a square-law relation with respect to the gate-to-source voltage Vgs. Transconductance Gm (ΔId/ΔVgs) of NMOS 230 is dependent on the total current Id flowing through NMOS 230. Assuming zero current flows into the gate terminal of NMOS 230, the voltage at the gate terminal is the input voltage 202 (V202).
[0030] Drain current Id maybe expressed by the following equation:
Id=Iq+Isignal Equation 1
Id=Iq+Isignal Equation 1
[0031] wherein, Iq is the constant current flowing into the current source (240 in FIG. 2 or cascode current source formed by transistors 310 and 320 in FIG. 3 ), and
[0032] Isignal (signal-dependent current) is the current representing input signal 202, and flows on path 234.
[0033] As is well known in the relevant arts, Isignal (the signal dependant current) may cause the voltage drop (Vdrop) between the gate and source terminals of NMOS 230 to vary, depending on the value of Isignal.
[0034] Output voltage 234 (V234) is related to V202 by the following equation:
V234=V202−Vdrop Equation 2
V234=V202−Vdrop Equation 2
[0035] wherein, Vdrop is the voltage between the gate and source terminals of NMOS 230.
[0036] Vdrop may, in turn be expressed by the following equation:
Vdrop=V202−(Vt+V(V202)) Equation 3
Vdrop=V202−(Vt+V(V202)) Equation 3
[0037] wherein,
[0038] Vt is a constant voltage, and
[0039] V(V202) represents a voltage that is a function of input voltage V202 or Isignal.
[0040] Since Vdrop is not a constant, but varies depending on input signal 202, it may be observed from equation 2 above that the relation between output voltage V234 and input voltage V202 is not linear. As a result, output signal 234 (which is sampled by conversion circuitry within conversion block 140 of FIG. 1 ) may not be a correct representation of input signal 202, and thus cause the output digital code generated by switched-capacitor ADC 110 (FIG. 1 ) to contain errors.
[0041] The extent of non-linearity noted above is generally greater when transconductance Gm has a lower value. Although implementation of the transistors of FIGS. 2 and 3 as BJTs may cause a relatively smaller degree of non-linearity (due to the inherent larger values of transconductance of BJTs), even such smaller degrees of non-linearities may be unacceptable at least in some operational environments.
[0042] Several aspects of the present invention provide a source/emitter follower buffer with improved non-linearity, and thus better suited to driving switching loads, as described next with respect to an example embodiment.
3. Source/Emitter Follower Buffer with Improved Linearity
[0043] FIG. 4 is a circuit diagram of a source/emitter follower buffer in an embodiment of the present invention. Buffer 130 is shown containing transistors 410, 420 and 430. Although represented in FIG. 4 as MOS devices, transistors 410, 420 and 430 may be implemented as either MOS or BJT devices. Terminals 401 and 499 represent power and ground terminals respectively.
[0044] Transistors 410 and 420 are connected in a cascode configuration, and operate as a high impedance current source, similar to the combination of transistors 310 and 320 of FIG. 3 . Bias voltages 405 and 415 for transistors 410 and 420 respectively may be generated internal to buffer 130, and operate to set the value of respective currents through the transistors 410 and 420, as is well known in the relevant arts. Transistor 430 receives input signal 101 on its gate terminal, and provides a buffered output signal 134 on its source terminal.
[0045] Capacitor 440 is connected between input path 101 and node 421, and passes signal current (Is) representing variations in input voltage 101 directly to a switching load (which may be connected to path 134, but not shown). Capacitor 440, thus, reduces (or removes completely) flow of signal-dependant current through transistor 430, as described below.
[0046] The looking-in impedance at node 421 (looking into transistor 410) is very low. Denoting the current through transistor 420 as 1420, and signal current through capacitor 440 as Is, current through transistors 410 can be expressed by the following equation:
I410=I420−Is Equation 4
I410=I420−Is Equation 4
[0047] wherein, 1410 is the current through transistor 410 (current 1420 through transistor 420 being constant due to the current source configuration).
[0048] Denoting the current on output path 134 as I0, the current through transistor 430 is provided by the following equation:
I430=I420−Is+I0 Equation 5
I430=I420−Is+I0 Equation 5
[0049] When a load (such as capacitor 270 of FIG. 3 ) is connected to output 134, Is equals (or very nearly equals) I0, if capacitor 440 equals the load on output path 134. As a result most of signal current Is flows through output path 134. Therefore, from equation 5 above, current 1430 through transistor 430 equals 1420, which is a constant value.
[0050] Therefore, capacitor 440 provides signal current Is (or at least a large proportion of Is) directly to a switching load connected to path 134, and no (or very little) signal-dependant current flows through transistor 430.
[0051] As a result, signal-dependant change in transconductance Gm of transistor 430, and therefore changes in the voltage drop (Vdrop of equations 2 and 3) between the gate and source terminals of transistor 430 are prevented, or at least minimized. Hence, output 134 of buffer 130 of FIG. 4 varies linearly as input 101 varies, and is a more accurate representation of input 101.
[0052] Transistor 430 of buffer 130 of FIG. 4 may be viewed as providing an output voltage at the output (source) terminal/node that varies linearly with the input voltage, while capacitor 440 passes the current due to (or caused by) the input signal directly to the switching load.
[0053] Thus, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the source/emitter follower buffer is minimized. It is noted that when the switching load is disconnected from output path 134, current through transistor 430 may change. However, such change in the disconnected state may not be of concern.
[0054] As noted above, output transients that may be caused by inductance present in the input path because of a switching load are also prevented, due to the high input impedance at the gate terminal of transistor 430. Source/emitter follower buffer 130 can, therefore, support high input signal frequencies as well.
[0055] Further, as most of the signal current from the input (101) is provided by capacitor 440 directly to the output (and to the switching load), power consumed by buffer 130 (current drawn from power supply 401) is reduced.
[0056] Buffer 130 of FIG. 4 may be implemented in switched-capacitor ADC 110 of FIG. 1 , and enables switched-capacitor ADC 110 to provide digital codes which represent input signal 101 more accurately.
[0057] It should be appreciated that the specific type of transistors (NMOS, BJT etc.) noted above are merely by way of illustration. However, alternative embodiments using different configurations and transistors will be apparent to one skilled in the relevant arts by reading the disclosure provided herein. For example, the NMOS transistors may be replaced with PMOS (P-type MOS) transistors, while also interchanging the connections to power and ground terminals.
[0058] Accordingly, in the instant application, the power and ground terminals are referred to as reference potentials, the source (emitter) and drain (collector) terminals of transistors (though which a current path is provided when turned on and an open path is provided when turned off) are termed as current terminals, and the gate (base) terminal is termed as a control terminal.
[0059] Furthermore, though the terminals are shown with direct connections to various other terminals, it should be appreciated that additional components (as suited for the specific environment) may also be present in the path, and accordingly the connections may be viewed as being electrically coupled to the same connected terminals.
[0060] In addition, the circuit topology of FIG. 4 is merely representative. Various modifications, as suited for the specific environment, without departing from the scope and spirit of several aspects of the present invention, will be apparent to one skilled in the relevant arts by reading the disclosure provided herein.
[0061] While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims
What is claimed is:
1. A buffer comprising:
an input terminal;
an output terminal;
a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the input terminal, and wherein the second passive electrode of the first transistor is coupled to the output terminal;
a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor receives a first bias voltage, and wherein the first passive electrode of the second transistor is coupled to the output terminal;
a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor receives a second bias voltage, and wherein the second passive electrode of the second transistor is coupled to the first passive electrode of the third transistor; and
a capacitor that is coupled between the input terminal and the first passive electrode of the third transistor.
2. The buffer of claim 1, wherein the third transistor is an NMOS transistor, wherein the first and second passive electrodes of the third transistor are its drain and source, respectively.
3. The buffer of claim 2, wherein the first transistor is an NMOS transistor, wherein the first and second passive electrodes of the first transistor are its drain and source, respectively.
4. The buffer of claim 3, wherein the second transistor is an NMOS transistor, wherein the first and second passive electrodes of the second transistor are its drain and source, respectively.
5. The buffer of claim 2, wherein the first transistor is an NPN transistor, wherein the first and second passive electrodes are the collector and emitter, respectively.
6. The buffer of claim 5, wherein the second transistor is an NPN transistor, wherein the first and second passive electrodes are the collector and emitter, respectively.
7. The buffer of claim 2, wherein the buffer further comprises analog- to-digital conversion circuitry that is coupled to the output terminal.
8. A buffer comprising:
a input terminal;
an output terminal;
a follower transistor that is coupled to the input terminal;
a first bias transistor that is coupled to the follower transistor and the output terminal and that receives a first bias voltage;
a second bias transistor that is coupled between the first bias transistor and ground and that receives a second bias voltage; and
a capacitor that is coupled between the input terminal and a node between the first bias transistor and the second bias transistor.
9. The buffer of claim 8, wherein the second bias transistor further comprises an NMOS transistor that receives the second bias voltage at its gate and that is coupled to the output terminal at its drain.
10. The buffer of claim 9, wherein the second bias transistor is coupled to ground at its source.
11. The buffer of claim 10, wherein the follower transistor further comprises an NMOS transistor that is coupled to the input terminal at its gate.
12. The buffer of claim 11, wherein the first bias transistor is an NMOS transistor that is coupled to the source of the follower transistor at its drain, that receives the first bias voltage at its gate, and that is coupled to the output terminal at its drain.
13. The buffer of claim 9, wherein the follower transistor is an NPN transistor that is coupled to the input terminal at its base.
14. The buffer of claim 13, wherein the first bias transistor is an NPN transistor that receives the first bias voltage at its base, that is coupled to the emitter of the follower transistor at its collector, and that is coupled to the output terminal at its collector.
15. The buffer of claim 9, wherein the buffer further comprises analog- to-digital conversion circuitry that is coupled to the output terminal.
16. An analog-to-digital converter comprising: a buffer having:
an input terminal that receives an input signal;
an output terminal; a first NPN transistor that is coupled to the input terminal at its base, that receives a supply voltage at its collector, and that is coupled to the output terminal at its emitter;
a second NPN transistor that is coupled to output terminal at its collector and that receives a first bias voltage at its base;
an NMOS transistor that is coupled to the emitter of the second NPN transistor at its drain, that receives a second bias voltage at its gate, and that is coupled to ground at its source; and
a capacitor that is coupled between the input terminal and the drain of the NMOS transistor; and
analog-to-digital conversion circuitry that is coupled to the output terminal of the buffer.
Patent Citations (46)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4628274(A) | 1986-12-01 | Vittoz et al. | Examiner |
| US4877979(A) | 1989-10-01 | Sempel | Examiner |
| US5280511(A) | 1994-01-01 | Fujii et al. | Examiner |
| US5365199(A) | 1994-11-01 | Brooks | Examiner |
| US5696459(A) | 1997-12-01 | Neugebauer et al. | Examiner |
| US5701136(A) | 1997-12-01 | Huq et al. | Examiner |
| US5872473(A) | 1999-02-01 | Williams | Examiner |
| US6181314(B1) | 2001-01-01 | Nakajima et al. | Examiner |
| US6225859(B1) | 2001-05-01 | Irvine et al. | Examiner |
| US6243066(B1) | 2001-06-01 | Murakami et al. | Examiner |
| US6255852(B1) | 2001-07-01 | Forbes et al. | Examiner |
| US6313819(B1) | 2001-11-01 | Maekawa et al. | Examiner |
| US6433592(B1) | 2002-08-01 | Ehben | Examiner |
| US6727729(B2) | 2004-04-01 | Brooks et al. | Examiner |
| US6756817(B2) | 2004-06-01 | Tamura et al. | Examiner |
| US6876235(B2) | 2005-04-01 | Li et al. | Examiner |
| US6927618(B2) | 2005-08-01 | Kimura et al. | Examiner |
| US6933874(B2) | 2005-08-01 | Pentakota | Applicant |
| US7049848(B2) | 2006-05-01 | Brooks et al. | Examiner |
| US7075342(B2) | 2006-07-01 | Nishimura | Examiner |
| US7123250(B2) | 2006-10-01 | Kimura et al. | Examiner |
| US7126377(B2) | 2006-10-01 | Brooks et al. | Examiner |
| US7158065(B2) | 2007-01-01 | Lin et al. | Examiner |
| US7221194(B2) | 2007-05-01 | Lin et al. | Examiner |
| US7327168(B2) | 2008-02-01 | Kimura | Examiner |
| US7339402(B2) | 2008-03-01 | Alenin et al. | Examiner |
| US7378883(B1) | 2008-05-01 | Hsueh | Examiner |
| US7405720(B2) | 2008-07-01 | Nakajima et al. | Examiner |
| US7411430(B2) | 2008-08-01 | Cheng et al. | Examiner |
| US7429873(B2) | 2008-09-01 | Peschke | Examiner |
| US7525386(B2) | 2009-04-01 | Kim et al. | Examiner |
| US7528643(B2) | 2009-05-01 | Kimura | Examiner |
| US7545184(B2) | 2009-06-01 | Sun | Examiner |
| US7557848(B2) | 2009-07-01 | Koyama | Examiner |
| US7586375(B2) | 2009-09-01 | Kim et al. | Examiner |
| US7636075(B2) | 2009-12-01 | Shin | Examiner |
| US7652702(B2) | 2010-01-01 | Murakami et al. | Examiner |
| US7675315(B2) | 2010-03-01 | Tadeparthy | Examiner |
| US2003/0174009(A1) | 2003-09-01 | Kimura et al. | Examiner |
| US2004/0095159(A1) | 2004-05-01 | Kimura | Examiner |
| US2004/0178831(A1) | 2004-09-01 | Li et al. | Examiner |
| US2004/0183772(A1) | 2004-09-01 | Nakajima et al. | Examiner |
| US2006/0152461(A1) | 2006-07-01 | Kida et al. | Examiner |
| US2007/0040591(A1) | 2007-02-01 | Yu et al. | Examiner |
| US2007/0090860(A1) | 2007-04-01 | Hsu | Examiner |
| US2007/0194809(A1) | 2007-08-01 | Tadeparthy | Examiner |