US 8,716,141 B2Grant

Electrode configurations for semiconductor devices

Issue Date:2014-05-06

•19 Claims

•16 Drawing Sheets

Abstract

A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.

Metadata

Assignee

Transphorm Inc.

Inventors

Yuvaraj Dora
Yifeng Wu

Application Information

Application Number:US 13/040,940

Filing Date:2011-03-04

Priority Date:2011-03-04

Art Unit:2898

Classifications

IPC:

H01L21/301H01L21/461H01L21/4763H01L21/283H01L21/285H01L29/20

Field of Search:

H01L 21/28H01L 21/283H01L 21/0254H01L 21/28581H01L 21/28264H01L 29/2003H01L 29/402

Patent Drawings (16 sheets)

Description

Technical Field

[0001] This invention relates to semiconductor electronic devices, specifically devices with electrodes connected to field plates.

Background

[0002] To date, modern power semiconductor diodes such as high-voltage P-I-N diodes, as well as power transistors such as power MOSFETs and Insulated Gate Bipolar Transistors (IGBT), have been typically fabricated with silicon (Si) semiconductor materials. More recently, silicon carbide (SiC) power devices have been researched due to their superior properties. III-Nitride (III-N) semiconductor devices are now emerging as an attractive candidate to carry large currents and support high voltages, and provide very low on resistance, high voltage device operation, and fast switching times. As used herein, the terms III-N or III-Nitride materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula Al_xIn_yGa_zN, where x+y+z is about 1.

[0003] Examples of III-N high electron mobility transistors (HEMTs) and III-N diodes, respectively, of the prior art are shown in FIGS. 1 and 2. The III-N HEMT of FIG. 1 includes a substrate 10, a III-N channel layer 11, such as a layer of GaN, atop the substrate, and a III-N barrier layer 12, such as a layer of Al_xGa_1-xN, atop the channel layer. A two-dimensional electron gas (2DEG) channel 19 is induced in the channel layer 11 near the interface between the channel layer 11 and the barrier layer 12. Source and drain contacts 14 and 15, respectively, form ohmic contacts to the 2DEG channel. Gate contact 16 modulates the portion of the 2DEG in the gate region, i.e., directly beneath gate contact 16. The III-N diode of FIG. 2 includes similar III-N material layers to those of the III-N HEMT of FIG. 1. However, the III-N diode of FIG. 2 only includes two contacts, an anode contact 27 and a cathode contact 28. The anode contact 27 is formed on the III-N barrier layer 12, and the cathode contact 28 is a single contact which contacts the 2DEG 19. The anode contact 27 is a Schottky contact, and the single cathode contact 28 is an ohmic contact. In FIG. 2, while there appears to be two cathode contacts, the two contacts are in fact electrically connected so as to form a single cathode contact 28.

[0004] Field plates are commonly used in III-N devices to shape the electric field in the high-field region of the device in such a way that reduces the peak electric field and increases the device breakdown voltage, thereby allowing for higher voltage operation. An example of a field plated III-N HEMT of the prior art is shown in FIG. 3. In addition to the layers included in the device of FIG. 1, the device in FIG. 3 includes a field plate 18 which is connected to gate 16, and an insulator layer 13, such as a layer of SiN, is between the field plate and the III-N barrier layer 12. Field plate 18 can include or be formed of the same material as gate 16. Insulator layer 13 can act as a surface passivation layer, preventing or suppressing voltage fluctuations at the surface of the III-N material adjacent to insulator layer 13.

[0005] Slant field plates have been shown to be particularly effective in reducing the peak electric field and increasing the breakdown voltage in III-N devices. A prior art III-N device similar to that of FIG. 3, but with a slant field plate 24, is shown in FIG. 4. In this device, gate 16 and slant field plate 24 are formed of a single electrode 29. Insulator layer 23, which can be SiN, is an electrode-defining layer that contains a recess which defines at least in part the shape of electrode 29. Electrode-defining layer 23 can also act as a surface passivation layer, preventing or suppressing voltage fluctuations at the surface of the III-N material adjacent to electrode-defining layer 23. The gate 16 and slant field plate 24 in this device can be formed by first depositing electrode-defining layer 23 over the entire surface of III-N barrier layer 12, then etching a recess through the electrode-defining layer 23 in the region containing gate 16, the recess including a slanted sidewall 25, and finally depositing electrode 29 at least in the recess and over the slanted sidewall 25. Similar slant field plate structures can be formed in III-N diodes. For example, a III-N diode similar to that of FIG. 2 can also include a slant field plate connected to the anode contact 27.

[0006] Slant field plates, such as field plate 24 in FIG. 4, tend to spread the electric fields in the device over a larger volume as compared to conventional field plates, such as field plate 18 in FIG. 3, which do not include a slanted portion. Hence, slant field plates tend to be more effective at reducing the peak electric field in the underlying device, thereby allowing for larger operating and breakdown voltages.

[0007] While slant field plates are desirable for many applications, they can be difficult to fabricate reproducibly. Field plate structures that can provide adequate suppression of peak electric fields and can be fabricated reproducibly are therefore desirable.

Summary

[0008] In one aspect, a III-N semiconductor device is described that includes an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.

[0009] In another aspect, a III-N semiconductor device is described that includes an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. At least one of the steps in the sidewall has a first surface that is substantially parallel to the surface of the III-N material structure and a second surface that is slanted, the second surface forming an angle of between 5 and 85 degrees with the surface of the III-N material structure.

[0010] Devices described herein may include one or more of the following features. The III-N material structure can include a first III-N material layer, a second III-N material layer, and a 2DEG channel induced in the first III-N material layer adjacent to the second III-N material layer as a result of a compositional difference between the first III-N material layer and the second III-N material layer. The first III-N material layer can include GaN. The second III-N material layer can include AlGaN or AlInGaN. A third III-N material layer can be included between the first III-N material layer and the second III-N material layer. The third III-N material layer can include AlN. The first III-N material layer and the second III-N material layer can be group III-face or [0 0 0 1] oriented or group-III terminated semipolar layers, and the second III-N material layer can be between the first III-N material layer and the electrode-defining layer. The first III-N material layer and the second III-N material layer can be N-face or [0 0 0 1 bar] oriented or nitrogen-terminated semipolar layers, and the first III-N material layer can be between the second III-N material layer and the electrode-defining layer.

[0011] The recess can extend through the entire thickness of the electrode-defining layer, or into the III-N material structure, or through the 2DEG channel. The recess can extend at least 30 nanometers into the III-N material structure. The recess can extend partially through the thickness of the electrode-defining layer. The electrode-defining layer can have a composition that is substantially uniform throughout. The electrode-defining layer can include SiN_x. A thickness of the electrode-defining layer can be between about 0.1 microns and 5 microns.

[0012] A dielectric passivation layer can be included between the III-N material structure and the electrode-defining layer, the dielectric passivation layer directly contacting a surface of the III-N material adjacent to the electrode. The dielectric passivation layer can include SiN_x. The dielectric passivation layer can be between the electrode and the III-N material structure, such that the electrode does not directly contact the III-N material structure. An additional insulating layer can be included between the dielectric passivation layer and the electrode-defining layer. The additional insulating layer can include AlN. The additional insulating layer can be less than about 20 nanometers thick.

[0013] The extending portion of the electrode can function as a field plate. The electrode can be an anode, and the device can be a diode. The electrode can be a gate, and the device can be a transistor. The device can be an enhancement-mode device, or a depletion-mode device, or a high-voltage device. The effective angle can be about 20 degrees or less, and a breakdown voltage of the device can be about 100V or larger. The effective angle can be about 10 degrees or less, and a breakdown voltage of the device can be about 300V or larger.

[0014] At least one of the steps can have a first surface that is substantially parallel to the surface of the III-N material structure and a second surface that is substantially perpendicular to the surface of the III-N material structure. At least one of the steps can have a first surface that is substantially parallel to the surface of the III-N material structure and a second surface that is slanted, the second surface forming an angle of between 5 and 85 degrees with the surface of the III-N material structure. The extending portion can directly contact the sidewall.

[0015] In another aspect, a method of forming a III-N device is described that includes forming an electrode-defining layer having a thickness on a surface of a III-N material structure, and patterning a masking layer over the electrode-defining layer, the masking layer including an opening having a width. The method also includes etching the electrode-defining layer to form a recess therein, the recess having a sidewall which comprises a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. The method further includes removing the masking layer, and forming an electrode in the recess, the electrode including an extending portion over the sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The etching step includes a first procedure and a second procedure, the first procedure comprising removing a portion of the electrode-defining layer, and the second procedure comprising removing a portion of the masking layer without entirely removing the masking layer. The second procedure causes an increase in the width of the opening in the masking layer.

[0016] Methods described herein can include one or more of the following. The first procedure can be performed a second time after the second procedure has been performed. The second procedure can be performed a second time after the first procedure has been performed a second time. The masking layer can include photoresist, and the photoresist in the masking layer can be redistributed prior to performing the etching step. Redistributing the photoresist can include thermally annealing the photoresist. Redistributing the photoresist can cause the masking layer to have slanted sidewalls adjacent to the opening. The etching step can result in the recess extending through the entire thickness of the electrode-defining layer. The etching step can be a first etching step, and the method can further comprise a second etching step resulting in the recess further extending into the III-N material structure.

[0017] The device can further comprise an additional dielectric layer having a thickness between the electrode-defining layer and the III-N material structure. The etching step can result in the recess further extending through the entire thickness of the additional dielectric layer. The electrode can be an anode, and the III-N device can be a diode. The electrode can be a gate, and the III-N device can be a transistor. The etching step can result in the sidewall forming an effective angle of about 40 degrees or less relative to the surface of the III-N material structure. The etching step can result in at least one of the steps in the sidewall having a first surface that is substantially parallel to the surface of the III-N material structure and a second surface that is slanted, the second surface forming an angle of between 5 and 85 degrees with the surface of the III-N material structure.

[0018] III-N devices which can be fabricated reproducibly, can support high voltages with low leakage, and at the same time can exhibit low on-resistance and high breakdown voltage, are described. Methods of forming the devices are also described. The III-N devices described herein can be transistors or diodes, and can be high-voltage devices suitable for high voltage applications. The details of one or more implementations of the invention are set forth in the accompanying drawings and description below. Other features and advantages of the invention will be apparent from the description and drawings, and from the claims.

Description of Drawings

[0019] FIG. 1 is a cross-sectional view of a III-N HEMT device of the prior art.

[0020] FIG. 2 is a cross-sectional view of a III-N diode of the prior art.

[0021] FIGS. 3-4 are cross-sectional views of III-N HEMT devices of the prior art.

[0022] FIG. 5 is a cross-sectional view of one implementation of a III-N diode.

[0023] FIG. 6 is a plan view of the electrode layout of a III-N diode.

[0024] FIG. 7 is a cross-sectional view of another implementation of a III-N diode.

[0025] FIG. 8 is a cross-sectional view of one implementation of a III-N HEMT device.

[0026] FIG. 9 is a cross-sectional view of another implementation of a III-N diode.

[0027] FIG. 10 is a cross-sectional view of another implementation of a III-N HEMT device.

[0028] FIGS. 11-20 illustrate a method of forming the III-N diode of FIG. 5.

[0029] Like reference symbols in the various drawings indicate like elements.

Detailed Description

[0030] Devices based on III-N heterostructures are described. An electrode of the device is designed such that the device can be fabricated reproducibly, can support high voltages with low leakage, and at the same time can exhibit low on-resistance. Methods of forming the devices are also described. The III-N devices described herein can, for example, be transistors or diodes, and can be high-voltage devices suitable for high voltage applications. In such a high-voltage diode, when the diode is reverse biased, the diode is at least capable of supporting all voltages less than or equal to the high-voltage in the application in which it is used, which for example may be 100V, 300V, 600V, 1200V, 1700V, or higher. When the diode is forward biased, it is able to conduct substantial current with a low on-voltage. The maximum allowable on-voltage is the maximum voltage that can be sustained in the application in which the diode is used. When a high voltage transistor is biased off (i.e., the voltage on the gate relative to the source is less than the transistor threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high-voltage in the application in which it is used. When the high voltage transistor is biased on (i.e., the voltage on the gate relative to the source is greater than the transistor threshold voltage), it is able to conduct substantial current with a low on-voltage. The maximum allowable on-voltage is the maximum voltage that can be sustained in the application in which the transistor is used.

[0031] Referring to FIG. 4, for a given thickness of the electrode-defining layer 23, the horizontal length of the region which the electric field is spread over, resulting from inclusion of the slant field plate 24, is largely determined by the angle 26 which the field plate forms with the surface 28 of the underlying III-N material structure. A smaller angle 26 results in a greater spreading of the electric fields, allowing for correspondingly larger operating and breakdown voltages of the device. For example, in a III-N device with an electrode-defining layer 23 which is about 0.85 microns thick, an angle of about 40 degrees or less may be required for reliable 50V or 100V operation, whereas an angle of about 10 degrees or less may be required for reliable 300V or 600V operation. However, it can be difficult to reproducibly fabricate slant field plates 24 with such small angles 26. A field plate structure which allows for comparable device operating and breakdown voltages but which can be fabricated reproducibly is necessary for large scale manufacturing.

[0032] As illustrated in FIGS. 5-10, the III-N devices described herein are transistors and diodes that each include an electrode-defining layer on top of a III-N material structure. The electrode-defining layer includes a recess, and an electrode is in the recess. The width at the top of the recess is greater than the width at the bottom of the recess. The electrode includes an extending portion which is over a portion of the electrode-defining layer and functions as a field plate. The electrode is deposited conformally in the recess in the electrode-defining region with the extending portion over a sidewall of the recess. Hence, the profile of the extending portion is at least partially determined by the profile of the sidewall. The sidewall of the recess underneath the extending portion of the electrode includes a plurality of steps. The sidewall forms an effective angle relative to the uppermost surface of the underlying III-N material structure. The effective angle can be small enough to allow for high voltage operation of the device, as required by the circuit application in which the device is used.

[0033] Referring to FIG. 5, a III-N diode includes a substrate 10, a first III-N layer 11 on top of the substrate, and a second III-N layer 12 on top of the first III-N layer. III-N layers 11 and 12 have different compositions from one another, the compositions selected such that a two-dimensional electron gas (2DEG) 19 (illustrated by a dashed line), i.e., a conductive channel, is induced in the first III-N layer 11 near the interface between the first and second III-N layers 11 and 12, respectively.

[0034] An electrode-defining layer 33 is formed over the second III-N layer 12, the electrode-defining layer 33 including a recess in which anode contact 39 is subsequently formed, extending through the entire thickness of the electrode-defining layer 33. The electrode-defining layer is typically between about 0.1 microns and 5 microns thick, such as about 0.85 microns thick. The electrode-defining layer 33 can have a composition that is substantially uniform throughout. The electrode-defining layer 33 is formed of an insulator, such as SiN_x. An anode contact 39 formed in the recess contacts the upper surface of the second III-N layer 12 in region 41 of the device. The anode contact 39 includes an extending portion 34, lying over a portion of the electrode-defining layer 33, that functions as a field plate. The anode contact 39 is deposited conformally in the recess in the electrode-defining layer 33 with the extending portion 34 over a sidewall 43 of the recess, the sidewall 43 extending from the portion of the electrode-defining layer 33 which is closest to region 41 (i.e., point 44) all the way to the point 45 at the top of the electrode-defining layer 33 just beyond where the electrode-defining layer 33 becomes substantially flat. Hence, the profile of the extending portion is at least partially determined by the profile of the sidewall 43. A single cathode contact 28 is formed which contacts the 2DEG 19 and is in close proximity to at least a portion of anode contact 39. The anode contact 39 is a Schottky contact, and the single cathode contact 28 is an ohmic contact.

[0035] As used herein, the term “single cathode contact” refers to either a single metallic contact which serves as a cathode, or to a plurality of contacts serving as cathodes which are electrically connected such that the electric potential at each contact is about the same, or is intended to be the same, during device operation. In the cross-sectional view of FIG. 5, while there appear to be two cathode contacts, the two contacts are in fact electrically connected so as to form a single cathode contact 28. This is shown more clearly in FIG. 6, which is a plan view diagram of the diode of FIG. 5. As used herein, two or more contacts or other elements are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other elements is about the same, or is intended to be the same, at all times during operation.

[0036] FIG. 6 is a plan view (top view) of an electrode configuration that may be used in the device of FIG. 5, and includes alternating “fingers” of cathode contact 28 and anode contact 39, connected to cathode and anode contact pads shown on the top and bottom, respectively, of FIG. 6. While the cross-sectional view of FIG. 5 only illustrates a single anode finger and two cathode fingers, additional cathode and anode fingers can be added, as shown in FIG. 6.

[0037] Referring back to FIG. 5, the diode may also optionally include a passivation layer 22 which contacts the III-N material surface at least between the anode and cathode contacts 39 and 28, respectively, and an additional dielectric layer 21 between the passivation layer 22 and the electrode-defining layer 33. The device may also include additional III-N layers (not shown), for example a III-N buffer layer between the first III-N layer 11 and the substrate 10, or a III-N layer such as AlN between the first III-N layer 11 and the second III-N layer 12.

[0038] The diode in FIG. 5 operates as follows. When the voltage at the anode contact 39 is less than that at the cathode contact 28, such that the Schottky junction between anode contact 39 and III-N layer 12 is reverse biased, the diode is in the OFF state with only a small reverse bias current flowing between the anode and cathode. Ideally, the reverse bias current is as small as possible. When the voltage at the anode contact 39 is greater than that at the cathode contact 28, the Schottky junction between anode contact 39 and III-N layer 12 is forward biased, and the diode is in the ON state. In this state, a substantial electron current flows from the cathode contact 28 predominantly through the 2DEG 19 and then through the forward biased Schottky junction into the anode contact 39. At least 99% of the total forward bias current flows from the anode to the cathode through the Schottky barrier and through the 2DEG channel. A small amount of leakage current can flow through other paths, such as along the surface of the device.

[0039] As stated earlier, III-N layers 11 and 12 have different compositions from one another. The compositions are selected such that the second III-N layer 12 has a larger bandgap than the first III-N layer 11, which helps enable the formation of 2DEG 19. If III-N layers 11 and 12 are composed of III-N material oriented in a non-polar or semi-polar orientation, then doping all or part of the second semiconductor layer 12 with an n-type impurity may also be required to induce the 2DEG 19. If the III-N layers 11 and 12 are oriented in a polar direction, such as the [0 0 0 1] (i.e., group III-face) orientation, then 2DEG 19 may be induced by the polarization fields without the need for any substantial doping of either of the III-N layers, although the 2DEG sheet charge concentration can be increased by doping all or part of the second III-N layer 12 with an n-type impurity. Increased 2DEG sheet charge concentrations can be beneficial in that they can reduce the diode on-resistance, but they can also lead to lower reverse breakdown voltages. Hence the 2DEG sheet charge concentration preferably is optimized to a suitable value for the application in which the diode is used.

[0040] III-N materials can be used for layers 11 and 12, the compositions of these layers being chosen such that the requirements for layers 11 and 12 are satisfied. As an example, III-N layer 11 can be GaN and III-N layer 12 can be AlGaN or AlInGaN, whereas layer 12 can be n-doped or can contain no significant concentration of doping impurities. In the case that layer 12 is undoped, the induced 2DEG results from the difference in polarization fields between layers 11 and 12. The III-N material configurations for the diode described above can also be used in a III-N HEMT device, as seen, for example, in FIGS. 1, 3, and 4. Hence, the diodes described herein can be integrated with III-N HEMT devices onto a single chip, thereby simplifying the fabrication process and reducing cost of circuits that require both diodes and HEMTs.

[0041] Substrate 10 can be any suitable substrate upon which III-N layers 11 and 12 can be formed, for example silicon carbide (SiC), silicon, sapphire, GaN, AlN, or any other suitable substrate upon which III-N devices can be formed. In some implementations, a III-N buffer layer (not shown) such as AlGaN or AlN is included between substrate 10 and semiconductor layer 11 to minimize material defects in layers 11 and 12.

[0042] The diode of FIG. 5 optionally includes a passivation layer 22 and an additional dielectric layer 21. Passivation layer 22, formed of an insulating dielectric material, such as SiN_x, atop the second III-N layer 12, maintains effective passivation of the uppermost III-N surface of the device. As used herein, a “passivation layer” refers to any layer or combination of layers grown or deposited on a surface of a semiconductor layer in a semiconductor device which can prevent or suppress voltage fluctuations at the surface during device operation, thereby preventing or suppressing dispersion. For example, a passivation layer may prevent or suppress the formation of surface/interface states at the uppermost III-N surface, or it may prevent or suppress the ability of surface/interface states to trap charge during device operation. Additional dielectric layer 21, which is optionally included between passivation layer 22 and electrode-defining layer 33, can simplify device fabrication by serving as an etch stop layer. Additional dielectric layer 21 can be formed of a material for which an etch chemistry exists that can etch the material of electrode-defining layer 33 but will not substantially etch the material of additional dielectric layer 21. Additionally, because the anode contact 39 is in contact with the underlying III-N materials, the recess in the electrode-defining layer 33 also extends entirely through the additional dielectric layer 21 and the passivation layer 22. In some implementations, passivation layer 22 and the additional dielectric layer 21 are omitted, and electrode-defining layer 33 maintains effective passivation of the uppermost III-N surface of the device.

[0043] Dispersion refers to a difference in observed current-voltage (I-V) characteristics when the device is operated under RF or switching conditions, as compared to when the device is operated under DC conditions. In III-N devices, effects such as dispersion are often caused by voltage fluctuations at uppermost III-N surfaces, the result of charging of the surface states during device operation. Accordingly, a passivation layer such as layer 22 prevents or suppresses dispersion by preventing or suppressing voltage fluctuations at the uppermost III-N surface.

[0044] Referring to the diode of FIG. 5, when passivation layer 22 is included, electrode-defining layer 33 in combination with passivation layer 22 maintains effective passivation of the uppermost III-N surface of the device. When an additional dielectric layer 21, such as AlN is included between the passivation layer 22 and electrode-defining layer 33, the additional dielectric layer 21 may need to be made thin enough, such as thinner than about 20 nm, thinner than about 10 nm, or thinner than about 5 nm, to ensure that effective passivation of the uppermost III-N surface is still maintained. Too thick an additional dielectric layer 21, such as greater than about 20 nm, can degrade the passivation effects of layers 22 and 33.

[0045] The portion 35 of anode contact 39 that is formed upon the surface of III-N layer 12 forms a Schottky contact to layer 12. Cathode contact 28 contacts the 2DEG 19 in ohmic region 49, forming a substantially ohmic contact. Cathode contact 28 can contact the 2DEG 19 in a number of ways. For example, a metal or combination of metals can be deposited in ohmic contact region 49 upon the surface of layer 12, followed by a thermal anneal which results in the deposited metal forming a metallic alloy with the underlying semiconductor material. Other methods by which the 2DEG can be contacted include, but are not limited to, ion implantation of n-type dopants into ohmic region 49, followed by a metal deposition atop this region, or by etching away the material in ohmic contact region 49 and regrowing n-type material, followed by a metal deposition atop this region. Anode contact 39 and cathode contact 28 may be any arbitrary shape, although the shape is ideally optimized to minimize the device area required for a given forward current.

[0046] The sidewall 43 (and hence also the extending portion 34 of the anode contact 39) includes a plurality of steps 46. FIG. 5 illustrates the case where three steps 46 are included. The horizontal width of the uppermost step is defined to be the average width of the other steps in the structure. Hence, the end of the sidewall 43 closest to the cathode contact 28 (i.e., the position of point 45) is defined to be at the end of the uppermost step. The sidewall 43 has an effective slope, which is equal to the slope of the dashed line 47 which passes through point 44 to point 45. As such, the sidewall 43 forms an effective angle 36 with the uppermost surface of the underlying III-N material structure.

[0047] For a given thickness of the electrode-defining layer 33, a smaller effective angle 36 tends to correspond to a smaller peak electric field in the underlying device. Hence, a smaller effective angle 36 tends to result in a device with a larger breakdown voltage and improved reliability at higher operating voltages. For example, a device designed to operate at a reverse bias of about 50V or 100V may require an effective angle 36 which is about 40 degrees or smaller. A device designed to operate at a reverse bias of about 200V may require an effective angle 36 which is about 20 degrees or smaller, and a device designed to operate at a reverse bias of about 300V or 600V may require an effective angle 36 which is about 10 degrees or smaller. While slant field plate structures with angles which are about 40 degrees or smaller tend to be difficult to manufacture reproducibly, especially as the electrode-defining layer 33 is made thicker, stepped field plate structures, such as those shown in FIG. 5, can be much more easily manufactured reproducibly with effective angles which are about 40 degrees or smaller.

[0048] As seen in FIG. 5, each of the steps 46 includes two surfaces (although the steps could each include additional surfaces). A first surface of the step 46 is substantially parallel to the uppermost surface of the III-N material structure, while a second surface is at an angle relative to the uppermost surface of the III-N material structure. The second surface of the step 46 can be substantially perpendicular to the uppermost surface of the III-N material structure, or the second surface can be slanted, for example forming an angle between about 5 degrees and 85 degrees with the uppermost surface of the III-N material structure. While it may be simpler to manufacture a step 46 where the second surface is substantially perpendicular to the uppermost surface of the III-N material structure, making the second surface slanted may be preferable, as this can further reduce the peak electric field in the underlying device, as well as allowing for a smaller effective angle 36 of the sidewall 43 relative to the uppermost surface of the III-N material structure.

[0049] Another implementation is shown in FIG. 7. The diode in FIG. 7 is similar to that of FIG. 5, but the recess in the electrode-defining layer 33 further extends into the III-N materials. As shown, the recess can extend at least through the 2DEG 19, such that the anode contact 39 is in direct contact with the first III-N layer 11 at the bottom of the recess. Furthermore, it has been found that the depth of the recess containing anode contact 39 in FIG. 7 (that is, its depth below the 2DEG 19) can control or vary shifts in the forward operating voltage V_on, and correspondingly the reverse bias current I_reverse, of the device. Changing the depth of the aperture modifies the electric field profile in the III-N materials near the portion of 2DEG 19 modulated by the voltage on the anode contact 39. A deeper recess reduces the peak electric field in the region near 2DEG 19 in much the same way as a conventional field plate, thereby leading to devices with higher forward operating voltages V_on, lower reverse bias currents I_reverse, and/or higher reverse breakdown voltages.

[0050] A III-N HEMT transistor which makes use of the stepped field plate structure of the diodes shown in FIGS. 5 and 7 to allow for high voltage operation as well as simplified and reproducible manufacturing procedures is shown in FIG. 8. As with the diodes of FIGS. 5 and 7, the III-N HEMT of FIG. 8 includes a substrate 10, a first III-N layer 11 on top of the substrate, and a second III-N layer 12 on top of the first III-N layer. III-N layers 11 and 12 have different compositions from one another, the compositions selected such that a two-dimensional electron gas (2DEG) 19 (illustrated by a dashed line), i.e., a conductive channel, is induced in the first III-N layer 11 near the interface between the first and second III-N layers 11 and 12, respectively. An electrode-defining layer 33 is formed over the second III-N layer, the electrode-defining layer 33 including a recess which extends through the entire thickness of the electrode-defining layer 33. The electrode-defining layer 33 is typically between about 0.1 microns and 5 microns thick, such as about 0.85 microns thick. The electrode-defining layer 33 can have a composition that is substantially uniform throughout. The electrode-defining layer 33 is formed of an insulator, such as SiN_x.

[0051] A gate 59 is formed in the recess. The gate 59 includes an active gate portion 61 in gate region 51 of the device, as well as an extending portion 54 which is over a portion of the electrode-defining layer in the drain access region 53, the extending portion 54 functioning as a field plate. The gate 59 is deposited conformally in the recess in the electrode-defining region with the extending portion over a sidewall 43 of the recess, the sidewall 43 extending from the portion of the electrode-defining layer 33 which is closest to region 51 (i.e., point 44) all the way to the point 45 at the top of the electrode-defining layer 33, just beyond where the electrode-defining layer 33 becomes substantially flat. Hence, the profile of the extending portion is at least partially determined by the profile of the sidewall 43. Source and drain contacts 14 and 15, respectively, are on opposite sides of the gate 59 and form ohmic contacts to the 2DEG channel 19. The device may also include additional III-N layers (not shown), for example a III-N buffer layer between the first III-N layer 11 and the substrate 10, or a III-N layer such as AlN between the first III-N layer 11 and the second III-N layer 12.

[0052] The III-N HEMT of FIG. 8 has a gate region 51, source and drain access regions 52 and 53, respectively, on opposite sides of the gate region, and ohmic regions 56. The source access region 52 is between the source contact 14 and portion 61 of the gate, and the drain access region 53 is between the drain contact 15 and portion 61 of the gate. As with the diodes of FIGS. 5 and 7, the III-N HEMT of FIG. 8 can also include a passivation layer 22 which contacts the III-N material surface at least in the access regions, and an additional dielectric layer 21 between the passivation layer 22 and the electrode-defining layer 33. However, as shown in FIG. 8, the recess in the electrode-defining layer 33 can extend through the entire thickness of the additional dielectric layer 21 but not through the passivation layer 22. Hence, passivation layer 22 can be between the III-N materials and portion 61 of the gate 59 in the gate region 51, thereby serving as a gate insulator. A gate insulator can help prevent gate leakage currents in the HEMT.

[0053] The III-N HEMT of FIG. 8 can be an enhancement-mode (i.e., normally off, with a threshold voltage greater than 0V) or a depletion-mode (i.e., normally on, with a threshold voltage less than 0V) device. Other configurations for the III-N HEMT of FIG. 8 are also possible. For example, in one implementation, the recess in the electrode-defining layer 33 only extends partially through the thickness of the electrode-defining layer 33, such that a portion of the electrode-defining layer 33 is between the III-N materials and portion 61 of the gate (not shown). In this case, electrode-defining layer 33 can also function as a gate insulator, and it may be possible to omit the passivation layer 22 and/or the additional dielectric layer 21. In another implementation, the recess in the electrode-defining layer 33 additionally extends through the entire thickness of the passivation layer 22, and the gate 59 directly contacts the underlying III-N material (not shown). In yet another implementation, the recess further extends into the III-N materials (not shown), such as through the 2DEG 19, as with the diode of FIG. 7. In the case where the recess extends through the 2DEG 19, the HEMT can be an enhancement-mode device.

[0054] More implementations of devices with stepped field plate structures are shown in FIGS. 9 and 10. FIG. 9 shows a cross-sectional view of a diode similar to the device in FIG. 5, but which is fabricated on III-N semiconductor material that is either oriented in the N-polar [0 0 0 1 bar] direction or is a nitrogen-terminated semipolar material. That is, the face of the III-N materials furthest from the substrate is either a [0 0 0 1 bar] face or is a nitrogen-terminated semipolar face. The device includes a substrate 200 which is suitable for growth of N-polar or semipolar III-N materials. Layer 201 is a buffer layer, such as GaN or AlN, which reduces the defect density in the overlying III-N material. In some cases, it is possible to omit layer 201 and grow III-N layer 204 directly on the substrate 200. The composition of III-N layers 204 and 202 are chosen such that a 2DEG 19 can be induced in layer 202 near the interface between layers 202 and 204. For example, layer 204 can be AlGaN or AlInGaN, and layer 202 can be GaN. An additional III-N layer (not shown), such as a layer of AlN, can be included between III-N layers 204 and 202. Electrode-defining layer 33 is similar to or the same as that used in the diode of FIG. 5. Anode contact 39, which is formed in the recess in the electrode-defining layer 33, contacts the surface of III-N layer 202 opposite the substrate 200. A single cathode contact 28 is formed which contacts the 2DEG 19 and is in close proximity to at least a portion of anode contact 39. The anode contact 39 is a Schottky contact, and the single cathode contact 28 is an ohmic contact. As in the diode of FIG. 5, a passivation layer 22, such as a layer of SiN_x, can be included on the uppermost surface of the III-N material structure, and an additional dielectric layer 21, such as a layer of AlN, can be included between the electrode-defining layer 33 and the passivation layer 22. Similarly to the diode of FIG. 7, the recess containing the anode contact 39 can also extend into the III-N material structure (not shown), for example extending through the 2DEG 19, and the anode contact 39 can contact III-N layer 204 at the bottom of the recess.

[0055] FIG. 10 shows a cross-sectional view of a III-N HEMT transistor similar to the device of FIG. 8, but which is fabricated on III-N semiconductor material that is either oriented in the N-polar [0 0 0 1 bar] direction or is a nitrogen-terminated semipolar material. The device includes a substrate 200 which is suitable for growth of N-polar or semipolar III-N materials. Layer 201 is a buffer layer, such as GaN or AlN, which reduces the defect density in the overlying III-N material. In some cases, it is possible to omit layer 201 and grow III-N layer 204 directly on the substrate 200. The composition of III-N layers 204 and 202 are chosen such that a 2DEG 19 can be induced in layer 202 near the interface between layers 202 and 204. For example, layer 204 can be AlGaN or AlInGaN, and layer 202 can be GaN. An additional III-N layer (not shown), such as a layer of AlN, can be included between III-N layers 204 and 202. Electrode-defining layer 33, which again includes a recess, is similar to or the same as that of FIG. 8. A gate 59 is formed in the recess. The gate 59 includes an active gate portion 61 in gate region 51 of the device, as well as an extending portion 54 which is over a portion of the electrode-defining layer in the drain access region 53, the extending portion 54 functioning as a field plate. The gate 59 is deposited conformally in the recess in the electrode-defining region with the extending portion over a sidewall 43 of the recess, the sidewall 43 extending from the portion of the electrode-defining layer 33 which is closest to region 51 (i.e., point 44) all the way to the point 45 at the top of the electrode-defining layer 33, just beyond where the electrode-defining layer 33 becomes substantially flat. Hence, the profile of the extending portion is at least partially determined by the profile of the sidewall 43. Source and drain contacts 14 and 15, respectively, are on opposite sides of the gate 59 and form ohmic contacts to the 2DEG channel 19.

[0056] As in the HEMT of FIG. 8, a passivation layer 22, such as a layer of SiN_x, can be included on the uppermost surface of the III-N material structure, and an additional dielectric layer 21, such as a layer of AlN, can be included between the electrode-defining layer 33 and the passivation layer 22. As shown in FIG. 10, the recess in the electrode-defining layer 33 can extend through the entire thickness of the additional dielectric layer 21 but not through the passivation layer 22, such that passivation layer 22 also serves as a gate insulator.

[0057] The III-N HEMT of FIG. 10 can be an enhancement-mode (i.e., normally off, with a threshold voltage greater than 0V) or a depletion-mode (i.e., normally on, with a threshold voltage less than 0V) device. Other configurations for the III-N HEMT of FIG. 10 are also possible. For example, in one implementation, the recess in the electrode-defining layer 33 only extends partially through the thickness of the electrode-defining layer 33, such that a portion of the electrode-defining layer 33 is between the III-N materials and portion 61 of the gate (not shown). In this case, electrode-defining layer 33 can also function as a gate insulator, and it may be possible to omit the passivation layer 22 and/or the additional dielectric layer 21. In another implementation, the recess in the electrode-defining layer 33 additionally extends through the entire thickness of the passivation layer 22, and the gate 59 directly contacts the underlying III-N material (not shown). In yet another implementation, the recess further extends into the III-N materials (not shown), such as through the 2DEG 19, as in the diode of FIG. 7.

[0058] A method of forming the device of FIG. 5 is illustrated in FIGS. 11-20. Referring to FIG. 11, III-N material layers 11 and 12 are formed on substrate 10, for example by metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Passivation layer 22, formed over the III-N material layers 11 and 12, is then deposited by methods such as MOCVD or plasma enhanced chemical vapor deposition (PECVD). Next, as seen in FIG. 12, a cathode contact 28 is formed which contacts the 2DEG 19 induced in the III-N material layers. Cathode contact 28 can be formed in a number of ways. For example, a metal or combination of metals can be deposited, for example by evaporation, sputtering, or CVD, in ohmic contact region 49 upon the surface of layer 12, followed by a thermal anneal which results in the deposited metal forming a metallic alloy with the underlying semiconductor material. Alternatively, n-type dopants can be ion implanted into ohmic region 49, followed by a metal deposition by evaporation, sputtering, or CVD, atop this region. Or the material in ohmic contact region 49 can be etched away, n-type material can be regrown in this region by MOCVD or MBE, and metal can then be deposited atop this region.

[0059] As seen in FIG. 13, the additional dielectric layer 21 and electrode-defining layer 33 are then deposited over passivation layer 22, for example by PECVD, sputtering, or evaporation. A recess is then etched through the electrode-defining layer, for example by reactive ion etching RIE or inductively coupled plasma (ICP) etching. The procedure for forming the recess is illustrated in FIGS. 14-19.

[0060] Referring to FIG. 14, a photoresist masking layer 71 is patterned on the electrode-defining 33 to have an opening 72. Patterning can be performed by standard lithography procedures. The photoresist in the masking layer 71 is then redistributed, for example by thermally annealing the structure, resulting in the photoresist profile shown in FIG. 15. The anneal is performed at a temperature that does not damage the photoresist layer 71 or any of the underlying layers. As illustrated in FIG. 15, following the redistribution of the photoresist, the photoresist masking layer has slanted sidewalls 73. The resulting profile of the photoresist layer 71 and the sidewalls 73 can be controlled by varying anneal conditions, such as anneal time, anneal temperature, and the chemistry of the ambient gas in which the anneal is performed. For example, a longer anneal time or a higher temperature may result in a smaller slope in the sidewalls 73.

[0061] Referring to FIG. 16, the recess in the electrode-defining layer 33 is then partially formed by performing a first etch employing an etch chemistry that etches both the photoresist in layer 71 and the material of the electrode-defining layer 33. For example, if the electrode-defining layer 33 is SiN_x, the first etch can be performed by Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP) etching using an etch chemistry that includes O₂and SF₆. In some implementations, the first etch is a substantially anisotropic etch.

[0062] As illustrated in FIG. 17, a second etch is then performed which etches the photoresist masking layer 71 without substantially etching the electrode-defining layer 33, thereby increasing the width of the opening 72. For example, if the electrode-defining layer 33 is SiN_x, the second etch can be performed by Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP) etching using an etch chemistry that includes only O₂. In some implementations, the second etch is a substantially isotropic etch. A third etch is then performed which, like the first etch, utilizes an etch chemistry that etches both the photoresist in layer 71 and the material of the electrode-defining layer 33, resulting in the profile of FIG. 18. The photoresist etch procedure, followed by the procedure for etching both layers 71 and 33, are then repeated multiple times, until the recess extends all the way through the electrode-defining layer 33, resulting in the aperture having a stepped sidewall. The photoresist masking layer 71 is then removed, for example by a solvent clean, resulting in the profile shown in FIG. 19. Additional dielectric layer 21 can be formed of a material that is not substantially etched by the etch procedure used to etch the recess in the electrode-defining layer 33.

[0063] Referring to FIG. 20, the portion of the additional dielectric layer 21 which is adjacent to the recess in electrode-defining layer 33 is then removed, for example by performing an etch which etches the material of the additional dielectric layer 21 but does not etch the material of electrode-defining layer 33 or passivation layer 22. For example, when layers 33 and 22 are both SiN_x, and layer 21 is AlN, the portion of layer 21 adjacent to the recess in electrode-defining layer 33 can be chemically etched in a base, such as a photoresist developer. Next, a portion of the passivation layer 22 adjacent to the recess is etched, for example by RIE or ICP etching, resulting in the structure of FIG. 20. Finally, electrode 39 is deposited conformally in the recess, for example by evaporation, sputtering, or CVD, and optionally the portion of layers 21 and 33 which are over the cathode contact 18 are removed, such as by chemical wet etching, or by RIE or ICP etching, resulting in the diode of FIG. 5.

[0064] The slanted angle of the sidewalls of each step structure in the recess through the electrode-defining layer 33 results from the slanted sidewall of the photoresist masking layer 71, as illustrated in FIG. 15. If a vertical sidewall is desired instead of a slanted sidewall for each step structure, then the photoresist redistribution procedure described above can be omitted, or altered to change the resulting photoresist profile.

[0065] The devices of FIGS. 7-10 can be formed using slightly modified versions of the methods described above. For example, the device of FIG. 7 can be formed using the procedures described above, with one additional step. Once the recess extends through the passivation layer 22 to the uppermost surface of the III-N materials, and prior to deposition of electrode 39, the structure can be etched using an etch chemistry that etches III-N materials at a higher etch rate than that of the materials used for electrode-defining layer 33 and passivation layer 22. For example, when electrode-defining layer 33 and passivation layer 22 are both SiN_x, a Cl₂RIE or ICP etch can be performed, resulting in the recess extending into the III-N material structure. The device of FIG. 8 can be formed using the procedures described above, with the exceptions that source and drain ohmic contacts 14 and 15, respectively, are formed in place of the cathode contact 18, and the step of etching the passivation layer 22 is omitted. The procedures for forming the devices of FIGS. 9 and 10 are the same as the procedures for forming those of FIGS. 5 and 8, respectively, with the exception that the III-N layers formed on the substrate in FIGS. 9 and 10 have a different crystallographic orientation as compared to the III-N layers formed on the substrate in FIGS. 5 and 8.

[0066] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. Features shown in each of the implementations may be used independently or in combination with one another. Accordingly, other implementations are within the scope of the following claims.

Claims

What is claimed is:

1. A method of forming a III-N device, comprising:

forming an electrode-defining layer having a thickness on a surface of a III-N material structure that has a 2DEG formed therein;

patterning a masking layer over the electrode-defining layer, the masking layer including an opening having a width;

performing an etching step, the etching step comprising etching the electrode-defining layer beneath the opening to form a recess therein, the recess having a sidewall which comprises a plurality of steps, a portion of the recess distal from the III-N material structure having a first width, and a portion of the recess proximal to the III-N material structure having a second width, the first width being larger than the second width;

removing the masking layer; and

forming an electrode in the recess, the electrode including an extending portion over the sidewall, a portion of the electrode-defining layer being between the extending portion and the III-N material structure; wherein

the etching step includes a first procedure and a second procedure, the first procedure comprising removing a portion of the electrode-defining layer, and the second procedure comprising removing a portion of the masking layer without entirely removing the masking layer and without substantially etching the electrode-defining layer, the second procedure causing an increase in the width of the opening in the masking layer,

wherein the masking layer comprises photoresist; wherein the method further comprises redistributing the photoresist in the masking layer prior to performing the etching step; and wherein redistributing the photoresist causes the masking layer to have slanted sidewalls adjacent to the opening.

2. The method of claim 1, wherein the first procedure is performed a second time after the second procedure has been performed.

3. The method of claim 2, wherein the second procedure is performed a second time after the first procedure has been performed a second time.

4. The method of claim 1, wherein redistributing the photoresist comprises thermally annealing the photoresist.

5. The method of claim 1, wherein the etching step results in the recess extending through the entire thickness of the electrode-defining layer.

6. The method of claim 5, wherein the etching step is a first etching step, the method further comprising performing a second etching step resulting in the recess further extending into the III-N material structure.

7. The method of claim 1, further comprising forming an additional dielectric layer having a thickness between the electrode-defining layer and the III-N material structure.

8. The method of claim 7, wherein the etching step results in the recess further extending through the entire thickness of the additional dielectric layer.

9. The method of claim 7, wherein the device further comprises a passivation layer having a thickness between the electrode-defining layer and the additional dielectric layer.

10. The method of claim 9, wherein the etching step results in the recess further extending through the entire thickness of the passivation layer.

11. The method of claim 1, wherein the electrode is an anode and the III-N device is a diode.

12. The method of claim 1, wherein the electrode is a gate, and the III-N device is a transistor.

13. The method of claim 1, wherein the etching step results in the sidewall forming an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.

14. The method of claim 1, wherein the etching step results in at least one of the steps in the sidewall having a first surface that is substantially parallel to the surface of the III-N material structure and a second surface that is slanted, the second surface forming an angle of between 5 and 85 degrees with the surface of the III-N material structure.

15. A method of forming a semiconductor device, comprising:

forming an electrode-defining layer having a thickness on a surface of a III-N semiconductor material structure that has a 2DEG formed therein;

patterning a photoresist layer over the electrode-defining layer, the photoresist layer including an opening having a width;

performing a first etch, the first etch comprising etching the electrode-defining layer beneath the opening to form a recess therein, the recess having a sidewall;

after etching the electrode-defining layer, performing a second etch which removes a portion of the masking layer without entirely removing the masking layer, the second etch increasing the width of the opening in the masking layer;

after performing the second etch, performing a third etch which etches more of the electrode-defining layer beneath the opening and extends the recess;

removing the photoresist layer; and

forming an electrode in the recess,

wherein the method further comprises redistributing the photoresist in the photoresist layer prior to performing the first etch; wherein redistributing the photoresist causes the masking layer to have slanted sidewalls adjacent to the opening.

16. The method of claim 15, wherein redistributing the photoresist comprises thermally annealing the photoresist.

17. The method of claim 15, wherein the first etch or the third etch results in the sidewall of the recess being a slanted sidewall.

18. The method of claim 15, wherein the second etch is a substantially isotropic etch.

19. The method of claim 15, wherein the second etch removes the portion of the masking layer without substantially etching the electrode-defining layer.

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Abstract