US 7,544,963 B2Grant
Binary group III-nitride based high electron mobility transistors
Issue Date:2009-06-09
•34 Claims
•7 Drawing Sheets
Abstract
Binary Group III-nitride high electron mobility transistors (HEMTs) and methods of fabricating binary Group III-nitride HEMTs are provided. In some embodiments, the binary Group III-nitride HEMTs include a first binary Group III-nitride barrier layer, a binary Group III-nitride channel layer on the first barrier layer; and a second binary Group III-nitride barrier layer on the channel layer. In some embodiments, the binary Group III-nitride HEMTs include a first AIN barrier layer, a GaN channel layer and a second AIN barrier layer.
Metadata
Assignee
- Cree, Inc.
Inventor
- Adam William Saxler
Application Information
Application Number:US 11/118,675
Filing Date:2005-04-29
Priority Date:2005-04-29
Art Unit:2895
Classifications
IPC:
H01L29/06H01L31/0328H01L31/0336H01L31/072H01L31/109
Patent Drawings (7 sheets)
Description
Field of the Invention
[0001] The present invention relates to semiconductor devices and, more particularly, to transistors that incorporate nitride-based active layers.
Background
[0002] Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide application in semiconductor devices for lower power and (in the case of Si) lower frequency applications. These, more familiar, semiconductor materials may not be well suited for higher power and/or high frequency applications, however, because of their relatively small bandgaps (e.g., 1.12 eV for Si and 1.42 for GaAs at room temperature) and/or relatively small breakdown voltages.
[0003] In light of the difficulties presented by Si and GaAs, interest in high power, high temperature and/or high frequency applications and devices has turned to wide bandgap semiconductor materials such as silicon carbide (2.996 eV for alpha SiC at room temperature) and the Group III nitrides (e.g., 3.36 eV for GaN at room temperature). These materials, typically, have higher electric field breakdown strengths and higher electron saturation velocities as compared to gallium arsenide and silicon.
[0004] A device of particular interest for high power and/or high frequency applications is the High Electron Mobility Transistor (HEMT), which, in certain cases, is also known as a modulation doped field effect transistor (MODFET). These devices may offer operational advantages under a number of circumstances because a two-dimensional electron gas (2DEG) is formed at the heterojunction of two semiconductor materials with different bandgap energies, and where the smaller bandgap material has a higher electron affinity. The 2DEG is an accumulation layer in the undoped (“unintentionally doped”), smaller bandgap material and can contain a very high sheet electron concentration in excess of, for example, 1013 carriers/cm2. Additionally, electrons that originate in the wider-bandgap semiconductor transfer to the 2DEG, allowing a high electron mobility due to reduced ionized impurity scattering.
[0005] This combination of high carrier concentration and high carrier mobility can give the HEMT a very large transconductance and may provide a strong performance advantage over metal-semiconductor field effect transistors (MESFETs) for high-frequency applications.
[0006] High electron mobility transistors fabricated in the gallium nitride/aluminum gallium nitride (GaN/AlGaN) material system have the potential to generate large amounts of RF power because of the combination of material characteristics that includes the aforementioned high breakdown fields, their wide bandgaps, large conduction band offset, and/or high saturated electron drift velocity. A major portion of the electrons in the 2DEG is attributed to polarization in the AlGaN. HEMTs in the GaN/AlGaN system have already been demonstrated. U.S. Pat. Nos. 5,192,987 and 5,296,395 describe AlGaN/GaN HEMT structures and methods of manufacture. U.S. Pat. No. 6,316,793, to Sheppard et al., which is commonly assigned and is incorporated herein by reference, describes a HEMT device having a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an aluminum gallium nitride barrier layer on the gallium nitride layer, and a passivation layer on the aluminum gallium nitride active structure.
Summary of the Invention
[0007] Some embodiments of the present invention provide high electron mobility transistors (HEMTs) and methods of fabricating HEMTs that include a first binary Group III-nitride barrier layer, a binary Group III-nitride channel layer on the first barrier layer; and a second binary Group 111-nitride barrier layer on the channel layer. In some embodiments, the first barrier layer comprises a doped binary Group III-nitride region adjacent the binary Group III-nitride channel layer. An undoped binary Group III-nitride layer may also be disposed between the doped binary Group III-nitride region and the channel layer.
[0008] In further embodiments of the present invention, the second barrier layer comprises a first doped binary Group III-nitride region adjacent the binary Group III-nitride channel layer. An undoped binary Group III-nitride layer may be disposed between the first doped binary Group III-nitride region of the second barrier layer and the channel layer.
[0009] In some embodiments of the present invention, the first barrier layer comprises an AIN layer, the channel layer comprises a GaN layer and the second barrier layer comprises an AIN layer. The first barrier layer may have a thickness of from about 1 nm to about 1 mm, the channel layer may have a thickness of from about 0.3 nm to about 10 nm and the second barrier layer may have a thickness of from about 0.5 nm to about 50 nm.
[0010] In additional embodiments of the present invention, a first doped AlN layer is disposed between the first AlN barrier layer and the GaN channel layer. The first doped AlN layer may comprise a Si, Ge and/or Sn doped AlN layer. The first doped AlN layer may have a thickness of from about 0.2 nm to about 10 nm. The first doped AlN layer may have a dopant concentration of from about 1×1017 cm−3 to about 1×1021 cm−3. A first undoped AlN layer may also be disposed between the first doped AlN layer and the GaN channel layer. The first undoped AlN layer may have a thickness of from about 0.3 nm to about 5 nm.
[0011] In further embodiments, a second doped AlN layer is disposed between the second AlN barrier layer and the GaN channel layer. The second doped AlN layer may comprise a Si, Ge and/or Sn doped AlN layer. The second doped AlN layer may have a thickness of from about 0.2 nm to about 10 nm. The second doped AlN layer may have a dopant concentration of from about 1×1017 cm−3 to about 1×1021 cm−3. A second undoped AlN layer may be disposed between the second doped AlN layer and the GaN channel layer. The second undoped AlN layer may have a thickness of from about 0.3 nm to about 5 nm.
[0012] In still further embodiments of the present invention, a GaN layer is provided on the second AlN barrier layer opposite the GaN channel layer. The GaN layer on the second AlN barrier layer opposite the GaN channel layer may have a thickness of from about 0.3 nm to about 100 nm and, in some embodiments, less than about 10 nm.
[0013] In some embodiments of the present invention, the first binary Group III-nitride barrier layer comprises AlN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises AlN. In other embodiments of the present invention, the first binary Group III-nitride barrier layer comprises GaN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises GaN. In still further embodiments of the present invention, the first binary Group III-nitride barrier layer comprises GaN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises AlN. In additional embodiments of the present invention, the first binary Group III-nitride barrier layer comprises AlN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises GaN.
[0014] In some embodiments of the present invention, the HEMT does not include a ternary or quaternary Group III-nitride layer in an active region of the HEMT.
Brief Description of the Drawings
[0015] FIG. 1 is a cross-section of a binary Group III-nitride based HEMT according to some embodiments of the present invention.
[0016] FIGS. 2A and 2B are cross-sections of binary GaN based HEMTs according to some embodiments of the present invention.
[0017] FIGS. 3A through 3H are graphs of carrier concentration and band diagrams from simulation models of transistors according to some embodiments of the present invention.
[0018] FIGS. 4A and 4B are cross-sections of binary GaN based HEMTs according to some embodiments of the present invention.
[0019] FIG. 5 is a cross-section of binary GaN based HEMTs according to some embodiments of the present invention.
Detailed Description of Embodiments of the Invention
[0020] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.
[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0022] It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Like numbers refer to like elements throughout the specification.
[0023] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
[0024] Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
[0025] Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have tapered, rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.
[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0027] It will also be appreciated by those of skill in the art that references to a structure or feature that is disposed “adjacent” another feature may have portions that overlap or underlie the adjacent feature.
[0028] Embodiments of the present invention provide binary nitride-based HEMTs such as Group III-nitride based devices. Binary Group III-nitride devices according to some embodiments of the present invention may have reducted or minimal alloy scattering as all of the layers of the active region of the device are binary Group III-nitrides. As used herein, the term “Group III nitride” refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, gallium (Ga), aluminum (Al) and/or indium (In). As is well understood by those in this art, the Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., InGaN), and quaternary compounds (AlInGaN). These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. Accordingly, formulas such as InxGa1-xN where 0≦x≦1 are often used to describe them.
[0029] Furthermore, as used herein, binary Group III nitrides refers to nitrogen and one of the Group III elements and the absence of other Group III elements intentionally incorporated into active layers of the Group III-nitride based device. In some embodiments of the present invention, a binary Group III-nitride compound has up to about 1% of a second Group III element without causing significant alloy scattering. For example, indium may be present in small amounts if it is used as a surfactant during growth of AlN or GaN. Accordingly, as will be understood by those of skill in the art in light of the present disclosure, references to binary Group III-nitride layers or regions includes non-ideal compounds. For example, an active layer of a device may be binary even if some of a third Group III element is present in the active layer, for example, through unintentional incorporation by contamination during fabrication. Active layers of a device are the layers of the device where the 2DEG is formed and layers disposed between the layers where the 2DEG is formed and the source, drain and/or gate contacts and/or contact layers (i.e. layers on which a contact is directly formed) of the device. Dopants, such as silicon may be incorporated in the layers that form the 2DEG while still providing binary Group III-nitride structures. In some embodiments of the present invention, non-Group III-nitride materials or ternary or quaternary compounds may be in layers between the layers that form the 2DEG and a substrate and/or in the substrate. For example, the substrate may be sapphire or SiC or graded transition layers may include AlGaN.
[0030] FIG. 1 illustrates a HEMT structure according to some embodiments of the present invention. As seen in FIG. 1 , a binary Group III-nitride channel layer 14, such as GaN, is provided on a first binary Group III-nitride barrier layer 12. A second binary Group III-nitride barrier layer 16 is provided on the channel layer 14. The first barrier layer 12 and the second barrier layer 16 may be, for example, AlN and may be undoped or include doped regions adjacent the channel layer 14.
[0031] Furthermore, the first barrier layer 12, channel layer 14 and the second barrier layer 16 may be deposited and/or grown by MOCVD or by other techniques known to those of skill in the art, such as MBE or HVPE. Techniques for fabricating AlN substrates, AlN layers, GaN layers and other binary Group III-nitride layers are known to those of skill in the art and need not be described further herein.
[0032] In particular embodiments of the present invention, the first barrier layer 12 may be provided as a substrate, such as an AlN substrate. Alternatively, the structure of FIG. 1 may be formed on a substrate. For example, the first barrier layer 12 may be provided by an AlN buffer layer on an AlN substrate. The AlN buffer layer may provide higher purity and/or quality AlN than is provided by the AlN substrate. Furthermore, use of an AlN substrate may eliminate a thermal barrier at the interface between the first barrier layer 12 and the substrate and AlN homoepitaxially grown on an AlN substrate may have a lower dislocation density that AlN grown heteroepitaxially. Suitable AlN substrates for use as the first barrier layer 12 or on which an AlN buffer layer may be provided as the first barrier layer 12 are available, for example, from Crystal IS, Inc. of Watervliet, N.Y.
[0033] Although AlN may be used as a substrate material, in which case the first barrier layer 12 may be provided by the substrate, embodiments of the present invention may utilize any suitable substrate, such as sapphire, silicon carbide, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP and the like. In some embodiments, an appropriate buffer layer also may be formed. For example, a nucleation layer and/or epitaxial lateral overgrowth (ELO) growth may be used in growing the binary Group III-nitride layers on a substrate such as silicon carbide or sapphire. Furthermore, growth conditions may be controlled to control the dislocation density and/or strain of the Group III-nitride layers so as to provide substantially relaxed layers.
[0034] The first barrier layer 12 may be an undoped or unintentionally doped binary Group III nitride, such as AlN. In some embodiments, the first barrier layer 12 may include a thick semi-insulating or insulating layer with an undoped, unintentionally and/or doped region adjacent the channel layer 14. For example, in some embodiments of the present invention, the first barrier layer 12 may be from about 1 nm to about 1 mm thick AlN. In some embodiments of the present invention, the first barrier layer 12 is about 1 μm thick.
[0035] In some embodiments of the present invention, the channel layer 14 is a binary Group III-nitride, such as GaN or InN, provided that the energy of the conduction band edge of the channel layer 14 is less than the energy of the conduction band edge of the second barrier layer 16 at the interface between the channel and second barrier layer. In particular, the channel layer 14 may have a bandgap that is less than the bandgap of the second barrier layer 16 and the channel layer 14 may also have a larger electron affinity than the second barrier layer 16. The channel layer 14 may be undoped or unintentionally doped and may be grown to a thickness of from about 3 to about 100 Å. For example, in some embodiments, the channel layer 14 may have a thickness of less than about 4 nm. The channel layer 14 should be sufficiently thin so that a two-dimensional hole gas does not form at the junction with the first barrier layer 12 and so that the channel layer 14 remains coherently strained.
[0036] In particular embodiments of the present invention, the second barrier layer 16 is thick enough and/or has a high enough doping to induce a significant carrier concentration at the interface between the channel layer 14 and the second barrier layer 16. As discussed above, the second barrier layer 16 may be a binary Group III-nitride, such as AlN, and has a bandgap larger than that of the channel layer 14 and a smaller electron affinity than the channel layer 14. The second barrier layer 16 may, for example, be from about 0.5 nm to about 50 nm thick, but is not so thick as to cause cracking or substantial defect formation therein. The second barrier layer 16 may be thicker than 50 nm if contact recesses are utilized. In certain embodiments of the present invention, the second barrier layer 16 is undoped or unintentionally doped.
[0037] Source and drain ohmic contacts 20 and 22 are provided on the second barrier layer 16 and a gate contact 24 is disposed between the source and drain contacts 20 and 22. Suitable ohmic contact materials may include, for example, Ti, Al, Ni, and/or Au. A very high anneal temperature may be used or a thin second barrier layer 16 may be used to provide a good ohmic contact. Furthermore, ion implantation (e.g., Si) and annealing and/or contact recesses may also be used to improve the quality of the ohmic contacts. Suitable gate materials may depend on the composition of the cap layer, however, in certain embodiments, conventional materials capable of making a Schottky contact to a nitride based semiconductor material may be used, such as Ni, Pt, NiSix, Cu, Pd, Cr, W and/or WSiN.
[0038] Embodiments of the present invention have been described above with reference to a binary Group III-nitride first barrier layer, a binary Group III-nitride channel layer and a binary Group III-nitride second barrier layer. In some embodiments of the present invention, the transistors have a GaN channel layer. For example, in FIG. 2A a GaN channel layer is provided between AlN layers, thus providing an AlN/GaN/AlN structure. In other embodiments of the present invention, an InN channel layer may be provided. Thus, for example, structures such as an AlN/InN/AlN, a GaN/InN/GaN, a GaN/InN/AlN or an AlN/InN/GaN structure may be provided while still being within the scope of some embodiments of the present invention. AlN/InN/GaN structures may be strain balanced if thicknesses of the layers are properly chosen and may have a very large 2DEG comparable to AlN/GaN structures.
[0039] FIG. 2A is a schematic diagram of HEMTs according to further embodiments of the present invention. As seen in FIG. 2A , a doped layer 130 is provided on a first AlN barrier layer 112. A GaN channel layer 114 is provided on the doped layer 130. The doped layer 130 may, in some embodiments, be provided as a doped AlN layer, a doped GaN layer and/or a delta-doped layer of, for example, Si, Ge and/or Sn, at the interface between the GaN channel layer 114 and the AlN barrier layer 112. The doped layer 130, for example a delta-doped layer, may provide a sheet charge density of from about 1×1012 cm−2 to about 1×1014 cm−2. A second AlN barrier layer 116 is provided on the GaN channel layer 114. The first AlN barrier layer 112 may be provided as described above with reference to the first barrier layer 12. The GaN layer 114 may be provided as described above with reference to the channel layer 14. The second AlN barrier layer 116 may be provided as described above with reference to the second barrier layer 116. Source and drain ohmic contacts 20 and 22 may be provided on the second barrier layer 116 and a gate contact 24 may be disposed between the source and drain contacts 20 and 22 as described above. Furthermore, the second AlN barrier layer 116 can be made thick if the first AlN barrier layer 112 is substantially relaxed (as in a substrate or thick epitaxial layer) so the GaN channel layer 114 is coherently strained to AlN. This is in contrast to AlN grown on substantially relaxed GaN where the AlN thickness may be limited.
[0040] In some embodiments of the present invention, the doped layer 130 may be doped with Si, Ge, and/or Sn and may have a dopant concentration of from about 1×1017 cm−3 to about 1×1021 cm−3. Doping beneath the channel layer 114 may be beneficial for Al polar devices due to band bending in the GaN channel layer 114 making it higher energy. In particular, however the doped layer 130 is provided (e.g., a doped GaN layer or a doped AlN layer), the dopant concentration may be light enough and the doped layer 130 thin enough so that all or substantially all of the electrons transfer to the GaN channel (e.g., no unintentional n-type layer is formed in the doped region) but should be thick enough and doped heavily enough so that the desired amount of charge is present in the channel. In particular embodiments of the present invention, the doped layer 130 may be from about 0.3 nm to about 5 nm thick.
[0041] Optionally, a GaN layer 117 may be provided on the second AIN barrier layer 116. The GaN layer 117 may increase the barrier to the surface or modify surface states. The GaN layer 117 may be doped or delta-doped at the GaN/AIN interface to reduce energy barrier to surface and reduce or minimize the effect on 2DEG density and reduce or prevent a 2D hole gas from forming. An optional AlInGaN or graded layer may, instead be provided on the second AIN barrier layer 116 provided the second AiN barrier layer 116 is sufficiently thick such that electrons in the channel do not significantly extend beyond the AIN barrier layer 116.
[0042] FIG. 2B illustrates further embodiments of the present invention that include an undoped AlN layer 140 may be disposed between the doped layer 130 and the GaN channel layer 114. In some embodiments of the present invention, the undoped AlN layer 140 may be from about 0.3 nm to about 5 nm thick. The undoped AlN layer 140 may space the doped layer 130 from the channel layer 114 to reduce and/or minimize ionized impurity scattering.
[0043] While embodiments of the present invention are illustrated in FIGS. 2A and 2B as including doped and/or undoped layers on one side of the channel layer 114, doped and/or undoped layers may also be included on the other side of the channel layer 114 as illustrated in Figures 4A and 4B or both sides of the channel layer 114 as illustrated in Figure 5 . Such layers may be provided as described above with reference to FIGS. 2A and 2B .
[0044] A passivation layer (not shown) may also be provided on the structures of FIGS. 1 , 2A and 2B. In certain embodiments of the present invention, the passivation layer may be silicon nitride, silicon dioxide, an ONO structure and/or an oxynitride. Furthermore, the passivation layer may be a single or multiple layers of uniform and/or non-uniform composition. Such passivation layer, however, may be unnecessary in light of the robustness of AlN as the outermost layer of the device.
[0045] Embodiments of the present invention utilizing AlN as the second barrier layer at the surface may have a chemically robust surface and may be substantially relaxed in strain if the first barrier layer is also substantially relaxed as for a substrate or thick epitaxial layer. Thus, the AlN second barrier layer may be grown to relatively large thicknesses provided the GaN channel layer is grown coherently. A GaN layer sandwiched between two AlN layers may have a high electric field resulting in a large barrier to electrons entering the first AlN barrier layer assuming Al polar material. AlN substrates typically have a higher thermal conductivity than GaN and low dislocation density. AlN buffer layers are expected to have substantially different trap levels than GaN buffers, possibly resulting in improved reliability.
[0046] FIGS. 3A through 3H are graphs of carrier concentration and band diagrams from simulation models of transistors according to some embodiments of the present invention. In the simulations reflected in FIGS. 3A through 3H , the binary Group III-nitrides are idealized and are modeled as having no impurities other than dopants. These simulations are not meant to be exact but are provided to illustrate possible trends and to estimate properties of different designs. Accordingly, these graphs are provided as a rough estimate of possible characteristics of the modeled device structures but are only as accurate as the underlying assumptions and models. Accordingly, the properties of actual devices may differ from those illustrated in FIGS. 3A through 3H .
[0047] FIG. 3A illustrates a modeled band diagram and electron concentration for a binary Group III-nitride HEMT with an AlN substrate, a 1 nm thick AlN layer doped with Si with a dopant concentration of 1×1020 cm−3 between the substrate and the channel layer, a 20 nm thick GaN channel layer and a 1 nm thick AlN layer. FIG. 3B illustrates a modeled band diagram and electron concentration for a binary Group III-nitride HEMT with an AlN substrate, a 1 nm thick AlN layer doped with Si with a dopant concentration of 1×1020 cm−3 between the substrate and the channel layer, a 2 nm thick GaN channel layer, a 10 nm thick AlN layer and a 1 nm thick GaN layer.
[0048] FIG. 3C illustrates a modeled band diagram and electron concentration for a binary Group III-nitride HEMT with an AlN substrate, a 1 nm thick AlN layer doped with Si with a dopant concentration of 1×1020 cm−3 between the substrate and the channel layer, a 2 nm thick GaN channel layer and a 10 nm thick AlN layer on the channel layer. As seen in FIG. 3C , the configuration of FIG. 3C is predicted to have a higher peak electron concentration than either of the configurations of FIGS. 3A and 3B . FIGS. 3B and 3C illustrate the difference between a GaN cap layer and no GaN cap layer. The GaN cap appears to provide a larger barrier but a lower 2DEG density.
[0049] FIG. 3D illustrates a modeled band diagram and electron concentration for a binary Group III-nitride HEMT with an AlN substrate, a 5 nm thick AlN layer doped with Si with a dopant concentration of 3×1019 cm−3 between the substrate and the channel layer, a 2 nm thick GaN channel layer and a 10 nm thick AlN layer on the channel layer. As seen in FIG. 3D , the configuration of FIG. 3D is predicted to have a higher peak electron concentration than either of the configurations of FIGS. 3A and 3B and about the same or slightly higher than the peak electron concentration predicted for the structure of FIG. 3C but more band bending that the structure of FIG. 3C in the bottom AlN.
[0050] FIG. 3E illustrates a modeled band diagram and electron concentration for a binary Group III-nitride HEMT with an AlN substrate, a 5 nm thick AlN layer doped with Si with a dopant concentration of 3×1016 cm−3 between the substrate and the channel layer, a 2 nm thick GaN channel layer and a 10 nm thick AlN layer on the channel layer. As seen in FIG. 3E , the configuration of FIG. 3E is predicted to have a lower peak electron concentration than the configuration of FIG. 3D but less band bending in the bottom AlN.
[0051] FIG. 3F illustrates a modeled band diagram and electron concentration for a binary Group III-nitride HEMT with an AlN substrate, a 5 nm thick AlN layer doped with Si with a dopant concentration of 3×1019 cm−3 and a 2 nm thick undoped AlN layer between the substrate and the channel layer, a 2 nm thick GaN channel layer and a 10 nm thick AlN layer on the channel layer. As seen in FIG. 3F , the configuration of FIG. 3F is predicted to have about the same peak electron concentration as the configuration of FIG. 3D but more band bending in the bottom AlGaN.
[0052] FIG. 3G illustrates a modeled band diagram and electron concentration for a binary Group III-nitride HEMT with an AlN substrate, a 1 nm thick AlN layer doped with Si with a dopant concentration of 1×1020 cm−3, a 2 nm thick GaN channel layer and a 1 nm thick AlN layer on the channel layer. The structure of FIG. 3G is similar to the structure of FIG. 3A except that it has less band bending due to the thinner GaN layer. The thinner GaN is less likely to lead to the formation of a 2D hole gas at the interface between the first AlN barrier and the GaN channel. While a larger 2DEG is predicted for the thicker GaN layer, a 2D hole gas is predicted for the thicker GaN layer.
[0053] FIG. 3H illustrates a modeled band diagram and electron concentration for a binary Group III-nitride HEMT with an AlN substrate, a 1 nm thick AlN layer doped with Si with a dopant concentration of 1×1020 cm−3, a 2 nm thick GaN channel layer and a 5 nm thick AlN layer on the channel layer. As seen in FIG. 3G , the configuration of FIG. 3G is predicted to have a slightly lower peak electron concentration than the configuration of FIG. 3H with the thicker AlN barrier layer.
[0054] In comparison to the structure of FIG. 3H , the structure of FIG. 3C may provide a slight increase in 2DEG density as the AlN thickness is increased for this model.
[0055] Table 1 below is a summary of the characteristics and properties of the structures simulated in FIGS. 3A through 3H .
[0056]
In general, a thicker top AlN, higher sheet doping density and no GaN cap are predicted to lead to higher electron density in the GaN channel layer.
| GaN cap | AIN cap | GaN channel | AIN spacer | doped AIN | sheet electron | |||
|---|---|---|---|---|---|---|---|---|
| thickness | thickness | thickness | thickness | thickness | doped AIN | sheet doping | density in GaN by | |
| Figure | (nm) | (nm) | (nm) | (nm) | (nm) | density (cm−3) | density (cm−2) | model (cm−2) |
| 3A | 0 | 1 | 5 | 0 | 1 | 1E+20 | 1E+13 | 1.7E+13 |
| 3B | 1 | 10 | 2 | 0 | 1 | 1E+20 | 1E+13 | 7.9E+12 |
| 3C | 0 | 10 | 2 | 0 | 1 | 1E+20 | 1E+13 | 2.1E+13 |
| 3D | 0 | 10 | 2 | 0 | 5 | 3E+19 | 1.5E+13 | 2.6E+13 |
| 3E | 0 | 10 | 2 | 0 | 5 | 3E+16 | 1.5E+10 | 1.2E+13 |
| 3F | 0 | 10 | 2 | 2 | 5 | 3E+19 | 1.5E+13 | 2.6E+13 |
| 3G | 0 | 1 | 2 | 0 | 1 | 1E+20 | 1E+13 | 1.2E+13 |
| 3H | 0 | 5 | 2 | 0 | 1 | 1E+20 | 1E+13 | 2.0E+13 |
In general, a thicker top AlN, higher sheet doping density and no GaN cap are predicted to lead to higher electron density in the GaN channel layer.
[0057] While embodiments of the present invention have been described herein with reference to particular HEMT structures, the present invention should not be construed as limited to such structures. For example, additional layers may be included in the HEMT device while still benefiting from the teachings of the present invention. In some embodiments, insulating layers such as SiN or an ONO structure may be deposited for making a MISHEMT and/or passivating the surface. The additional layers may also include a compositionally graded transition layer or layers.
[0058] Also, other structures, such as recessed or “T” gate structures, regrown contact regions or the like may also be provided. Accordingly, some embodiments of the present invention provide binary Group III-nitride embodiments of structures such as those described in, for example, U.S. Pat. No. 6,316,793 and U.S. Patent Publication No. 2002/0066908A1 filed Jul. 12, 2001 and published Jun. 6, 2002, for “ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME,” U.S. Pat. No. 6,849,882 to Smorchkova et al., entitled “GROUP-III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER”, U.S. patent application Ser. No. 10/617,843 filed Jul. 11, 2003 for “NITRIDE-BASED TRANSISTORS AND METHODS OF FABRICATION THEREOF USING NON-ETCHED CONTACT RECESSES,” U.S. patent application Ser. No. 10/772,882 filed Feb. 5, 2004 for “NITRIDE HETEROJUNCTION TRANSISTORS HAVING CHARGE-TRANSFER INDUCED ENERGY BARRIERS AND METHODS OF FABRICATING THE SAME,” U.S. patent application Ser. No. 10/897,726, filed Jul. 23, 2004 entitled “METHODS OF FABRICATING NITRIDE-BASED TRANSISTORS WITH A CAP LAYER AND A RECESSED GATE,” U.S. patent application Ser. No. 10/849,617, filed May 20, 2004 entitled “METHODS OF FABRICATING NITRIDE-BASED TRANSISTORS HAVING REGROWN OHMIC CONTACT REGIONS AND NITRIDE-BASED TRANSISTORS HAVING REGROWN OHMIC CONTACT REGIONS,” U.S. patent application Ser. No. 10/849,589, filed May 20, 2004 and entitled “SEMICONDUCTOR DEVICES HAVING A HYBRID CHANNEL LAYER, CURRENT APERTURE TRANSISTORS AND METHODS OF FABRICATING SAME,” U.S. Patent Publication No. 2003/0020092 filed Jul. 23, 2002 and published Jan. 30, 2003 for “INSULATING GATE ALGAN/GAN HEMT”, U.S. patent application Ser. No.10/996,249, filed Nov. 23, 2004 and entitled “CAP LAYERS AND/OR PASSIVATION LAYERS FOR NITRIDE-BASED TRANSISTORS, TRANSISTOR STRUCTURES AND METHODS OF FABRICATING SAME,” U.S. patent application Ser. No. 11/080,905, filed Mar. 15, 2005 and entitled “GROUP III NITRIDE FIELD EFFECT TRANSISTORS (FETs) CAPABLE OF WITHSTANDING HIGH TEMPERATURE REVERSE BIAS TEST CONDITIONS,” U.S. patent application Ser. No. 11/005,107, filed Dec. 6, 2004 and entitled “HIGH POWER DENSITY AND/OR LINEARITY TRANSISTORS,” and U.S. patent application Ser. No. 11/005,423, filed Dec. 6, 2004 and entitled “FIELD EFFECT TRANSISTORS (FETs) HAVING MULTI-WATT OUTPUT POWER AT MILLIMETER-WAVE FREQUENCIES,” the disclosures of which are incorporated herein as if described in their entirety. Embodiments of the present invention may also be utilized with HEMT structures such as described in, for example, Yu et al., “Schottky barrier engineering in III-V nitrides via the piezoelectric effect,” Applied Physics Letters, Vol. 73, No. 13, 1998, or in U.S. Pat. No. 6,584,333 filed Jul. 12, 2001, for “ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME,” the disclosures of which are incorporated herein by reference as if set forth fully herein.
[0059] In the drawings and specification, there have been disclosed typical embodiments of the invention, and, although specific terms have been employed, they have been used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
That which is claimed is:
1. A high electron mobility transistor (HEMT), comprising:
a first binary Group III-nitride barrier layer;
a binary Group III-nitride channel layer on the first barrier layer;
a second binary Group III-nitride barrier layer on the channel layer, wherein the first barrier layer comprises a doped binary Group III-nitride region; and
an undoped binary Group III-nitride layer disposed between the doped binary Group III-nitride region and the channel layer.
2. The HEMT of claim 1 wherein the first barrier layer comprises an AIN layer, the channel layer comprises a GaN layer and the second barrier layer comprises an AIN layer.
3. The HEMT of claim 2, wherein the first barrier layer has a thickness of from about 1 nm to about 1 mm, the channel layer has a thickness of from about 0.3 nm to about 10 nm and the second barrier layer has a thickness of from about 0.5 nm to about 50 nm.
4. The HEMT of claim 2, further comprising a GaN layer on the second AIN barrier layer opposite the GaN channel layer.
5. The HEMT of claim 4, wherein the GaN layer on the second AIN barrier layer opposite the GaN channel layer has a thickness of from about 0.3 nm to about 10 nm.
6. The HEMT of claim 4, wherein the GaN layer on the second AIN barrier layer opposite the GaN channel layer is doped or delta doped at an interface between the GaN layer and the second AIN barrier layer.
7. The HEMT of claim 1, wherein the first binary Group III-nitride barrier layer comprises AIN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises AIN.
8. The HEMT of claim 1, wherein the first binary Group III-nitride barrier layer comprises GaN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises GaN.
9. The HEMT of claim 1, wherein the first binary Group III-nitride barrier layer comprises GaN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises AIN.
10. The HEMT of claim 9, wherein GaN, InN and AIN layers are strain balanced.
11. The HEMT of claim 10, further comprising a GaN cap layer on the AIN layer.
12. The HEMT of claim 1, wherein the first binary Group III-nitride barrier layer comprises AIN, the binary Group III-nitride channel layer on the first barrier layer comprises InN and the second binary Group III-nitride barrier layer on the channel layer comprises GaN.
13. The HEMT of claim 1, wherein the HEMT does not include a ternary or quaternary Group III-nitride layer in an active region of the HEMT.
14. A high electron mobility transistor (HEMT), comprising:
a first binary Group III-nitride barrier layer;
a binary Group III-nitride channel layer on the first barrier layer; and
a second binary Group III-nitride barrier layer on the channel layer, wherein the first barrier layer comprises a doped binary Group III-nitride region, wherein the second barrier layer comprises a first doped binary Group III-nitride region on the binary Group III-nitride channel layer opposite the first barrier layer.
15. The HEMT of claim 14, further comprising an undoped binary Group III-nitride layer disposed between the first doped binary Group III-nitride region and the channel layer.
16. A high electron mobility transistor (HEMT). comprising:
a first binary Group III-nitride barrier layer;
a binary Group III-nitride channel layer on the first barrier layer;
a second binary Group III-nitride barrier layer on the channel layer, wherein the second barrier layer comprises a first doped binary Group III-nitride region on the binary Group III-nitride channel layer opposite the first barrier layer; and
an undoped binary Group III-nitride layer disposed between the first doped binary Group III-nitride region and the channel layer.
17. A high electron mobility transistor (HEMT), comprising:
a first binary Group III-nitride barrier layer;
a binary Group III-nitride channel layer on the first barrier layer;
a second binary Group III-nitride barrier layer on the channel layer, wherein the first barrier layer comprises an AIN layer, the channel layer comprises a GaN layer and the second barrier layer comprises an AIN layer; and
a first doped AIN layer disposed between the first AIN barrier layer and the GaN channel layer.
18. The HEMT of claim 17, wherein the first doped AIN layer comprises a Si doped AIN layer.
19. The HEMT of claim 17, wherein the first doped AIN layer has a thickness of from about 0.2 nm to about 10 nm.
20. The HEMT of claim 17, wherein the first doped AIN layer has a dopant concentration of from about 1×1017 cm−3 to about 1×1021 cm−3.
21. The HEMT of claim 17, further comprising a first undoped AIN layer disposed between the first doped AIN layer and the GaN channel layer.
22. The HEMT of claim 21, wherein the first undoped AIN layer has a thickness of from about 0.3 nm to about 5 nm.
23. The HEMT of claim 17, further comprising a second doped AIN layer disposed between the second AIN barrier layer and the GaN channel layer.
24. The HEMT of claim 23, wherein the second doped AIN layer comprises a Si doped AIN layer.
25. The HEMT of claim 23, wherein the second doped AIN layer has a thickness of from about 0.2 nm to about 10 nm.
26. The HEMT of claim 23, wherein the second doped AIN layer has a dopant concentration of from about 1×1017 cm−3 to about 1×1021 cm−3.
27. The HEMT of claim 23, further comprising a second undoped AIN layer disposed between the second doped AIN layer and the GaN channel layer.
28. The HEMT of claim 27, wherein the second undoped AIN layer has a thickness of from about 0.3 nm to about 5 nm.
29. A high electron mobility transistor (HEMT), comprising:
a first binary Group III-nitride barrier layer;
a binary Group III-nitride channel layer on the first barrier layer;
a second binary Group III-nitride barrier layer on the channel layer, wherein the first barrier layer comprises an AIN layer, the channel layer comprises a GaN layer and the second barrier layer comprises an AIN layer; and
a doped AIN layer disposed between the second AIN barrier layer and the GaN channel layer.
30. The HEMT of claim 29, wherein the doped AIN layer comprises a Si doped AIN layer.
31. The HEMT of claim 29, wherein the doped AIN layer has a thickness of from about 0.2 mu to about 10 nm.
32. The HEMT of claim 29, wherein the doped AIN layer has a dopant concentration of from about 1×1017 cm−3 to about 1×1021 cm−3.
33. The HEMT of claim 29, further comprising an undoped AIN layer disposed between the doped AIN layer and the GaN channel layer.
34. The HEMT of claim 33, wherein the undoped AIN layer has a thickness of from about 0.3 nm to about 5 nm.
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