US 7,709,269 B2Grant
Methods of fabricating transistors including dielectrically-supported gate electrodes
Issue Date:2010-05-04
•24 Claims
•10 Drawing Sheets
Abstract
Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and second openings. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. Related devices and fabrication methods are also discussed.
Metadata
Assignee
- Cree, Inc.
Inventors
- Richard Peter Smith
- Scott T. Sheppard
Application Information
Application Number:US 11/493,069
Filing Date:2006-07-26
Priority Date:2006-01-17
Art Unit:2813
Classifications
IPC:
H01L21/338
Patent Drawings (10 sheets)
Description
Cross-Reference to Related Application
[0001] The present application is a continuation-in-part of U.S. patent application Ser. No. 11/333,726 filed Jan. 17, 2006, now U.S. Pat. No. 7,592,211 entitled METHODS OF FABRICATING TRANSISTORS INCLUDING SUPPORTED GATE ELECTRODES AND RELATED DEVICES, the disclosure of which is hereby incorporated by reference as if set forth fully herein.
Field of the Invention
[0002] The present invention relates to semiconductor devices, and, more particularly, to methods of fabricating transistors and related devices.
Background of the Invention
[0003] Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide application in semiconductor devices for lower power and, in the case of Si, lower frequency applications. However, these more familiar semiconductor materials may not be well suited for higher power and/or high frequency applications, for example, due to their relatively small bandgaps (e.g., 1.12 eV for Si and 1.42 for GaAs at room temperature) and/or relatively small breakdown voltages.
[0004] In light of the difficulties presented by Si and GaAs, interest in high power, high temperature and/or high frequency applications and devices has turned to wide bandgap semiconductor materials such as silicon carbide (2.996 eV for alpha SiC at room temperature) and the Group III nitrides (e.g., 3.36 eV for GaN at room temperature). These materials, typically, may have higher electric field breakdown strengths and higher electron saturation velocities as compared to gallium arsenide and/or silicon.
[0005] A device of particular interest for high power and/or high frequency applications is the High Electron Mobility Transistor (HEMT), which is also known as a modulation doped field effect transistor (MODFET). In a HEMT device, a two-dimensional electron gas (2DEG) may be formed at the heterojunction of two semiconductor materials with different bandgap energies. The smaller bandgap material may have a higher electron affinity than the wider bandgap material. The 2DEG is an accumulation layer in the undoped (“unintentionally doped”) smaller bandgap material, and can contain a relatively high sheet electron concentration, for example, in excess of 1013 carriers/cm2. Additionally, electrons that originate in the wider bandgap semiconductor may transfer to the 2DEG, allowing a relatively high electron mobility due to reduced ionized impurity scattering. This combination of relatively high carrier concentration and relatively high carrier mobility can give the HEMT a relatively large transconductance, and may provide a performance advantage over metal-semiconductor field effect transistors (MESFETs) for high-frequency applications.
[0006] High electron mobility transistors fabricated in the gallium nitride/aluminum gallium nitride (GaN/AlGaN) material system can generate large amounts of RF power due to a combination of material characteristics, such as relatively high breakdown fields, relatively wide bandgaps, relatively large conduction band offset, and/or relatively high saturated electron drift velocity. A major portion of the electrons in the 2DEG may be attributed to polarization in the AlGaN.
[0007] HEMTs in the GaN/AlGaN system have already been demonstrated. For example, U.S. Pat. Nos. 5,192,987 and 5,296,395 describe AlGaN/GaN HEMT structures and methods of manufacture. In addition, U.S. Pat. No. 6,316,793, to Sheppard et al., which is commonly assigned and incorporated by reference herein, describes a HEMT device having a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an aluminum gallium nitride barrier layer on the gallium nitride layer, and a passivation layer on the aluminum gallium nitride active structure. Moreover, U.S. Patent Application Publication No. US2005/0170574 to Sheppard et al., which is also commonly assigned and incorporated by reference herein, describes a HEMT device including a protective layer and/or a low damage recess fabrication technique which may reduce damage to the semiconductor in the gate region of the transistor that may occur during an anneal of ohmic contacts of the device.
[0008] One step in the fabrication of HEMT devices is the formation of the gate electrode. Conventional methods of gate electrode formation may include depositing a dielectric, etching through the dielectric using a mask and/or other sacrificial layer, and depositing a T-shaped gate electrode (referred to as a “T-gate”) into the etched portion of the dielectric. However, in such conventional methods, gaps may be formed between the edges of the dielectric and the gate electrode, due to isotropy of the dielectric etch. This may be detrimental to device operation, as the unpassivated semiconductor surface exposed by the gap may cause current collapse and/or drift in the device. In addition, although a passivation layer may be formed in the gap after formation of the gate, the passivation properties of such a post-gate passivation layer may be inferior to that of the initial pre-gate dielectric. This may be due to the fact that the pre-gate dielectric can be formed at relatively high temperatures, which may not be feasible once the gate metallization has been deposited.
[0009] Accordingly, other methods of gate electrode formation have been developed to prevent formation of such a gap. For example, the mask and/or other sacrificial layer may be removed from the dielectric prior to formation of the gate electrode in the etched portion of the dielectric. As such, the gate electrode may completely fill the etched portion of the dielectric, and “wings” or sidelobes of the gate electrode may be formed directly on the dielectric surface. Such a gate electrode is referred to as a dielectrically-supported T-gate, or a “gamma” gate. However, because portions of the dielectric may be sandwiched between the sidelobes and the active channel, gate-drain capacitance (cgd) and/or gate-source capacitance (cgs) may be increased, which may detrimentally affect device performance.
Summary of the Invention
[0010] According to some embodiments of the present invention, a method of fabricating a transistor may include forming a protective layer having a first opening extending therethrough. A dielectric layer may be formed on the protective layer. The dielectric layer may have a second opening extending therethrough that is wider than the first opening. A gate electrode may be formed in the first and second openings such that a first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening, and a second portion of the gate electrode laterally extends beyond the first portion on portions of the dielectric layer outside the second opening.
[0011] In some embodiments, the dielectric layer may have a lower dielectric index than the protective layer. For example, the dielectric layer may be an oxide layer. More particularly, the dielectric layer may be a high-temperature oxide (HTO) layer, and the protective layer may be a high-purity nitride (HPN) layer. For instance, the protective layer may be stoichiometric silicon nitride, and the dielectric layer may be silicon dioxide.
[0012] In other embodiments, the dielectric layer may be a high-quality oxide layer. The high-quality oxide layer may have a dielectric index of less than about 1.5.
[0013] In some embodiments, the dielectric layer may have a thickness greater than that of the protective layer. For example, the dielectric layer may have a thickness of about 500 Angstroms (Å) to about 3000 Å, and the protective layer may have a thickness of about 200 Å to about 2000 Å. The thickness and/or the dielectric index of the dielectric layer may be sufficient to reduce the gate-to-drain and/or gate-to-source capacitance of the device.
[0014] In other embodiments, forming the dielectric layer may include depositing an oxide layer on the protective layer using a chemical vapor deposition (CVD) process. The oxide layer may be deposited at a temperature of greater than about 500° C.
[0015] In some embodiments, forming the dielectric layer having the second opening extending therethrough may include forming the dielectric layer on the protective layer including a recess extending therethrough. The recess may expose a portion of the protective layer. The recess in the dielectric layer may be widened to define the second opening. The second opening may expose the first opening, and may expose surface portions of the protective layer on opposite sides of the first opening.
[0016] In other embodiments, the protective layer and the dielectric layer may be formed of different materials. Accordingly, prior to widening the recess in the dielectric layer, the protective layer may be patterned using the dielectric layer as a mask to form the first opening extending through the protective layer.
[0017] In some embodiments, the recess in the dielectric layer may be widened by symmetrically expanding the recess in the dielectric layer so that the second opening and the first opening are self-aligned. For example, the recess may be symmetrically expanded by etching the dielectric layer using wet oxide etchant that is selective with respect to the protective layer, such as a buffered oxide etchant (BOE).
[0018] In other embodiments, the method of fabricating the transistor may include forming a channel layer, and forming a barrier layer on the channel layer. The protective layer may be formed on the barrier layer. The gate electrode may be formed extending through the first opening in the protective layer to contact the barrier layer. A junction between the channel layer and the barrier layer may define a heterojunction.
[0019] In some embodiments, first and second ohmic contact regions may be formed on the barrier layer adjacent to and spaced apart from the protective layer so that the protective layer is between the first and second ohmic contact regions. More particularly, the dielectric layer and the protective layer may be patterned to expose first and second portions of the barrier layer. After patterning the dielectric layer and the protective layer, the first and second ohmic contact regions may be respectively formed on the first and second portions of the barrier layer adjacent to and spaced apart from the patterned protective layer. First and second ohmic metal regions may be annealed to form the first and second ohmic contacts.
[0020] In other embodiments, before forming the dielectric layer, the protective layer may be patterned to expose the first and second portions of the barrier layer. The dielectric layer may be formed on the protective layer and on the first and second portions of the barrier layer. The dielectric layer may be patterned to define first and second recesses therein respectively exposing the first and second portions of the barrier layer. In addition, the first and second recesses in the dielectric layer may be symmetrically expanded using a wet oxide etchant, such as a buffered oxide etchant (BOE).
[0021] In some embodiments, the dielectric layer may be patterned to expose first and second portions of the protective layer. The protective layer may be patterned using the dielectric layer as a mask to expose the first and second portions of the barrier layer.
[0022] In other embodiments, the gate electrode may be formed in the first opening directly on opposing sidewalls of the protective layer.
[0023] In some embodiments, a dielectric liner may be formed in the first opening on opposing sidewalls of the protective layer. For example, the dielectric liner may be a silicon dioxide liner or a nitride liner. After forming the dielectric liner, the gate electrode may be formed in the first opening directly on the dielectric liner.
[0024] In some embodiments, the barrier layer may be formed of Group-III nitride layer, and the channel layer may be formed of an undoped Group-III nitride layer. For example, the barrier layer may be formed of aluminum gallium nitride (AlGaN), and the channel layer may be formed of gallium nitride (GaN). The protective layer may be a dielectric material, such as silicon nitride (SiN), aluminum nitride (AlN), and/or silicon dioxide (SiO2).
[0025] According to further embodiments of the present invention, a transistor may include a protective layer having a first opening extending therethrough, and a dielectric layer on the protective layer. The dielectric layer may have a second opening extending therethrough that is wider than the first opening. The transistor may also include a gate electrode in the first and second openings. The gate electrode may include a first portion laterally extending on surface portions of the protective layer outside the first opening, and a second portion laterally extending beyond the first portion on portions of the dielectric layer outside the second opening. For example, the first and second openings may define a stair-step profile.
[0026] In some embodiments, the dielectric layer and the protective layer may be formed of different materials. The dielectric layer may have a lower dielectric index than the protective layer. For example, the dielectric layer may be an oxide layer. More particularly, the dielectric layer may be a high-temperature oxide (HTO) layer, and the protective layer may be a high-purity nitride (HPN) layer. For instance, the protective layer may be stoichiometric silicon nitride, and the dielectric layer may be silicon dioxide.
[0027] In other embodiments, the dielectric layer may be a high-quality oxide layer. The high-quality oxide layer may have a dielectric index of less than about 1.5.
[0028] In still other embodiments, the dielectric layer may have a thickness greater than that of the protective layer. For example, the dielectric layer may have a thickness of about 500 Angstroms (Å) to about 3000 Å, and the protective layer may have a thickness of about 200 Å to about 2000 Å. The thickness and/or the dielectric index of the dielectric layer may be sufficient to reduce the gate-to-drain and/or gate-to-source capacitance of the device.
[0029] In some embodiments, the transistor may further include a channel layer and a barrier layer on the channel layer. The protective layer may be on the barrier layer, and the gate electrode may extend through the first opening in the protective layer to contact the barrier layer. The channel layer and the barrier layer may be configured to provide a High Electron Mobility Transistor (HEMT). For example, the channel layer and the barrier layer have different lattice constants, and as such, may provide a pseudomorphic HEMT.
[0030] In other embodiments, the transistor may include first and second ohmic contact regions on the barrier layer at opposite sides of the gate electrode and spaced apart from the protective layer. For example, the dielectric layer may extend between the first and second ohmic contact regions and the protective layer.
[0031] In some embodiments, the gate electrode may be directly on opposing sidewalls of the first opening in the protective layer.
[0032] In other embodiments, a dielectric liner may extend in the first opening between a sidewall of the protective layer and the gate electrode. The gate electrode may be directly on the dielectric liner.
[0033] In some embodiments, the barrier layer may be a Group-III nitride layer, and the channel layer may be an undoped Group-III nitride layer. For example, the barrier layer may be aluminum gallium nitride (AlGaN), and the channel layer may be gallium nitride (GaN). The protective layer may also be a dielectric material. For example, the protective layer may be silicon nitride, aluminum nitride, and/or silicon dioxide. In other embodiments, the substrate may be silicon carbide.
Brief Description of the Drawings
[0034] FIGS. 1 to 9 are cross-sectional views illustrating intermediate fabrication steps in operations for fabricating transistor devices according to some embodiments of the present invention.
[0035] FIG. 10 is a cross-sectional view illustrating a transistor device according to some embodiments of the present invention.
[0036] FIGS. 11 to 18 are cross-sectional views illustrating intermediate fabrication steps in operations for fabricating transistor devices according to further embodiments of the present invention.
Detailed Description of Embodiments of the Invention
[0037] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.
[0038] It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
[0039] It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
[0040] Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
[0041] The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0042] Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
[0043] Unless otherwise defined, all terms used in disclosing embodiments of the invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and are not necessarily limited to the specific definitions known at the time of the present invention being described. Accordingly, these terms can include equivalent terms that are created after such time. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the present specification and in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.
[0044] Embodiments of the present invention may be particularly well suited for use in nitride-based HEMTs, such as Group III-nitride based devices. As used herein, the term “Group III nitride” refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. As is well understood by those in this art, the Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN) compounds. These compounds may all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. Accordingly, formulas such as AlxGa1-xN, where 0≦x≦1, may be used to describe these compounds.
[0045] Suitable structures for GaN-based HEMTs that may utilize embodiments of the present invention are described, for example, in commonly assigned U.S. Pat. No. 6,316,793 and U.S. Patent Publication No. 2002/0066908A1 filed Jul. 12, 2001 and published Jun. 6, 2002, for “ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME”, United States Patent Publication No. 2002/0167023A1 to Smorchkova et al., published Nov. 14, 2002, entitled “GROUP-III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER”, and U.S. patent application Ser. No. 10/617,843 filed Jul. 11, 2003 for “NITRIDE-BASED TRANSISTORS AND METHODS OF FABRICATION THEREOF USING NON-ETCHED CONTACT RECESSES,” the disclosures of which are hereby incorporated herein by reference in their entirety.
[0046] Some embodiments of the present invention may arise from a realization that, for devices operating at relatively high frequencies (for example, above the X-band frequency range), and particularly for millimeter wave radio frequency (RF) devices, a tradeoff may exist between minimizing peak electric fields and/or surface-related trapping and maintaining relatively low capacitance values. Accordingly, some embodiments of the present invention provide a transistor device that combines some of the positive aspects of a T-gate (such as relatively low gate resistance and/or relatively low cgd and cgs) with some of the positive attributes of a gamma gate (such as pre-gate passivation and/or peak electric field reduction).
[0047] FIGS. 1 to 9 are cross-sectional views illustrating exemplary intermediate fabrication steps in methods for fabricating transistor devices according to some embodiments of the present invention. Referring now to FIG. 1 , a substrate 10 is provided on which a transistor device may be formed. A channel layer 20 is formed on the substrate 10, and a barrier layer 22 is formed on the channel layer 20. The substrate 10 may be a semi-insulating silicon carbide (SiC) substrate that may be, for example, the 4H polytype of silicon carbide. Other silicon carbide candidate polytypes may include the 3C, 6H, and 15R polytypes. The term “semi-insulating” is used descriptively herein, rather than in an absolute sense. In some embodiments of the present invention, the silicon carbide bulk crystal may have a resistivity equal to or higher than about 1×105 Ω-cm at room temperature.
[0048] Silicon carbide has a much closer crystal lattice match to Group III nitrides (which may be employed in the channel layer 20 and/or the barrier layer 22) than does sapphire (Al2O3), which may be a common substrate material for Group III nitride devices. The closer lattice match may result in Group III nitride films of higher quality than those generally available on sapphire. Silicon carbide also has a relatively high thermal conductivity, and as such, the total output power of Group III nitride devices formed on silicon carbide may not be as limited by thermal dissipation of the substrate as similar devices formed on sapphire and/or silicon. Also, semi-insulating silicon carbide substrates may provide for device isolation and reduced parasitic capacitance. Exemplary SiC substrates that may be used in some embodiments of the present invention are manufactured by, for example, Cree, Inc., of Durham, N.C., the assignee of the present invention, and methods for producing such substrates are described, for example, in U.S. Pat. Nos. Re. 34,861; 4,946,547; 5,200,022; and 6,218,680, the disclosures of which are incorporated by reference herein in their entireties. Similarly, techniques for epitaxial growth of Group III nitrides have been described in, for example, U.S. Pat. Nos. 5,210,051; 5,393,993; 5,523,589; and 5,292,501, the disclosures of which are also incorporated by reference herein in their entireties.
[0049] It is to be understood that, although silicon carbide may be employed as a substrate, embodiments of the present invention may utilize any suitable substrate for the substrate 10, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), gallium arsenide (GaAs), LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), and the like.
[0050] Optional buffer, nucleation and/or transition layers (not shown) may also be provided on the substrate 10. For example, an AlN buffer layer may be provided to provide an appropriate crystal structure transition between a silicon carbide substrate and the remainder of the device. Additionally, strain balancing transition layer(s) may also be provided as described, for example, in commonly assigned United States Patent Publication 2003/0102482A1, filed Jul. 19, 2002 and published Jun. 5, 2003, and entitled “STRAIN BALANCED NITRIDE HETEROJUNCTION TRANSISTORS AND METHODS OF FABRICATING STRAIN BALANCED NITRIDE HETEROJUNCTION TRANSISTORS, and U.S. Provisional Patent Application Ser. No. 60/337,687, filed Dec. 3, 2001 and entitled “STRAIN BALANCED NITRIDE HETEROJUNCTION TRANSISTOR,” the disclosures of which are incorporated by reference herein as if set forth fully herein.
[0051] Still referring to FIG. 1 , a channel layer 20 is provided on the substrate 10. The channel layer 20 may be deposited on the substrate 10 using buffer layers, transition layers, and/or nucleation layers as described above. The channel layer 20 may be under compressive strain. Furthermore, the channel layer 20 and/or buffer, nucleation, and/or transition layers may be deposited by metal-organic chemical vapor deposition (MOCVD) or by other techniques known to those of skill in the art, such as molecular beam epitaxy (MBE) and/or hydride vapor phase epitaxy (HVPE). In some embodiments of the present invention, the channel layer 20 may be a Group III-nitride layer, such as GaN. The channel layer 20 may also include other Group III-nitride layers, such as indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), or the like. The channel layer 20 may be undoped (i.e., “unintentionally doped”), and may be grown to a thickness of greater than about 20 Å. The channel layer 20 may also be a multi-layer structure, such as a superlattice or combinations of GaN, AlGaN, or the like.
[0052] As further shown in FIG. 1 , a barrier layer 22 is provided on the channel layer 20. For example, the barrier layer 22 may be deposited on the channel layer 20. The barrier layer 22 may be a Group III-nitride layer, such as AlxGa1-xN (where 0<x<1). The barrier layer 22 may also include other Group III-nitride layers, such as AlInGaN, AlN, and/or combinations of layers thereof. The barrier layer 22 may, for example, be from about 0.1 nm to about 100 nm thick, but may not be so thick as to cause cracking or substantial defect formation therein. In certain embodiments of the present invention, the barrier layer 22 may be a highly-doped n-type layer. For example, the barrier layer 22 may be doped to a concentration of less than about 1019 cm−3.
[0053] Some embodiments of the present invention may be applicable in high electron mobility transistors (HEMTs). More particularly, the channel layer 20 and the barrier layer 22 may be formed of materials having different bandgaps, such that an interface between the channel layer and the barrier layer defines a heterojunction. For example, the channel layer 20 may have a bandgap that is less than the bandgap of the barrier layer 22. As such, the energy of the conduction band edge of the channel layer 20 may be less than the energy of the conduction band edge of the barrier layer 22 at the junction between the channel 20 and barrier 22 layers, and the channel layer 20 may have a greater electron affinity than the barrier layer 22. For example, where both the channel layer 20 and the barrier layer 22 are formed of Group III-nitride layers, the channel layer 20 may be a GaN layer, and the barrier layer 22 may be a AlGaN layer.
[0054] Examples of layers according to certain embodiments of the present invention are described in United States Patent Publication No. 2002/0167023A1, to Smorchkova et al., entitled “GROUP-III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER” the disclosure of which is incorporated herein by reference as if set forth fully herein. In particular embodiments of the present invention, the barrier layer 22 may have a thickness, Al composition, and/or doping sufficient to induce a significant carrier concentration at the interface between the channel layer 20 and the barrier layer 22 through polarization effects when the barrier layer 22 is buried under ohmic contact metal. Also, the barrier layer 22 may be thick enough to reduce or minimize scattering of electrons in the channel due to ionized impurities deposited at the interface between the barrier layer 22 and a subsequently formed protective layer.
[0055] In addition, in other embodiments of the present invention, the channel layer 20 and the barrier layer 22 may have different lattice constants. For example, the barrier layer 22 may be a relatively thin layer having a smaller lattice constant than the channel layer 20, such that the barrier layer 22 “stretches” at the interface between the two. Accordingly, a pseudomorphic HEMT (PHEMT) device may be provided.
[0056] FIG. 2 illustrates formation of a protective layer 24 on the barrier layer 22. The protective layer 24 may be dielectric material, such as silicon nitride (SixNy), aluminum nitride (AlN), silicon dioxide (SiO2), and/or other suitable protective material. Other materials may also be utilized for the protective layer 24. For example, the protective layer 24 may also include magnesium oxide, scandium oxide, aluminum oxide and/or aluminum oxynitride. Furthermore, the protective layer 24 may be a single layer or may include multiple layers of uniform and/or non-uniform composition.
[0057] The protective layer 24 may be blanket formed on the barrier layer 22. For example, the protective layer 24 may be a silicon nitride (SiN) layer formed by high quality sputtering and/or plasma-enhanced chemical vapor deposition (PECVD). The protective layer 24 may have a thickness of about 30 nm, however, other thickness layers may also be utilized. For example, the protective layer may be sufficiently thick so as to protect the underlying layer during a subsequent anneal of ohmic contacts. Layers as thin as two or three monolayers may be sufficient for such purposes. However, in general, the protective layer 24 may have a thickness of from about 10 nm to about 500 μm. Also, a high quality SiN protective layer may be grown in-situ with the MOCVD growth of the group III nitride layers.
[0058] In particular embodiments of the present invention, the protective layer 24 may be SiN. The SiN protective layer may be formed by PVD and/or CVD and may be non-stoichiometric in compressive or tensile strain. For example, the SiN protective layer may have a stress of between about −100 MPa and about 100 MPa. In certain embodiments of the present invention, the SiN protective layer may have an index of refraction at a 633 nm wavelength of from about 1.6 to about 2.2. In particular embodiments, the index of refraction of the SiN protective layer may be 1.98±0.05.
[0059] FIG. 3 illustrates formation of ohmic contact regions 30 on the barrier layer 22. Referring now to FIG. 3 , the protective layer 24 is patterned to expose portions of the barrier layer 22, and first and second ohmic contact regions 30 are formed on the barrier layer 22. For example, windows may be etched into the protective layer 24 to expose the underlying barrier layer 22. The windows may be etched utilizing a patterned mask and a low-damage etch with respect to the barrier layer 22. Examples of low damage etch techniques may include etching techniques other than reactive ion etching, such as inductively coupled plasma or electron cyclotron resonance (ECR) or downstream plasma etching with no DC component to the plasma. For example, for a SiO2 barrier layer, a wet etch with buffered hydrofluoric acid may be used. A selective etch of SiN and/or SiO2 to an etch stop layer, such as ITO, SCO, MgO or the like, followed by a low damage removal of the etch stop layer may also be performed. For a SiN barrier layer, SiO2 may be used as an etch stop layer. In such embodiments, the protective layer 24 may include the SiN, AlN, and/or SiO2 layers, as well as the etch stop layer. Thus, in certain embodiments of the present invention, the protective layer 24 may include multiple layers.
[0060] Still referring to FIG. 3 , using a subsequent photolithography step and evaporation, ohmic metal is formed on the exposed portions of the barrier layer 22. The ohmic metal is patterned so as to be smaller than the window in the protective layer 24, and the ohmic metal is annealed to provide the first and second ohmic contact regions 30. As such, the edges of the ohmic contact regions 30 may be spaced apart from the adjacent protective layer 24.
[0061] The anneal may be a relatively high temperature anneal. For example, the anneal may be performed at a temperature of greater than about 900° C. By using such an ohmic contact anneal, the resistance of the ohmic contact regions 30 may be reduced from a relatively high resistance to, for example, less than about 1 Ω-mm. Thus, as used herein, the term “ohmic contact” may refer to a non-rectifying contact that has a contact resistance of less than about 1 Ω-mm. The presence of the protective layer 24 during the high temperature process steps may reduce and/or inhibit damage to the barrier layer 22 that may be caused by such steps. Thus, for example, the sheet resistance of the gate region 21 (i.e., the length of the channel between the ohmic contact regions 30) after the high temperature ohmic contact anneal may be substantially the same as the sheet resistance of the gate region 21 as-grown (i.e., before the contact anneal).
[0062] The ohmic contact regions 30 may be spaced apart from the protective layer 24 by a distance that is sufficient to allow for misalignment tolerances in the formation and/or patterning of the ohmic contact metal. For example, the edges of the ohmic contact regions 30 may be spaced apart from the protective layer 24 by a distance of about 0.1 micrometer (μm) to about 0.2 μm. It may be desirable to prevent contact between the ohmic metal and the protective layer 24 to reduce the likelihood of the metal diffusing into the protective layer 24 during subsequent heating steps, which may result in a short between a gate contact and the ohmic contact region(s) 30. However, the gaps between the ohmic contact regions 30 and the protective layer 24 need not be so large as to defeat the protective purpose of the protective layer 24 (and/or substantially degrade the performance of the device), but may not be so small as to risk contact between the ohmic material and the protective layer 24. Thus, in certain embodiments of the present invention, the gaps may be in the range of about 0.1 micrometer (μm) to about 0.5 μm.
[0063] FIG. 4 illustrates the formation of a second layer 31 on the ohmic contact regions 30 and the protective layer 24. The second layer 31 may be a dielectric layer having a lower dielectric index than the protective layer 24. For instance, the second layer 31 may be a high-quality oxide layer, such as a high-temperature oxide (HTO) layer. The second layer 31 may also be a sacrificial layer, which may be removed in a subsequent step. For example, the second layer 31 may be a photoresist layer. Also, the second layer 31 may be a polymide layer. As shown in FIG. 4 , the second layer 31 includes a hole or recess 3 that extends through the second layer 31 and exposes a portion of the protective layer 24. For example, the second layer 31 may be photolithographically patterned to form the recess 3.
[0064] FIG. 5 illustrates the formation of an opening or “window” in the protective layer 24, where the gate electrode may be formed in a subsequent step. As shown in FIG. 5 , an opening 4 is formed extending through the protective layer 24 to expose a portion of the barrier layer 22. More particularly, the exposed portion of the protective layer 24 is patterned using the second layer 31 as a mask to form the opening 4. The opening 4 may be formed by selectively etching the portion of the protective layer 24 exposed by the recess 3 in the second layer 31 using a low damage etch technique, as described above, to facilitate the formation of a low-leakage Schottky gate contact on the exposed surface of the barrier layer 22. Note that the opening 4 in the protective layer 24 may be wider than the recess 3 in the second layer 31, due to isotropy (i.e., undercutting) of the etch. In particular embodiments, the ohmic contacts 30 may provide source and drain contacts, and the opening 4 may be offset between the source and drain contacts such that the opening 4, and subsequently the gate contact, may be closer to the source contact than the drain contact.
[0065] Referring now to FIG. 6 , the recess 3 in the second layer 31 is widened to define a second opening 5 that is wider than the first opening 4. As such, the second opening 5 exposes the first opening 4 as well as surface portions of the protective layer 24 on opposite sides of the first opening 4. The recess 3 in the second layer 31 may be symmetrically expanded so that the second opening 5 and the first opening 4 are self-aligned. For example, where the second layer 31 is formed of a different material than the protective layer 24, the recess 3 in the second layer 31 may be widened by selectively etching the second layer 31 using a wet etching technique. More particularly, where the second layer 31 is an oxide layer, the recess 3 may be widened by selectively etching the second layer 31 using a buffered oxide etchant (BOE). In addition or in an alternative, where the second layer 31 is a photoresist layer, the recess may be widened by ashing the second layer 31 using an oxygen plasma and/or hard baking the device, for example, at a temperature above 100 degrees Celsius (C) but below 150 degrees C.
[0066] Accordingly, as shown in FIGS. 5 and 6 , the protective layer 24 may be selectively etched using the second layer 31 as a mask to form the first opening 4, and the recess 3 in the second layer 31 may be selectively widened around the first opening 4 to form the second opening 5. As such, the first opening 4 and the second opening 5 may be self-aligned. In some embodiments, the second layer 31 may be any material which may be selectively etched relative to the protective layer 24.
[0067] FIG. 7 illustrates the formation of a gate electrode 32. As shown in FIG. 7 , the gate electrode 32 is formed in the second opening 5 and the first opening 4, and extends through the protective layer 24 to contact the exposed portion of the barrier layer 22. The gate electrode 32 may be formed in the first opening 4 directly on opposing sidewalls of the protective layer 24, such that a gap may not be formed between the two. Suitable gate materials may depend on the composition of the barrier layer 24. However, in certain embodiments, conventional materials capable of making a Schottky contact to a nitride based semiconductor material may be used, such as Ni, Pt, NiSix, Cu, Pd, Cr, TaN, W and/or WSiN.
[0068] Still referring to FIG. 7 , first portions 6 (also referred to as “wings” or “sidelobes”) of the gate electrode 32 laterally extend on surface portions of the protective layer 24 outside the first opening 4, and second portions 7 of the gate electrode 32 that are spaced vertically apart from the protective layer 24 laterally extend on surface portions of the second layer 31 outside the second opening 5. As used herein, the term “laterally” refers to a direction that is substantially parallel with respect to a surface of the substrate. The second portions 7 of the gate electrode 32 may laterally extend beyond the first portions 6. Because the first opening 4 and the second opening 5 may be self-aligned by the processes described thus far, the length by which the first portions 6 of the gate electrode 32 extend onto the protective layer 24 may be controlled. As such, according to some embodiments of the present invention, gate-to-drain capacitance (cgd) and/or gate-to-source capacitance (cgs) of the transistor device that may be caused by the extension of the gate electrode 32 onto the protective layer 24 may also be controlled. Accordingly, a modified gamma gate 32 having self-aligned sidelobes 6 may be formed.
[0069] FIG. 8 illustrates removal of the sacrificial second layer 31. As shown in FIG. 8 , the second layer 31 is removed after the gate electrode 32 is formed. The second layer 31 may be formed using conventional techniques, depending on the composition of the second layer 31.
[0070] FIG. 9 illustrates the formation of a passivation layer 34. The passivation layer 34 may provide environmental protection for the transistor device. For example, the passivation layer 34 may be a thicker nitride or relatively low-k encapsulation layer, and may be formed to improve coverage of the protective layer 24. The passivation layer 34 may be blanket deposited on the structure of FIG. 8 after removal of the second layer 31. As such, the second portions 7 of the gate electrode 32 laterally extend on portions of the passivation layer 34. In particular embodiments, the passivation layer 34 may be deposited so as to substantially fill the gaps between the protective layer 24 and the ohmic contacts 30. In certain embodiments of the present invention, the passivation layer 34 may be silicon nitride, aluminum nitride, silicon dioxide, and/or an oxynitride. Furthermore, the passivation layer 34 may be a single or multiple layers of uniform and/or non-uniform composition.
[0071] FIG. 10 is a cross-sectional view illustrating a high electron mobility transistor (HEMT) device 100 according to further embodiments of the present invention. As shown in FIG. 10 , the gate electrode 32 of the HEMT device 100 extends through the protective layer 24 to contact the barrier layer 22. The gate electrode 32 includes first portions 6 laterally extending on surface portions of the protective layer 24 outside the opening therein, and second portions 7 spaced vertically apart from the protective layer 24 by the passivation layer 34 and laterally extending on portions of the passivation layer 34 beyond the first portions 6. In other words, the first and second portions 6 and 7 of the gate electrode 32 define a stair-step profile. The second portions 7 of the gate electrode 32 may be spaced apart from the protective layer 24 by about 1000 Angstroms (Å) to about 6000 Å. The gate electrode 32 also extends directly on opposing sidewalls of the opening in the protective layer 24, such that a gap may not be present between the gate electrode 32 and the protective layer 24. The first portions 6 of the gate electrode 32 may also be formed directly on the protective layer 24.
[0072] In addition, because the first opening (in the protective layer 24) and the second opening (in the second layer 31 of FIG. 6 ) may be self-aligned by the processes described above, a width of the second opening (illustrated as LG2) may be self-aligned and symmetric around a width of the first opening, which defines the gate length LG1. As such, the gate length LG1 may be tuned for an operational frequency of interest based on formation of the opening in the protective layer 24. For example, the gate length LG1 may be about 0.05 micrometer (μm) to about 2.0 μm. In addition, a length ΔLG by which the first portion 6 of the gate electrode 32 extends onto the protective layer 24 may also be controlled, by widening the opening in the sacrificial second layer, as described above. The thickness d1 of the protective layer 24 and the length ΔLG of first portion of the gate electrode 32 may be optimized to reliably support the peak gate-to-drain voltage VGD and to minimize and/or reduce the gate-to-drain capacitance cgd and the gate-to-source capacitance cgs. For example, the length ΔLG may be about 0.1 micrometer (μm) to about 0.6 μm, and the thickness d1 may be about 300 Angstroms (Å) to about 5000 Å. In addition, the angle Ø of the sidewalls of the protective layer 24 defining the first opening may also be optimized, for example, between about 45 degrees to about 90 degrees.
[0073] As described above, in some embodiments, the protective layer 24 may be SiN, the barrier layer 22 may be AlGaN, and the channel layer 20 may be GaN. The transistor 100 also includes a nucleation layer 15 between the substrate 10 and the channel layer 20, as also discussed above.
[0074] Also, FIG. 10 illustrates that the ohmic contact regions may be source/drain contact regions 30. The protective layer 24 may be formed to a thickness that is at least about as thick as the ohmic contact regions. For example, the protective layer 24 may be formed to a thickness in the range of about 500 Angstroms (Å) to about 5000 Å. In addition, the passivation layer 34 may substantially fill the gap between the protective layer 24 and the source/drain regions 30. In certain embodiments of the present invention, the passivation layer 34 may be formed of the same material as the protective layer 24. As such, the passivation layer 34 may be silicon nitride, aluminum nitride, silicon dioxide and/or an oxynitride. Furthermore, the passivation layer 34 may be a single or multiple layers of uniform and/or non-uniform composition.
[0075] In other embodiments of the present invention, the second layer 31 may not be a sacrificial layer. As such, second layer 31 may not be removed, and the passivation layer 34 may not be formed. Thus, FIG. 7 illustrates a high electron mobility transistor (HEMT) device according to other embodiments of the present invention. For example, as noted above, the second layer 31 may be a dielectric layer. More particularly, the second layer 31 may be an oxide layer, such as a HTO layer and/or other high-quality oxide layer, and the protective layer 24 may be a nitride layer, such as a high-purity nitride (HPN) layer, and/or another protective layer that may be selectively etched with respect to the oxide layer. Such an oxide layer may provide a lower impurity concentration and/or other improved electrical characteristics in comparison to the passivation layer 34. Accordingly, further embodiments of the present invention will be described with reference to FIGS. 11 to 18 .
[0076] FIGS. 11 to 18 are cross-sectional views illustrating examples of intermediate fabrication steps in methods for fabricating transistor devices according to further embodiments of the present invention. Referring now to FIG. 11 , a barrier layer 22 and a channel layer 20 may be formed a substrate 10 on which a transistor device may be formed, as described above with reference to FIG. 1 . For example, the substrate 10 may be a semi-insulating silicon carbide (SiC) substrate. Optional buffer, nucleation and/or transition layers (not shown) may also be provided on the substrate 10, for example, to provide an appropriate crystal structure transition between a silicon carbide substrate and the remainder of the device. The channel layer 20 may be single or multi-layer Group III-nitride layer, such as a superlattice. The barrier layer 22 may be a Group III-nitride layer, such as AlxGa1-xN (where 0<x<1). The barrier layer 22 may also include other Group III-nitride layers, such as AlInGaN, AlN, and/or combinations of layers thereof.
[0077] The channel layer 20 and the barrier layer 22 may be formed of materials having different bandgaps, such that an interface between the channel layer and the barrier layer defines a heterojunction. More particularly, the channel layer 20 may have a bandgap that is less than the bandgap of the barrier layer 22. For example, where both the channel layer 20 and the barrier layer 22 are formed of Group III-nitride layers, the channel layer 20 may be a GaN layer, and the barrier layer 22 may be a AlGaN layer. In addition, the channel layer 20 and the barrier layer 22 may have different lattice constants. For example, the barrier layer 22 may be a relatively thin layer having a smaller lattice constant than the channel layer 20, such that the barrier layer 22 “stretches” at the interface between the two. Accordingly, a pseudomorphic HEMT (PHEMT) device may be provided.
[0078] Still referring to FIG. 11 , a protective layer 24 is formed on the barrier layer 22. The protective layer 24 may be dielectric material, such as silicon nitride (SixNy), aluminum nitride (AlN), silicon dioxide (SiO2), and/or other suitable protective material. The protective layer 24 may be a single layer or may include multiple layers of uniform and/or non-uniform composition. Other materials may also be utilized for the protective layer 24.
[0079] In some embodiments of the present invention, the protective layer 24 may be a high purity nitride (HPN) layer. As described herein, a HPN layer may refer to a nitride layer having significantly lower overall impurity levels as compared to some other nitride layers. More particularly, the impurity levels of a HPN layer may generally be one to three orders of magnitude smaller than the impurity levels in nitride layers grown by PECVD and/or by sputtering. For example, HPN may refer to nearly stoichiometric silicon nitride (i.e., Si3N4) having relatively low impurity concentrations in the Si3N4 layer itself as well as at the interface between the Si3N4 layer and the underlying layer. This may be achieved by depositing the HPN layer in the same reactor as the underlying layer and using the conditions described further herein.
[0080] For example, the protective layer 24 may include a high purity SiN layer as described in U.S. patent application Ser. No. 11/286,805 filed on Nov. 23, 2005 entitled “GROUP III NITRIDE SEMICONDUCTOR DEVICES WITH SILICON NITRIDE LAYERS AND METHODS OF MANUFACTURING SUCH DEVICES,” the disclosure of which is incorporated herein by reference as if fully set forth herein. The SiN layer may be formed, for example, by Low Pressure Chemical Vapor Deposition (LPCVD) and/or Metal-Organic Chemical Vapor Deposition (MOCVD). In particular, pursuant to certain embodiments of the present invention, a SiN protective layer 24 may be grown at relatively high temperatures (e.g., above about 700° C.) in situ with the MOCVD growth of the Group III nitride layers. For example, where the channel layer 20 is GaN, the protective layer 24 may be grown in the GaN epitaxial reactor without cooling the substrate 10 from the growth temperatures of the Group III nitride layers. In particular embodiments, the SiN layers may be grown at a temperature in the range of about 900° C. to about 1000° C. Such high-temperature growth may also facilitate reducing the impurity levels in the SiN layer and at the interface between a Group III nitride layer and the SiN layer. Additionally, high growth rates may be employed which may facilitate reducing the levels of background reactor impurities incorporated into the SiN layer.
[0081] Forming the SiN layer in situ may also reduce the levels of impurities that are incorporated into the top surface of the uppermost Group III nitride layer and/or into the SiN layer itself. In particular, when the device is removed from the reactor and the SiN layer is formed via a post-MOCVD growth process such as, for example, sputtering or PECVD, a number of different mechanisms may introduce impurities. For example, as discussed in detail in U.S. Pat. No. 6,498,111, if hydrogen is present in an MOCVD reactor during the growth of a Group III nitride layer, the hydrogen may tend to incorporate into the Group III nitride layer during cooling of the reactor following growth. Likewise, exposure of the device to the atmosphere upon removal from the reactor may allow for incorporation of oxygen atoms. In addition, various other impurities may be introduced, particularly adjacent the outer surfaces of the device, as a result of handling of the device and/or chemical cleaning of the device. Impurities may also be added if post-growth processing such as wet etching, electrode deposition, annealing steps, etc. are performed prior to deposition of the SiN protective/passivation layer. These impurities may change the surface states at the interface between the Group III nitride layer and the SiN layer in ways that may be undesirable and/or difficult to control/reproduce. For example, the presence of impurities can increase trapping at the interface between the SiN layer and the underlying Group III nitride layer, thereby increasing the sheet resistance of the channel.
[0082] In certain embodiments of the present invention, the silicon nitride layer may be formed using a high purity silicon gas (e.g., 99.99% pure) source. For example, high purity silane (SiH4) may be used as a source gas in the growth of the SiN layer(s). As is known to persons of skill in the art, silane is often used as a source for silicon dopants in the growth of n-doped Group III nitride layers. Typically, diluted silane gas is used in such applications as it is less expensive and easier to use than pure silane, which may be highly combustible. The use of such pure silane may facilitate reducing the level of impurities at, for example, the interface between the Group III nitride layer and the SiN layer and/or within the SiN layer, which may, in certain circumstances, improve the performance and/or reproducibility of the device. In particular, a higher-quality (i.e., more pure) SiN layer may help reduce or minimize trapping within the body of the insulative layer, thereby providing a higher breakdown critical field. Pure disilane (Si2H6) or other pure silicon gas sources may also be used instead of high purity silane (SiH4). When such a pure silane gas source is included with the reactor, it may still be desirable to include a diluted silane source as well, so that diluted silane gas may be used as the dopant gas source during the growth of, for example, an n-doped or co-doped Group III nitride layer.
[0083] In some embodiments, the high purity SiN layer 24 may be stoichiometric. The term “stoichiometry” may refer to the molar proportions of elements in stoichiometric compounds. In such stoichiometric compounds, the molar proportions are whole numbers. For example, the stoichiometry of silicon and nitrogen in Si3N4 is about 3:4. The stoichiometry of a SiN layer may also affect the index of refraction of the layer. In certain embodiments of the present invention, a SiN protective layer 24 may have an index of refraction at a 633 nm wavelength of from about 1.6 to about 2.2. Stoichiometric SiN may also be characterized by a relatively low etch rate in a buffered oxide etch (BOE). For example, the etch rate of stoichiometric SiN in BOE may be less than about 10 Angstroms per minute. In contrast, PECVD silicon nitride may have a BOE etch rate on the order of about 100 Angstroms per minute, and sputtered silicon nitride may have a BOE etch rate on the order of about 1000 Angstroms or more per minute. The stoichiometry of a SiN layer may be adjusted, for example, by adjusting the relative flow rates of SiH4 and NH3 source gases in a CVD process. Moreover, when formed at relatively high temperatures, CVD-grown SiN tends to be stoichiometric.
[0084] In some embodiments of the present invention, the protective layer 24 may include a HPN layer that is sufficiently thick so as to reduce and/or inhibit damage to the barrier layer 22 during subsequent high temperature process steps. For instance, the HPN layer may have a thickness of from about 200 Angstroms (Å) to about 2000 Å. In addition, the protective layer 24 may include multiple layers of HPN and silicon dioxide (SiO2) and/or plasma enhanced chemical vapor deposition (PECVD) silicon nitride (SiN). It will be understood that the terms “SixNy,” “SiN” and “silicon nitride” are used herein interchangeably to refer to both stoichiometric and non-stoichiometric silicon nitride. However, embodiments of the present invention are not limited by these examples, for example, any HPN can be used as the high quality dielectric protective layer 24. More generally, the material of the protective layer 24 should have appropriate interface characteristics, should be capable of withstanding relatively high temperatures, and should be capable of being removed without significantly damaging the underlying barrier layer 22.
[0085] FIG. 12 illustrates formation of a dielectric layer, such as an oxide layer 33, on the protective layer 24. For example, the oxide layer 33 may be deposited on the protective layer 24 using a chemical vapor deposition (CVD) process at a temperature of greater than about 500° C. In addition and/or alternatively, the oxide layer 33 may be formed in situ. The oxide layer 33 may be formed to a thickness that is greater than the thickness of the protective layer 24. For example, the oxide layer 33 may have a thickness of about 300 Angstroms (Å) to about 5000 Å.
[0086] The oxide layer 33 may also have a lower dielectric index than the protective layer 24. For instance, the oxide layer 33 may be a high-quality oxide layer, such as a high-temperature oxide (HTO) layer. The high-quality oxide layer 33 may have a dielectric constant or dielectric index of less than about 1.5. In addition, the high-quality oxide layer 33 may have a relatively low impurity concentration, for example, as may be measured by a secondary ion mass spectroscopy (SIMS) analysis. As such, a high-quality oxide layer according to some embodiments of the present invention may have improved electrical characteristics as compared to a layer formed by a PECVD process, such as the post-gate passivation layer 34 of FIG. 10 .
[0087] For example, in some embodiments, the HTO layer may be a silicon dioxide (SiO2) layer deposited by a LPCVD process at a temperature of about 900° C. The LPCVD nature of the deposition may allow the oxide layer 33 to be formed while reducing and/or minimizing negative effects on the underlying semiconductor layer(s). In addition, the relatively high temperature of deposition may allow for the formation of a relatively dense oxide layer 33, with measured dielectric strength of about 8-9 MV/cm (i.e., about 80-90% of the theoretical value for SiO2).
[0088] In certain embodiments of the present invention, the oxide layer 33 may be stoichiometric SiO2. The SiO2 layer may have an index of refraction at a 633 nm wavelength of from about 1.36 to about 1.56. In particular embodiments, the index of refraction of an SiO2 protective layer may be 1.46±0.03 as measured by ellipsometry. In addition, the SiO2 layer may provide reduced levels of charges, traps, and other electrically active non-idealities (impurities) therein, which may, in certain circumstances, improve the performance and/or reproducibility of the device. In particular, a high-quality (i.e., more pure) SiO2 layer may help reduce or minimize trapping within the body of the insulative layer, thereby providing a higher breakdown critical field. More generally, the oxide layer 33 may be selected to provide a thickness, impurity concentration, dielectric index, and/or other characteristics that may be sufficient to reduce gate-to-drain and/or gate-to-source capacitance in a HEMT device.
[0089] Referring now to FIG. 13 , the oxide layer 33 and the protective layer 24 are patterned to expose portions of the barrier layer 22. For example, utilizing a patterned mask (not shown), the oxide layer 33 may be patterned to define recesses 9 exposing first and second portions of the protective layer 24, and the protective layer 24 may be patterned using the oxide layer 33 as a mask to define windows 8 exposing portions of the barrier layer 22. More particularly, a dry etching process may be used to define the recesses 9 in the oxide layer 33, and a low-damage wet etching process may be used to selectively etch the protective layer 24 to define the windows 8. A selective etch of the protective layer 24 to an etch stop layer, such as ITO, SCO, MgO or the like, followed by a low damage removal of the etch stop layer may also be performed. In such embodiments, the protective layer 24 may include SiN, AlN, and/or SiO2 layers, as well as the etch stop layer. Alternatively, with both layers 33 and 24 deposited, a low-damage dry etch may be used to etch through both the oxide layer 33 and the protective layer 24 in a single step. Examples of such low damage etch techniques may include etching techniques other than reactive ion etching, such as inductively coupled plasma or electron cyclotron resonance (ECR) or downstream plasma etching with no DC component to the plasma.
[0090] Also, in some embodiments, the protective layer 24 may be patterned to define the windows 8 exposing portions of the barrier layer 22 before forming the oxide layer 33. As such, the oxide layer may be formed on the protective layer 24 and on the first and second portions of the barrier layer 22. The oxide layer may then be patterned to define recesses 9 exposing portions of the barrier layer 22. The recesses 9 may be narrower than the windows 8 etched into the protective layer 24. As such, portions of the oxide layer 33 may remain along the sidewalls of the windows 8 in the protective layer 24. Accordingly, when ohmic contact regions are formed on the barrier layer 22 in a subsequent step, the edges of the ohmic contact regions may be spaced apart from the adjacent protective layer 24 due to the presence of the oxide layer 33 therebetween.
[0091] FIG. 14 illustrates formation of ohmic contacts 30 on the barrier layer 24. Referring now to FIG. 14 , metal may be deposited on the portions of the barrier layer 22 exposed by the windows 8 and the recesses 9, for example, by evaporation, to provide ohmic metal regions on the barrier layer 22. Suitable metals may include refractory metals, such as titanium (Ti), tungsten (W), titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silicide (WSi), rhenium (Re), Niobium (Nb), nickel (Ni), gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), nickel silicide (NiSi), titanium silicide (TiSi), titanium nitride (TiN), tungsten silicon nitride (WSiN), platinum (Pt) and the like. Any unwanted metal may be removed using, for example, a solvent. The ohmic metal regions may be patterned to be smaller than the window in the protective layer 24, and may be annealed to provide the first and second ohmic contact regions 30. As such, the ohmic contact regions 30 may be spaced apart from the protective layer 24 by a distance that is sufficient to allow for misalignment tolerances in the formation and/or patterning of the ohmic contact metal. For example, the edges of the ohmic contact regions 30 may be spaced apart from the protective layer 24 by a distance of about 0.1 micrometer (μm) to about 0.5 μm.
[0092] Still referring to FIG. 14 , the anneal may be a relatively high temperature anneal. For example, the anneal may be performed at a temperature of greater than about 900° C. By using such an ohmic contact anneal, the resistance of the ohmic contact regions 30 may be reduced from a relatively high resistance to, for example, less than about 1 Ω-mm. Thus, as used herein, the term “ohmic contact” may refer to a non-rectifying contact that has a contact resistance of less than about 1 Ω-mm. The presence of the protective layer 24 during the high temperature process steps may reduce and/or inhibit damage to the barrier layer 22 that may be caused by such steps. Thus, for example, the sheet resistance of the gate region 21 (i.e., the length of the channel between the ohmic contact regions 30) after the high temperature ohmic contact anneal may be substantially the same as the sheet resistance of the gate region 21 as-grown (i.e. before the contact anneal).
[0093] It will be appreciated that, in some embodiments, it may not be necessary to anneal the deposited metal in order to form the ohmic contacts 30. For example, where the ohmic contacts 30 are formed on implanted source/drain regions in the barrier layer 22, the metal may be ohmic as-deposited. Since a contact anneal may not be required, it may be acceptable for the metal of the ohmic contacts 30 to contact the protective layer 24. Thus, in some embodiments of the invention, a lithography step that may otherwise be required to ensure that the ohmic contacts 30 are spaced away from the protective layer 24 may be avoided as a result of the implantation of impurities into the barrier layer 22. In addition, since the ohmic contacts 30 may be formed on the implanted regions, the ohmic contacts may have a lower resistivity than ohmic contacts formed on non-implanted regions. Thus, the on-resistance of devices formed according to some embodiments of the invention may be lowered. Moreover, some embodiments of the present invention may employ semiconductor fabrication methods as discussed in currently commonly assigned U.S. patent application Ser. No. 11/302,062 entitled SEMICONDUCTOR DEVICES INCLUDING IMPLANTED REGIONS AND PROTECTIVE LAYERS AND METHODS OF FORMING THE SAME, and U.S. patent application Ser. No. 11/434,853 entitled SEMICONDUCTOR DEVICES INCLUDING SELF ALIGNED REFRACTORY CONTACTS AND METHODS OF FABRICATING THE SAME, the disclosures of which are incorporated by reference herein in their entireties.
[0094] FIG. 15 illustrates the formation of a hole or recess 3 in the oxide layer 33. More particularly, a mask (not shown) is formed on the ohmic contacts 30 and the oxide layer 33, and the oxide layer 33 is patterned to form the recess 3. The oxide layer 33 may be selectively patterned, for example, by one of the etch techniques described above. The recess 3 extends through the oxide layer 33 and exposes a portion of the protective layer 24.
[0095] FIG. 16 illustrates the formation of an opening or “window” in the protective layer 24 where the gate electrode may be formed in a subsequent step. As shown in FIG. 16 , an opening 4 is formed extending through the protective layer 24 to expose a portion of the barrier layer 22. More particularly, the exposed portion of the protective layer 24 is patterned using the oxide layer 33 as a mask to form the opening 4. The opening 4 may be formed by selectively etching the portion of the protective layer 24 exposed by the recess 3 in the oxide layer 33 using a low damage etch technique, as described above, to thereby facilitate the formation of a low-leakage Schottky gate contact on the exposed surface of the barrier layer 22. Note that the opening 4 in the protective layer 24 may be wider than the recess 3 in the oxide layer 33, due to isotropy (i.e., undercutting) of the etch. In particular embodiments, the ohmic contacts 30 may provide source and drain contacts, and the opening 4 may be offset between the source and drain contacts such that the opening 4, and subsequently the gate contact, may be closer to the source contact than the drain contact.
[0096] It is to be understood that, in some embodiments, a low-damage dry etch may be used to etch through both the oxide layer 33 and the protective layer 24 in a single step to define the recess 3 in the oxide layer 33 and the opening 4 in the protective layer 24 to expose the barrier layer 22. In addition, in some embodiments, the oxide layer 33 and the protective layer 24 may be patterned to define the recesses 3 and 9 and the openings 4 and 8 using a single mask. More generally, although illustrated and described with reference to particular intermediate fabrication steps, some steps may be combined, divided, and/or eliminated in particular embodiments of the present invention.
[0097] Referring now to FIG. 17 , the recess 3 in the oxide layer 33 is widened to define a second opening 5 that is wider than the first opening 4. As such, the second opening 5 exposes the first opening 4 as well as surface portions of the protective layer 24 on opposite sides of the first opening 4. The recess 3 in the oxide layer 33 may be symmetrically expanded so that the second opening 5 and the first opening 4 are self-aligned. For example, the recess 3 in the oxide layer 33 may be widened by selectively etching the oxide layer 33 using a buffered oxide etchant (BOE). In addition, in some embodiments, the recesses 9 in the oxide layer 33 used in the formation of the ohmic contacts 30 may also be symmetrically expanded by the buffered oxide etchant (BOE).
[0098] Accordingly, as shown in FIGS. 16 and 17 , the protective layer 24 may be selectively etched using the oxide layer 33 as a mask to form the first opening 4, and the recess 3 in the oxide layer 33 may be selectively widened around the first opening 4 to form the second opening 5. As such, the first opening 4 and the second opening 5 may be self-aligned. In some embodiments, the oxide layer 33 may be formed of another high-quality dielectric material which may be selectively etched relative to the protective layer 24.
[0099] FIG. 18 illustrates the formation of a gate electrode 32 to provide a high electron mobility transistor (HEMT) device 200 according to further embodiments of the present invention. As shown in FIG. 18 , the ohmic contact regions may be source/drain contact regions 30. Also, the gate electrode 32 is formed in the second opening 5 and the first opening 4, and extends through the protective layer 24 to contact the exposed portion of the barrier layer 22. The gate electrode 32 may be formed in the first opening 4 directly on opposing sidewalls of the protective layer 24, such that a gap may not be formed between the two. In addition and/or alternatively, a dielectric liner (not shown), such as a high-quality silicon dioxide liner or a nitride liner, may be formed in the first opening on opposing sidewalls of the protective layer 24. The gate electrode 32 may be formed directly on the dielectric liner to provide a metal-insulator-semiconductor (MIS) HEMT device.
[0100] Suitable gate materials may depend on the composition of the barrier layer 24. However, in certain embodiments, conventional materials capable of making a Schottky contact to a nitride based semiconductor material may be used, such as Ni, Pt, NiSix, Cu, Pd, Cr, TaN, W and/or WSiN. In addition, in some embodiments, the gate material may also be deposited on the source/drain contact regions 30 during the formation of the gate electrode 32. More particularly, the gate material may be deposited in the first opening 4 in the protective layer 24, and in the second opening 5 and the recesses 9 in the oxide layer 33. The gate material may then be patterned to define the gate electrode 32 such that portions thereof remain on the source/drain contact regions 30 in the recesses 9. Forming the gate material (or other conductive layer) on the source/drain contact regions 30 may facilitate contact to the relatively small source/drain contact regions 30, for example, for probe access and/or wire bonding.
[0101] Still referring to FIG. 18 , first portions 6 (also referred to as “wings” or “sidelobes”) of the gate electrode 32 laterally extend on surface portions of the protective layer 24 outside the first opening 4, and second portions 7 of the gate electrode 32 that are spaced vertically apart from the protective layer 24 laterally extend on portions of the oxide layer 33 outside the second opening 5. As used herein, the term “laterally” refers to a direction that is substantially parallel with respect to a surface of the substrate. The second portions 7 of the gate electrode 32 may laterally extend beyond the first portions 6. In other words, the first and second portions 6 and 7 of the gate electrode 32 define a stair-step profile. Accordingly, a modified gamma gate 32 having self-aligned sidelobes 6 may be formed.
[0102] Also, as shown in FIG. 18 , because the first opening 4 and the second opening 5 may be self-aligned by widening the opening in the oxide layer 33 as described above, the length ΔLG by which the first portions 6 of the gate electrode 32 extend onto the protective layer 24 may be controlled. In addition, the second portions 7 of the gate electrode 32 may be spaced apart from the protective layer 24 based on the thickness of the oxide layer 33. As such, according to some embodiments of the present invention, gate-to-drain capacitance (cgd) and/or gate-to-source capacitance (cgs) of the transistor device that may be caused by the extension of the gate electrode 32 onto the protective layer 24 may also be controlled. The relatively low dielectric index of the high-quality oxide layer 33, may further contribute to the reduction in gate-to-drain and/or gate-to-source capacitance.
[0103] The thickness d1 of the protective layer 24 and the length ΔLG of first portion of the gate electrode 32 may also be optimized to reliably support the peak gate-to-drain voltage VGD and/or to minimize and/or reduce the gate-to-drain capacitance cgd and/or the gate-to-source capacitance cgs. For example, the length ΔLG may be about 0.1 micrometer (μm) to about 0.6 μm, and the thickness d2 may be about 200 Angstroms (Å) to about 2000 Å. In addition, the thickness d2 of the oxide layer 33 may be about 500 Angstroms (Å) to about 3000 Å. The angle Ø of the sidewalls of the protective layer 24 defining the first opening may also be optimized, for example, between about 45 degrees to about 90 degrees. Also, a width of the second opening (illustrated as LG2) may be self-aligned and symmetric around a width of the first opening, which defines the gate length LG1. As such, the gate length LG1 may be tuned for an operational frequency of interest based on formation of the opening in the protective layer 24. For example, the gate length LG1 may be about 0.05 micrometer (μm) to about 2.0 μm.
[0104] Thus, some embodiments of the present invention may combine many of the positive qualities of a T-gate with those of a dielectrically-supported gate electrode, or gamma gate. Accordingly, a modified gamma gate structure with self-aligned wings/sidelobes is provided having relatively low gate resistance, relatively low gate-to-drain and/or gate-to-source capacitance, and relatively high gain. In addition, gaps between the gate electrode and the protective layer may be reduced and/or avoided, and the peak electric fields may be reduced.
[0105] While embodiments of the present invention have been described herein with reference to particular HEMT structures, the present invention should not be construed as limited to such structures, and may be applied to formation of gate electrodes in many different transistor structures, such as pseudomorphic HEMTs (pHEMTs) (including GaAs/AlGaAs pHEMTs) and/or GaN MESFETs. More generally, embodiments of the present invention may be applied in any electronic device where a gate electrode may be formed and/or where preservation of the as-grown surface properties may be imperative. For example, silicon nitride and/or other removable encapsulant can be used in the fabrication sequence of AlGaN metal-semiconductor-metal (MSM) detectors, RF limiter diode structures, and/or power switching Schottky diodes.
[0106] Also, additional layers may be included in transistor devices while still benefiting from the teachings of the present invention. Such additional layers may include GaN cap layers, as for example, described in Yu et al., “Schottky barrier engineering in III-V nitrides via the piezoelectric effect,” Applied Physics Letters, Vol. 73, No. 13, 1998, or in U.S. Patent Publication No. 2002/0066908A1 published Jun. 6, 2002, for “ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME,” the disclosures of which are incorporated by reference as if set forth fully herein. In some embodiments, insulating layers such as SiNe, or relatively high quality AlN may be deposited for making a MISHEMT and/or passivating the surface. The additional layers may also include a compositionally graded transition layer or layers. In addition, the barrier layer 22 described above may also include multiple layers. Thus, embodiments of the present invention should not be construed as limiting the barrier layer to a single layer but may include, for example, barrier layers having combinations of GaN, AlGaN and/or AlN layers. For example, a GaN, AlN structure may be utilized to reduce or prevent alloy scattering.
[0107] In the drawings and specification, there have been disclosed typical embodiments of the invention, and, although specific terms have been employed, they have been used in a generic and descriptive sense only and not for purposes of limitation.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
That which is claimed:
1. A method of fabricating a transistor, the method comprising:
forming a protective layer;
forming a dielectric layer on the protective layer, the dielectric layer having a recess extending therethrough and exposing a portion of the protective layer, wherein the protective layer and the dielectric layer comprise different materials;
patterning the protective layer using the dielectric layer as a mask to form a first opening extending through the protective layer; then
widening the recess in the dielectric layer to define a second opening extending therethrough that is wider than the first opening, the second opening exposing the first opening and exposing surface portions of the protective layer on opposite sides of the first opening;
forming a gate material in the first and second openings and on the dielectric layer outside the second opening; and
patterning the gate material on the dielectric layer outside the second opening to define a gate electrode including first and second laterally extending portions, wherein the first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening and wherein the second portion of the gate electrode laterally extends beyond the first portion on portions of the dielectric layer outside the second opening.
2. The method of claim 1, wherein the dielectric layer has a lower dielectric index than the protective layer.
3. The method of claim 2, wherein the dielectric layer comprises an oxide layer.
4. The method of claim 3, wherein forming the dielectric layer comprises performing a chemical vapor deposition (CVD) process at a temperature of about 900 degrees Celsius (C) to form a high-temperature oxide (HTO) layer on the protective layer.
5. The method of claim 1, wherein the dielectric layer comprises a high-quality oxide layer having a dielectric index of less than about 1.5.
6. The method of claim 1, wherein the dielectric layer has a thickness greater than that of the protective layer.
7. The method of claim 6, wherein the dielectric layer has a thickness of about 500 Angstroms (Å) to about 3000 Å, and wherein the protective layer has a thickness of about 200 Å to about 2000 Å.
8. The method of claim 1, wherein widening the recess in the dielectric layer comprises:
symmetrically expanding the recess in the dielectric layer so that the second opening and the first opening are self-aligned.
9. The method of claim 8, wherein symmetrically expanding the recess in the dielectric layer comprises:
etching the dielectric layer using a wet oxide etchant, wherein the wet oxide etchant is selective with respect to the protective layer.
10. The method of claim 1, further comprising:
forming a channel layer; and
forming a barrier layer on the channel layer,
wherein forming the protective layer comprises forming the protective layer on the barrier layer, wherein forming the gate electrode comprises forming the gate electrode extending through the first opening in the protective layer to contact the barrier layer, and wherein a junction between the channel layer and the barrier layer define a heterojunction.
11. The method of claim 10, further comprising:
forming first and second ohmic contact regions on the barrier layer adjacent to and spaced apart from the protective layer so that the protective layer is between the first and second ohmic contact regions.
12. The method of claim 11, wherein forming the first and second ohmic contact regions comprises:
patterning the dielectric layer and the protective layer to expose first and second portions of the barrier layer; and
after patterning the dielectric layer and the protective layer, respectively forming the first and second ohmic contact regions on the first and second portions of the barrier layer adjacent to and spaced apart from the patterned protective layer.
13. The method of claim 12, wherein patterning the dielectric layer and the protective layer comprises:
before forming the dielectric layer, patterning the protective layer to expose the first and second portions of the barrier layer, wherein forming the dielectric layer comprises forming the dielectric layer on the protective layer and on the first and second portions of the barrier layer; and then
patterning the dielectric layer to define first and second recesses therein respectively exposing the first and second portions of the barrier layer.
14. The method of claim 12, wherein patterning the dielectric layer and the protective layer comprises:
patterning the dielectric layer to expose first and second portions of the protective layer; and
patterning the protective layer using the dielectric layer as a mask to expose the first and second portions of the barrier layer.
15. The method of claim 1, wherein forming the gate electrode further comprises:
forming the gate electrode in the first opening directly on opposing sidewalls of the protective layer.
16. The method of claim 1, wherein forming the gate electrode comprises:
forming a dielectric liner in the first opening on opposing sidewalls of the protective layer; and
after forming the dielectric liner, forming the gate electrode in the first opening directly on the dielectric liner.
17. The method of claim 1, wherein the gate electrode is directly on the barrier layer, wherein the first portion of the gate electrode laterally extends directly on the protective layer, and wherein the second portion of the gate electrode laterally extends directly on the dielectric layer and substantially parallel to the first portion.
18. A method of fabricating a transistor, the method comprising:
forming a protective layer, the protective layer having a first opening extending therethrough, wherein forming the protective layer comprises performing a chemical vapor deposition (CVD) process at a temperature of more than about 900 degrees Celsius (C) to form a high-purity nitride (HPN) layer on an underlying layer in a same reactor in which the underlying layer was grown;
forming a dielectric layer on the protective layer, the dielectric layer having a second opening extending therethrough that is wider than the first opening, wherein the dielectric layer comprises an oxide layer having a lower dielectric index than the protective layer, and wherein forming the dielectric layer comprises performing a chemical vapor deposition (CVD) process at a temperature of about 900 degrees Celsius (C) to form a high-temperature oxide (HTO) layer on the protective layer;
forming a gate material in the first and second openings and on the dielectric layer outside the second opening; and
patterning the gate material on the dielectric layer outside the second opening to define a gate electrode including first and second laterally extending portions, wherein the first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening and wherein the second portion of the gate electrode laterally extends beyond the first portion on portions of the dielectric layer outside the second opening.
19. The method of claim 18, wherein the protective layer comprises stoichiometric silicon nitride, and wherein the dielectric layer comprises silicon dioxide.
20. A method of fabricating a transistor, the method comprising:
forming a protective layer;
forming a dielectric layer on the protective layer, the dielectric layer having a recess extending therethrough and exposing a portion of the protective layer;
patterning the protective layer using the dielectric layer as a mask to form a first opening extending through the protective layer; then
widening the recess in the dielectric layer to define a second opening in the dielectric layer that is wider than the first opening and exposing surface portions of the protective layer on opposite sides of the first opening; and
forming a gate electrode in the first and second openings so that a first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening and so that a second portion of the gate electrode laterally extends beyond the first portion on portions of the dielectric layer outside the second opening.
21. A method of fabricating a transistor, the method comprising:
providing a protective layer;
providing a dielectric layer on the protective layer, the dielectric layer having a recess extending therethrough and exposing a portion of the protective layer;
patterning the protective layer using the dielectric layer as a mask; then
widening the recess in the dielectric layer; and
providing a gate electrode on the protective layer and on the dielectric layer, the gate electrode comprising a first portion that laterally extends on surface portions of the protective layer and a second portion that laterally extends on surface portions of the dielectric layer outside the widened recess and beyond the first portion.
22. The method of claim 21, wherein patterning the protective layer comprises:
patterning the protective layer using the dielectric layer as a mask to form a first opening extending through the protective layer.
23. The method of claim 22, wherein widening the recess in the dielectric layer comprises:
widening the recess in the dielectric layer to define a second opening in the dielectric layer that is wider than the first opening in the protective layer and exposes the surface portions of the protective layer on opposite sides of the first opening.
24. The method of claim 23, wherein widening the recess in the dielectric layer comprises:
symmetrically expanding the recess in the dielectric layer so that the second opening and the first opening are self-aligned.
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