Semiconductor device having lateral high breakdown voltage element

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device having a lateral high breakdown voltage element, and more specifically, to a semiconductor device having a lateral high breakdown voltage element with an SOI (Semiconductor on Insulator) structure and capable of maintaining a high breakdown voltage.

[0004] 2. Description of the Background Art

[0005] First, a conventional technique will be described.

[0006] FIG. 36 is a schematic cross sectional view showing a first example of a conventional semiconductor device. With reference to FIG. 36, the semiconductor device is provided with an insulation substrate 103. An n⁻ semiconductor layer 102 (referred to as an SOI layer) is formed on insulation substrate 103. An n⁺ semiconductor region 104 with low resistance is formed in the surface of n⁻ semiconductor layer 102. A p⁺ semiconductor region 105 is formed to surround the n⁻ semiconductor layer 102. A cathode electrode 106 is electrically connected to n⁺ semiconductor region 104. An anode electrode 107 is electrically connected to p⁺ semiconductor region 105. A back electrode 108 is formed on the back surface of insulation substrate 103. An insulation film 109 is provided in n⁻ semiconductor layer 102 for electrically isolating n⁻ semiconductor layer 102 to provide a plurality of portions. An insulation layer 111 is provided on n⁻ semiconductor layer 102 for electrically isolating cathode and anode electrodes 106 and 107 from other portions.

[0007] The operation of the semiconductor device will now be described.

[0008] With reference to FIG. 37, when anode and back electrodes 107 and 108 are at 0V and + voltage is applied to cathode electrode 106, a depletion layer 133 extends from a pn junction between n⁻ semiconductor layer 102 and p⁺ semiconductor region 105. The extension of depletion layer 133 stops when it reaches n⁺ semiconductor region 104. Depletion layer 133 is a kind of insulator, allowing no current flow between cathode and anode electrodes 106 and 107. Such a semiconductor device is referred to as a diode.

[0009] Furthermore, addition of an insulation gate structure to this structure enables fabrication of a self-arc-extinguishing device such as an MOS (Metal Oxide Semiconductor) transistor, an IGBT (Insulated Gate Bipolar Transistor) or the like. It is noted that voltage is not allotted to insulation layer 103 in the above structure.

[0010] N⁻ semiconductor layer 102 must be large to retain the major part of electric field in order to achieve higher breakdown voltage with a semiconductor device having the above structure. While horizontal (normal to the sheet of drawings) extension of the layer can be relatively readily achieved, vertical (longitudinal direction in the drawings) extension disadvantageously expands the isolation region as large thickness t_soiof the SOI layer is required, making techniques for isolation and burying difficult.

[0011] FIG. 38 is a schematic cross sectional view showing a second example of a conventional semiconductor device. With reference to FIG. 38, n⁻ semiconductor layer 102 is formed on a semiconductor substrate 101 with a buried insulation layer 103 formed of an oxide film interposed. Since other members in the drawing are almost the same as those for the conventional semiconductor device shown in FIG. 36, the same or corresponding portions have the same reference numerals and description thereof will not be repeated here.

[0012] The operation will now be described.

[0013] With reference to FIG. 39, when anode and back electrodes 107 and 108 are at 0V and + voltage is applied to cathode electrode 106, a depletion layer A extends from a pn junction between n⁻ semiconductor layer 102 and p⁺ semiconductor region 105. At the time, semiconductor substrate 101 is generally at 0V and functions as a field plate through buried insulation layer 103, so that a depletion layer B extends from the interface between n⁻ semiconductor layer 102 and buried insulation layer 103 toward the surface of n⁻ semiconductor layer 102 in addition to the above mentioned depletion layer A. On the other hand, the electric field at the pn junction between n⁻ semiconductor layer 102 and p⁺ semiconductor region 105 is reduced as depletion layer B facilitates the extension of depletion layer A.

[0014] The effect is generally called RESURF (Reduced Surface Field) effect, and it is described in J. A. Appels et al., “HIGH VOLTAGE THIN LAYER DEVICES (RESURF DEVICES)”, IEEE IEDM Tech. Dig.,1979, pp. 238-241 that extending the pn junction along the interface rather than buried insulation layer 103 provides a similar effect.

[0015] In the above structure, a ratio of divided voltage per unit thickness of oxide film to silicon is that of a reciprocal of their dielectric constants (∈_oxi=3.9, ∈_si=11.7), that is, about 3:1. Thus, breakdown voltage can be increased by increasing the thickness of buried oxide film 3 retaining a considerable part of voltage.

[0016] This is shown FIG. 40. RESURF effect is effective in the region where breakdown voltage increases with thickness. As the thickness of a film is simply increased, breakdown voltage (BV) reversely begins to decrease at a certain value. This is because the amount of extension for depletion layer B decreases as it is away from the ground voltage of semiconductor substrate 101 assisting the extension of depletion layer B, thereby undermining electric field reduction effect for depletion layer A. Accordingly, the thickness of the buried oxide film must be around 7 μm to achieve as high a breakdown voltage as 600V. In a film formation method, however, the formation of such a film with thickness of around 7 μm disadvantageously increases cost as considerably long processing time is required as shown in FIG. 41.

[0017] A technique disclosed in Japanese patent Laying-Open No. 7-183522 will now be described as a conventional example for forming the thinnest possible buried oxide film while maintaining high breakdown voltage.

[0018] FIG. 42 is a schematic cross sectional view showing a structure of a semiconductor device disclosed in the aforementioned laid open application. With reference to FIG. 42, a semiconductor layer 102 is formed on a semiconductor substrate 101 with a buried insulation layer 103 interposed. A field oxide film layer 111band an LDMOS transistor are formed in the surface of semiconductor layer 102.

[0019] The LDMOS transistor includes a channel region 105a, a source region 105b, a drain region 104, a drift region 120, a gate oxide insulation layer 111aand a gate electrode layer 112. Channel region 105ais formed on one side of field oxide film layer 111b, whereas source region 105bis positioned in the surface of channel region 105a. Drain region 104 is positioned in the surface on the side opposite to source region 105bwith field oxide insulation layer 111asandwiched.

[0020] Gate electrode layer 112 is formed on channel region 105awith gate oxide insulation layer 111atherebetween and extends over field oxide layer 111b.

[0021] Drift region 120 is formed from the bottom surface of field oxide insulation layer 111ato that of semiconductor layer 102 and toward the side of drain region 104 from that of source region 105b, and formed of SiC (Silicon Carbide), for example.

[0022] In addition, a source electrode 107 and a drain electrode 106 are formed to be electrically connected to source and channel regions 105band 105aas well as drain region 104, respectively.

[0023] An SiC layer used for drift region 120 does not exert any influence specific to SiC in chemical treatment, photolithography and implantation diffusion steps for the surface of SOI layer, thereby allowing fabrication of a device directly using a standard Si process.

[0024] SiC has a wider band gap than Si (Silicon), the material used for forming the semiconductor layer. Thus, replacing Si by SiC can enhance avalanche electric field strength, thereby increasing breakdown voltage without increasing the thickness of buried isolation layer 103.

[0025] In this structure, however, a gate is formed offset, and therefore laterally applied voltage V concentrates in a short distance W₁between gate electrode layer 122 and drain electrode 106, increasing electric field strength. This is shown by the equipotential line and electric field strength distribution in FIGS. 43A and 43B. It is noted that FIG. 43B shows the electric field strength distribution in the surface portion of SOI layer 102 along the line XLIIIB—XLIIIB in FIG. 43A.

[0026] With reference to FIGS. 43A and 43B, avalanche electric field strength is more easily attained when electric field strength E is increased. If avalanche electric field strength is attained in the surface portion of SOI layer 102, breakdown voltage can not effectively be enhanced even when the bottom portion of the SOI layer is formed of an SiC layer. Therefore, the effect of offset can be achieved only in a limited region having relatively low breakdown voltage, which is capable of retaining the concentrated electric field in the surface by means of a field oxide film.

[0027] Further, distance W₁between gate electrode layer 112 and drain electrode 106 can be made longer to prevent the concentration of laterally applied voltage. In this case, electric field strength generally decreases as compared with FIG. 43B. Nevertheless, a high electric field region is likely to be formed locally in the opposite ends R and electric field strength peak P is in the high electric field region. Electric field strength E in the peak portion P is therefore likely to attain avalanche electric field strength, and once avalanche electric field strength is attained, breakdown voltage cannot effectively be increased as mentioned in the foregoing.

[0028] A combination of parameters required for a substrate (thickness and resistance values of SOI layer, thickness of buried insulation layer or the like) can be optimized to decrease the peak value. This may however result in disadvantageous introduction of new rate-limiting factors.

[0029] It is an object of the present invention to provide a semiconductor device having a lateral high breakdown voltage element with extremely high breakdown voltage which is not restricted by electric field concentration in the surface of an SOI layer.

[0030] A semiconductor device having a lateral high breakdown voltage element according to et first aspect of the present invention has a semiconductor layer formed on a semiconductor substrate with a buried insulation layer interposed and a high breakdown voltage element formed in the semiconductor layer, and provided with a wide band gap layer and a conductive layer for a field plate. The high breakdown voltage element includes first and second impurity regions of mutually opposite conductivity types formed on the semiconductor layer. The wide band gap layer is located at least in the region to have the highest electric field strength in the semiconductor layer when breakdown voltage is applied to the high breakdown voltage element and formed of a material having a band gap wider than that of the semiconductor layer. The conductive layer for a field plate is formed in a floating state on that region of semiconductor layer which is between first and second impurity regions with an insulation layer interposed, and is capable of storing capacitance between itself and a first electrode electrically connected to the first impurity region as well as between itself and a second electrode electrically connected to second impurity region.

[0031] In a semiconductor device having a lateral high breakdown voltage element according to the first aspect of the present invention, a conductive layer for a field plate is provided, so that electric field in the surface of the semiconductor layer can be uniformly distributed. As a result, the electric field strength in the surface of the semiconductor layer cannot attain avalanche electric field strength. Therefore, extremely high breakdown voltage can be achieved through a synergistic effect of breakdown voltage enhancement effects due to the conductive layer for a field plate and the wide band gap layer provided in the region where the highest electric field strength is attained.

[0032] In the above aspect, the wide band gap layer preferably has an SiC layer. The use of the SiC layer enables fabrication of a device directly using a standard Si process.

[0033] In the above aspect, preferably, further provided is a drift region located within the semiconductor layer between the fist and second impurity regions, having the same conductivity type as the first impurity region and lower impurity concentration than that of the first impurity region, and forming a pn junction between itself and the second impurity region. The provision of the drift region enables high breakdown voltage.

[0034] In the above aspect, preferably, first impurity region is formed in the surface of the semiconductor layer and the wide band gap layer is located near the surface of the semiconductor layer where the first impurity region is formed. As a result, even when the electric field strength near the region having the first impurity region becomes the highest, it cannot attain avalanche electric field strength.

[0035] In the above aspect, the wide band gap layer is preferably provided immediately below the first impurity region. As a result, even when the electric field strength immediately below the first impurity region becomes the highest, it cannot attain avalanche electric field strength.

[0036] In the above aspect, the wide band gap layer is preferably located on the bottom surface of the semiconductor layer on the side of the buried insulation film. As a result, even when the electric field strength in the bottom surface of the semiconductor layer becomes the highest, it cannot attain avalanche electric field strength.

[0037] In the above aspect, the wide band gap layer is preferably spaced apart from the bottom surface of the semiconductor layer on the side of buried insulation layer. As a result, the wide band gap layer can prevent the extension of an avalanche region from the bottom surface of the semiconductor layer, resulting in high breakdown voltage. Further, strong adhesion between the semiconductor layer and the buried insulation layer can readily be ensured and plastic deformation caused by the stress due to the difference in coefficient of heat expansion can be prevented as direct contact between the wide band gap layer and the buried insulation layer can be avoided.

[0038] In the above aspect, preferably, the wide band gap layer has the impurity of the same conductivity type as the drift region and the impurity concentration therefor is at least twice to at most ten times that of the drift region. As a result, a still higher breakdown voltage enhancement effect can be achieved due to still higher critical electric field strength.

[0039] A semiconductor device having a lateral high breakdown voltage element according to another aspect of the present invention has a semiconductor layer formed on a semiconductor substrate with a buried insulation layer interposed, a high breakdown voltage element formed in a semiconductor layer and a wide band gap layer. The high breakdown voltage element includes first and second impurity regions of mutually opposite conductivity types formed in the semiconductor layer, and a drift region located between the first and the second impurity regions and having the same conductivity type as the first impurity region and a lower impurity concentration than that of the first impurity region. The wide band gap layer is located at least in the region, which is to have the highest electric field strength in semiconductor layer when breakdown voltage is applied to the high breakdown voltage element, and formed of a material having a band gap wider than that of the semiconductor layer. The wide band gap layer has the impurity of the same conductivity type as the second impurity region and electrically short-circuited to the second impurity region.

[0040] In a semiconductor device having a lateral high breakdown voltage according to another aspect of the invention, a wide band gap layer has the impurity of the same conductivity type as the second impurity region and electrically connected to a second impurity region. As a result, extremely high breakdown voltage can be achieved through a synergistic effect of breakdown voltage enhancement effects due to the wide band gap layer thus formed and that provided in that region which is to have the highest electric field strength.

[0041] In the above aspect, preferably, the wide band gap layer and a third impurity region are formed adjacent to each other on the bottom surface of the semiconductor layer on the side of a buried insulation layer, and the third impurity region is of the same conductivity type as and electrically short-circuited to the second impurity region. As a result, higher breakdown voltage can be achieved.

[0042] In the above aspect, preferably, fourth and fifth impurity regions of mutually opposite conductivity types alternately located along the direction in which the bottom surface of the semiconductor layer extends is further provided. The wide band gap layer is formed to sandwich the fourth and fifth impurity regions with the second impurity region, and electrically short-circuited to the second impurity region through the fifth impurity region. As a result, carrier implantation from a collector region to a wide band gap layer can be prevented during on operation when the lateral high breakdown voltage is an IGBT, thereby increasing the number of carriers contributable to conductivity modulation and avoiding increase in on voltage.

[0043] In the above aspect, preferably, a conductive layer for a field plate is further provided which is formed on that region of the semiconductor layer which is sandwiched between the first and second impurity regions with an insulation layer interposed in a floating state, and capable of storing capacitance between itself and a first electrode electrically connected to the first impurity region as well as between itself and a second electrode electrically connected to the second impurity region. The provision of the conductive layer for a field plate allows uniform distribution of the electric field in the surface of the semiconductor layer. As a result, the electric field strength in the surface of the semiconductor layer cannot attain avalanche electric field strength. Thus, extremely high breakdown voltage can be achieved through a synergistic effect of breakdown voltage enhancement effects due to the conductive layer for a field plate and the wide band gap layer provided in the region to have the highest electric field strength.

[0044] A semiconductor device having a lateral high breakdown voltage element according to still another aspect of the present invention has a semiconductor layer formed on a semiconductor substrate with a buried insulation layer interposed, a high breakdown voltage element formed in the semiconductor layer and a wide band gap layer. The high breakdown voltage element has first and second impurity regions of mutually opposite conductivity types formed in the semiconductor layer. The wide band gap layer is located at least in the region which is to have the highest electric field strength in the semiconductor layer when breakdown voltage is applied to the high breakdown voltage element, and formed of a material having a band gap wider than that of the semiconductor layer. The wide band gap layer is porous.

[0045] In a semiconductor device having a lateral high breakdown element according to still another aspect of the present invention, a wide band gap layer is porous, so that diffusion and proliferation of avalanche current can be prevented due to the presence of pores. As a result, extremely high breakdown voltage can be achieved through a synergistic effect of an effect due to pores and a breakdown voltage enhancement effect due to a wide band gap layer provided in the region which is to have the highest electric field strength.

[0046] In the above aspect, preferably, the wide band gap layer is of the same conductivity type as a first impurity region. Thus, higher breakdown voltage can be achieved.

[0047] In the above aspect, preferably, the wide band gap layer has the impurity of the same conductivity type as and electrically short-circuited to a second impurity region. As a result, extremely high breakdown voltage can be achieved through a synergistic effect of breakdown voltage enhancement effects due to the wide band gap layer thus provided and that provided in the region which is to have the highest electric field strength.

[0048] In the above aspect, the wide band gap layer and a third impurity region are preferably formed adjacent to each other in the surface of the semiconductor layer on the side of a buried insulation layer. The third impurity region is of the same conductivity type as the second impurity region, and porous. Thus, diffusion and proliferation of avalanche current can be prevented due to pores also in the third impurity region.

[0049] In the above aspect, preferably, a conductive layer for a field plate is further provided which is formed in a floating state on that region of the semiconductor layer which is sandwiched between first and second impurity regions with an insulation layer interposed, and capable of storing capacitance between itself and a first electrode electrically connected to the first impurity region as well as between itself and a second electrode electrically connected to the second impurity region. The provision of the conductive layer for a field plate allows uniform distribution of electric field in the surface of the semiconductor layer. Thus, the electric field strength in the surface of the semiconductor layer cannot attain avalanche electric field strength. As a result, extremely high breakdown voltage can be achieved through a synergistic effect of breakdown voltage enhancement effects due to the conductive layer for a field plate and the wide band gap layer provided in the region which is to have the highest electric field strength.

[0050] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

[0051] FIG. 1 is a cross sectional view schematically showing a structure of a semiconductor device having a lateral high breakdown voltage element according to a first embodiment of the present invention.

[0052] FIG. 2 is a graph comparing breakdown voltages for a structure according to the first embodiment of the present invention and a conventional structure without an SiC layer.

[0053] FIG. 3 is a partial sectional view showing in enlargement a part of a capacitive coupled multiple field plate shown in FIG. 1.

[0054] FIG. 4 is a view showing a function of the capacitive coupled multiple field plate.

[0055] FIGS. 5A to 5C are diagrams showing the uneven distribution of electric field can be prevented in the semiconductor device having a lateral high breakdown voltage element according to the first embodiment of the present invention, where FIG. 5A shows electric field distribution, FIG. 5B electric field strength distribution along the line VB—VB in FIG. 5A and FIG. 5C electric field strength distribution along the line VC—VC in FIG. 5A.

[0056] FIG. 6 is a cross sectional view schematically showing a structure of a semiconductor device having a lateral high breakdown voltage element according to a second embodiment of the present invention.

[0057] FIGS. 7 to 10 are first to fourth diagrams showing electric field concentration.

[0058] FIG. 11 is a diagram showing how a breakpoint changes with the impurity concentration in an SOI layer.

[0059] FIGS. 12 to 15 are cross sectional views schematically showing a structure of a semiconductor device having a lateral high breakdown voltage element according to third to sixth embodiments of the present invention.

[0060] FIG. 16 is a graph showing impurity concentration distribution along the line XVI—XVI in FIG. 15.

[0061] FIGS. 17 to 19 are cross sectional views schematically showing a structure of a semiconductor device having a lateral high breakdown voltage element according to seventh to ninth embodiments of the present invention.

[0062] FIG. 20 is a schematic cross sectional view taken along the line XX—XX in FIG. 19.

[0063] FIGS. 21 to 23 are cross sectional views schematically showing a structure of a semiconductor device having a lateral high breakdown voltage element according to tenth to twelfth embodiments of the present invention.

[0064] FIG. 24 is a schematic cross sectional view taken along the line XXIV—XXIV in FIG. 23.

[0065] FIGS. 25 to 28 are schematic cross sectional views showing in order a method of manufacturing a semiconductor device having a lateral high breakdown voltage element according to a thirteenth embodiment of the present invention.

[0066] FIGS. 29 to 31 are schematic cross sectional views showing in order a method of manufacturing a semiconductor device having a lateral high breakdown voltage element according to a fourteenth embodiment of the present invention.

[0067] FIGS. 32 to 35 are schematic cross sectional views showing in order a method of manufacturing a semiconductor device having a lateral high breakdown voltage according to a fifteenth embodiment of the present invention.

[0068] FIG. 36 is a schematic cross sectional view showing a first example of a semiconductor device having a conventional lateral high breakdown voltage element.

[0069] FIG. 37 is a view showing the operation of the high breakdown voltage element shown in FIG. 36.

[0070] FIG. 38 is a schematic cross sectional view showing a second example of a semiconductor device having a conventional lateral breakdown voltage element.

[0071] FIG. 39 is an illustration showing the operation of the lateral high breakdown voltage element shown in FIG. 38.

[0072] FIG. 40 is a graph showing the change in breakdown voltage with the thickness of a buried oxide film.

[0073] FIG. 41 is a graph showing a relation between oxidation time and the thickness of oxide film when a buried oxide film is formed by means of film formation method.

[0074] FIG. 42 is a cross section schematically showing a structure of a semiconductor device disclosed in aforementioned laid open application.

[0075] FIGS. 43A and 43B are diagrams showing that electric field is unevenly distributed in the structure shown in FIG. 42, where FIG. 43A shows electric field distribution and FIG. 43B electric field strength distribution along the line XLIIIB—XLIIIB in FIG. 43A.

[0076] Embodiments of the present invention will now be described with reference to the drawings.

[0077] First Embodiment

[0078] With reference to FIG. 1, an n⁻ semiconductor layer (SOI layer) 2 is formed on a semiconductor substrate 1 with a buried insulation 3 interposed. A diode is formed in the n⁻ semiconductor layer 2.

[0079] The diode has an n⁺ semiconductor region 4 and a p⁺ semiconductor region 5. The region of n⁻ semiconductor layer 2 is herein used as an n⁻ drift region as it is and forms a pn junction with p⁺ semiconductor region 5. Further, p⁺ semiconductor region 4 is formed in the surface of semiconductor layer 2 within n−drift region 2.

[0080] Cathode and anode electrodes 6 and 7 are formed to be electrically connected to the n⁺ semiconductor region 4 and p⁺ semiconductor region 5, respectively. An insulation layer 11 is provided on n⁻ semiconductor layer 2 for electrically isolating cathode and anode electrodes 6 and 7 from other portions.

[0081] In the lateral high breakdown voltage element such as this diode, a wide band gap layer 20 is formed at least in a region which is to have the highest electric field strength within n⁻ semiconductor layer 2 when breakdown voltage is applied (for example when 0V and + voltage are applied to anode and cathode electrodes 7 and 6, respectively). The wide band gap layer 20 is formed of a material, such as SiC, having a band gap wider than Si used for semiconductor layer 2.

[0082] A capacitive coupled multiple field plate including a plurality of conductive layers 31 and 32 is formed on insulation layer 11 between cathode and anode electrodes 6 and 7. Each of the plurality of conductive layers 31 and 32 is insulated by insulation layer 33 and formed in a floating state (in an island state).

[0083] A back electrode 8 is formed on the back surface of semiconductor substrate 1.

[0084] In the semiconductor device having such a lateral high breakdown voltage element, a high electric field region is locally formed in the bottom portion of SOI layer 2 due to electric field concentration when reverse blocking voltage is applied (when breakdown voltage is applied). This is well known, for example from Akiyama et al., Materials from Association of Electronic Device-Semiconductor Power Conversion, EDD-92-106 (SPC-92-72), 1992 or the like. Then, noting that avalanche electric field strength for SiC is 4.0×10⁶V/cm, approximately one order of magnitude higher than 3.7×10⁵V/cm for Si, an SiC thin film layer 20 having thickness of about 0.4 to 0.6 μm can be applied to the portion likely to have the highest electric field strength in SOI layer 2 in order to essentially enhance avalanche resistance amount and breakdown voltage.

[0085] Accordingly, how much breakdown voltage can effectively be improved in the present invention as compared with a conventional example was calculated by means of device simulation. The condition and result will now be described.

[0086] First, the inventive example is defined as a device having SiC layer 20 as shown in FIG. 1, whereas a conventional example is defined as that without SiC layer. In addition, the common conditions for SOI substrates is that the thickness of the SOI layer is 15 μm, the thickness of the buried oxide film is 5 μm and the distance between A (anode) and K (cathode) of the device is 88 μm. Based on the common conditions, the breakdown voltages for the present and conventional examples are compared using Si-SOI resistivity as a parameter. The result is shown in FIG. 2.

[0087] With reference to FIG. 2, although the conventional and inventive examples are different in that RESURF effect is seen at 6 Ω·cm or more for the conventional example and at 10 Ω·cm for the inventive example, the highest breakdown voltages are 661V and 1126V, respectively, the inventive example resulting in breakdown voltage enhancement effect twice as high as that for the conventional example. This confirmed the fact that the provision of SiC film layer in the region which would have locally high electric field can increase breakdown voltage.

[0088] The mere provision of SiC layer 20 can, however, result in extremely limited breakdown voltage enhancement effect due to uneven distribution of electric field strength as in the conventional example shown in FIG. 42. The present embodiment therefore provides capacitive coupled multiple field plates 31 and 32 between cathode and anode electrodes 6 and 7.

[0089] The capacitive coupled multiple field plates 31 and 32 form a capacitor between cathode and anode electrodes 6 and 7 with conductive layers 31 and 32 when potential is applied to cathode and anode electrodes 6 and 7 as shown in FIG. 3. As shown in FIG. 4, a plurality of capacitors are connected in series between cathode and anode electrodes 6 and 7.

[0090] Such capacitors between cathode and anode electrodes 6 and 7 make lines of electric force in the surface of a semiconductor layer 2 almost uniform as shown in Fig. 5A. As a result, electric field strength on the surface side of semiconductor layer 2 is almost uniformly distributed as shown in FIG. 5B, avoiding uneven distribution of electric field strength.

[0091] Thus, although only the bottom portion of semiconductor layer 2 has relatively high electric field strength, breakdown voltage can be even more effectively increased because of an SiC thin film layer 20 formed in the bottom portion. In other words, the present embodiment provides uniform distribution of electric field strength in semiconductor layer 2 by replacing the region where avalanche is experienced with SiC thin film layer 20 to increase electric field strength at which avalanche is caused, and at the same time provides a capacitive coupled multiple field plate in the surface portion of semiconductor layer 2. A lateral high breakdown voltage element with much higher breakdown voltage than in the conventional examples can be achieved only through synergizing these two effects.

[0092] Second Embodiment

[0093] With reference to FIG. 6, an SiC thin film layer 20 is formed in the surface of a semiconductor layer 2 in the present embodiment.

[0094] It is noted that other parts of the structure are almost the same as those in the above mentioned first embodiment (FIG. 1), and therefore the same component has the same reference numeral and the description thereof is will not be repeated here.

[0095] The structure of the present embodiment is effective in manufacturing an SOI active layer substrate 2 with resistivity higher than that optimally required for maintaining high breakdown voltage due to RESURF effect in a power device, especially from the need in designing, such as in the case of one chip inverter where a power device and a logic IC (Integrated Circuit) are formed together. This is described in the following in further detail.

[0096] FIGS. 7 to 10 are diagrams showing potential distributions for different impurity concentrations in the SOI layer which are herein incorporated from the above mentioned reference Akiyama, Materials from association of Electronic Device-Semiconductor Power Conversion, EDD-92-106 (SPC-92-72), 1992. Impurity concentrations Nsoi for each SOI layer are 5.0×10¹⁴cm⁻³in FIG. 7, 1.0×10¹⁵cm⁻³in FIG. 8, 2.0×10¹⁵cm⁻³in FIG. 9 and4.0×10¹⁵cm⁻³in FIG. 10, respectively.

[0097] With reference to FIGS. 7 to 10, electric field is concentrated in the surface side of the SOI active layer at a higher resistivity of 10 Ω·cm (5×10¹⁴cm⁻³in FIG. 7) and 5 Ω·cm (1×10¹⁵cm⁻³in FIG. 8), on the bottom side of the SOI active layer at a resistivity of 3 Ω·cm (2×10¹⁵cm⁻³in FIG. 9) and RESURF effect is reduced at a lower resistivity of 1 Ω·cm (4×10¹⁵cm⁻³in FIG. 10). The change in the position of a breakpoint due to electric field concentration for these changes in impurity concentration is shown FIG. 11.

[0098] With reference to FIG. 11, the position of a breakpoint due to electric field concentration is in the surface of the SOI layer (a, b) with relatively low concentration in the SOI layer, moves to the bottom portion of the SOI layer (c) with increased impurity concentration in the SOI layer, and then to the junction surface (d) between a p⁺ semiconductor region and an n−semiconductor region. It is noted that reference numerals a, b, c and d in the drawing respectively correspond to conditions in FIGS. 7 to 10.

[0099] As shown in FIG. 6, in the present embodiment, SiC layer 20 is formed on the surface of SOI layer 2, resulting in extremely high breakdown voltage enhancement effect under the condition of higher resistivity in the SOI active layer corresponding to a and b in FIG. 11.

[0100] Third Embodiment

[0101] With reference to FIG. 12, in the present embodiment, an SiC thin film layer 20 is located immediately below a cathode electrode 6 in the bottom surface of a semiconductor layer 2. It is noted that other parts of the structure are almost the same as those in the first embodiment shown in FIG. 1, and therefore the same component has the same numeral and the description thereof will not be repeated here.

[0102] In the present embodiment, as described in conjunction with c in FIG. 11, extremely high breakdown voltage enhancement effect can be achieved when the breakdown voltage determined by RESURF effect causes avalanche phenomenon immediately below cathode electrode 6 in the bottom surface portion of SOI layer 2.

[0103] Fourth Embodiment

[0104] With reference to FIG. 13, in the present embodiment, an SiC thin film layer 20 is selectively formed near an n⁺ semiconductor region 4 in the surface of a semiconductor layer 2. It is noted that the other part of the structure is almost the same as that in the first embodiment shown in FIG. 1, and therefore the same component has the same reference numeral and the description thereof will not be repeated here.

[0105] In the present embodiment, extremely high breakdown voltage enhancement effect can be achieved when the breakdown voltage determined by RESURF effect causes avalanche phenomenon in the surface portion of a semiconductor layer 2 right below a cathode electrode 6 as shown at a and b in FIG. 11.

[0106] Fifth Embodiment

[0107] With reference to FIG. 14, in the present embodiment, an SiC thin film layer 20 is spaced apart from the bottom surface of a semiconductor layer 2 by a distance d. The distance d is 0.5 μm at most. It is noted that the other parts of the structure are almost the same as those shown in the first embodiment shown in FIG. 1, and therefore the same component has the same reference numeral and description thereof will not be repeated here.

[0108] In the present embodiment, as described in conjunction with c in FIG. 11, extremely high breakdown voltage enhancement effect can be achieved when the breakdown voltage determined by RESURF effect causes avalanche phenomenon in the bottom surface potion of a semiconductor layer 2 immediately below a cathode electrode 6.

[0109] When breakdown voltage is applied, avalanche phenomenon keeps increasing starting from an avalanche phenomenon starting point indicated at a point C₁in FIG. 14 until it reaches an SiC thin film layer 20 separated by distance d, where the extension of the avalanche region is restrained. In addition, as distance d is relatively short and 0.5 μm at most, a stage for rate-limiting breakdown voltage characteristics is not attained, and finally, breakdown voltage is not determined until avalanche phenomenon proceeds in SiC thin film layer 20. As a result, high breakdown voltage is achieved.

[0110] Further, a structure of the present embodiment is effective when an interface of SiC thin film layer 20 and a buried insulation layer 3 directly adjacent to each other is to be avoided in device processing as SiC thin film layer 20 is formed spaced apart from the interface. It is especially effective, for example, when strong adhesion cannot be readily ensured or plastic deformation may occur in the SOI substrate due to the stress caused by the difference in coefficients of thermal expansion.

[0111] Sixth Embodiment

[0112] With reference to FIGS. 15 and 16, in the present embodiment, although an SiC thin film layer 20 is located in the same position as that in the first embodiment shown in FIG. 1, the impurity concentration distribution in the SiC thin film layer 20 differs from that in the first embodiment. In the present embodiment, the impurity of the same conductivity type (n type) as a semiconductor layer 2 is contained in the SiC thin film layer 20 having a concentration from at least twice to at most ten times that of the impurity in semiconductor layer 2. It is noted that the other parts of the structure are almost the same as those in the first embodiment shown in FIG. 1, and therefore the same component has the same reference numeral and the description thereof will not be repeated here.

[0113] A solid line indicating impurity concentration distribution in the SiC thin film layer in FIG. 16 shows a conventional example, a dotted line shows impurity concentration distribution generally admitted when SiC thin film layer 20 is formed by means of C (carbon) ion implantation in the semiconductor layer (the first example of the present invention), and a chain-dotted line shows impurity concentration distribution for the present embodiment (the second example of the present invention).

[0114] Although it is apparent that the first example of the present invention in FIG. 16 can achieve breakdown voltage enhancement effect as compared the conventional example, the second example of the present invention can achieve still higher breakdown voltage enhancement effect as compared with the first example of the present invention. This is because still higher critical electric field strength can be achieved with higher impurity concentration in SiC thin film layer 20 where avalanche phenomena starts within the range satisfying a condition for depletion required for RESURF effect when reverse blocking voltage applied.

[0115] Seventh Embodiment

[0116] With reference to FIG. 17, in the present embodiment, an SiC thin film layer 20 is formed on the bottom surface of an SOI layer 2 and is the opposite conductivity type (p type) of an n⁻ semiconductor layer 2. A p⁻ semiconductor region 5aformed adjacent to SiC thin film layer 20 is formed on SiC thin film layer 20 to be also electrically short-circuited to a p⁺ semiconductor region 5. Impurity concentrations of p⁻ semiconductor region 5aand SiC thin film layer 20 are lower than that of p⁺ semiconductor region 5.

[0117] It is noted that the other parts of the structure are almost the same as those in a first embodiment shown in FIG. 1, and therefore the same component has the same reference numeral and the description thereof will not be repeated here.

[0118] The operation will now be described.

[0119] With reference to FIG. 17, a depletion layer starts extending from a junction interface between n⁻ semiconductor layer 2 and p⁺ semiconductor region 5 as well as that between p⁻ semiconductor region 5aand n⁻ semiconductor layer 2. The extension of the depletion layer extending from both portions can be promoted by RESURF effect. Reducing p type impurity concentration for p⁻ semiconductor region 5aand SiC thin film layer 20 to approximately the same level of concentration for n⁻ semiconductor region 2 allows complete depletion of both of thin film layers 20 and 5awith relatively low reverse bias voltage, and the voltage exceeding the low reverse bias voltage will be allotted to a buried insulation layer 3.

[0120] In the present embodiment, the provision of SiC thin film layer 20 makes it possible to set electric field strength allowing avalanche in the portion having concentrated electrode field strength higher by one order of magnitude, so that higher breakdown voltage can be achieved as described in the first embodiment.

[0121] Eight Embodiment

[0122] With reference to FIG. 18, in the present embodiment, an SiC thin film layer 20 has the opposite conductivity type (p type) of an n⁻ semiconductor layer 2 and is electrically directly short-circuited to a p⁺ semiconductor region 5. In addition, SiC thin film layer 20 has impurity concentration lower than that of p⁺ semiconductor region 5. It is noted that the other parts of the structure are almost same as those in the first embodiment shown in FIG. 1, and therefore the same component has the same reference numeral and the description thereof will not be repeated here.

[0123] The operation of the present embodiment is almost the same as that in the seventh embodiment shown in FIG. 17.

[0124] Further, in the present embodiment, the provision of SiC thin film layer 20 makes it possible to set electric field strength allowing avalanche in the portion having concentrated electric field strength higher by one order of magnitude, so that higher breakdown voltage can be achieved as described in the first embodiment.

[0125] Ninth Embodiment

[0126] FIG. 19 is a cross section taken along the line XIX—XIX in FIG. 20. A semiconductor substrate under a buried insulation layer 3 is conveniently omitted for description.

[0127] With reference to FIGS. 19 and 20, a lateral high breakdown voltage element in the present embodiment is an IGBT which includes a p⁺ semiconductor region 5a, an n⁺ emitter region 5b, an n type semiconductor region 4a, a p⁺ collector region 4band a gate electrode layer 12.

[0128] The region of n⁻ semiconductor layer 2 is herein used as it is as an n⁻ drift region, forming a pn junction with p⁺ semiconductor region 5a. The n⁺ emitter region 5bis formed in the surface of p⁺ semiconductor region 5a. Further, n type semiconductor region 4ais formed in the surface of n⁻ drift region 2 and p⁺ collector region 4bis formed in the surface of n type semiconductor region 4a. A gate electrode layer 12 is formed to face the surface region of p⁺ semiconductor region 5asandwiched between n⁺ emitter region 5band n⁻ drift region 2 with a gate insulation layer (not shown) interposed.

[0129] Further, a p⁻ SiC thin film layer 20ais formed immediately below n type semiconductor region 4ain the bottom surface of a semiconductor layer 2. The n⁻ drift region 2 and p⁻ semiconductor region 5care alternately formed along the bottom surface of semiconductor layer 2 between p⁻ SiC thin film layer 20 and p⁺ semiconductor region 5a. The p⁻ SiC thin film layer 20 is electrically short-circuited to p⁺ semiconductor region 5awith p⁻ semiconductor region 5cinterposed.

[0130] In a plan view shown in FIG. 20, preferably, p⁻ semiconductor region 5coccupies at most twenty percent and n⁻ drift region 2 occupies at least eighty percent.

[0131] In the present embodiment, a depletion layer extends and high breakdown voltage can be achieved upon application of reverse bias basically in the same manner as in the above described seventh and eighth embodiments. Another advantage can additionally be obtained as an IGBT during on operation in the present embodiment. This is now described.

[0132] Hole current (h⁺) introduced from a p⁺ collector region 4bduring on operation of the IGBT is likely to be re-introduced in p⁻ SiC thin film layer 20 located at a very short distance. In an IGBT, accumulation of sufficient current carriers in n⁻ drift region 2 in a turn on process allows low resistance condition referred to as conductivity modulation due to electron—hole pair, and the turn on process is completed. On the other hand, re-introduction of hole current (h⁺) into p⁻ SiC thin film layer 20 may disadvantageously decrease the number of holes to be accumulated within n⁻ drift region 2 and increase on voltage, as the ratio contributable to conductivity modulation decreases.

[0133] Accordingly, the present embodiment provides higher resistance Rh⁺ for p⁻ semiconductor region 5cby adopting a structure having alternately arranged p⁻ semiconductor region 5cand n⁻ drift region 2 as shown in FIG. 20. The high resistance Rh⁺ makes it difficult for hole current introduced into p⁻ SiC thin film layer 20 to flow into the p⁺ semiconductor region, thereby preventing introduction of hole current into p⁻ SiC thin film layer 20. As a result, the decrease in the number of holes to be accumulated within the n⁻ drift region can be prevented, thereby avoiding the increase in on voltage.

[0134] It is noted that a capacitive coupled multipled field plate can be provided also in the present embodiment.

[0135] Tenth Embodiment

[0136] With reference to FIG. 21, in the present embodiment, a porous n⁻ SiC thin film layer 20 is formed over the entire bottom surface of a semiconductor layer 2 and adjacent to an n⁻ drift layer 2 and a buried insulation layer 3. It is noted that other parts of the structure are almost the same as those in the first embodiment shown in FIG. 1, and therefore the same component has the same reference numeral and the description thereof will not be repeated here.

[0137] Means for making a porous SiC thin film layer 20 is disclosed, for example, in Liang-Sheng Liao et al., “Intense blue emission from porous β-SiC formed on C⁺-implanted silicon”, Appl. Phys. Lett. 66 (18), pp. 2382-2384, May 1, 1995. According to the disclosed method, a porous layer can be achieved through relatively simple electric field wet treatment, and the thickness of pore formation layer, pore diameter and pore density are sufficiently controllable.

[0138] Application of reverse bias to thus formed device allows rapid depletion of the entire region of semiconductor layer 2 while basically maintaining RESURF effect, so that the portion close to a cathode of porous n⁻ SiC thin film layer 20 has the highest electric field strength. Although avalanche current generates from SiC thin film layer 20 as the strength comes near to avalanche electric field strength, the diffusion and proliferation thereof can be prevented because of pores. As a result, still higher breakdown voltage can be achieved in addition to the above described effects in the seventh to ninth embodiments.

[0139] Eleventh Embodiment

[0140] With reference to FIG. 22, in the present embodiment, a porous p⁻ SiC thin film layer 20 is formed on the bottom surface of a semiconductor layer 2 and a p⁻ semiconductor region 30 is formed over and adjacent to the p⁻ SiC thin film layer 20. The p⁻ SiC thin layer 20 and a p⁻ semiconductor region 30 are electrically short-circuited to a p⁺ semiconductor region 5 and are made porous. It is noted that the other parts of the structure are almost the same as those in the first embodiment shown in FIG. 1, and therefore the same component has the same reference numeral and the description thereof will not be repeated.

[0141] Anodized current flows only within p⁻ SiC thin film layer 20 which is a p type semiconductor region and p⁻ semiconductor region 30, so that these layers 20 and 30 can controllably be made porous.

[0142] In the present embodiment, higher breakdown voltage can be achieved upon application of reverse bias for the same reason as in the tenth embodiment.

[0143] Twelfth Embodiment

[0144] FIG. 23 is a cross section taken along the line XXIII—XXIII in FIG. 24.

[0145] With reference to FIGS. 23 and 24, in the present embodiment, a p⁻ SiC thin film layer 20 in the bottom surface of a semiconductor layer 2 is made porous. A p⁻ semiconductor region 5clocated between p⁻ SiC thin film layer 20 and a p⁺ semiconductor region 5ais also made porous.

[0146] It is noted that other parts of the structure are almost the same as those in the ninth embodiment shown in FIGS. 19 and 20, and therefore the same component has the same reference numeral and the description thereof will not be repeated here.

[0147] The advantage of higher breakdown voltage upon application of reverse bias and the effect of preventing the increase in on voltage during on operation in the present embodiment are the same as those mentioned in the ninth embodiment.

[0148] In addition, porous p⁻ SiC thin film layer 20 and p⁻ semiconductor region 5ccan prevent the diffusion and proliferation of avalanche current as described in the tenth and eleventh embodiments, so that higher breakdown voltage can be achieved.

[0149] It is noted that a capacitive coupled multiple field plate can be provided in the present invention.

[0150] Thirteenth Embodiment

[0151] A method of manufacturing an SOI substrate of a semiconductor device according to the above mentioned first, third and fourth embodiments will now be described as a thirteenth embodiment.

[0152] First, with reference to FIG. 25, C (carbon) ion is implanted in the surface on the side for application of a semiconductor layer 2 formed of silicon. The temperature should be maintained at 800° C. or higher during implantation and dosage is not less than 1×10¹⁶cm⁻².

[0153] With reference to FIG. 26, SiC is crystallized by heat treatment at 1100° C. or higher for at least 3 hours after C ion implantation to form an SiC thin film layer 20 in semiconductor layer 2.

[0154] With reference to FIG. 27, the surface on the side for application of semiconductor layer 2 is precisely polished by means of CMP (Chemical Mechanical Polishing) or the like, and a part or entire portion of the thin film SiC layer 2 remaining on the side for application of SiC thin film layer 20 is removed. As a result, the surface on the side for application of semiconductor substrate 2 is planarized.

[0155] With reference to FIG. 28, a buried oxide film 3 and a silicon substrate 1 are applied over the surface on the side for application of semiconductor layer 2 and an SOI substrate is formed.

[0156] The application in accordance with the manufacturing method according to the present embodiment allows yield increase and manufacture of the SOI substrate having a stable applied interface characteristics.

[0157] Fourteenth Embodiment

[0158] With reference to FIG. 29, an implantation thick film mask 40, formed of a silicon oxide film (SiO₂film) or a silicon nitride film (Si₃N₄film) having thickness of at least 2000 Å is formed over the surface on the side for application of a semiconductor layer 2 formed of silicon.

[0159] With reference to FIG. 30, C ion is implanted into semiconductor substrate 2 through implantation thick film mask 40. The temperature should be maintained at least at 800° C. during implantation and dosage is at least 1×10¹⁶cm⁻².

[0160] With reference to FIG. 31, SiC is crystallized by heat treatment at 1100° C. or higher for at least 3 hours after the C ion implantation to form an SiC thin film layer 20 in semiconductor layer 2. Meanwhile, SiC is crystallized while the surface on the side for application of semiconductor layer 2 is kept planar because of the presence of implantation thick film mask 40.

[0161] Subsequently, an SOI substrate is formed through similar steps in the thirteenth embodiment shown in FIGS. 27 and 28 after removal of implantation thick film mask 40.

[0162] The application in accordance with the manufacturing method of the present embodiment allows yield increase and the manufacture of an SOI substrate having a stable applied interface characteristics.

[0163] Implantation thick film mask 40 can also be formed by means of sputtering of SiC, plasma CVD or the like. This is especially effective when introduction of different impurity may have adverse affect device characteristics, such as a knock on phenomena, during C ion implantation.

[0164] Fifteenth Embodiment

[0165] With reference to FIG. 32, implantation thick film mask 40 is formed over the surface on the side for application of a silicon substrate 2.

[0166] With reference to FIG. 33, Si ion is implanted into silicon layer 2 through implantation thick film mask 40. Thus, an amorphous silicon layer 2ais formed in a prescribed position in a semiconductor layer 2.

[0167] With reference to FIG. 34, C ion is implanted into silicon layer 2 through implantation thick film mask 40 with a shallower range than Si ion implantation (FIG. 33).

[0168] With reference to FIG. 35, SiC is crystallized by heat treatment at 1100° C. or higher for at least 3 hours after C ion implantation to form an SiC thin film layer 20 in semiconductor layer 2. Meanwhile, SiC crystallization proceeds in a direction toward the back side because of the presence of amorphous layer 2a, facilitating control of SiC crystal. In addition, SiC crystallization proceeds while the surface side is kept crystallized and planarized because of implantation thick film mask 40.

[0169] It is noted that though the above mentioned thirteenth to fifteenth embodiments are all based on C ion implantation, there are other applications based on a method of forming SiC by means of film formation such as CVD, disclosed, for example, in Japanese Patent Laying-Open No. 1-135070 or European Patent Application (EP-0317-445-B1) as an example which can result in a similar structure. The thirteenth to fifteenth embodiments of the present invention is effective in that planarization can be basically maintained during application and a combination for application can be selected from Si/SiO₂, SiC/SiO₂, SiC/Si, SiO₂/SiO₂and the like, according to the purpose.

[0170] Further, while the SiC thin film layer is described as a wide band gap layer 20 in the first to fifteenth embodiments above, any material having a band gap wider than semiconductor layer 2 can be used. In addition, the material for wide band gap layer 20 is more preferably a material allowing fabrication of a device directly using a standard Si process.

[0171] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.