US 8,519,438 B2Grant
Enhancement mode III-N HEMTs
Issue Date:2013-08-27
•58 Claims
•16 Drawing Sheets
Abstract
A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.
Metadata
Assignee
- Transphorm Inc.
Inventors
- Umesh Mishra
- Robert Coffie
- Likun Shen
- Ilan Ben-Yaacov
- Primit Parikh
Application Information
Application Number:US 12/108,449
Filing Date:2008-04-23
Priority Date:2008-04-23
Art Unit:2896
Classifications
IPC:
H01L29/66
Patent Drawings (16 sheets)
Description
Technical Field
[0001] This invention relates to enhancement mode III-nitride devices.
Background
[0002] Most power semiconductor devices, including devices such as power MOSFETs and insulated gate bipolar transistors (IGBTs), typically have been fabricated with silicon (Si) semiconductor material. More recently, silicon carbide (SiC) power devices have been considered due to their superior properties. III-N semiconductor devices, such as gallium nitride (GaN) devices are now emerging as attractive candidates to carry large currents, support high voltages and to provide very low on-resistance and fast switching times.
[0003] Typical GaN high electron mobility transistors (HEMTs) and related devices are normally on, which means that they conduct current at zero gate voltage. These typical devices are known as depletion mode (D-mode) devices. However, it is more desirable in power electronics to have normally off devices—called enhancement mode (E-mode) devices—that do not conduct current at zero gate voltage and thus avoid damage to the device or to other circuit components by preventing accidental turn on of the device.
[0004] FIG. 1 shows a prior art Ga-face GaN HEMT depletion mode structure. Substrate 10 may be GaN, SiC, sapphire, Si, or any other suitable substrate upon which a GaN device may be formed. GaN buffer layer 14 and AlxGaN layer 18 on top of it are oriented in the [0 0 0 1] (C-plane) direction. The conducting channel consists of a two-dimensional electron gas (2 DEG) region, shown by a dotted line in GaN buffer layer 14 in FIG. 1 , is formed in layer 14 near the interface between layer 14 and AlxGaN layer 18. A thin, 0.6 nm AlN layer (not shown) is optionally included between GaN layer 14 and AlxGaN layer 18 in order to increase the charge density and mobility in the 2 DEG region. The region of layer 14 between the source 27 and the gate 26 is referred to as the source access region. The region of layer 14 between the drain 28 and gate 26 is referred to as the drain access region. The source 27 and drain 28 both make contact with buffer layer 14. With no applied gate voltage, the 2 DEG region extends all the way from the source 27 to the drain 28, forming a conducting channel and rendering the device normally on, making it a depletion mode device. A negative voltage must be applied to the gate 26 to deplete the 2 DEG region under the gate 26, and thus to turn the device OFF.
[0005] Another related prior art III-N HEMT device is the subject of provisional application Ser. No. 60/972,481, filed Sep. 14, 2007, entitled “III-N Devices with Recessed Gates,” which application is hereby incorporated by reference herein.
Brief Summary
[0006] The device of the invention is an enhancement mode HEMT. Different from a depletion mode HEMT, an enhancement-mode HEMT has two requirements. First, the source and drain access regions should contain a 2 DEG region that results in a conductivity of those regions at least as large as the conductivity of the channel region beneath the gate when the device is in the ON state. Preferably, the conductivity of these access regions is as large as possible, as access resistance is thereby reduced, thus reducing the on-resistance Ron—a desirable characteristic for a switching device. The second requirement of an enhancement mode HEMT is for the channel region underneath the gate to have no 2 DEG at zero gate voltage. A positive gate voltage therefore is required to induce a 2 DEG charge in this region beneath the gate, and thus to turn the device ON.
[0007] Therefore, at all times (whether the device is on or off), an E-mode HEMT has a 2 DEG region across both the access regions. When 0V is applied to the gate, there is no 2 DEG under the gate, but when a large enough voltage is applied to the gate (i.e., Vgs>Vth) a 2 DEG region forms underneath the gate and the channel becomes fully conductive between source and drain.
[0008] Briefly, the disclosed semiconductor device includes a substrate and a nitride channel layer on the substrate, the channel layer including a first channel region beneath a gate region, and two channel access regions on opposite sides of the first channel region. The composition of the nitride channel layer is selected from the group consisting of the nitrides of gallium, indium and aluminum, and combinations thereof. Adjacent the channel layer is an AlXN layer wherein X is selected from the group consisting of gallium, indium or their combination. An n-doped GaN layer is adjacent the AlXN layer in the areas adjacent to the channel access regions, but not in the area adjacent to the first channel region beneath the gate region.
[0009] The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration and doping profile in the n-doped GaN layer all are selected to induce a 2 DEG charge in channel access regions adjacent the AlXN layer, without inducing any substantial 2 DEG charge in the first channel region beneath the gate, so that the channel is not conductive in the absence of a control voltage applied to the gate, but can readily become conductive when a control voltage is applied to the gate.
[0010] A similar disclosed semiconductor device includes a substrate, a nitride channel layer on the substrate including a first channel region beneath a gate region, and two channel access regions on opposite sides of the first channel region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof. The device also has a first AlXN layer adjacent the channel layer wherein X is selected from the group consisting of gallium, indium or their combination, and a second AlXN layer adjacent the first AlXN layer, the first AlXN layer having a substantially higher concentration of Al than the second AlXN layer.
[0011] In this device, the concentration of the Al in each of the first and second AlXN layers, respectively, and their respective thicknesses are selected to induce a 2 DEG charge in channel access regions adjacent the first AlXN layer, without inducing any substantial 2 DEG charge in the first channel region beneath the gate, so that the channel is not conductive in the absence of a control voltage applied to the gate, but can readily become conductive when a control voltage is applied to the gate.
[0012] Another disclosed device includes a substrate, a nitride channel layer on the substrate, including a first channel region, the material of which is selected from the group consisting of nitrides of gallium, indium, aluminum and combinations thereof. The device further comprises an AlXN layer adjacent to the channel and a III-N adjacent to the AlXN layer, the III-N layer also including two channel access region on the opposite sides of the gate, wherein X is selected from the group consisting of gallium, indium or their combination, and the III material is Al, Ga or In. The channel access regions in this device are in a different layer from the channel region being modulated by the gate.
[0013] In the above devices, a nitride layer, such as AlN, may be interposed between the AlXN layer and the nitride channel layer.
Description of the Drawings
[0014] FIG. 1 is a cross-sectional view of a device of the prior art.
[0015] FIG. 2 is a cross-sectional view of a device of one embodiment of the invention.
[0016] FIGS. 3 a and 3b are graphs showing the relationship of the thickness of one layer of the device of FIG. 2 and the sheet charge density.
[0017] FIG. 4 is a cross-sectional view of a device of another embodiment of the invention.
[0018] FIG. 5 is a cross-sectional view of a device of another embodiment of the invention.
[0019] FIG. 6 is a cross-sectional view of a device of another embodiment of the invention.
[0020] FIG. 7 is a graph showing the transfer characteristics of the device of FIG. 5 .
[0021] FIGS. 8 a-8d show a method of fabrication for the device of FIG. 9 .
[0022] FIG. 9 is a cross-sectional view of a device of another embodiment of the invention.
[0023] FIG. 10 is a cross-sectional view of a device of another embodiment of the invention.
[0024] FIG. 11 is a cross-sectional view of a device of another embodiment of the invention.
[0025] FIG. 12 is a cross-sectional view of a device of another embodiment of the invention.
[0026] FIGS. 13 a and 13b are cross-sectional views of a device of another embodiment of the invention.
[0027] FIGS. 14 a and 14b are cross-sectional views of a device of another embodiment of the invention.
[0028] FIG. 15 is a cross-sectional view of a device of another embodiment of the invention.
[0029] FIG. 16 is a cross-sectional view of a device of another embodiment of the invention.
[0030] FIG. 17 is a cross-sectional view of a device of another embodiment of the invention.
[0031] FIGS. 18 a and 18b are cross-sectional views of a device of two other embodiments of the invention.
[0032] FIGS. 19-23 are cross-sectional views of devices of other embodiments of the invention.
[0033] FIGS. 24 a, 24b and 24c are graphs depicting the operation of the device of FIG. 23 .
Description of Preferred Embodiments
[0034] FIG. 2 shows one embodiment of an E-mode GaN HEMT device of this invention. Substrate 30 may be GaN, SiC, sapphire, Si, or any other suitable substrate for a GaN device as is known in the art. Nitride channel layer 34 may be placed upon substrate 30. This layer may be a nitride of gallium, indium or aluminum, or combinations of those nitrides. A preferred material is GaN. Layer 34 may be made semi-insulating, such as by doping with iron. Preferably channel layer 34 may be C-plane oriented, such that the surfaces furthest from the substrate are [0 0 0 1] surfaces. Alternatively, it may be a semi-polar structure with Ga termination, as is known in the art. Alternatively, it may be grown as a non-polar structure using n-doping, as will be described below.
[0035] A thin layer 38 of AlxXN is placed on top of the GaN layer 34. In this layer, the “X” material may be gallium, indium or a combination of the two. A preferable material for this layer 38 is AlxGaN. For this embodiment, layer 38 will be referred to as an AlxGaN layer, although it may be these other materials as well. In another embodiment of the invention, layer 38 may be AlN. AlxGaN layer 38 should be sufficiently thin so that no significant 2 DEG is established underneath the gate 31 when zero volts is applied to the gate. Layer 35 is formed over layer 38, and it may be n-doped, as will be discussed below.
[0036] Gate 31 source 33 and drain 39 may be any suitable metal or other electrically conductive material. Preferably, an insulating layer 36 is formed between gate 31 and adjacent layers 35 and 38. Prior to the formation of source and drain contacts 33 and 39, respectively, layers 35 and 38 are etched so that the bottoms of these source and drain contacts can make electrical contact with nitride channel layer 34.
[0037] The graphs of FIGS. 3 a and 3b show a plot of the 2 DEG sheet charge density ns underneath the gate 31 of the device shown in FIG. 2 with zero volts applied to the gate, versus the AlxGaN layer 38 thickness (t) for a number of different Al compositions. The graph of FIG. 3 a illustrates the charge density for a device structure without an intermediate AlN layer; the graph of FIG. 3 b illustrates the charge density for a device structure with an intermediate AlN layer.
[0038] For appropriately chosen thicknesses of the layers, it is possible to keep the polarization-induced charge density ns small, or to eliminate it completely. As seen in FIGS. 2 and 3 a and 3b, for a given Al concentration in the AlxGaN layer 38, there is a minimum layer thickness required to form a 2 DEG under the gate at zero gate bias. For structures in which the AlxGaN thickness is less than a minimum thickness, no 2 DEG region is formed underneath the gate at zero gate voltage, which prevents the device from being normally ON. Thus the minimum thickness required to form a 2 DEG underneath the gate at zero gate bias is about the same as the maximum thickness for which the device will be normally OFF and therefore operate as an enhancement mode device.
[0039] The maximum thickness of the AlxGaN layer 38 such that no significant 2 DEG charge is present in the channel region underneath the gate at zero gate voltage depends upon how much Al is present in the layer, as illustrated in FIGS. 3 a and 3b. In general, the greater the Al concentration, the thinner the layer must be to ensure that no significant 2 DEG charge is present in the channel region underneath the gate at zero gate voltage. Referring to FIGS. 2 and 3 a, for a device without an intermediate AlN layer and 20% Al (the top curve 50), no charge will be induced if the thickness of the layer 38 is below about 6 nm, whereas for 10% Al, no charge will be induced if the thickness of the layer 38 is below about 12 nm. Similarly, for FIG. 3 b, measured with a device with a 0.6 nm thick intermediate AlN layer, for 20% Al (the top curve 51), no charge will be induced if the thickness of the layer 38 is below about 1 nm, whereas for 10% Al, no charge will be induced if the thickness of the layer 38 is below about 2 nm.
[0040] In devices where the AlxGaN layer 38 is thin enough such that no significant 2 DEG exists underneath the gate at zero gate voltage, for a given thickness of layer 38, the leakage current when the device is in the OFF state increases with increasing Al composition, as a result of the corresponding decrease in the source-drain barrier when the device is in the OFF state. For example, a device with a 5 nm thick AlxGaN layer that contains 20% Al will exhibit more leakage than a device with a 5 nm thick AlxGaN layer containing 10% Al. Therefore, for a given thickness of layer 38, a lower Al composition results in a higher threshold voltage and lower leakage when the device is biased OFF, both of which are desirable in an enhancement mode device.
[0041] However, as will be further discussed below, the maximum 2 DEG charge that can be induced in the access regions increases with increasing Al concentration in layer 38. Increasing the 2 DEG charge in the access regions reduces the on-resistance Ron of the device. Therefore, the Al composition in layer 38 should be at least high enough that a sufficient amount of charge can be induced in the access regions to satisfy the Ron requirements of the application for which the device is being used.
[0042] In the embodiment of the invention shown in FIG. 2 , on top of AlxGaN layer 38 is a second AlyGaN layer 35. If desired, y can be 0, so that the layer is entirely GaN. Layer 35 is required to provide 2 DEG charge in the channel access regions of layer 34 between the source 33 and the gate 31, and between the drain 39 and the gate 31. For devices in which layer 35 is entirely GaN, there is no net polarization-induced field in layer 35 contributing to the formation of 2 DEG charge in the channel access regions. Therefore, for devices in which layer 35 is undoped or unintentionally doped GaN, no significant 2 DEG will be present in the access regions, and an enhancement mode device would not be feasible.
[0043] For devices in which y>0 in AlyGaN layer 35 and layer 35 is undoped or unintentionally doped, the polarization-induced field in this layer can contribute to the formation of a 2 DEG charge in the channel access regions. For a given Al composition and thickness of layer 38 and a given Al composition in layer 35, there is a minimum thickness of layer 35 required to induce a 2 DEG charge in the channel access regions. This minimum thickness decreases by increasing the Al composition in layer 35 and/or in layer 38. For structures where layer 35 is greater than a minimum thickness, the 2 DEG charge concentration in the channel access regions increases with increasing thickness of layer 35, but can never exceed the saturation charge concentration for the structure. The saturation charge concentration, which is the maximum charge that can be induced in the 2 DEG regions, depends upon the Al composition in layers 35 and 38 and upon the thickness of layer 38. Increasing the Al composition in layer 35 increases the saturation charge concentration for the 2 DEG region.
[0044] In view of these relationships, the thickness and Al content of layer 35 are selected so that, by itself, layer 35 doesn't add charge in the structure below, or adds an amount of charge in the access regions which is not large enough to satisfy the Ron requirements of the application for which the device is being used. However, it is desirable, as discussed above, to have charge present in the channel access regions even when there is no voltage on the gate 31, and the charge density in the channel access regions is preferably greater than the charge density in the channel region underneath the gate when the gate is biased such that the device is in the ON state. One way to achieve this is to n-dope AlyGaN layer 35 with Si, which acts as an n-type dopant in III-N devices. The greater the n-doping, the greater the resultant 2 DEG charge in the channel access regions of layer 34. A preferred doping technique is called silicon delta doping, well known in the art. Alternatively, a uniform doping in layer 35 could be used, or other arbitrary doping profile.
[0045] If doping is used, the minimum effective amount is that required to achieve the target 2 DEG charge in the channel access regions. Increasing the 2 DEG charge, of course, increases the maximum ON current of the device, but also causes it to have a lower breakdown voltage. As the device must block voltage in the OFF condition, it is undesirable to have too low a breakdown voltage. Therefore, in selecting the amount of n-doping, it is necessary to provide a sufficiently high breakdown voltage for the applications for which the device will be used.
[0046] As an example, a device of the invention can have a switching voltage greater than 2 volts, preferably 2.5 volts, and a current flow through the channel of at least 200 mA per mm of gate width, preferably at least 300 mA per mm, when the channel is conductive. Preferably, the current through the channel when the channel is conductive should be at least 10,000 times the current that flows when the channel is not conductive.
[0047] Furthermore, there is a maximum charge, known as the saturation charge value, that is possible in the channel access regions, the magnitude of which depends upon the composition of layer 38. In general, if layer 38 is AlxGaN, a higher Al composition in layer 38 results in a larger saturation charge value in the access regions. Therefore there is no need to dope region 35 beyond the amount required to create the maximum charge in the access regions.
[0048] The amount of required doping further depends upon the doping profile. If the dopant is placed near the bottom of layer 38, closer to channel layer 34, a larger 2 DEG region is induced than if the dopant is placed farther away from channel layer 34. But it is undesirable to dope too close to the interface between layers 38 and 34 because that would lessen the mobility of electrons in the 2 DEG region, which would increase the resistance of the 2 DEG region, and thus the channel resistance.
[0049] One way to determine the aluminum concentration of layer 35 is to select the concentration so that, without the n-doping, no 2 DEG charge will be formed in the channel access regions in the absence of the application of a gate voltage. Then the n-doping will create the 2 DEG charge.
[0050] If desired, an additional cap nitride layer (not shown) can be placed atop layer 35. The nitride used may be In, Ga, or Al, or a combination of one or more of them. This layer may improve the surface properties of the device.
[0051] During device fabrication, a portion of AlyGaN layer 35 is removed in region 36 under and around the gate region by a conventional etching step. This step, for example, can be a plasma RIE or ICP etch. The resulting structure has no charge under the gate region at 0 gate voltage, while a desired 2 DEG charge still exists in the channel access regions shown within layer 34 by the two dotted lines. Where Si-doping is used, this 2 DEG region is at least partially induced by the Si-doped layer 35.
[0052] Next, a conformal gate insulator 36 is deposited by methods well known in the art, such as PECVD, ICP, MOCVD, sputtering or other well know techniques. This insulator 36 can be silicon dioxide, silicon nitride, or any other insulator or combination of insulators. Alternatively, at least one of the insulators of layer 36 is a high-K dielectric, such as HfO2, Ta2O5, or ZrO2. Preferably at least one of the insulators contains or induces negative charge, thereby acting to deplete the channel region underneath the insulator. Examples of insulators which may act to deplete the underlying channel are AlSiN, HfO2, and Ta2O5.
[0053] Next, the source and drain ohmic contacts 33 and 39 and the gate contact 31 are deposited by well known techniques. The order of these process steps may be changed, as is well known in the art. In addition, if desired, one or more field plates externally connected to either the gate 31 or source 33 may be used. SiN or other passivation layers may also be deposited over the entire structure including the contacts, as is known in the art.
[0054] Thus in the fully fabricated device, the AlxGaN layer 38 under the gate is thinner than the minimum required to form a 2 DEG region beneath the gate at 0 gate voltage. The upper limit of this layer 38 thickness is called the “critical thickness.” The minimum gate voltage for which a 2 DEG region exists underneath the gate, thus rendering the channel conductive, is called the device threshold voltage Vth. For example, a Vth of 0-3 volts may be used. If, for example, a Vth of 3 volts were selected, a positive gate voltage greater than 3 volts is required to turn the device ON, thus inducing a 2 DEG region under the gate region and achieving enhancement mode operation where current is conducted between source 33 and drain 39. If the gate voltage were less than 3 volts, the device would remain OFF. A higher threshold voltage is preferable to prevent accidental turn on of the device and to decrease leakage currents when it is intended to be OFF.
[0055] Without using the gate insulator 36, the maximum positive bias voltage that may be applied to the gate is limited by the schottky barrier forward turn on voltage of the gate junction, thus limiting the maximum full channel current. Using a gate insulator, a higher positive bias may be applied to the gate to accumulate a high channel 2 DEG charge under the gate region when the device is ON, thus achieving substantial operating current. Furthermore, the gate insulator is also used to increase the external threshold voltage of an already normally-off device. In the case where the gate insulator acts to deplete charge from the underlying channel, the intrinsic threshold voltage is increased, and OFF state leakage decreases, since the source-drain barrier when the device is in the OFF state is increased.
[0056] Another embodiment of the device of the invention is shown in FIG. 4 . The layers that are the same as in FIG. 2 have the same reference numerals. This device is similar to the one in FIG. 2 , except that a nitride buffer layer 32 is included in between the nitride channel layer 34 and the substrate 30. Buffer layer 32 may be a nitride of gallium, indium or aluminum, or combinations of those nitrides. The composition of this buffer layer 32 is chosen such that the bandgap of the material is greater than that of the material of the channel layer 34, and the lattice constant is smaller than that of channel layer 34. Therefore, these two layers must be different materials. The larger bandgap of buffer layer 32 creates a back-barrier which reduces source-to-drain leakage currents when the device is in the OFF state. The smaller lattice constant of buffer layer 32 causes the overlying material of the channel layer 34 to be under compressive strain, which modifies the polarization field in these overlying materials in such a way that reduces the polarization-induced contribution to the 2 DEG channel charge, thereby increasing the threshold voltage and reducing source-to-drain leakage currents when the device is in the OFF state. If, for example, buffer layer 32 is AlbIncGa1-b-cN, increasing b while keeping c constant increases the bandgap and decreases the lattice constant of layer 32, while increasing c while keeping b constant decreases the bandgap and increases the lattice constant. Therefore b and c are chosen in such a way that ensures that the bandgap of the material of buffer layer 32 is greater than that of the material of the channel layer 34, and the lattice constant of buffer layer 32 is smaller than that of channel layer 34.
[0057] When GaN is used for channel layer 34, buffer layer 32 is preferably AlzGaN, where z is between a finite value greater than 0, and 1. The AlzGaN buffer layer 32 acts as a back-barrier, further increasing the source-drain barrier when the device is in the OFF state and increasing the device threshold voltage, as compared to the device of FIG. 2 .
[0058] In the device shown in FIG. 4 , the GaN layer 34 and AlGaN layer 38, which both overlie the AlzGaN buffer layer 32 are conformally strained to the AlzGaN, which modifies the polarization fields in those two layers and thereby reduces the polarization-induced contribution to the 2 DEG channel charge. The net result of these effects is that the “critical thickness” of the AlxGaN layer 38 is increased as compared to layer 38 of the device of FIG. 2 . Having a thicker AlxGaN layer 38 in the device of FIG. 4 , with buffer layer 32, is helpful in enabling manufacturability of these devices.
[0059] Source and drain contacts 33 and 39, respectively, are formed through the top surface of the device. Prior to the formation of source and drain contacts 33 and 39, respectively, layers 35, and 38 are etched so that the bottoms of these source and drain contacts can make electrical contact with nitride channel layer 34.
[0060] A preferred embodiment of the device of the invention is shown in FIG. 5 . A GaN buffer layer 41 is grown on a SiC substrate 40, followed by the deposition of a 3 nm thick Al.2GaN layer 43, which is less than the critical thickness and hence does not induce any 2 DEG region in area of the underlying GaN layer beneath gate 45. Next a 20 nm thick GaN layer 44 delta doped with Si between about 6×1012 atoms/cm2 and 8×1012 atoms/cm2 is formed atop Al.2GaN layer 43. The Al.2GaN layer 43 thickness in the area beneath the gate 45 needs to be about 5 nm thick or less. Source and drain regions 47 and 49 are formed on the top surface. Prior to the formation of source and drain contacts 47 and 49, respectively, layers 46, 44 and 43 are etched so that the bottoms of these source and drain contacts can make electrical contact with nitride buffer layer 41.
[0061] An alternative embodiment of the device of FIG. 5 is shown in FIG. 6 . The layers that are the same as in FIG. 5 have the same reference numerals. However in this embodiment, a thin intermediate AlN layer 48 is interposed between layers 41 and 43. Where such an intermediate AlN layer 48 is present, and where Al.2GaN is used for layer 43, the Al.2GaN layer 43 thickness in the area beneath the gate 45 needs to be about 1 nm or less.
[0062] Still referring to FIG. 5 , a selective gate recess etch was performed to etch away the Si doped GaN layer 44 under and around the gate region 45, such that the gate recess etch stops at the Al.2GaN layer 43. Selective etches are well known in the art that etch GaN (having no Al content) faster than AlGaN. The etch rate through the AlGaN layer 43 depends upon the percentage of Al in the layer, as these selective etches etch faster through layers with low aluminum content than through layers with higher Al content. Thus, according to the invention, a selective etch will etch in the area beneath gate 45 through the GaN layer 44 (that has no aluminum) at a faster rate than through Al.2GaN layer 43, allowing Al.2GaN layer 43 to act as an etch stop. The etch chemistry used is BCl3/SF6. The selectivity of the BCl3/SF6 selective etch of GaN over AlGaN(x=0.2) is about 25. When AlGaN is etched, the AlF3 that is formed is non-volatile. Therefore the etch rate is reduced.
[0063] The higher the concentration of Al in layer 43, the more effective it will be as an etch stop. A preferred etch process for this purpose is inductively coupled plasma ion etching (“ICP”) using a BCl3/SF6 etchant. Other Cl2 or Fl2 based reactive ion etching (“RIE”) or plasma etching processes known in the art may be used.
[0064] A SiN layer 46 is then deposited to form the gate insulator, for example using a metal-organic CVD (MOCVD) or other suitable deposition process known in the art. The device is completed by forming source and drain ohmic contacts and a gate contact in a conventional manner to complete the structure of FIGS. 5 and 6 . A further SiN passivation layer may be added to the full structure. The transfer characteristics of this device demonstrated enhancement mode operation with a +3 volt threshold, as shown in FIG. 7 .
[0065] A method of fabrication of a device of one embodiment of the invention is illustrated in FIGS. 8 a-8d. Referring to FIG. 8 a, on top of substrate 60 are formed, in order, III-nitride layers 64, 68 and 65. On top of GaN layer 65 is formed a passivation layer 67 of SiN. Next, as shown in FIG. 8 b, layer 67 is etched away in the gate region 69 using an etch chemistry which does not substantially etch III-nitride materials, such as CF4/O2, CHF3 or SF6. The etch process used results in a slanted sidewall, as shown, and the underlying layer 65 is not etched. This sidewall slant of opening 69 is achieved by methods well known in the art, for example by choosing a photoresist which has a slanted sidewall as a mask for the etch. Next, as seen in FIG. 8 c, III-nitride layer 65 is etched in the gate region using previously etched layer 67 as an etch mask. The etch chemistry used must have certain properties. It must selectively etch nitride layer 65 at a higher rate than the underlying nitride layer 68. Thus, layer 68 serves as an etch stop, and so the etch terminates at the interface between layers 65 and 68 with a high level of precision. The etch chemistry must also etch passivation layer 67 at a rate which is the same or similar to the etch rate of layer 65. This ensures that the sidewall of opening 69 through layers 65 and 67 are tapered (as opposed to vertical), as shown. Next, as shown in FIG. 8 d, a gate insulator 62, such as SiN, is deposited conformally over the surface of opening 69 and the top of layer 67.
[0066] To complete the device, as shown in FIG. 9 , source 63, drain 70, and gate 61 electrodes are deposited. Prior to the formation of source and drain contacts 63 and 70, respectively, layers 67, 65, and 68 are etched so that the bottoms of these source and drain contacts can make electrical contact with nitride channel layer 64. In the embodiment of the invention shown in FIG. 9 , the substrate and III-nitride material layers are similar to those of FIG. 2 . However, the embodiment shown in FIG. 9 also contains a dielectric passivation layer 67 which covers the surface of the gallium nitride layer 65 furthest from substrate. Layer 67 is comprised of any material suitable for surface passivation of III-nitride devices as is known in the art, for example, SiN. Nitride layer 65 and passivation layer 67 are tapered down as shown underneath the sides of the gate metal. Having a tapered sidewall of the gate (as opposed to a perfectly vertical one) allows the gate metal also to act as a slant field plate in region 66, which increases the device breakdown voltage by decreasing the maximum electric field in the device.
[0067] Another embodiment of the invention is a vertical device shown in FIG. 10 . In a vertical device the source and gate contacts 78 and 79, respectively, are on the top surface of the device while the drain contact 80 is at the bottom, as shown. Vertical devices have the benefit of using less wafer area for a similar size device as compared to the lateral devices described earlier.
[0068] To make a vertical device for enhancement mode operation, a lightly doped (n−) GaN drift layer 72 is incorporated below the GaN channel layer 74. The thickness of drift layer 72 determines the blocking voltage capability of the device, as this layer sets the effective gate-to-drain spacing. The doping amount for layer 72 is chosen to maximize its conductivity, thereby minimizing its resistance, and to support the required blocking voltage, as discussed earlier. If the doping is too low, the resistance can be too high. If the doping is too high, the blocking voltage can be too low.
[0069] Blocking layer 73 blocks direct current flow from source 78 to drain 80. If such direct current flow were permitted, it would provide an undesirable, parasitic leakage current path in the device. Blocking layer 73 can be made in various ways. In one method, p-type regions 73 are formed by suitable techniques, for example ion implantation, or by using a 2-step growth process in which a p-type layer 73 is grown completely across n−GaN layer 72, and is then removed under the gate region (where the current path is indicated by the arrows), followed by a growth of layers 74 and above. The material of layer 74 merely fills in where layer 73 had been removed.
[0070] In another method an insulating GaN layer is used for the blocking layer 73. This can be formed by suitable techniques such as doping GaN layer 73 with iron, or by an isolation ion implantation of Al or other suitable material that results in the placement of an insulating GaN material in the blocking regions 73. Other methods, such as a regrowth of material in layer 73 may also be used.
[0071] Another embodiment of the invention, shown in FIG. 11 , employs a blocking layer, and a highly doped n+GaN contact layer 81 is placed below the GaN drift layer 72. The entire structure is grown on a semi-insulating substrate 71. Prior to deposition of drain ohmic contact 80, via 82 is formed by etching through substrate 71. The drain ohmic contact 80 makes contact with layer 81 through via 82.
[0072] The drain contact to layer 81 may be made in other ways. As shown in FIG. 11 the device is grown on a conducting substrate 71, which may, for example, be conducting silicon, GaN or SiC. In this structure, via 82 is not required, since the drain contact 80 is simply made to the bottom of the substrate 71. In the embodiment of FIG. 11 which uses an insulating substrate, a via is etched through the substrate through which the drain contact with layer 81 is made.
[0073] In another implementation shown in FIG. 12 , a lateral mesa is etched as shown, and the drain contact 80 is made on the top side of the highly doped GaN contact layer 81.
[0074] Another embodiment of this invention is show in FIGS. 13 a and 13b. The device of FIG. 13 b includes a substrate 90, a nitride channel layer 94 on the substrate, including a first channel region shown as a dotted line 102 in layer 94 beneath the gate 91. The material of the nitride channel layer 94 is selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof. The device has an AlXN layer 98 adjacent the channel layer 94, where X is selected from the group consisting of gallium, indium or their combination. A III-N layer 95 is adjacent the AlXN layer, that includes two channel access regions shown by dotted lines on opposite sides of the gate 91 and the first channel regions 102. This III-N layer can be GaN, InN or a combination of the two, preferably GaN. These two channel access regions are respectively connected to the source 93 and the drain 99. In one embodiment of this device, there is an AlmGaN layer 100 atop the III-N layer 95 that is used for enabling the 2 DEG charge in the channel access regions. m is in the range of 0.1 to 0.3 and the thickness of the layer 100 is in the range of 100-500 Angstroms, the composition and thickness range being selected to achieve an equivalent sheet resistance of under 700 ohms/square in this region.
[0075] In this embodiment, the 2 DEG channel access regions are formed in a different layer 95 from the first channel region 102 controlled by the gate 91. In an enhancement-mode device, the channel access regions need to be as conductive as possible at all times, whereas the first channel region 102 beneath the gate needs to be depleted of conducting charge in the absence of a control voltage applied to the gate 91. The device in FIGS. 13 a and 13b, having the charge in the channel access regions in a different layer 95 from the layer 94, that contains the charge 102 beneath the gate that is only present when the device is “ON”, has more flexible design parameters than devices that have their the channel access regions and their first channel region in the same layer or devices that involve substantial trade-offs in access region charge vs. the charge in the nitride channel layer 94 that is modulated by the gate.
[0076] FIG. 13 a illustrates a device where there is no voltage applied to the gate, and FIG. 13 b shows the device when a positive control voltage is applied to gate. The material layers are similar to the layers in prior embodiments, except that the thicknesses and compositions of layers 95 and 100 are adjusted so that, in the absence of a control voltage applied to the gate, a substantial 2 DEG channel exists in the access regions in layer 95 but not in the first channel region 102. As seen in FIG. 13 b, when a positive control voltage is applied to the gate electrode 91, a conducting 2 DEG channel shown by the dotted line is formed in layer 94 adjacent to the interface between layers 94 and 98 in region 102 underneath the gate 91. Further, a vertical conducting region is formed in layer 95 adjacent the sidewall 97 of insulator 96, resulting from the accumulation of charge from the positive control voltage on the gate. In addition, a path is formed via the mechanisms of tunneling through the barrier or emission over the barrier or both, through layer 98 which connects the 2 DEG and conducting regions in layer 95 to the conducting 2 DEG channel in region 94, completing the conduction path from source 93 to drain 99. Thus, an important feature of this structure is that the gate is modulating charge both beneath itself and along its sides when a switching voltage is applied to the gate.
[0077] When a switching voltage is applied to the gate, the conducting channel extends all the way from the source 93 to the drain 99, and the device is turned ON. In this embodiment, source 93 and drain 99 extend downwardly from the surface of the device at least deep enough so that they are in electrical contact with the 2 DEG region in layer 95 (shown by the dotted lines), but not necessarily any deeper. This is different from previous embodiments where the 2 DEG access regions are in the same layer as the 2 DEG first channel region that is formed under the gate in the presence of a gate voltage above a threshold, where the source and drain contacts must extend downwardly even farther.
[0078] This device of this embodiment of the invention may be constructed in a number of ways. For example, source 93 and drain 99 may be formed by depositing a metal layer 100, such as a Ti/Al/Ni/Au stack, in the source and drain regions 93 and 99, and then annealing the device at an elevated temperature such that the metal and underlying semiconductor material form a conducting alloy which extends at least beyond the interface of layers 100 and 95, as shown in FIGS. 13 a and 13b. Alternatively, source 93 and drain 99 may be formed by implanting an n-type dopant, such as silicon, into layers 100 and 95 in the places where the source and drain are to be formed and in the source and drain access regions, and then depositing a metal, such as Ti, Al, Ni, Au, or a combination thereof atop the implanted areas to serve as the source and drain contacts. In this case, source 93 and drain 99 are comprised of a combination of the metal and the implanted semiconductor material.
[0079] Source 93 and drain 99 may extend deeper than the minimum depth illustrated in FIGS. 13 a and 13b. As shown in FIGS. 14 a and 14b, the source and drain 93 and 99 extend downwardly beyond the interface of layers 94 and 98, as will be discussed below. As shown in FIG. 14 a, the Al compositions of layers 98, 95, and 100 are adjusted such that a 2 DEG region shown by the dotted line is present in the access regions in layers 95 and 94, but not underneath the gate 91, in the absence of an applied gate voltage.
[0080] By way of example, the embodiment of the invention shown in FIGS. 14 a and 14b can be achieved with the following parameters for layers 98, 95, and 100: layer 98 is a 3 nm thick AlxGaN layer with x=0.23; layer 95 is a 3nm thick GaN layer; and layer 100 is a 15 nm AlmGaN layer with m=0.23. In this example, a 2 DEG region is expected to be present in the access regions in layers 95 and 94, shown by the dotted lines, and the 2 DEG sheet charge density in layer 94 is approximately two times that in layer 95.
[0081] As shown in FIG. 14 b, when a positive control voltage is applied to the gate electrode 91, a conducting 2 DEG channel 102 is formed beneath gate 91, shown by the dotted line in layer 94, adjacent the interface between layers 94 and 98 in region 102 underneath the gate. Further, a vertical conducting region is formed in layer 95 adjacent sidewall 97 of insulator 96, resulting from the accumulation of charge from the positive control voltage on the gate 91. In addition, a path via the mechanisms of tunneling through the barrier or emission over the barrier, or both, is formed through layer 98. This path connects the 2 DEG channel access regions in layer 95 to the conducting 2 DEG channel in layer 94, completing the conduction path from source 93 to drain 99. Thus, when the device is ON, as shown in FIG. 14 b, the conducting channel from source 93 to drain 99 comprises the 2 DEG channel in layer 94 underneath the gate, along with the two in-line 2 DEG channel access regions in layer 95 which are connected by the vertical conducting regions in layers 95 and 98. This is shown in FIG. 14 b.
[0082] This structure of this device reduces the access resistance and thereby reduces the device ON resistance Ron, because the contacts for the source 93 and drain 99 extend downwardly beyond the interface of layers 94 and 98. That allows the 2 DEG regions in the access regions of layers 95 and 2 DEG conductive region of layer 94 that is present when the device is ON, to form a conductive path between the source 93 and drain 99.
[0083] The device of FIG. 14 will operate properly as an enhancement-mode device if source 93 and drain 99 extend downwardly just beyond the interface of layers 100 and 95, as was the case for the device in the embodiment shown in FIG. 13 . However, in that case the source 93 and drain 99 will only contact the 2 DEG region in layer 95 and not that in layer 94, so the access resistance and device on resistance Ron remain similar to the device in FIG. 13 .
[0084] Additionally, layers 95, 94, 98 and/or layer 100 may be doped with an n-type dopant, such as Si, to further enhance 2 DEG charge in the access regions of layer 95 and/or layer 94. Furthermore, an additional III-N layer (not shown), such as AlInGaN, may be included on top of AlmGaN layer 100 in the devices shown in FIGS. 13 and 14 , to help mitigate dispersion in the device.
[0085] Another embodiment of the device of the invention is shown in FIG. 15 . The layers that are the same as the devices in FIGS. 13 and 14 have the same reference numerals. This device is similar to the one shown in FIG. 13 , except that a nitride buffer layer 92 is included between the nitride channel layer 94 and the substrate 90. This buffer layer has the same parameters and is used for the same purpose described above with respect to the embodiment shown in FIG. 4 .
[0086] Another embodiment of the invention is shown in FIG. 16 . This device is the same as that of FIG. 13 , except that it has no buffer layer between the nitride channel layer 94 and the substrate 90, but has a thin AlN layer 101 is included in between GaN layer 95 and AlmGaN 100. This AlN layer 101 causes an increase in the charge density and electron mobility in the 2 DEG charge in the access regions in layer 95, thereby decreasing the access resistance and thus the device on-resistance Ron. Preferably this layer should be between about 4 Å and 30 Å thick.
[0087] Another embodiment of the invention is shown in FIG. 17 . This device is the same as that of FIG. 14 , except that a thin AlN layer 103 is included between channel layer 94 and AlxGaN 98. This AlN layer 103 causes an increase in the charge density and electron mobility in the 2 DEG charge access regions in layer 94, thereby decreasing the access resistance and thus device on-resistance Ron. Additionally, the gate 91 is deposited in the gate recess opening, which was formed by first recess etching and then filling the recess with an insulator 96, as discussed in connection with earlier embodiments, and the gate recess stops precisely at the upper surface of layer 98, as shown in FIG. 17 .
[0088] Another embodiment of this invention is shown in FIGS. 18 a and 18b. This device is the same as that of FIG. 17 , except that the AlxGaN and AlN layers between layers 95 and 94 have been omitted. Furthermore, the recess etched gate 91 extends below the interface between layers 95 and 94 further down inside the bulk of layer 94, as shown in FIG. 18 a, and the source 93 and drain 99 extend only into layer 95 so as to contact the 2 DEG region shown by the dotted line in layer 95, but not so far as to contact layer 94.
[0089] The difference between the device of FIG. 18 a and the device of FIG. 18 b is that, in FIG. 18 b, the gate insulator region 96 stops precisely at the top of nitride channel layer 94, but in the device of FIG. 18 a, the gate insulator region 96 extends beyond the interface between layers 94 and 95. When a positive control voltage is applied to the gate 91 of the device of FIG. 18 b, the conducting channel produced underneath the gate 91 may be a 2 DEG region, or alternatively may be an electron accumulation layer.
[0090] Although the transfer characteristics of the device of FIG. 18 a may be inferior compared to those of the device in FIG. 18 b, this device is more tolerant to variations in processing conditions, since it does not rely upon a precise etch stop at the top of layer 94 to operate properly. It is therefore more easily manufacturable.
[0091] Another embodiment of this invention is shown in FIG. 19 . This device is similar to that of FIG. 13 , except that all of the III-nitride layers are grown in a nonpolar or semipolar (Ga terminated) orientation (as compared to the [0 0 0 1] orientations of the other embodiments of this invention). Using semipolar or nonpolar layers increases the threshold voltage of the device as well as increasing the barrier between source and drain when the device is in the OFF state, thereby reducing OFF state leakage. However, in this structure of FIG. 19 , AlmGaN layer 100 and/or GaN layer 95 is doped with an n-type dopant, such as Si, to ensure that a conducting channel exists at all times in the 2 DEG access regions in layer 95.
[0092] More embodiments of this invention are shown in FIGS. 20-22 . These are all vertical devices similar to those shown in FIGS. 10-12 , except that the 2 DEG access regions are contained in layer 116, and when the device is biased ON, a vertical conduction region is induced in region 116 by the gate 119, and a conducting path is formed through layer 115, to connect the access regions in layer 116 to the 2 DEG region in layer 114 underneath the gate 119, much like the device in FIG. 13 .
[0093] Another embodiment of this invention is shown in FIG. 23 . This device is similar to the device in FIG. 14 , but the slanted gate 131, the SiN passivation layer 137 and the gate insulator layer 132 make this device similar to the device of FIG. 9 .
[0094] A device having the structure shown in FIG. 16 was fabricated and had the output characteristics shown in FIGS. 24 a, 24b and 24c. The threshold voltage Vth was 1.5V, the ON-resistance Ron was 12 ohm-mm, and the maximum source-drain current Imax was 700 mA/mm at a gate voltage VG=8V.
[0095] There may be many variations on the structures and methods described above that are, or will become apparent to those skilled in the art, that may be used in connection with, but without departing from the spirit and scope of this invention.
Claims
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What is claimed is:
1. A III-N semiconductor device comprising:
a gate;
a nitride channel layer including a first channel region beneath the gate, and two channel access regions on opposite sides of the first channel region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof;
an AlXN layer adjacent the channel layer, wherein X is selected from the group consisting of gallium, indium or their combination; and
an n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions, but not in the area adjacent to the first channel region;
the concentration of Al in the AlXN layer, the AlXN layer thickness, and the n-doping concentration in the n-doped GaN layer being selected to induce a 2DEG charge in the channel access regions adjacent the AlXN layer without inducing any substantial 2DEG charge in the first channel region, so that the channel is not conductive in the absence of a switching voltage applied to the gate region, but can readily become conductive when a switching voltage greater than a threshold voltage is applied to the gate region.
2. The III-N semiconductor device of claim 1 having a substrate and an additional nitride layer between the substrate and the nitride channel layer, the additional nitride layer being selected from the group consisting of nitrides of gallium, indium and aluminum and combinations thereof, wherein the channel layer is GaN and the additional nitride layer is AlzGaN, where z is between a finite value greater than 0, and 1.
3. The III-N semiconductor device of claim 1 wherein the n-doped GaN layer is doped with silicon.
4. The III-N semiconductor device of claim 3 wherein the switching voltage is greater than 2.5 volts and a current flows through the channel of at least 300 mA per mm of gate width when the channel is conductive.
5. The III-N semiconductor device of claim 3 wherein the switching voltage is greater than 2 volts and a current flows through the channel of at least 200 mA per mm of gate width when the channel is conductive.
6. The III-N semiconductor device of claim 5 wherein the current through the channel when the channel is conductive is at least 10,000 times the current when the channel is not conductive.
7. A III-N semiconductor device comprising:
a nitride channel layer including a first channel region beneath a gate region, and two channel access regions on opposite sides of the first channel region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof;
a first AlXN layer adjacent the channel layer wherein X is selected from the group consisting of gallium, indium or their combination;
a second AlXN layer adjacent the first AlXN layer in the areas adjacent to the channel access regions, but not in the area adjacent to the first channel region, the first AlXN layer having a substantially higher concentration of Al than the second AlXN layer;
the concentration of Al in each of the first and second AlXN layers, respectively, and their respective thicknesses being selected to induce a 2DEG charge in channel access regions adjacent the first AlXN layer without inducing any substantial 2DEG charge in the first channel region, so that the channel is not conductive in the absence of a switching voltage applied to the gate region, but is conductive when a switching voltage greater than a threshold voltage is applied to the gate region.
8. The III-N semiconductor device of claim 7 wherein the concentration of Al in the first AlXN layer is at least twice the concentration of Al in the second AlXN layer.
9. The III-N semiconductor device of claim 7 wherein the second AlXN layer is n-doped.
10. The III-N semiconductor device of claim 9 wherein the n-dopant is Si.
11. The III-N semiconductor device of claim 7 having a substrate and an additional nitride layer between the substrate and the nitride channel layer, the additional nitride layer being selected from the group consisting of nitrides of gallium, indium and aluminum and combinations thereof, wherein the channel layer is GaN and the additional nitride layer is AlzGaN, where z is between a finite value greater than 0, and 1.
12. The III-N semiconductor device of claim 11 wherein the additional nitride layer is AlXN.
13. A III-N semiconductor device comprising:
a nitride channel layer including a first channel region beneath a gate region, and two channel access regions on opposite sides of the first channel region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof;
a first AlXN layer adjacent the channel layer wherein X is selected from the group consisting of gallium, indium or their combination;
a second AlXN layer adjacent the first AlXN layer, the first AlXN layer having a substantially higher concentration of Al than the second AlXN layer;
a gate region formed in the second AlXN layer, the gate region comprising an aperture in the second AlXN layer and an insulator covering at least part of the aperture; and
a conductive gate contact atop the insulator and insulated from the first and second AlXN layers; wherein
the concentration of Al in each of the first and second AlXN layers, respectively, and their respective thicknesses being selected to induce a 2DEG charge in channel access regions adjacent the first AlXN layer without inducing any substantial 2DEG charge in the first channel region, so that the channel is not conductive in the absence of a switching voltage applied to the gate region, but is conductive when a switching voltage greater than a threshold voltage is applied to the gate region.
14. The III-N device of claim 13 wherein the aperture has slanted sides.
15. The III-N device of claim 13 wherein conductive contacts are formed to make source and drains electrical contacts with opposing ends of the channel layer.
16. The III-N device of claim 15 wherein a passivating layer is applied to the top surface of the device, including at least part of the gate, source and drain contacts.
17. A GaN semiconductor device comprising:
a GaN channel layer, including a first channel region beneath a gate region, and two channel access regions on opposite sides of the first channel region;
a layer of AlxGaN on the channel layer, where x is between about 0.05 and 0.3;
an n-doped GaN layer adjacent the AlxGaN layer in the areas adjacent to the channel access regions, but not in the area adjacent to the first channel region;
the concentration of Al in the AlxGaN layer, the AlxGaN layer thickness and the n-doping concentration in the n-doped GaN layer being selected to induce a 2DEG charge in channel access regions adjacent the AlxGaN layer without inducing any substantial 2DEG charge in the first channel region, so that the channel is not conductive in the absence of a switching voltage applied to the gate region, but can readily become conductive when a switching voltage greater than a threshold voltage is applied to the gate region.
18. The GaN semiconductor device of claim 17 having an additional SiN layer on top of the n-doped GaN layer.
19. The GaN semiconductor device of claim 17 wherein the n-doped GaN layer is doped with silicon.
20. The GaN semiconductor device of claim 19 wherein the n-doped GaN layer is delta-doped.
21. The GaN semiconductor device of claim 17 wherein the substrate is SiC.
22. The GaN semiconductor device of claim 17 having an AlzGaN buffer layer between the GaN channel layer and the substrate, where z is between 1 and a finite value greater than 0, and wherein x is between 0.05 and 0.4.
23. The GaN semiconductor device of claim 17 having an additional AlXN layer on top of the n-doped GaN layer, wherein X is selected from the group consisting of gallium, indium or their combination.
24. The GaN semiconductor device of claim 23 having an additional SiN layer on top of the additional AlXN layer.
25. A III-N semiconductor device comprising:
a gate in a recessed gate region;
a nitride channel layer including a first channel region beneath the recessed gate region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof;
an AlXN layer adjacent the channel layer wherein X is selected from the group consisting of gallium, indium or their combination;
a III-N layer adjacent the AlXN layer and surrounding the recessed gate region, the III-N layer including two channel access regions on opposite sides of the first channel region respectively connected to a source and a drain,
an AlmYN layer adjacent to the III-N layer and surrounding the recessed gate region, wherein Y is selected from the group consisting of gallium, indium or their combination, the concentration m of Al in the AlmYN layer and its thickness being selected to induce a 2DEG charge in the two channel access regions,
the first channel region being non-conductive in the absence of a switching voltage applied to the gate, but being conductive in the presence of a gate voltage greater than a threshold voltage, creating a 2DEG region in the first channel region and through a gate-induced, substantially vertical conducting region through the AlXN layer, thereby completing the conduction path through the access regions from the source to the drain.
26. The III-N semiconductor device of claim 25 wherein the III-N layer or the AlmYN layer is n-doped.
27. The III-N semiconductor device of claim 26 wherein the n-dopant is Si.
28. The III-N semiconductor device of claim 25 having an additional nitride layer between the substrate and the nitride channel layer, wherein the channel layer is GaN.
29. The III-N semiconductor device of claim 28 wherein the additional nitride layer is AlXN where X is selected from the group consisting of gallium, indium, aluminum and combinations thereof.
30. The III-N semiconductor device of claim 28 wherein the additional nitride layer is AlzGaN, where z is between a finite value greater than 0, and 1.
31. The III-N semiconductor device of claim 25 wherein the conduction path through the AlXN layer is created by tunneling.
32. The III-N semiconductor device of claim 25 wherein the conduction path through the AlXN layer is created by thermionic emission.
33. The III-N semiconductor device of claim 25 wherein the conduction path through the AlXN layer is created by both tunneling and thermionic emission.
34. The III-N semiconductor device of claim 25 wherein the conduction path is modulated by the switching voltage and runs along a side of and beneath the gate.
35. The III-N semiconductor device of claim 25 wherein the gate has a bottom and substantially vertical or tapered sides, whereby charge is modulated along both the sides and the bottom when the switching voltage is present.
36. The III-N semiconductor device of claim 25 where m is between about 0.1 to 0.3.
37. The III-N semiconductor device of claim 25 having an additional AlN layer between about 4-30 Å thick in between the AlmYN layer and the III-N layer.
38. The III-N semiconductor device of claim 37 having a threshold voltage of at least 1 volt, less than 20 ohm-mm on resistance and current carrying capability between source and drain when the device is on of greater than 400 mA/mm.
39. The III-N semiconductor device of claim 37 having a threshold voltage of at least 1.5 volts, less than 15-ohm-mm on resistance and current carrying capability between the source and the drain when the device is on of greater than 600 mA/mm.
40. The III-N semiconductor device of claim 25 having an additional III-N layer adjacent to the AlmYN layer, the additional III-N layer also being recessed in the gate region.
41. The III-N semiconductor device of claim 40 wherein the additional III-N layer is n-doped.
42. The III-N semiconductor device of claim 25 wherein the recessed gate includes a gate insulator composed substantially of a material selected from the group consisting of SiN, AlSiN, SiO2, HfO2, ZrO2, Ta2O5 or a combination thereof.
43. The III-N semiconductor device of claim 42 wherein at least one of the insulating materials is a high-K dielectric.
44. The III-N device of claim 42 further including an additional SiN layer on the AlmYN layer, the SiN layer being recessed with a tapered sidewall, the tapered sidewall further continuing through the AlmYN layer and the III-N layer, and a gate metal layer deposited in the recessed gate region over the gate insulator, a portion of the gate metal extending over the gate insulator on both sides.
45. The III-N device of claim 44 having an additional SiN passivation layer applied on top of the device and beneath the gate metal.
46. The III-N device of claim 45 having a field plate metal deposited on the SiN passivation layer, the field plate metal connected electrically either to the source or the gate contact.
47. A III-N transistor having a source, a drain and a gate, comprising:
a first layer of a first material including two 2DEG-containing channel access regions adjacent the gate, one coupled to the source and the other coupled to the drain;
a second layer of a second material having a channel region coupled between the two channel access regions and beneath the gate, wherein the channel region is depleted of conducting charge and is not conductive in the absence of a switching voltage being applied to the gate, but which comprises a 2DEG channel and becomes conductive when a switching voltage greater than a threshold voltage is applied to the gate, thereby completing a conductive path between the source and the drain.
48. The transistor of claim 47, wherein when the switching voltage is applied to the gate, the two channel access regions are connected to the channel region via substantially vertical conducting regions induced by the gate voltage.
49. The III-N semiconductor device of claim 25 wherein the nitride channel layer contains a second pair of channel access regions respectively underneath the two channel access regions in the III-N layer.
50. The III-N semiconductor device of claim 49 where the nitride channel layer makes electrical contact to the source and drain.
51. The III-N semiconductor device of claim 49 having an additional AlN layer between about 4 and 30 Å thick between the nitride channel layer and the AlXN layer.
52. The III-N semiconductor device of claim 25 wherein the nitride channel layer, the AlXN layer, the III-N layer, and the AlmYN layer are all oriented in a nonpolar direction or in a Ga-terminated semipolar direction.
53. The III-N semiconductor device of claim 52 wherein the III-N layer or the AlmYN layer is n-doped.
54. The III-N semiconductor device of claim 53 wherein the n-dopant is Si.
55. A III-N semiconductor device comprising:
a nitride channel layer including a first channel region beneath a recessed gate region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof;
a III-N layer adjacent the nitride channel layer and surrounding the recessed gate region, the III-N layer including two channel access regions on opposite sides of the first channel region and respectively connected to a source and a drain,
an AlmYN layer adjacent to the III-N layer and surrounding the recessed gate region, wherein Y is selected from the group consisting of gallium, indium or their combination,
the first channel region being non-conductive in the absence of a switching voltage applied to the gate, but being conductive in the presence of a switching voltage greater than a threshold voltage applied to the gate, creating a 2DEG region in the first channel region and through a gate-induced, substantially vertical conducting region through the III-N layer, thereby completing the conduction path through the two channel access regions, the first channel region and the vertical conducting region from the source to the drain.
56. The device of claim 55 having an additional AlN layer between about 4 and 30 Å thick between the III-N layer and the AlmYN layer, and wherein the concentration m of Al in the AlmYN layer and its thickness are selected to induce a 2DEG charge in the two channel access regions.
57. The III-N semiconductor device of claim 25 wherein the thickness of the additional III-N layer is in the range of about 200 Å to 2000 Å.
58. The III-N semiconductor device of claim 41 wherein the thickness of the additional III-N layer is in the range of about 200 Å to 2000 Å.
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