GATE DRIVE FOR LOWER SWITCHING NOISE EMISSION

[0001] This application claims the benefit and priority of U.S. Provisional patent application Ser. No. 60/736,799 filed Nov. 15, 2005 entitled GATE DRIVE FOR LOWER SWITCHING NOISE EMISSION, the entire disclosure of which is incorporated herein by reference.

[0002] The invention relates to gate drive circuits and, in particular to such circuits with reduced electromagnetic interference (EMI) emission without sacrificing efficiency as compared to conventional circuits, such as those requiring large gate resistor insertion.

[0003] In general, switching applications have a trade off between efficiency and EMI emissions. In order to get better efficiency, higher switching speed is required. The higher the speed, the steeper the transient which is generated due to stray inductances and capacitances and the greater the EMI.

[0004] An aim of this invention is to reduce EMI emission without reducing efficiency significantly.

[0005] In a typical hard switching application, one of the main noise sources of EMI emission is di/dt spikes caused by the body diode reverse recovery charge Q_RR which usually has sharp waveforms and triggers harmful ringing. This Qrr discharging current can be sharp and large because of low impedance between the power supply top rail and bottom rail and high resonant factor Q.

[0006] One of the simplest conventional methods for reducing EMI noise in gate driving stages is to place a resistor Rg in series with the gate of the MOSFET, slowing down turn-on/turn-off speed by limiting the amount of gate drive current.

[0007] One problem with this method is the effectiveness of this gate resistor is not equal to either the Qrr discharging period or transition period. The effectiveness of Rg varies during the turning on process due to the Millar effect; the resistor slows down the turn-on process the most when the drain voltage is in transition. However, the time period when di/dt needs to be reduced for smaller Qrr is before the drain-source voltage starts to fall. As a result, the amount of resistance which is required to slow down the process has more effect in the reverse recovery discharging period than in the voltage transition period. Therefore switching loss increases significantly even though reverse recovery discharging is slowed down.

[0008] According to the invention, a gate driver stage is provided wherein the turn-on speed is dynamically adjusted based on the status of the MOSFET. The gate driver slowly turns on the MOSFET at the beginning of the turn-on process, then it speeds up once the drain-source voltage starts to drop.

[0009] In the embodiment described, the gate driver has a pair of current sourcing transistors, e.g., FETS, to drive the gate of the MOSFET switch. One transistor is for slow turn-on, the other for faster turn-on. When the gate driver initially starts to turn-on the MOSFET, only the smaller transistor is activated. A dV/dt detection block monitors the voltage transition in the drain node with respect to the source. Once the dV/dt detection block senses that the drain-source voltage starts to fall, the larger gate driver transistor is turned on to accelerate the turn-on process.

[0010] Although the embodiment described has two current sourcing transistors for driving the MOSFET gate, the invention could be implemented using a different number of transistors, e.g., one current sourcing transistor or three or more. If one is used, the same transistor can initially be driven on slowly to deliver a lower gate current, and once the voltage across the driven MOSFET begins to drop, the gate sourcing transistor can be driven on more rapidly, thus implementing the invention.

[0011] If three or more gate sourcing transistors are used, the transistors can be driven on in a phased sequence when VDS of the driven MOSFET begins to drop or some of these transistors can be driven on simultaneously in order to achieve the desired gate drive waveform to reduce EMI and obtain the other benefits described herein.

[0012] Considering the fact that the voltage across the body diode of the power MOSFET switch can not be reverse biased before Qrr discharges, by the time the drain-source voltage transition begins, the process of the Qrr discharge is completed. Thus, the later faster switching process can reduce switching losses without affecting the body diode discharging process which is considered to be the trigger of harmful ringing.

[0013] Another benefit of this method is that the magnitude of the Qrr itself is reduced by decreasing the di/dt by slowing down the turn-on of the MOSFET. The di/dt is usually what triggers harmful ringing. This method is effective to reduce reverse recovery charge by reducing di/dt at the turning on edge of the MOSFET, while it can still keep the same dV/dt transition time in order not to increase switching losses further.

[0014] Thus, the invention changes the gate driving sourcing current in accordance with the change in drain to source voltage of the MOSFET being driven. The MOSFET is turned on slowly when the drain voltage has not yet started to fall. The MOSFET is turned on rapidly after the drain-source voltage transition starts. This function is enabled only when the gate drive signal is supposed to be high. The dead-time amount can be changed according to the dV/dt in accordance with the invention.

[0015] A primary application of the invention is Class D audio amplifier gate drivers for audio systems, for example, automotive audio systems. This gate drive technique is applicable to any MOSFET or IGBT gate driver where di/dt is a primary concern for EMI, which tends to be significant in lower voltage, higher current applications

[0016] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.

[0017] FIG. 1 shows a circuit diagram of a gate driver according to the invention;

[0018] FIG. 2 shows waveforms for the circuit of FIG. 1;

[0019] FIG. 3 shows prior art waveforms; and

[0020] FIG. 4 shows how the booster of the circuit of FIG. 1 is controlled.

[0021] With reference to FIG. 1, the gate drive circuit of the invention comprises two current sourcing switches, e.g. FETs Q2 and Q4. Q2 is smaller than Q4 and sources less current. Transistor Q1 is driven in complementary fashion to Q2 by the inverter INV2. The common node between Q1 and Q2 drives the gate of the power MOSFET Q6, here shown as the low side switch, but the circuit is applicable to the high side power MOSFET Q5 also. Q5 and Q6 comprise a typical half bridge output stage, driving the load indicated as inductor L, capacitor C and resistor R across which VOUT is generated. The load may be, for example, a loudspeaker of a Class D audio amplifier.

[0022] A supply voltage VCC is provided to power the driver. A transistor Q3 acts as an enabling stage to allow the booster transistor Q4 to be turned on only when the LO signal is high, i.e., when LONOT is low. An RC circuit comprising a resistor R1 and capacitor C1 acts as a dv/dt detector.

[0023] Again turning to FIG. 1, assuming initially, the high side FET Q5 is on and low side FET Q6 is off, during low side off state (LO=0), Q1 and Q3 are on. Q3 disables the dV/dt boost action of transistor Q4 when the low side switch Q6 is off. This can avoid the potential misfiring of Q4 causing shoot-through from noise on +B bus voltage. As soon as the high side turns off, the inductor L current IL starts to flow through the body diode of the high side FET. The inductor L current IL flows through the body diode of the high side switch Q5 during the dead-time period. After the dead-time period, the low side switch Q6 starts to turn-on when switch Q2 is turned on (LO=1). Q3 is also turned off and enables the dV/dt booster FET Q4 to be ready to be turned on. As soon as the low side switch Q6 turns on, the reverse recovery charge Q_RR stored in the body diode of the high side switch starts to discharge. During the discharge period, the voltage potential of the switching node Vs stays at +B. Therefore Q4 does not turn on. After the Qrr discharge, the switching node voltage Vs starts to decrease. The dV/dt of the switching node Vs is detected by the capacitor C1, coupling the dV/dt spike to the gate of Q4, turning on the booster FET Q4. Once the low side switch Q6 completely turns on, Q4 is turned off, with Q2 remaining on.

[0024] FIG. 2 shows the waveforms for the circuit of FIG. 1. This example of the operation shows how the low side FET is driven. The high side FET implementation can be done in a similar way.

[0025] With the proposed method, the peak from Qrr is reduced by the slow initial turn-on. However, it does not impact the switching transition time as the booster FET comes on as soon as Vds starts to fall.

[0026] FIG. 3 shows waveforms for the conventional method. With the conventional method, the Vds transition time duration gets longer as Rg increases. In the circuit of FIG. 1, the switching duration Vds does not change appreciably and EMI is also reduced because of the reduced di/dt.

[0027] Booster gating switch Q3 disables the booster FET Q4 from turning on when the FET is not supposed to be turned on. The gating signal is fed by the drive input signal LO/HO. Without this gating, the power MOSFET could be turned on when the bus voltage has large noise that can trigger dv/dt detection of Vds, causing shoot-through. The booster gating is shown in FIG. 4. When Q3 gate is low, the booster Q4 is enabled (when LO=1).

[0028] Although FETs Q5 and Q6 are shown in the drawings, the invention is also applicable to IGBTs. Furthermore, the gate drive circuit described shows FETs, but other transistors could be used, e.g., bipolar transistors, to implement the gate drive circuit.

[0029] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore the present invention should be limited not by the specific disclosure herein, but only by the appended claims.