US 8,520,420 B2Grant
Controller for modifying dead time between switches in a power converter
Issue Date:2013-08-27
•20 Claims
•6 Drawing Sheets
Abstract
A power converter employing a controller configured to increase a dead time between conduction periods of first and second power switches therein and method of operating the same. In one embodiment, the power converter includes first and second power switches coupled to an input thereof, and a sensor configured to provide a sensed signal representative of at least one of a current level and a power level of the power converter. The power converter also includes a controller configured to increase a dead time between conduction periods of the first and second power switches when the sensed signal indicates a decrease of at least one of the current level and the power level of the power converter.
Metadata
Assignee
- Power Systems Technologies, Ltd.
Inventors
- Aaron Jungreis
- Antony Brinlee
- Paul Garrity
Application Information
Application Number:US 12/642,448
Filing Date:2009-12-18
Priority Date:2009-12-18
Art Unit:2838
Classifications
IPC:
H02M3/335
Patent Drawings (6 sheets)
Description
Technical Field
[0001] The present invention is directed, in general, to power electronics and, more specifically, to a power converter employing a controller configured to control a dead time between conduction periods of power switches and method of operating the same.
Background
[0002] A switched-mode power converter (also referred to as a “power converter” or “regulator”) is a power supply or power processing circuit that converts an input voltage waveform into a specified output voltage waveform. Dc-dc power converters convert a direct current (“dc”) input voltage into a dc output voltage. Controllers associated with the power converters manage an operation thereof by controlling conduction periods of power switches employed therein. Some power converters include a controller coupled between an input and output of the power converter in a feedback loop configuration (also referred to as a “control loop” or “closed control loop”) to regulate an output characteristic of the power converter. Typically, the controller measures the output characteristic (e.g., an output voltage, an output current, or a combination of an output voltage and an output current) of the power converter, and based thereon modifies a duty cycle, an on time or a switching frequency of a power switch of the power converter to regulate the output characteristic. Other power converters operate in an open-loop manner wherein an output voltage is produced substantially proportional to an input voltage.
[0003] A power converter with a low power rating designed to convert an alternating current (“ac”) mains voltage to a dc output voltage to power a load such as an electronic device (e.g., a printer, a modem, or a personal computer) is generally referred to as an “ac power adapter” or a “power adapter,” or, herein succinctly, as an “adapter.” Industry standards and market needs have required continual reductions in no load and low-load power supply loss to reduce power consumed by millions of power converters that may remain plugged in, but are not in use, or that may supply a light load level to an electronic device that is not operating at its full capacity. Efficiency requirements at low output power levels have become important in view of the typical load presented by an electronic device in an idle or sleep mode, or an electronic device not operating at full capacity, which are common operational states for a large fraction of the time for electronic devices such as personal computers and printers in a home or office environment.
[0004] Power loss of a power converter is dependent on gate drive voltages for the power switches and other continuing power losses that generally do not vary substantially with the load. These power losses are commonly addressed at very low power levels by using a burst mode of operation wherein the controller is disabled for a period of time (e.g., one second) followed by a short period of high power operation (e.g., 10 milliseconds (“ms”)) to provide a low average output power with low dissipation.
[0005] Light load power losses, while relatively small, have now become substantial hindrances to improving power converter efficiency as industry requirements become stricter. Thus, despite the development of numerous strategies to reduce power losses of power converters, no satisfactory strategy has emerged to provide substantial reduction of power dissipation while the power converter provides minimal or no power to a load. Accordingly, what is needed in the art is a design approach and related method for a power converter that enables further reduction of power converter losses without compromising product performance, and that can be advantageously adapted to high-volume manufacturing techniques.
Summary of the Invention
[0006] These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by advantageous embodiments of the present invention, including a power converter employing a controller configured to control a dead time between conduction periods of power switches and method of operating the same. In one embodiment, the power converter includes first and second power switches coupled to an input thereof, and a sensor configured to provide a sensed signal representative of at least one of a current level and a power level of the power converter. The power converter also includes a controller configured to increase a dead time between conduction periods of the first and second power switches when the sensed signal indicates a decrease of at least one of the current level and the power level of the power converter.
[0007] The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
Brief Description of the Drawings
[0008] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
[0009] FIGS. 1 and 2 illustrate schematic diagrams of embodiments of power converters constructed according to the principles of the present invention;
[0010] FIG. 3 illustrates a graphical representation of an exemplary operation of a power converter in accordance with the principles of the present invention;
[0011] FIG. 4 illustrates a graphical representation of an exemplary power converter efficiency versus load according to the principles of the present invention;
[0012] FIG. 5 illustrates a schematic diagram of an embodiment of sensor constructed according to the principles of the present invention; and
[0013] FIG. 6 illustrates a schematic diagram of an embodiment of a controller constructed according to the principles of the present invention.
[0014] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated, and may not be redescribed in the interest of brevity after the first instance. The FIGUREs are drawn to illustrate the relevant aspects of exemplary embodiments.
Detailed Description of Illustrative Embodiments
[0015] The making and using of the present exemplary embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
[0016] The present invention will be described with respect to exemplary embodiments in a specific context, namely, a power converter configured to provide reduced power dissipation at no load or at light load. While the principles of the present invention will be described in the environment of a power converter, any application that may benefit from a power converter with reduced power dissipation including a bias supply, a power amplifier, or a motor controller is well within the broad scope of the present invention.
[0017] A resonant full-bridge or half-bridge power converter, or other resonant power converter topology with a substantially symmetric input current waveform, may be employed in low power and other applications such as in a power adapter for a printer because of its low cost and high power conversion efficiency at power levels of interest for these applications. Power converters are typically designed to operate continuously at their full rated output power level. Recall that loads coupled to power converters such as a load provided by a printer and personal computer are generally variable and usually do not operate for an extended period of time at a rated power level. A consideration for the design of power converters for such applications is power conversion efficiency at no load and at light loads.
[0018] A conventionally designed power converter may employ a burst mode of operation to reduce no load or light load losses of a power converter by using a short duration of operation (i.e., by employing a high power “burst” followed by a longer idle period). An output capacitor coupled across output terminals of the power converter stores energy to maintain an output voltage during the idle period. At the beginning of the high power burst, current drawn by the power converter from the ac mains is high and may remain so throughout the burst. The duration of the idle periods are typically fixed, and on periods are adjusted to provide output voltage regulation. Thus, a conventionally designed power converter operates in a burst mode only at a high power level or is turned off for fixed periods of time.
[0019] Turning now to FIG. 1 , illustrated is a schematic diagram of an embodiment of a power converter (e.g., a resonant half-bridge dc-dc power converter) constructed according to the principles of the present invention. The power converter includes first and second power switches Q1, Q2 in series with a dc bus (at an input of the power converter) produced by a dc input voltage source 110, represented in FIG. 1 by a battery, and filtered by an electromagnetic interference (“EMI”) filter 120. First and second switch capacitors CQ1, CQ2 represent capacitances of the first and second power switches Q1, Q2, respectively, or alternatively, discrete capacitors optionally included in the power converter to retard voltage changes across the first and second power switches Q1, Q2. The EMI filter 120 provides a substantially filtered dc bus voltage or input voltage Vin to a magnetic device (e.g., an isolating transformer or transformer T1). Typically, the dc input voltage source 110 would be produced by a bridge rectifier or by a power-factor correction stage. Although the EMI filter 120 illustrated in FIG. 1 is positioned between the dc input voltage source 110 and the half-bridge capacitor voltage divider formed by first and second divider capacitors C4, C5, the EMI filter 120 may contain filtering components positioned elsewhere in the power converter. The transformer T1, coupled to the first and second power switches Q1, Q2, has a primary winding Np and secondary windings Ns1, Ns2 with a turns ratio n:1:1 that is selected to provide an output voltage Vout with consideration of the range of the input voltage Vin and stress on the power train of the power converter. A resonant full-bridge dc-dc power converter may be formed with two power switches substituted for the first and second divider capacitors C4, C5. Each of the added power switches in a full-bridge configuration would be switched substantially synchronously with a diagonally oriented power switch.
[0020] The first and second power switches Q1, Q2 (e.g., n-channel field-effect transistors) are controlled by a controller 140 that produces control signals (e.g., gate-drive signals DQ1, DQ2) to control the first and second power switches Q1, Q2 to conduct for particular intervals of time (i.e., for particular “on” times). The term “signal” is used herein to represent, without limitation, a physical voltage or current. The first and second power switches Q1, Q2 alternately conduct in response to the gate-drive signals DQ1, DQ2 (e.g., gate-drive voltages) produced by the controller 140 with a switching frequency (designated “fs”) and a corresponding switching period Ts=1/fs. The ac voltage appearing or present on the secondary windings Ns1, Ns2 of the transformer T1 is rectified by first and second diodes D1, D2, and the dc component of the resulting waveform is coupled to the output through the low-pass output filter formed with output filter capacitor Cout to produce the output voltage Vout. A sensor (e.g., a current-sense circuit 130) senses a condition of the power converter such as a current level of the primary current Ipri that flows through the primary winding Np of the transformer T1 and provides a sensed signal (e.g., a sensed current IT) for the controller 140 representative of a level of the primary current Ipri, such as a peak or root-mean-square value of the primary current Ipri. Thus, the current-sense circuit 130 is coupled to a resonant circuit (see below) and is configured to provide a sensed signal (e.g., a sensed current IT) representative of a current level or a power level of the power converter.
[0021] The power converter is operated as a resonant half-bridge topology. The term “resonant” is employed herein to refer to a switch-mode topology employing a resonant tank circuit or resonant circuit formed principally by a resonant capacitor C1 and a resonant inductor Lres to produce a current waveform that is a portion of, but typically not a full, sinusoidal waveform. The resonant circuit is series-coupled to the transformer T1. The circuit node between the first and second divider capacitors C4, C5 substantially remains at a voltage approximately equal to half of the input voltage Vin with respect to a primary ground, which is identified with the symbol “p.” The secondary ground is identified with the symbol “s.” The source of second power switch Q2 is coupled to the primary ground p.
[0022] The resonant capacitor C1 and the first and second divider capacitors C4, C5 are coupled together at common circuit node N0. The first and second divider capacitors C4, C5 are roughly equal in capacitance and the combination is larger in capacitance than that of the resonant capacitor C1. Such a structure provides symmetry from an EMI perspective for high frequency currents fed back to the dc input voltage source 110, and also provides a relatively unvarying voltage at the common circuit node N0. In an alternative embodiment, one or both of the resonant capacitor C1 and the first divider capacitor C4 can be omitted from the power converter. If both the resonant capacitor C1 and the first divider capacitor C4 are omitted from the power converter, the second divider capacitor C5 would be selected with a capacitance similar to that of resonant capacitor C1. First and second clamping diodes DU, DL provide a clamping mechanism to limit the voltage at the common node N0 to be no greater than the input voltage Vin, and no lower than the primary ground p.
[0023] The resonant inductor Lres includes the leakage inductance of the transformer T1 referenced to its primary winding. The effective resonant capacitance is Ceff; given by the equation:
Ceff=C1·(C4+C5)/(C1+C4+C5).
The half period Thalf of the resonant circuit, which is the period during which a power switch is turned on, can be represented approximately by the equation:
Thalf=π·√{square root over (Lres·Ceff)}.
Ceff=C1·(C4+C5)/(C1+C4+C5).
The half period Thalf of the resonant circuit, which is the period during which a power switch is turned on, can be represented approximately by the equation:
Thalf=π·√{square root over (Lres·Ceff)}.
[0024] Provided that the power switch on times are approximately equal to the half period Thalf shown above, the power converter operates as a “dc transformer” that produces an output voltage Vout substantially proportional to the input voltage Vin. The output-to-input voltage ratio is substantially fixed by the transformer T1 turns ratio, and thus the power converter per se does not provide output voltage regulation. The output voltage Vout is substantially independent of the switching frequency of the first and second power switches Q1, Q2 over an operating range. Regulation of the output voltage Vout can be provided by a pre-converter stage (not shown) that regulates the input voltage Vin to the power converter illustrated in FIG. 1 .
[0025] As introduced herein, control (e.g., modification, alteration, variation, etc.) of the switching frequency is employed to reduce power converter power dissipation at a low load or at no load. In an embodiment, the dead time between fixed on times (or conduction periods) of the first and second power switches Q1, Q2 is varied to control the switching frequency. Neither the dead times between power switch conduction periods nor the on times of the first and second power switches Q1, Q2 are required to be equal. In an embodiment, the on times of the first and second power switches Q1, Q2 are substantially equal to the half period Thalf defined by the resonant inductor Lres and the effective resonant capacitance is Ceff. Of course, the dead times may be substantially equal.
[0026] Turning now to FIG. 2 , illustrated is a schematic diagram of an embodiment of a power converter (e.g., a resonant half-bridge dc-dc power converter) constructed according to the principles of the present invention. The power converter illustrated in FIG. 2 is similar to that illustrated in FIG. 1 but now includes first and second impedances Z1, Z2 coupled across (e.g., parallel-coupled to) the first and second diodes D1, D2, respectively. The first and second impedances Z1, Z2 may be formed with ceramic capacitors substantially tuned to a frequency of a damped oscillation of a voltage produced across the first and second diodes D1, D2 when the diodes are back biased during a switching cycle of the power converter. The first and second impedances Z1, Z2 are configured to convert the damped oscillatory voltage produced across the first and second diodes D1, D2 to a dc current supplied to the output voltage Vout of the power converter as a further efficiency enhancing process. The first and second impedances Z1, Z2 may include a nonlinear circuit element such as a diode to enable conversion of the oscillatory voltage produced across the first and second diodes D1, D2 to the dc current supplied to the output voltage Vout of the power converter.
[0027] Turning now to FIG. 3 , illustrated is a graphical representation of an exemplary operation of a power converter (e.g., the power converter of FIG. 1 ) in accordance with the principles of the present invention. The first two waveforms (designated DQ1 and DQ2) illustrate the control signals (gate-drive signals) produced by the controller 140 for the first and second power switches Q1, Q2, respectively, in time (milliseconds (“ms”)). The third waveform (designated Ipri) illustrates the current (in milliamperes (“mA”) versus time in milliseconds) that flows through the primary winding of the transformer T1. The fourth waveform (designated Idrain) illustrates a drain current (in amperes (“A”) versus time in milliseconds) of the second power switch Q2. The fifth waveform (designated Vds —Q2) illustrates the drain-to-source voltage (in volts (“V”) versus time in milliseconds) of the second power switch Q2. FIG. 3 illustrates dead times (designated “dead time”) between the on times (or conduction periods) of the first and second power switches Q1, Q2 that are controlled by the controller 140. In addition, FIG. 3 illustrates a pulse of current 310 that flows out the drain (designated Idrain) of the second power switch Q2 to discharge an output capacitance thereof (e.g., the second switch capacitor CQ2). FIG. 3 also illustrates that a portion 320 of the waveform of current that flows through the primary winding (designated Ipri) of the transformer T1 is a portion of a sinusoidal waveform.
[0028] At a high output power level, the power train is operated at a switching frequency that is a little lower, for example ten percent lower, than the resonant frequency fres of the resonant circuit. At a high output power level, the on time Ton of each of the first and second power switches Q1, Q2 corresponds to an on time that is equivalent to a frequency that is a little higher, for example three percent higher, than the resonant frequency of the resonant circuit. In other words, the on time Ton for each of the first and second power switches Q1, Q2 is a little shorter or less than the half period Thalf of the resonant circuit, and together the first and second power switches Q1, Q2 are on for a period of time that is a little shorter or less than twice the half period Thalf. The on times Ton of the first and second power switches Q1, Q2 are not necessarily equal. Thus, the first and second power switches Q1, Q2 and the first and second diodes D1, D2 are turned off prior to the time the current in the resonant circuit reaches zero, and the switching period is kept long enough (including delay times) to assure that, throughout the tolerance band of variations of power converter inductances and capacitances, the current through a diode on a primary side of the power converter will shift to an anti-parallel diode (or body diode) of the power switch that is about to be turned on prior to turning on the same or that the resonant current has decayed to approximately zero.
[0029] In a conventional design, the power converter illustrated in FIG. 1 is operated at a fixed switching frequency. A drawback of a fixed switching frequency is that switching losses remain substantially constant and relatively high at light loads. The efficiency of the conventionally designed power converter is generally satisfactory over much of the load range except for light loads. The current through the resonant circuit, transformer, and output diodes decreases with load, thus decreasing conduction losses as the load is reduced. However, at light loads the circulating current in the resonant circuit as well as switching losses become high compared to conduction losses. Thus, power conversion efficiency of a conventionally designed converter is generally poor at light loads.
[0030] As introduced herein, a variable dead time dependent on a sensed signal (e.g., a power converter parameter) such as a power level or current level is employed between resonant pulses of a power converter such as a resonant bridge power converter. The current may be sensed on the primary side of the power converter by averaging a ripple voltage in a resonant circuit of the power converter. The sensed current is indicative of a power level of the power converter. Unlike small variations in dead time, such as 100 or 200 nanoseconds (“ns”) variations in dead time employed in conventional designs, to enable zero-voltage switching of a power converter over a range of power converter operating conditions, a variation (e.g., a substantial variation) in dead time is employed herein to improve power conversion efficiency at light loads. Variations in dead time sufficient to provide, without limitation, a factor of ten or more reduction in switching frequency at light loads may be employed herein.
[0031] In U.S. patent application Ser. No. 12/486,520, entitled “Power Converter Employing a Variable Switching Frequency and a Magnetic Device with a Non-Uniform Gap,” to A. Brinlee, et al. (“Brinlee”), filed Jun. 17, 2009, which is incorporated herein by reference, a switching frequency of a power switch of a power converter is controlled as a function of a condition of the power converter representing an output power. Also, a duty cycle of the power switch is controlled to regulate an output characteristic of the power converter. As introduced herein in an exemplary embodiment, dead times between on times (or conduction periods) of power switches is varied, and the power switches in a resonant bridge power converter are operated with a constant (or substantially constant) on time. Additionally, the on time of the power switches may be controlled (e.g., slightly modulated) to reduce or cancel a ripple voltage (e.g., a 120 hertz ripple voltage) of an input voltage source such as an upstream power converter (e.g., a power factor correction converter) to the power converter employing the power switches.
[0032] The dead times may be increased as the load is decreased as indicated by a decrease of a current level or power level of the power converter. This causes the switching frequency of the power converter to decrease at light loads, thereby reducing switching losses. The resonant bridge power converter continues to operate as a dc transformer. Therefore, increasing the dead time causes current through the resonant circuit to increase and sufficient power converter output power is automatically maintained to ensure adequate power transfer to maintain dc-transformer operation. The dead times are advantageously increased for loads below a chosen load point so that power losses can be reduced at low load levels, and conduction- and switching-loss trade-offs can be made for the power converter.
[0033] Turning now to FIG. 4 , illustrated is a graphical representation of an exemplary power converter efficiency versus load according to the principles of the present invention. A first waveform 410 demonstrates the efficiency for a conventional resonant bridge power converter and the second waveform 420 demonstrates an exemplary efficiency for a power converter (e.g., a resonant bridge power converter) constructed according to the principles of the present invention. The efficiency of a conventional resonant bridge power converter typically exhibits a maximum at about 50 to 75 percent load. As illustrated by the second waveform 420, if the dead times are kept relatively low from about 75 to 100 percent load, but is increased for loads below about 50 to 75 percent, the efficiency of the resonant bridge power converter according to the present invention remains relatively high down to small loads. It should be understood that the load point may be selected at a difference level and still fall within the broad scope of the present invention.
[0034] Turning now to FIG. 5 , illustrated is a schematic diagram of an embodiment of sensor (e.g., a current-sense circuit) 510 constructed according to the principles of the present invention. The current-sense circuit 510 produces a sensed signal (e.g., a sensed current IT) representative of a current in a power converter such as the resonant bridge power converter illustrated in FIG. 1 . The current-sense circuit 510 illustrates the use of a one-shot 520 to produce a variable delay. For purposes of illustration, the second divider capacitor C5 and the resonant inductor Lres from FIG. 1 are illustrated herein.
[0035] A typical way to use a one-shot 520 is to connect a timing capacitor CT (e.g., 100 pico farads) between the input pin RTCT and local circuit ground (which is identified with the symbol “p”), and a timing resistor RT (e.g., one mega ohm) from the pin RTCT to a positive bias voltage source VCC. When the one-shot 520 is triggered, it releases the pin RTCT to rise. The rate of rise is controlled by current flowing through the timing resistor RT. When a certain threshold voltage level is reached at the pin RTCT, the one-shot 520 pulls the pin RTCT down again, and keeps the pin RTCT low until it receives another trigger input.
[0036] Control of the dead times is implemented by monitoring average ripple voltage at a resonant capacitor (such as the resonant capacitor C1 of FIG. 1 ) and supplying the sensed current IT representative of a current in the resonant capacitor C1. The ripple voltage is coupled to the current-sense circuit 510 with high-voltage sense capacitor Csense. After sensing the ripple voltage with the high-voltage sense capacitor Csense in conjunction with a bleeder resistor Rbleeder (e.g., one mega ohm), the voltage is clamped to local circuit ground p with clamp diode D3 so that the sense capacitor Csense becomes charged to a value that represents the sensed current as a positive voltage. The first and second delay resistors R1, R2 set the maximum and minimum delays. Typically, the first delay resistor R1 is less than one kilo ohm and the second delay resistor R2 is greater than one mega ohm. Actual values may be determined by the switching frequency range desired. A positive voltage injects the sensed current IT through the second delay resistor R2 into the timing capacitor CT. The timing resistor RT also injects a dc current into the timing capacitor CT slightly less than VCC/RT.
[0037] In an alternative embodiment, the timing resistor RT coupled to the bias voltage source VCC can be replaced with a current source providing a current slightly less than VCC/RT. A limiting diode (e.g., Zener diode Z) can be used to limit the sensed current IT to a maximum value, thereby limiting a maximum value of the load at which the dead time varies (i.e., limiting a modification of the dead time to a dead time limit). A current in the resonant circuit or in another circuit element can be sensed with a different current-sense circuit including a current-sense transformer and a resistor-diode network coupled to a secondary side of the current-sense transformer to produce the sensed current IT. A current-sense resistor coupled to an operational amplifier can also be employed to sense the current in the resonant bridge power converter to produce the sensed current IT.
[0038] As illustrated in FIG. 5 , the sensed current IT is coupled to the RTCT timing pin of one-shot (“monostable multivibrator”) 520 such as a CD4528 one-shot (e.g., a MM74HC4538 produced by Fairchild Semiconductor, described in the Fairchild Semiconductor datasheet titled “MM74HC4538 Dual Retriggerable Monostable Multivibrator,” dated August 2000, which is incorporated herein by reference). The delay produced by one-shot 520 is controlled by the timing capacitor CT and the charging current flowing thereto set by the timing resistor RT coupled to the bias voltage source VCC. A diode DA may be included in the current-sense circuit 510 to add nonlinearity to the timing change produced by the sensed current.
[0039] A lower limit for the switching frequency may be employed by choice of values for the first and second delay resistors R1, R2 and the timing resistor RT to prevent the switching frequency from decreasing into an audible range, such as a range of frequencies below 20 kilohertz (“kHz”). A substantial change in the switching frequency, such as a factor of ten or more change in the switching frequency over a range of loads presented to the power converter, may be employed to improve power conversion efficiency at a low power level. A lower limit of the switching frequency of one or four kilohertz may be employed to produce a substantial change in power conversion efficiency. A small varnished or potted transformer operated at a switching frequency of one or four kilohertz will generally not produce an objectionable level of audible noise. A burst mode of operation may also be employed at a very low load level to provide further improvement in power conversion efficiency.
[0040] Turning now to FIG. 6 , illustrated is a schematic diagram of an embodiment of a controller constructed according to the principles of the present invention. The controller is responsive to a sensed signal (e.g., a sensed current IT) to produce gate-drive signals DQ1, DQ2. Control of the dead times is implemented using a one-shot as illustrated and described with respect to FIG. 5 . A first one-shot 620 creates a fixed pulse length to control the gate-drive signals DQ1, DQ2 whose lengths are slightly less than half of a resonant circuit period. The first one-shot 620 is employed to produce a fixed delay using a conventional resistor-capacitor connection to a RTCT timing pin (not shown). The fixed delay may be set equal to, less than, or greater than a half period of a resonant circuit. This fixed delay corresponds to the on time of the power switches. If the on time of the power switches is greater than a half period of a resonant circuit, an opposing diode will conduct current while the driven power switch is still on, which may cause a current shoot-through that can destroy the power converter. Thus, it is preferable under such circumstances that the fixed delay remains less than or equal to a resonant half-period. A second one-shot 640 is responsive to the sensed current IT representative of the current in the resonant circuit, which is related to power converter load current, to adjust the dead-time length between the conduction periods of power switches such as the first and second power switches Q1, Q2 of the power converter FIG. 1 . In the illustrated embodiment, a current source 690 produces the sensed current IT, which may be representative of the sensed current IT from the current-sense circuit 510 illustrated and described above with respect to FIG. 5 .
[0041] A startup step voltage 605 enables the controller to operate. The startup step voltage 605 is coupled to an input of an AND gate 610, the output of which produces the input for the first one-shot 620 to produce a fixed on time (e.g., 20 microseconds) for the first and second power switches Q1, Q2. The output of the first one-shot 620 is inverted by an inverter 630. The output of the inverter 630 provides a clocked input voltage “clk” for a D-type (“delay”) flip-flop 650. The output of the inverter 630 also provides an input for the second one-shot 640. The output of the second one-shot 640 is inverted by an inverter 660 to provide a variable off-time delay for the first and second power switches Q1, Q2. The output of the second one-shot 640 and the Q and QN (i.e., the normal and the inverted) outputs of the D-type flip-flop 650 are coupled to the inputs of AND gates 670, 680 to provide the gate-drive signals DQ1, DQ2. Analogous to FIG. 5 , a timing capacitor CT is coupled to the input pin RTCT and local circuit ground (which is identified with the symbol “p”) of the second one-shot 640, and a timing resistor RT from the pin RTCT to a positive bias voltage source VCC of the second one-shot 640.
[0042] Thus, a power converter (e.g., a resonant bridge power converter) has been introduced wherein a dead time between conduction periods of power switches therein is controlled in response to a voltage or current representative of a power level or a current level of the power converter. The power converter includes first and second power switches coupled to an input of the power converter, and a sensor coupled to the power converter configured to provide a sensed signal representative of at least one of a current level and a power level of the power converter. The power converter also includes a controller configured to increase a dead time between conduction periods of the first and second power switches when the sensed signal indicates a decrease of at least one of the current level and the power level of the power converter. In a related embodiment, a transformer is coupled to the first and second power switches, and a resonant circuit is series-coupled to a primary winding of the transformer. The sensor is configured to provide the sensed signal by monitoring an average ripple voltage of the resonant circuit. The resonant circuit may include a resonant inductor and a resonant capacitor coupled to the primary winding of the transformer.
[0043] In an alternative embodiment, the sensor may include a sense capacitor, a clamp diode, and at least one delay resistor, and the controller may include a timing resistor, a timing capacitor and a one-shot. The sensor may be configured to limit a value of the sensed signal, thereby limiting a modification of the dead times to a dead time limit. The sensor may also include a limiting diode configured to limit a value of the sensed signal.
[0044] In related embodiments, the controller is configured to control the dead times to control a switching frequency of the first and second power switches. The controller is also configured to control the conduction periods of the first and second power switches to be substantially constant. The controller may be configured to control a conduction period of at least one of the first and second power switches to be substantially equal to (including slightly less than) a half period of a resonant circuit of the power converter. In a further embodiment, a diode and a parallel-coupled impedance are coupled to a secondary winding of the transformer. The parallel-coupled impedance may be configured to convert a damped oscillatory voltage produced across a diode to a dc current supplied to an output of the power converter.
[0045] In another aspect, the present invention provides a method of operating a power converter. The method includes coupling first and second power switches to an input of the power converter, providing a sensed signal representative of at least one of a current level and a power level of the power converter, and controlling a dead time between conduction periods of the first and second power switches as a function of the sensed signal. In a related embodiment, the power converter may include a transformer coupled to the first and second power switches and a resonant circuit in series with a primary winding of the transformer. In accordance therewith, the method may provide the sensed signal by monitoring an average ripple voltage of the resonant circuit.
[0046] Those skilled in the art should understand that the previously described embodiments of a power converter including circuits to reduce no load or light load losses and related methods of operating the same are submitted for illustrative purposes only. While a power converter including circuits to reduce no load or light load losses has been described in the environment of a power converter, these processes may also be applied to other systems such as, without limitation, a bias supply, a power amplifier, or a motor controller.
[0047] For a better understanding of power converters, see “Modern DC-to-DC Power Switch-mode Power Converter Circuits,” by Rudolph P. Severns and Gordon Bloom, Van Nostrand Reinhold Company, New York, N.Y. (1985) and “Principles of Power Electronics,” by J. G. Kassakian, M. F. Schlecht and G. C. Verghese, Addison-Wesley (1991).
[0048] Also, although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
[0049] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
What is claimed is:
1. A power converter, comprising:
first and second power switches coupled to an input of said power converter;
a sensor configured to provide a sensed signal representative of at least one of a current level and a power level of said power converter, and limit a value of said sensed signal; and
a controller configured to increase a dead time between conduction periods of said first and second power switches when said sensed signal indicates a decrease of at least one of said current level and said power level of said power converter, a modification of said dead time being constrained to a dead time limit in accordance with said limit of said value of said sensed signal.
2. The power converter as recited in claim 1 wherein said conduction periods of said first and second power switches are substantially constant.
3. The power converter as recited in claim 1 wherein said controller is configured to control said conduction period of at least one of said first and second power switches to be substantially equal to a half period of a resonant circuit of said power converter.
4. The power converter as recited in claim 1, further comprising:
a transformer coupled to said first and second power switches; and
a resonant circuit coupled to a primary winding of said transformer, wherein said sensor is configured to provide said sensed signal by monitoring an average ripple voltage of said resonant circuit.
5. The power converter as recited in claim 1, further comprising:
a transformer coupled to said first and second power switches; and
a resonant circuit including a resonant inductor and a resonant capacitor coupled to a primary winding of said transformer.
6. The power converter as recited in claim 1 wherein said sensor includes a sense capacitor, a clamp diode, and at least one delay resistor, and said controller includes a timing resistor, a timing capacitor and a one-shot.
7. The power converter as recited in claim 1 wherein said sensor is configured to limit said value of said sensed signal with a limiting diode.
8. The power converter as recited in claim 1 wherein said controller is configured to control said dead time to control a switching frequency of said first and second power switches.
9. The power converter as recited in claim 1 further comprising a diode and a parallel-coupled impedance coupled to a secondary winding of a transformer of said power converter, said impedance being configured to convert a damped oscillatory voltage produced across said diode to a dc current supplied to an output of said power converter.
10. The power converter as recited in claim 1 wherein said controller is configured to control said conduction period of at least one of said first and second power switches to reduce a ripple voltage with respect to an input voltage source at said input of said power converter.
11. A method of operating a power converter, comprising:
coupling first and second power switches to an input of said power converter;
providing a sensed signal representative of at least one of a current level and a power level of said power converter;
limiting a value of said sensed signal; and
controlling said first and second power switches by increasing a dead time between conduction periods thereof when said sensed signal indicates a decrease of at least one of said current level and said power level of said power converter, a modification of said dead time being constrained to a dead time limit in accordance with limiting said value of said sensed signal.
12. The method as recited in claim 11 wherein said controlling said first and second power switches includes controlling said conduction periods of said first and second power switches to be substantially constant.
13. The method as recited in claim 11 wherein said controlling said first and second power switches includes controlling said conduction period of at least one of said first and second power switches to be substantially equal to a half period of a resonant circuit of said power converter.
14. The method as recited in claim 11, further comprising:
coupling a transformer to said first and second power switches;
coupling a resonant circuit to a primary winding of said transformer; and
providing said sensed signal by monitoring an average ripple voltage of said resonant circuit.
15. The method as recited in claim 11, further comprising:
coupling a transformer to said first and second power switches; and
coupling a resonant circuit including a resonant inductor and a resonant capacitor to a primary winding of said transformer.
16. The method as recited in claim 11 wherein said providing said sensed signal is performed by a sensor including sense capacitor, a clamp diode, and at least one delay resistor and said controlling said first and second power switches is performed by a controller including a timing resistor, a timing capacitor and a one-shot.
17. The method as recited in claim 11 wherein said limiting said value of said sensed signal is performed with a limiting diode.
18. The method as recited in claim 11 wherein said controlling said first and second power switches includes controlling a switching frequency thereof.
19. The method as recited in claim 11, further comprising:
coupling a transformer to said first and second power switches;
coupling a diode to a secondary winding of said transformer, and
converting a damped oscillatory voltage produced across said diode to a dc current supplied to an output of said power converter.
20. The method as recited in claim 11 wherein said controlling said first and second power switches includes controlling said conduction period of at least one of said first and second power switches to reduce a ripple voltage with respect to an input voltage source at said input of said power converter.
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