Method and apparatus for measuring the switching current of power converter operated at continuous current mode

[0001] The present application claims the benefit of U.S. provisional application entitled “Method and apparatus for measuring the switching current of power converter operated at continuous current mode”, Ser. No. 61/131,906, filed Jun. 13, 2008.

[0002] 1. Field of the Invention

[0003] The present invention relates generally to a switching control circuit, and more specifically to a method and apparatus for detecting a switching current of a power converter operated at continuous current mode.

[0004] 2. Description of the Related Art

[0005] A power converter is used to convert an unregulated power source to a regulated voltage or current source. The power converter normally includes a transformer or a magnetic device having a primary winding and a secondary winding to provide isolation. A switching device connected with the primary winding to control energy transfer from the primary winding to the secondary winding. FIG. 1 shows a conventional power converter. A controller 50 generates a switching signal V_G to regulate the output of the power converter in response to a feedback signal V_FB. The feedback signal V_FB is correlated to the output V_O of the power converter. The switching signal V_G drives a power transistor 20 for switching a transformer 10. The transformer 10 is connected to an input voltage V_IN of the power converter. The energy of the transformer 10 is transferred to the output V_O of the power converter through a rectifier 40 and a capacitor 45. A resistor 30 is connected serially with the power transistor 20 to generate a switching current signal V_I in response to a switching current I_P of the transformer 10. The switching current signal V_I is coupled to the controller 50 for the control the power converter. The power converter will be operated at discontinuous current mode (DCM) when the transformer 10 is fully discharged before the start of the switching cycle. If the switching signal V_G is enabled before the transformer 10 is fully discharged, the power converter will be operated at continuous current mode (CCM). A continuous current will be remained in the transformer when the power converter operated in the CCM. FIG. 2 shows a CCM waveform of the switching current I_P, in which the continuous current I_A represents the energy stored in the transformer 10. A ramp current I_C is the energy that is further charged into the transformer 10 during the on time T_ON of this switching cycle T. The continuous current I_A stands for a major energy transfer of the transformer 10. A voltage spike and noise are generated at the rising edge of the switching current I_P. The voltage spike and noise will generate error for the sampling. The object of the present invention is to develop a method and apparatus to measure the continuous current I_A and the ramp current I_C of the switching current I_P.

[0006] The present invention proposes an apparatus and a method for detecting a switching current of the power converter, wherein the apparatus comprises a signal generation circuit, a sample-and-hold circuit, and a calculating circuit. Wherein the signal generation circuit generates a sample signal in accordance with the pulse width of a switching signal. The sample-and-hold circuit is coupled to receive the sample signal and switching current signal for generating a first current signal and a second current signal. The calculating circuit is coupled to receive the first current signal and the second current signal for generating output signals. Wherein the switching signal is used for switching the magnetic device of the power converter, and the switching current signal is correlated to the switching current of the power converter; the output signals are correlated to the value of the switching current of the power converter.

[0007] It is to be understood that both the foregoing general descriptions and the following detailed descriptions are exemplary, and are intended to provide further explanation of the invention as claimed. Still further objects and advantages will become apparent from a consideration of the ensuing description and drawings.

[0017] The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0018] FIG. 3 is the circuit schematic of the controller 50 of the invention. A flip-flop 70 and an AND gate 75 generates switching signals S_W and V_G for driving the transistor 20 and switching the transformer 10 (shown in FIG. 1). A detection circuit 100 is coupled to receive the switching current signal V_I for generating the DC-output signal V_XA and the AC-output signal V_XC. The detection circuit 100 includes a signal generation circuit 150, a sample-and-hold circuit 200 and a calculating circuit 300. The signal generation circuit 150 generates a sample signal S₂ in accordance with the pulse width of the switching signal S_W. The sample-and-hold circuit 200 is coupled to receive the sample signal S₂ and switching current signal V_I for generating a first current signal I_MB and a second current signal I_MD. A calculating circuit 300 is couple to receive the first current signal I_MB and the second current signal I_MD for generating output signals DC-output signal V_XA and the AC-output signal V_XC. The output signals DC-output signal V_XA and the AC-output signal V_XC are correlated to the value of the switching current I_P of the power converter.

[0019] Referring to FIG. 4 to FIG. 6, wherein FIG. 4 shows the signal generation circuit 150. It includes a charge circuit, capacitors 160, 161, and an output circuit. A current source 151 and switches 153, 154, 157 develop the charge circuit. It is coupled for charging the capacitors 160 and 161. The capacitor 160 generates a slope signal S_S. The capacitor 161 generates a level signal S_L in response to the current charged in the capacitor 160 during last switching cycle. The level signal S_L is correlated to the pulse width of the switching signal S_W. A divider, formed by resistors 167 and 168, generates a divided-signal S_d in accordance with the level signal S_L through the buffer 165. The divided-signal S_d is therefore correlated to the ratio

[0020] $\left(\mathrm{for}\mathrm{example},\frac{n-1}{n}\right)$
of the level signal S_L. An output circuit developed by a NOR gate 171, a comparator 170 and a flip-flop 175 generates the sample signal S₂ in response to a comparing result signal S_C and a first one shot signal S_M1. The comparing result signal S_C is generated in response to the divided-signal S_d and the slope signal S_S through a comparator 170. The signal generation circuit 150 further comprises one shot circuits 181 and 182 for generating the first one shot signal S_M1 and a second one shot signal S_M2.

[0021] FIG. 5 shows the schematic view of the one-shot circuit such as one-shot circuits 181 and 185 shown in FIG. 4, a constant current source 190 is used to charge a capacitor 193 once a transistor 192 is turned off. The input terminal IN of the one-shot circuit 181 and 185 is connected to the gate of the transistor 192 and one input of a NOR gate 196. The other input of the NOR gate 196 is connected to the capacitor 193. Therefore, the one-shot circuit generates a one-shot signal at the output of the NOR gate 196 in response to the falling edge of the input signal of the one-shot circuit. The current of the constant current source 190 and the capacitance of the capacitor 194 determine the pulse width of the one-shot signal.

[0022] FIG. 6 shows the waveforms of the circuit illustrated in FIG. 4 and FIG. 5. Because the value of the divided-signal S_d is correlated to the ratio of the level signal S_L, and the level signal S_L is correlated to the pulse width of the switching signal S_W, therefore the sample signal S₂ is reset once the level of the slope signal S_S is larger than the level signal S_L.

[0023] FIG. 7 shows an embodiment of the sample-and-hold circuit 200. Referring to FIG. 6 together. The sample-and-hold circuit 200 includes a first capacitor 216 coupled to receive the switching current signal V_I for generating a first sample signal S_f1 in response to the switching signal S_W and transfer the first sample signal S_f1 to the capacitor 217 in response to the second one shot signal S_M2. A second capacitor 256 is coupled to the switching current signal V_I to generate a second sample signal S_f2 in response to the sample signal S₂ and transfer the second sample signal S_f2 to the capacitor 257 in response to the enabled second one shot signal S_M2. A first V-to-I circuit developed by an operational amplifier 220, a transistor 225 and a resistor 221 generates a first V-to-I current I_V1 in accordance with the first sample signal S_f1. A second V-to-I circuit developed by an operational amplifier 260, a transistor 265 and a resistor 261 generates a second V-to-I current I_V2 in accordance with the second sample signal S_f2. A first current mirror (transistors 230, 231, 232 and 233) generates current signals I_MB I_MB1 and I_MB2 (first current signal) in response to the first V-to-I current I_V1. In the embodiment, the ratio of the first current mirror is equal to 1, I_MB=I_MB1=I_MB2. A second current mirror (transistors 270, 271, 275, 276) whose ratio is equal to 1 generates current signal I_MM proportional to the second V-to-I current I_V2, and a second current signal I_MD in response to the differential of the first current signals I_MB and the current signal I_MM. Because the first current signal I_MB is mirrored from the first V-to-I current I_V1, and current signals I_MM is mirrored from the second V-to-I current I_V2, the second current signal I_MD is therefore in proportion to the differential of the first current signals I_MB and the current signal I_MM.

[0024] FIG. 8 shows the waveform of the switching current signal V_I. Point C and B represent a peak point and a sampled point in the waveform respectively. I_B shows the peak current of the peak point C, and I_M represents the sample current of the sample point B; I_D represents the differential of the peak current I_B and the sample current I_M. The continuous current I_A represents the energy stored in the transformer 10. The ramp current I_C is the energy that is further charged into the transformer 10 during the on time T_ON. The continuous current I_A and the ramp current I_C can be expressed, Because Slope S_CB=S_CA.

[0025] $\begin{array}{cc}\frac{I_D}{T_M}=\frac{I_C}{T_{\mathrm{ON}}}& \left(1\right)\end{array}$
T_ON=n×T_M  (2)
I_D=I_B−I_M  (3)
I_C=n×I_D  (4)

[0026] From the equations (1) to (4), we can get
I_C=n×(I_B−I_M)  (5)
I_A=I_B−I_C  (6)

[0027] FIG. 9 is the calculating circuit 300. It is couple to receive the first current signals I_MB1 and I_MB2 and the second current signal I_MD for generating DC-output signal V_XA and the AC-output signal V_XC. The calculating circuit 300 comprises a first current mirror (transistors 310, 311), second current mirror (transistors 315, 316, and 317) and a third current mirror (327, 328) coupled to receive the first current signal I_MB and the second current signal I_MD for generating the DC-output signal V_XA through a resistor R₃₆₀. A fourth current mirror (transistors 353, 354) and a fifth current mirror (transistors 356, 357) are coupled to generate the AC-output signal V_XC. In the embodiment, the ratio of the each of the second current mirror, the third current mirror, the fourth current mirror, and the fifth current mirror is equal to 1. The current signals I_O1 ˜I_O5 of the calculating circuit 300 can be express by,
I_O1=n×I_MD=n×(I_MB1−I_MM)=n×(I_MB−I_MM)  (7)
I_O2=I_MB1−I_O1=I_MB−n(I_MB−I_MM)   (8)
I_O3=I_MB2−I_O2=I_MB−[I_MB−n(I_MB−I_MM)]=n(I_MB−I_MM)  (9)
V_XC=I_O5×R₃₆₀=I_O3×R₃₆₀=n(I_MB−I_MM)×R₃₆₀  (10)
V_XA=I_O4×R₃₇₀=I_O2×R₃₇₀=[I_MB−n(I_MB−I_MM)]×R₃₇₀  (11)

[0028] From the above description, and referring to FIG. 6 to FIG. 8. The first current signal I_MB is mirrored form the first V-to-I current I^V1, and the first V-to-I current I_V1 represents the peak current I_B. The current signal I_MM is mirrored form the second V-to-I current I_V2, and the second V-to-I current I_V2 represents the sample current I_M. Where first current signal I_MB and current signal I_MM can be expressed,
I_MB=I_V1=I_B  (12)
I_MM=I_V2=I_m  (13)
So the first signal I_MB represents the peak current I_B, the current signal I_MM represents the sample current I_M,

[0029] Form the equations (12) and (13), the equations (10) and (11) can be expressed,
V_XC=n(I_MB−I_MM)×R₃₆₀=n(I_B−I_M)×R₃₆₀=I_C×K₀  (14)
V_XA=[I_MB−n(I_MB−I_MM)]×R=[I_B−n(I_B−I_M)]×R=I_A×K₁  (15)
where n is the constant of the ratio and K₀ and K₁ are constant.

[0030] So, from the equations (14) and (15), the DC-output signal V_XA and the AC-output signal V_XC are correlated to the value of the switching current.

[0031] In summary, we can sample the signal in accordance with the pulse width of a switching signal of the power converter, and the voltage spike and noise will not influence the sampling. The sampling is can be designed before the falling edge of the switching current I_P.

[0032] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.