Apparatus and method thereof for measuring output current from primary side of power converter

[0001] 1. Field of the Invention

[0002] The present invention relates to a power converter, and more specifically, to a monitoring and control method thereof.

[0003] 2. Description of the Related Art

[0004] Various power converters have been widely used to provide regulated voltage and current. For the sake of safety, an off-line power converter must provide galvanic isolation between its primary side and secondary side. In case that a control circuit is configured at the primary-side of the power converter, it would be difficult to measure an output current. Therefore it is desirable to provide an apparatus and method thereof for measuring the output current of the power converter at the primary side thereof. The measured output current thus can serve for further output current control and/or the power converter protection, etc.

[0005] In one aspect of the present invention, a method for measuring an output current from a primary side of a power converter is provided. The apparatus includes a peak detector to sample a converted voltage of a primary-side switching peak current, a zero-current detector for detecting a discharging time of a secondary-side switching current via an auxiliary winding of the transformer, an oscillator generating a switching signal for switching the power converter, and an integrator for generating an integrated signal by integrating the converted voltage of the primary-side switching peak current with the discharging time. In order to obtain an output current of the power converter, the integrated signal is proportional to the output current since a time constant of the integrator is correlated with the switching period of the switching signal.

[0006] In another aspect of the present invention, the method for measuring output current from the primary side of power converter is provided. The method includes sampling converted voltage of a primary-side switching peak current by a peak detector, detecting the discharging time of the secondary-side switching current via an auxiliary winding of the transformer by a zero-current detecting device, generating a switching signal for switching the power converter by an oscillating device, and generating an integrated signal by integrating the converted voltage of the primary side switching peak current with the discharging time.

[0007] It is to be understood that both the foregoing general descriptions and the following detailed descriptions are exemplary, and are intended to provide further explanation of the invention as claimed. Still further objects and advantages will become apparent from consideration of the ensuing description and drawings.

[0013] Referring to FIG. 1, a schematic circuit diagram of a power converter according to one embodiment of the present invention is illustrated. The power converter includes a transformer 10 having an auxiliary winding N_A, a primary winding N_P, and a secondary winding N_S. In order to regulate an output voltage V_O and/or an output current I_O of the power converter, a controller 70 generates a PWM control signal V_PWM to switch the transformer 10 by switching a transistor 20. Referring to FIG. 2, a schematic diagram of various signal waveforms of the power converter in FIG. 1 is illustrated. As the PWM control signal V_PWM raises to high, a primary-side switching current I_P is generated accordingly. The primary-side switching current I_P is given by,

[0014] $\begin{array}{cc}{I}_P=\frac{V_{\mathrm{IN}}}{L_P}\times T_{\mathrm{ON}}& \left(1\right)\end{array}$
where V_IN is an input voltage applied to the transformer 10, L_P is the inductance of the primary winding N_P of the transformer 10, and T_ON is an on-time interval of the PWM control signal V_PWM.

[0015] As the PWM control signal V_PWM drops to low, energy stored in the transformer 10 will be delivered to a secondary side of the transformer 10 and to an output of the power converter via a rectifier 40. A secondary-side switching current I_S can be expressed as:

[0016] $\begin{array}{cc}{I}_S=\frac{\left(V_O+V_F\right)}{L_S}\times T_{\mathrm{DS}}& \left(2\right)\end{array}$
where V_O is the output voltage of the power converter, V_F is the forward voltage drop across the rectifier 40, L_S is the inductance of the secondary winding N_S of the transformer 10, and T_DS is a discharging time of the secondary-side switching current Is.

[0017] In the mean time, a reflected voltage V_AUX is generated at the auxiliary winding N_A of the transformer 10. The reflected voltage V_AUX is given as:

[0018] $\begin{array}{cc}{V}_{\mathrm{AUX}}=\frac{T_{\mathrm{NA}}}{T_{\mathrm{NS}}}\times \left(V_O+V_F\right)& \left(3\right)\end{array}$
where T_NA and T_NS are respectively the winding turns of the auxiliary winding N_A and the secondary winding N_S.

[0019] The reflected voltage V_AUX will start to decrease as the secondary-side switching current I_S reduces to zero. This also indicates that energy of the transformer 10 is fully released at this moment. Therefore, as shown in FIG. 2, the discharging time T_DS in equation (2) can be measured from the falling edge of the PWM control signal V_PWM to the falling point of the reflected voltage V_AUX.

[0020] Referring to FIG. 1, the controller 70 has a supply terminal VCC, a voltage-detection terminal VDET, a ground terminal GND, a current-sense terminal VS, and an output terminal VPWM. The output terminal V_PWM outputs the PWM control signal V_PWM. The voltage-detection terminal VDET is connected to the auxiliary winding N_A via a resistor 50 for detecting the reflected voltage V_AUX. The reflected voltage V_AUX further charges a supply capacitor 65 via a rectifier 60 to power the controller 70. A current-sense resistor 30 is connected from a source of the transistor 20 to a ground reference level for converting the primary-side switching current I_P to be a converted voltage V_S.

[0021] Referring to FIG. 3, a schematic circuit diagram for measuring the output current I_O according to one embodiment of the present invention is illustrated. A peak detector 300 samples the converted voltage V_S of a primary-side switching peak current. A zero-current detector (ZCD) 100 detects the discharging time T_DS of the secondary-side switching current I_S via the auxiliary winding N_A of the transformer 10. An oscillator 200 generates a high-frequency signal to switch the power converter. A pulse signal PLS is generated from the oscillator 200 for synchronizing and generating the PWM control signal V_PWM. An integrator 500 is designed to generate an integrated signal V_X by integrating the converted voltage V_S of the primary-side switching peak current with the discharging time T_DS. A time constant of the integrator 500 is correlated with the switching period T of the switching frequency. The integrated signal V_X is therefore proportional to the output current I_O of the power converter. The primary-side switching peak current is a peak value of the primary-side switching current I_P. The primary-side switching current I_P and the secondary-side switching current I_S are respectively the switching current in the primary side and the secondary side of the transformer 10. According to the waveforms in FIG. 2, the output current I_O of the power converter is given as:

[0022] $\begin{array}{cc}{I}_O=I_S\times \frac{T_{\mathrm{DS}}}{2\times T}& \left(4\right)\end{array}$

[0023] The primary-side switching current I_P and the winding turns of the transformer 10 determines the secondary-side switching current I_S. The secondary-side switching current I_S can be given by,

[0024] $\begin{array}{cc}{I}_S=\frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\times I_P& \left(5\right)\end{array}$
where T_NP is the winding turns of the primary winding N_P of the transformer 10.

[0025] The primary-side switching current I_P is converted to the converted voltage V_S through the current-sense resistor 30. R_S is the resistance of the current-sense resistor 30. The peak detector 300 generates a peak voltage signal V_SP by sampling the converted voltage V_S. The integrated signal V_X can be expressed as:

[0026] $\begin{array}{cc}{V}_X=\frac{V_{\mathrm{SP}}\times T_{\mathrm{DS}}}{T_I}& \left(6\right)\end{array}$

[0027] It is noted that in equations (4)–(6) the integrated signal V_X can be rewritten as:

[0028] $\begin{array}{cc}{V}_X=\frac{2T}{T_I}\times \frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\times R_S\times I_O& \left(7\right)\end{array}$
where T_I is the time constant of the integrator 500.

[0029] It can be found that the integrated signal V_X is proportional to the output current I_O of the power converter as shown in equation (7).

[0030] Further referring to FIG. 3, the peak detector 300 includes a comparator 71 having a positive input connected to the current-sense terminal VS. The value of the converted voltage V_S is proportional to the value of the primary-side switching current I_P. A capacitor 91 is used for holding the peak value of the converted voltage V_S. The peak voltage signal V_SP is thus obtained across the capacitor 91. A negative input of the comparator 71 is connected to the capacitor 91. A constant current source 73 is applied to charge the capacitor 91. A switch 75 is connected between the constant current source 73 and the capacitor 91. The switch 75 is turned on/off by an output of the comparator 71. A transistor 84 is connected in parallel with the capacitor 91 to discharge the capacitor 91.

[0031] The integrator 500 includes a switch 76 used for periodically sampling the peak voltage signal V_SP from the capacitor 91 to a capacitor 92. An operational amplifier 72, a resistor 90 and a transistor 80 form a first V-to-I converter for generating a programmable current I₈₀ in response to a voltage across the capacitor 92. A positive input of the operational amplifier 72 is connected to the capacitor 92. A negative input of the operational amplifier 72 is connected to a resistor 90. A transistor 81 and a transistor 82 form a current mirror. The current mirror mirrors a programmable charge current I₈₂ from the programmable current I₈₀. A drain and a gate of the transistor 81 are connected to a drain of the transistor 80. A drain of the transistor 82 outputs the programmable charge current I₈₂. A switch 78 is connected between the drain of the transistor 82 and a capacitor 95. The switch 78 is only turned on during the period of the discharge-time T_DS. A transistor 85 is connected in parallel with the capacitor 95 to discharge the capacitor 95. A switch 79 is used to periodically sample a voltage across the capacitor 95 to an output capacitor 96. The integrated signal V_X is therefore obtained across the output capacitor 96. The resistor 90 and the capacitor 95 determine the time constant of the integrator 500.

[0032] Referring to FIG. 4, an oscillator 200 of the power converter according to one embodiment of the present invention is illustrated. An operational amplifier 201, a resistor 210 and a transistor 250 form a second V-to-I converter. The second V-to-I converter generates a reference current I₂₅₀ in response to a reference voltage V_REF. A plurality of transistors, such as 251, 252, 253, 254 and 255 form current mirrors for generating an oscillator charge current I₂₅₃ and an oscillator discharge current I₂₅₅ in response to the reference current I₂₅₀ A drain of the transistor 253 generates the oscillator charge current I_253. The oscillator discharge current I₂₅₅ flows via a drain of the transistor 253. A switch 230 is connected between the drain of the transistor 253 and a capacitor 215. A switch 231 is connected between the drain of the transistor 255 and the capacitor 215. A comparator 205 has a positive input connected to the capacitor 215. The comparator 205 outputs a pulse signal PLS. The pulse signal PLS determines the switching frequency and turns on/off the switch 76 and the switch 79 as shown in FIG. 3. A first terminal of a switch 232 is supplied with a high-threshold voltage V_H. A first terminal of a switch 233 is supplied with a low-threshold voltage V_L. A second terminal of the switch 232 and a second terminal of the switch 233 are both connected to a negative input of the comparator 205. An input of an inverter 260 is connected to an output of the comparator 205 for producing an inverse pulse signal /PLS. The pulse signal PLS turns on/off the switch 231 and the switch 233. The inverse pulse signal /PLS turns on/off the switch 230 and the switch 232. Inverters 261, 262, 263 and 264 are connected in series. An input of the inverter 261 is supplied with the pulse signal PLS. An AND gate 270 generates a clear signal CLR. A first input of the AND gate 270 is connected to an output of the inverter 264. A second input of the AND gate 270 is connected to an output of the inverter 261. The clear signal CLR turns on/off the transistor 84 and the transistor 85. The resistance R₂₁₀ of the resistor 210 and the capacitance C₂₁₅ of the capacitor 215 determine the switching period T of the switching frequency,

[0033] $\begin{array}{cc}T=\frac{C_{215}\times V_{\mathrm{OSC}}}{V_{\mathrm{REF}}/R_{210}}=R_{210}\times C_{215}\times \frac{V_{\mathrm{OSC}}}{V_{\mathrm{REF}}}& \left(8\right)\end{array}$
where V_OSC=V_H−V_L

[0034] Referring to FIG. 5, the zero-current detector 100 of the power converter according to one embodiment of the present invention is illustrated. A delay circuit of the zero-current detector 100 includes an inverter 150, a transistor 122, a constant current source 120, a capacitor 121 and an AND gate 155. An input of the delay circuit is supplied with the PWM control signal V_PWM. The delay circuit provides a propagation delay time for the falling edge of the PWM control signal V_PWM. The current of the constant current source 120 and the capacitance of the capacitor 121 determine the propagation delay time. An inverter 151, an inverter 152, a transistor 125, a constant current source 123, a capacitor 124 and an AND gate 156 form a one-shot signal generator for generating a voltage sample signal SMP. An input of the one-shot signal generator is connected to an output of the delay circuit, which is also an output of the AND gate 155. The current of the constant current source 123 and the capacitance of the capacitor 124 determine a pulse width of the voltage sample signal SMP.

[0035] An operational amplifier 101 is performed as a buffer amplifier. A negative input and an output of the operational amplifier 101 are connected together. A positive input of the operational amplifier 101 is an input of the buffer amplifier that is connected to the voltage-detection terminal VDET. The voltage-detection terminal VDET is connected to the auxiliary winding N_A of the transformer 10 via the resistor 50 for detecting the reflected voltage V_AUX. A switch 109 is connected between an output of the buffer amplifier and a capacitor 112. The voltage sample signal SMP turns on/off the switch 109. Therefore, the reflected voltage V_AUX is sampled as a voltage V_DET. The voltage V_DET will be held in the capacitor 112. A comparator 105 is used to detect the decrement of the reflected voltage V_AUX, in which a positive input of the comparator 105 is connected to the capacitor 112. A reference threshold voltage source 106 is coupled between a negative input of the comparator 105 and the output of the buffer amplifier to provide a threshold for detecting the decrement of the reflected voltage V_AUX. Therefore, the comparator 105 will output a logic-high signal once the decrement of the reflected voltage is beyond the voltage of the reference threshold voltage source 106. An input of an inverter 115 is supplied with the PWM control signal V_PWM. An input of an inverter 116 is supplied with the voltage sample signal SMP. An AND gate 119 has a first input connected to an output of the comparator 105. A SR flip-flop 117 and a SR flip-flop 118 have a rising-edge triggered set-input and a high-level reset-input respectively. The set-input of the SR flip-flop 118 is connected to an output of the inverter 116. The reset-input of the SR flip-flop 118 is supplied with the PWM control signal V_PWM. An output of the SR flip-flop 118 is connected to a second input of the AND gate 119. The SR flip-flop 117 is used for generating a discharge-time signal S_DS. The set-input of the SR flip-flop 117 is connected to an output of the inverter 115. The reset-input of the SR flip-flop 117 is connected to an output of the AND gate 119. The discharge-time signal S_DS turns on/off the switch 78, in which the pulse width of the discharge-time signal S_DS is correlated to the discharge-time T_DS of the secondary-side switching current I_S.

[0036] According to the above descriptions of the embodiment of the present invention referred to FIG. 3˜5, the integrated signal V_X is correlated to the secondary-side switching current I_S and the output current I_O of the power converter. Thus, the equation (7) can be rewritten as:

[0037] $\begin{array}{cc}{V}_X=m\times \frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\times R_S\times I_O& \left(9\right)\end{array}$
where m is a constant which can be determined by:

[0038] $\begin{array}{cc}m=\frac{2\times R_{210}\times C_{215}}{R_{90}\times C_{95}}\times \frac{V_{\mathrm{OSC}}}{V_{\mathrm{REF}}}& \left(10\right)\end{array}$

[0039] The resistance R₉₀ of the resistor 90 in FIG. 3 is correlated to the resistance R₂₁₀ of the resistor 210 in FIG. 4. The capacitance C₉₅ of the capacitor 95 in FIG. 3 is correlated to the capacitance C₂₁₅ of the capacitor 215 in FIG. 4. Therefore, the integrated signal V_X is proportional to the output current I_O of the power converter.

[0040] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.