Switching control circuit for primary-side controlled power converters

[0001] 1. Field of the Invention

[0002] The present invention relates to a control circuit for a power converter, and more specifically, to a switching control circuit for switching mode power converters.

[0003] 2. Description of Related Art

[0004] Various power converters have been widely used to provide regulated voltage and current. For the sake of safety, an off-line power converter must provide galvanic isolation between its primary side and secondary side. When a control circuit is equipped at the primary side of a power converter, an optical-coupler and a secondary-side regulator are needed to regulate the output voltage and output current. The object of the present invention is to provide a switching control circuit for controlling the output voltage and the output current of a power converter at the primary side without the optical-coupler and secondary-side regulator. Furthermore, frequency hopping is developed for spreading the switching frequency of the switching signal and reducing the EMI (electric and magnetic interference). Therefore, the size and the cost of the power converter can be effectively reduced.

[0005] A switching control circuit for a primary-side-controlled power converter comprises a switching device to switch a transformer. A switching signal drives the switching device for regulating an output voltage and a maximum output current of the power converter. A controller is coupled to the transformer and a current-sense device to generate a voltage-feedback signal and a current-feedback signal by sampling a voltage signal and a discharge time of the transformer during the off-time of the switching signal, and measuring a current signal of the transformer during the on-time of the switching signal. The switching signal is generated in response to the voltage-feedback signal and the current-feedback signal.

[0006] The controller further comprises a voltage-waveform detector for multi-sampling the voltage signal and producing the voltage-feedback signal and a discharge-time signal. The voltage-waveform detector is connected to an auxiliary winding of a transformer through a resistor of a voltage divider. The discharge-time signal represents the discharge time of the transformer and stands for the discharge time of a secondary-side switching current. A current-waveform detector generates a current-waveform signal by measuring the current signal. An oscillator generates an oscillation signal for determining a switching frequency of the switching signal. An integrator is used for generating the current-feedback signal by integrating the current-waveform signal with the discharge time. A first operational amplifier and a first reference voltage develop a voltage-loop error amplifier to amplify the voltage-feedback signal and provide a loop gain for output voltage control. A second operational amplifier and a second reference voltage form a current-loop error amplifier to amplify the current-feedback signal and provide a loop gain for output current control. A PWM circuit associates with a first comparator and a second comparator to control the pulse width of the switching signal in response to the output of the voltage-loop error amplifier and the output of the current-loop error amplifier. A programmable current source is connected to the input of the voltage-waveform detector for temperature compensation. The programmable current source produces a programmable current in response to the temperature of the controller, which compensates the temperature deviation of the power converter.

[0007] A pattern generator generates a digital pattern code. A first programmable capacitor is coupled to the oscillator and the pattern generator for modulating the switching frequency in response to the digital pattern code. The spectrum of the switching frequency is extended, thus the EMI of the power converter is reduced. A second programmable capacitor is coupled to the integrator and the pattern generator for correlating a time constant of the integrator with the switching frequency. The current-feedback signal is therefore proportional to the output current of the power converter. The capacitance of the first programmable capacitor and the second programmable capacitor are controlled by the digital pattern code.

[0008] It is to be understood that both the foregoing general descriptions and the following detailed descriptions are exemplary, and are intended to provide further explanation of the invention as claimed. Still further objects and advantages will become apparent from a consideration of the ensuing description and drawings.

[0021] FIG. 1 shows a power converter. The power converter includes a transformer 10 having an auxiliary winding N_A, a primary winding N_P, and a secondary winding N_S. The primary winding N_P is supplied with an input voltage V_IN of the power converter. In order to regulate an output voltage V_O and an output current I_O of the power converter, a controller 70 generates a switching signal V_PWM, which controls a switching device, such as a transistor 20, to switch the transformer 10. A current-sense resistor 30 serves as a current-sense device.

[0022] FIG. 2 shows various signal waveforms of the power converter in FIG. 1. As the switching signal V_PWM becomes logic-high, a primary-side switching current I_P will be generated accordingly. A peak value I_P1 of a primary-side switching current I_P can be given by,

[0023] $\begin{array}{cc}{I}_{\mathrm{P1}}=\frac{V_{\mathrm{IN}}}{L_P}\times T_{\mathrm{ON}}& \left(1\right)\end{array}$

[0024] where L_P is the inductance of the primary winding N_P of the transformer 10; T_ON is an on-period of the switching signal V_PWM.

[0025] Once the switching signal V_PWM becomes logic-low, the energy stored in the transformer 10 will be delivered to the secondary side of the transformer 10 and to an output of the power converter via a rectifier 40. Therefore, a secondary-side switching current I_S is generated accordingly. A peak value I_S1 of a secondary-side switching current I_S can be expressed by,

[0026] $\begin{array}{cc}{I}_{\mathrm{S1}}=\frac{\left(V_O+V_F\right)}{L_S}\times T_{\mathrm{DS}}& \left(2\right)\end{array}$

[0027] where V_O is the output voltage of the power converter; V_F is a forward voltage drop of the rectifier 40; L_S is the inductance of the secondary winding N_S of the transformer 10; T_DS is a discharge time of the secondary-side switching current Is.

[0028] Meanwhile, a voltage signal V_AUX is generated at the auxiliary winding N_A of the transformer 10. A voltage level V_AUX1 of the voltage signal V_AUX is shown as,

[0029] $\begin{array}{cc}{V}_{\mathrm{AUX1}}=\frac{T_{\mathrm{NA}}}{T_{\mathrm{NS}}}\times \left(V_O+V_F\right)& \left(3\right)\end{array}$

[0030] where T_NA and T_NS are respectively the winding turns of the auxiliary winding N_A and the secondary winding N_S of the transformer 10.

[0031] The voltage signal V_AUX starts to decrease as the secondary-side switching current I_S drops to zero. This also indicates that the energy of the transformer 10 is fully released at this moment. Therefore, as shown in FIG. 2, the discharge time T_DS in equation (2) can be measured from a falling edge of the switching signal V_PWM to a point that the voltage signal V_AUX starts to fall. The secondary-side switching current I_S is determined by the primary-side switching current I_P and the winding turns of the transformer 10. The secondary-side switching current I_S can be expressed by,

[0032] $\begin{array}{cc}{I}_S=\frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\times I_P& \left(4\right)\end{array}$

[0033] where T_NP is the winding turns of the primary winding N_P of the transformer 10.

[0034] The controller 70 comprises a supply terminal VCC and a ground terminal GND for receiving power. A resistor 50 and a resistor 51 are connected in series to form a voltage divider, which is connected between the auxiliary winding N_A of the transformer 10 and a ground reference level. A detection terminal DET of the controller 70 is connected to a joint of the resistor 50 and the resistor 51. A voltage V_DET generated at the detection terminal DET can be given by,

[0035] $\begin{array}{cc}{V}_{\mathrm{DET}}=\frac{R_{51}}{R_{50}+R_{51}}\times V_{\mathrm{AUX}}& \left(5\right)\end{array}$

[0036] where R₅₀ and R₅₁ are respectively the resistance of resistors 50 and 51.

[0037] The voltage signal V_AUX further charges a capacitor 65 via a rectifier 60 for powering the controller 70. The current-sense resistor 30 is connected from a source of the transistor 20 to the ground reference level for converting the primary-side switching current I_P to a current signal V_CS. A sense terminal CS of the controller 70 is connected to the current-sense resistor 30 for detecting the current signal V_CS.

[0038] An output terminal OUT of the controller 70 generates the switching signal V_PWM to switch the transformer 10. A compensation network is connected to a voltage-compensation terminal COMV of the controller 70 for voltage-loop frequency compensation. The compensation network can be a capacitor connected to the ground reference level, such as a capacitor 31. Another compensation network is connected to a current-compensation terminal COMI of the controller 70 for current-loop frequency compensation. The compensation network can also be a capacitor connected to the ground reference level, such as a capacitor 32.

[0039] FIG. 3 shows an embodiment of the controller 70. A voltage-waveform detector 100 produces a voltage-feedback signal V_V and a discharge-time signal S_DS by multi-sampling the voltage V_DET. The discharge-time signal S_DS represents the discharge time T_DS of the secondary-side switching current I_S. A current-waveform detector 300 generates a current-waveform signal V_W by measuring the current signal V_CS. An oscillator 200 generates an oscillation signal PLS for determining a switching frequency of the switching signal V_PWM. An integrator 400 produces a current-feedback signal V_I by integrating the current-waveform signal V_W with the discharge time T_DS. An operational amplifier 71 and a reference voltage V_REF1 develop a voltage-loop error amplifier for amplifying the voltage-feedback signal V_V and providing a loop gain for output voltage control. An operational amplifier 72 and a reference voltage V_REF2 develop a current-loop error amplifier for amplifying the current-feedback signal V_I and providing a loop gain for output current control.

[0040] A switching circuit 500 associates with comparators 73 and 75 to control the pulse width of the switching signal V_PWM in response to the outputs of the voltage-loop error amplifier and the current-loop error amplifier. Both operational amplifiers 71 and 72 have trans-conductance output. An output of the operational amplifier 71 is connected to the voltage-compensation terminal COMV and a positive input of the comparator 73. An output of the operational amplifier 72 is connected to the current-compensation terminal COMI and a positive input of the comparator 75. A negative input of the comparator 73 is connected to an output of an adder 600. A negative input of the comparator 75 is supplied with a ramp signal RMP that is produced from the oscillator 200.

[0041] The adder 600 generates a slope signal V_SLP by adding the current signal V_CS with the ramp signal RMP, which forms a slope compensation for the voltage-loop. A positive input of a comparator 74 is supplied with a reference voltage V_REF3. A negative input of the comparator 74 is connected to the sense terminal CS for achieving a cycle-by-cycle current limit. Three inputs of a NAND gate 79 are respectively connected to the outputs of comparators 73, 74 and 75. An output of the NAND gate 79 generates a reset signal RST. The reset signal is applied to the PWM circuit 500 for controlling the duty cycle of the switching signal V_PWM.

[0042] A current control loop is formed from the detection of the primary-side switching current I_P to the pulse width modulation of the switching signal V_PWM for controlling the magnitude of the primary-side switching current I_P in response to the reference voltage V_REF1. The secondary-side switching current I_Sis a ratio of the primary-side switching current I_P as shown in equation (4). According to the signal waveforms in FIG. 2, the output current I_O of the power converter is the average of the secondary-side switching current I_S. It can be expressed by,

[0043] $\begin{array}{cc}{I}_O=I_S\times \frac{T_{\mathrm{DS}}}{2T}& \left(6\right)\end{array}$

[0044] Therefore, the output current I_O of the power converter is regulated.

[0045] The current-waveform detector 300 detects the current signal V_CS and generates the current-waveform signal V_W. The integrator 400 further produces the current-feedback signal V_I by integrating the current-waveform signal V_W with the discharge time T_DS. The current-feedback signal V₁ is thus designed as,

[0046] $\begin{array}{cc}{V}_1=\frac{V_W}{2}\times \frac{T_{\mathrm{DS}}}{T_1}& \left(7\right)\end{array}$
where the current-waveform signal V_W is expressed as,

[0047] $\begin{array}{cc}{V}_W=\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\times R_S\times I_S& \left(8\right)\end{array}$
where T_I is a time constant of the integrator 400.

[0048] It can be seen from equations (6)-(8), the current-feedback signal V_I can be rewritten as,

[0049] $\begin{array}{cc}{V}_1=\frac{T}{T_1}\times \frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\times R_S\times I_O& \left(9\right)\end{array}$

[0050] It can be found that the current-feedback signal V_I is proportional to the output current I_O of the power converter. The current-feedback signal V_I is increased as the output current I_O increases. A maximum value of the current-feedback signal V_I is limited to the value of the reference voltage V_REF2 through the regulation of the current control loop. Under feedback control of the current control loop, a maximum output current I_O(max) is given by,

[0051] $\begin{array}{cc}{I}_{O\left(\max \right)}=\frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\times \frac{G_A\times G_{\mathrm{SW}}\times V_{\mathrm{REF2}}}{1+\left(G_A\times G_{\mathrm{SW}}\times \frac{R_S}{K}\right)}& \left(10\right)\end{array}$

[0052] where K is a constant equal to T_I/T; G_A is the gain of the current-loop error amplifier; G_SW is the gain of the switching circuit.

[0053] As the loop gain of the current control loop is high (G_A×G_SW>>1), the maximum output current I_O(max) could be briefly defined as,

[0054] $\begin{array}{cc}{I}_{O\left(\max \right)}=K\times \frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\times \frac{V_{\mathrm{REF}}}{R_S}& \left(11\right)\end{array}$

[0055] The maximum output current I_O(max) of the power converter is thus regulated as a constant current in response to the reference voltage V_REF2.

[0056] Besides, a voltage control loop is developed from the voltage signal V_AUX sampling to the pulse width modulation of the switching signal V_PWM, which controls the magnitude of the voltage signal V_AUX in response to the reference voltage V_REF1. The voltage signal V_AUX is a ratio of the output voltage V_O as shown in equation (3). The voltage signal V_AUX is further attenuated to the voltage V_DET as shown in equation (5). The voltage-waveform detector 100 generates the voltage-feedback signal V_V through multi-sampling the voltage V_DET. The value of the voltage-feedback signal V_V is controlled in response to the value of the reference voltage V_REF1 through the regulation of the voltage control loop. The voltage-loop error amplifier and the switching circuit provide the loop gain for the voltage control loop. Therefore the output voltage V_O can be briefly defined as,

[0057] $\begin{array}{cc}{V}_O=\left(\frac{R_{50}+R_{51}}{R_{50}}\times \frac{T_{\mathrm{NS}}}{T_{\mathrm{NA}}}\times V_{\mathrm{REF1}}\right)-V_F& \left(12\right)\end{array}$

[0058] The voltage signal V_AUX is multi-sampled by the voltage-waveform detector 100. The voltage is sampled and measured instantly before the secondary-side switching current I_S drops to zero. Therefore the variation of the secondary-side switching current I_S does not affect the value of the forward voltage drop V_F of the rectifier 40. However, the voltage drop V_F of the rectifier 40 varies when temperature changes. A programmable current source 80 is connected to an input of the voltage-waveform detector 100 for temperature compensation. The programmable current source 80 produces a programmable current I_T in response to the temperature of the controller 70. The programmable current I_T associates with the resistors 50, 51 to generate a voltage V_T to compensate the temperature variation of the forward voltage drop V_F of the rectifier 40.

[0059] $\begin{array}{cc}{V}_T=I_T\times \frac{R_{50}\times R_{51}}{R_{50}+R_{51}}& \left(13\right)\end{array}$

[0060] Referring to equations (12) and (13), we can find the ratio of resistors R₅₀ and R₅₁ determines the output voltage V_O. The resistance of resistors R₅₀ and R₅₁ determine the temperature coefficient for compensating the voltage drop V_F of the rectifier 40. Based on the programmable current source 80, the equation (12) can be rewritten as,

[0061] $\begin{array}{cc}{V}_O=\left(\frac{R_{50}+R_{51}}{R_{50}}\times \frac{T_{\mathrm{NS}}}{T_{\mathrm{NA}}}\times V_{\mathrm{REF1}}\right)-V_F+V_T& \left(14\right)\end{array}$

[0062] Furthermore, in order to produce frequency hopping for reducing the EMI of the power converter, a pattern generator 900 generates a digital pattern code P_N. . . P₁. A first programmable capacitor 910 is coupled to the oscillator 200 and the pattern generator 900 for modulating the switching frequency of the switching signal V_PWM in response to the digital pattern code P_N. . . . P₁. A second programmable capacitor 930 is coupled to the integrator 400 and the pattern generator 900 for correlating the time constant T₁ of the integrator 400 with the switching frequency. The capacitance of the first programmable capacitor 910 and the second programmable capacitor 930 are controlled by the digital pattern code P_N. . . P₁.

[0063] FIG. 10 shows an embodiment of the pattern generator 900 according to the present invention. A clock generator 951 generates a clock signal CK. A plurality of registers 971, 972 . . . 975 and a XOR gate 952 develop a linear shift register for generating a linear code in response to the clock signal CK. The inputs of the XOR gate 952 determine the polynomials of the linear shift register and decide the output of the linear shift register. The digital pattern code P_N. . . P₁ can be obtained from the part of the linear code to optimize the application.

[0064] FIG. 4 shows an embodiment of the voltage-waveform detector 100 according to the present invention. A sample-pulse generator 190 produces a sample-pulse signal for multi-sampling operation. A threshold voltage 156 adds to the voltage signal V_AUX to produce a level-shift signal. A first signal generator includes a D flip-flop 171, two AND gates 165, 166 for producing a first sample signal V_SP1 and a second sample signal V_SP2. A second signal generator comprises a D flip-flop 170, a NAND gate 163, an AND gate 164 and a comparator 155 for producing the discharge-time signal S_DS. A time-delay circuit includes an inverter 162, a current source 180, a transistor 181 and a capacitor 182 for generating a delay time T_d as the switching signal V_PWM is disabled. An input of an inverter 161 is supplied with the switching signal V_PWM. An output of the inverter 161 is connected to an input of the inverter 162, a first input of the AND gate 164 and a clock-input of the D flip-flop 170. An output of the inverter 162 turns on/off the transistor 181. The capacitor 182 is connected in parallel with the transistor 181. The current source 180 is applied to charge the capacitor 182. Therefore the current of the current source 180 and the capacitance of the capacitor 182 decide the delay time T_d of the time-delay circuit. The capacitor 182 is the output of the time-delay circuit. A D-input of the D flip-flop 170 is pulled high by a supply voltage V_CC. An output of the D flip-flop 170 is connected to a second input of the AND gate 164. The AND gate 164 outputs the discharge-time signal S_DS. The discharge-time signal S_DS is thus enabled as the switching signal V_PWM is disabled. The output of the NAND gate 163 is connected to a reset-input of the D flip-flop 170. The inputs of the NAND gate 163 are connected to the output of the time-delay circuit and an output of the comparator 155. A negative input of the comparator 155 is supplied with the level-shift signal. A positive input of the comparator 155 is supplied with the voltage-feedback signal V_V. Therefore, after the delay time T_d, the discharge-time signal S_DS can be disable once the level-shift signal is lower than the voltage-feedback signal V_V. Besides, the discharge-time signal S_DS can also be disabled as long as the switching signal V_PWM is enabled.

[0065] The sample-pulse signal is supplied to a clock-input of the D flip-flop 171 and third inputs of AND gates 165 and 166. A D-input and an inverse output of the D flip-flop 171 are connected together to form a divided-by-two counter. An output and the inverse output of the D flip-flop 171 are respectively connected to second inputs of AND gates 165 and 166. First inputs of AND gates 165 and 166 are both supplied with the discharge-time signal S_DS. Fourth inputs of AND gates 165 and 166 are connected to the output of the time-delay circuit. Therefore the first sample signal V_SP1 and the second sample signal V_SP2 are generated in response to the sample-pulse signal. Besides, the first sample signal V_SP1 and the second sample signal V_SP2 are alternately produced during an enabled period of the discharge-time signal S_DS. However, the delay time T_d is inserted at the beginning of the discharge-time signal S_DS to inhibit the first sample signal V_SP1 and the second sample signal V_SP2. The first sample signal V_SP1 and the second sample signal V_SP2 are thus disabled during the period of the delay time T_d.

[0066] The first sample signal V_SP1 and the second sample signal S_SP2 are used for alternately sampling the voltage signal V_AUX via the detection terminal DET and the divider. The first sample signal V_SP1 and the second sample signal V_SP2 control a switch 121 and a switch 122 for obtaining a first hold voltage and a second hold voltage across a capacitor 110 and a capacitor 111 respectively. A switch 123 is connected in parallel with the capacitor 110 to discharge the capacitor 110. A switch 124 is connected in parallel with the capacitor 111 to discharge the capacitor 111. A buffer amplifier includes operational amplifiers 150 and 151, diodes 130,131, a current source 135 for generating a hold voltage. The positive inputs of operational amplifiers 150 and 151 are connected to the capacitor 110 and capacitor 111 respectively. The negative inputs of the operational amplifiers 150 and 151 are connected to an output of the buffer amplifier. The diode 130 is connected from an output of the operational amplifier 150 to the output of the buffer amplifier. The diode 131 is connected from an output of the operational amplifier 151 to the output of the buffer amplifier. The hold voltage is thus obtained from the higher voltage of the first hold voltage and the second hold voltage. The current source 135 is used for the termination. A switch 125 periodically conducts the hold voltage to a capacitor 115 for producing the voltage-feedback signal V_V. The switch 125 is turned on/off by the oscillation signal PLS. The first sample signal V_SP1 and the second sample signal V_SP2 start to produce the first hold voltage and the second hold voltage after the delay time T_d, which eliminates the spike interference of the voltage signal V_AUX. The spike of the voltage signal V_AUX would be generated when the switching signal V_PWM is disabled and the transistor 20 is turned off.

[0067] The voltage signal V_AUX starts to decrease as the secondary-side switching current I_S drops to zero, which is detected by the comparator 155 to disable the discharge-time signal S_DS. The pulse width of the discharge-time signal S_DS is therefore correlated to the discharge time T_DS of the secondary-side switching current I_S Meanwhile the first sample signal V_SP1 and the second sample signal V_SP2 are disabled, and the multi-sampling operation is stopped as the discharge-time signal S_DS is disabled. At the moment, the hold voltage generated at the output of the buffer amplifier represents an end voltage. The end voltage is thus correlated to the voltage signal V_AUX that is sampled just before the secondary-side switching current I_S dropping to zero. The hold voltage is obtained from the higher voltage of the first hold voltage and the second hold voltage, which will ignore the voltage that is sampled when the voltage signal V_AUX starts to decrease.

[0068] FIG. 5 shows an embodiment of the oscillator 200 according to the present invention. An operational amplifier 201, a resistor 210 and a transistor 250 form a first V-to-I converter. The first V-to-I converter generates a reference current I₂₅₀ in response to a reference voltage V_REF. A plurality of transistors, such as 251, 252, 253, 254, 255 form current mirrors for generating an oscillator charge current I₂₅₃ and an oscillator discharge current I₂₅₅ in response to the reference current I₂₅₀. A drain of the transistor 253 generates the oscillator charge current I₂₅₃. A drain of the transistor 255 generates the oscillator discharge current I₂₅₅. A switch 230 is connected between the drain of the transistor 253 and a capacitor 215. A switch 231 is connected between the drain of the transistor 255 and the capacitor 215. The ramp signal RMP is obtained across the capacitor 215. A comparator 205 has a positive input connected to the capacitor 215. The comparator 205 outputs the oscillation signal PLS. The oscillation signal PLS determines the switching frequency. A first terminal of a switch 232 is supplied with a high threshold voltage V_H. A first terminal of a switch 233 is supplied with a low threshold voltage V_L. A second terminal of the switch 232 and a second terminal of the switch 233 are both connected to a negative input of the comparator 205. An input of an inverter 260 is connected to an output of the comparator 205 for producing an inverse oscillation signal/PLS. The oscillation signal PLS turns on/off the switch 231 and the switch 233. The inverse oscillation signal/PLS turns on/off the switch 230 and the switch 232. The first programmable capacitor 910 in FIG. 3 is connected in parallel with the capacitor 215 for modulating the switching frequency in response to the digital pattern code P_N. . . P₁. The resistance R₂₁₀ of the resistor 210, the capacitance C₂₁₅ of the capacitor 215 and the capacitance C₉₁₀ of the first programmable capacitor 910 determine the switching period T of the switching frequency. The switching period T is given by,

[0069] $\begin{array}{cc}T=\frac{\left(C_{215}+\mathrm{C910}\right)\times V_{\mathrm{OSC}}}{V_{\mathrm{REF}}/R_{210}}=R_{210}\times \left(C_{215}+\mathrm{C910}\right)\times \frac{V_{\mathrm{OSC}}}{V_{\mathrm{REF}}}& \left(15\right)\end{array}$
where V_OSC=V_H−V_L.

[0070] The capacitance C₉₁₀ of the first programmable capacitor 910 varies in response to the variation of the digital pattern code P_N. . . P₁.

[0071] FIG. 6 shows an embodiment of the current-waveform detector 300 according to the present invention. A peak detector includes a comparator 310, a current source 320, switches 330, 340, and a capacitor 361. The peak value of the current signal V_CS is sampled for generating a peak-current signal. A positive input of the comparator 310 is supplied with the current signal V_CS. A negative input of the comparator 310 is connected to the capacitor 361. The switch 330 is connected between the current source 320 and the capacitor 361. The output of the comparator 310 turns on/off the switch 330. The switch 340 is connected in parallel with the capacitor 361 for discharging the capacitor 361. A switch 350 periodically conducts the peak-current signal to a capacitor 362 for producing the current-waveform signal V_W. The switch 350 is turned on/off by the oscillation signal PLS.

[0072] FIG. 7 shows an embodiment of the integrator 400 according to the present invention. A second V-to-I converter comprises an operational amplifier 410, a resistor 450 and transistors 420, 421, and 422. A positive input of the operational amplifier 410 is supplied with the current-waveform signal V_W. A negative input of the operational amplifier 410 is connected to the resistor 450. An output of the operational amplifier 410 drives a gate of the transistor 420. A source of the transistor 420 is coupled to the resistor 450. The second V-to-I converter generates a current I₄₂₀ via a drain of the transistor 420 in response to the current-waveform signal V_W. Transistors 421 and 422 form a current mirror having a 2:1 ratio. The current mirror is driven by the current I₄₂₀ to produce a programmable charge current I_PRG via a drain of the transistor 422. The programmable charge current I_PRG can be expressed by,

[0073] $\begin{array}{cc}{I}_{\mathrm{PRG}}=\frac{1}{R_{450}}\times \frac{V_W}{2}& \left(16\right)\end{array}$
where R₄₅₀ is the resistance of the resistor 450.

[0074] A capacitor 471 is used to produce an integrated signal. A switch 460 is connected between the drain of the transistor 422 and the capacitor 471. The switch 460 is turned on/off by the discharge-time signal S_DS. A switch 462 is connected in parallel with the capacitor 471 for discharging the capacitor 471. The second programmable capacitor 930 in FIG. 3 is connected in parallel with the capacitor 471 at a C_X terminal of the integrator 400 for correlating the time constant T_I of the integrator 400 with the switching frequency. The capacitance C₉₃₀ of the second programmable capacitor 930 varies in response to the variation of the digital pattern code P_N. . . P₁. A switch 461 periodically conducts the integrated signal to a capacitor 472 for producing the current-feedback signal V_I. The switch 461 is turned on/off by the oscillation signal PLS. The current-feedback signal V_I is therefore obtained across the capacitor 472.

[0075] $\begin{array}{cc}{V}_1=\frac{1}{R_{450}\times \left(C_{471}+C_{930}\right)}\times \frac{V_W}{2}\times T_{\mathrm{DS}}& \left(17\right)\end{array}$

[0076] According to equations (4)-(7), the current-feedback signal V_I is correlated to the secondary-side switching current I_S and the output current I_O of the power converter. Thus, equation (9) can be rewritten as,

[0077] $\begin{array}{cc}{V}_1=m\times \frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\times R_S\times I_O& \left(18\right)\end{array}$
where m is a constant which is determined by,

[0078] $\begin{array}{cc}m=\frac{R_{210}\times \left(C_{215}+C_{910}\right)}{R_{450}\times \left(C_{471}+C_{930}\right)}\times \frac{V_{\mathrm{OSC}}}{V_{\mathrm{REF}}}& \left(19\right)\end{array}$

[0079] The resistance R₄₅₀ of the resistor 450 is correlated to the resistance R₂₁₀ of the resistor 210. The capacitance C₄₇₁ of the capacitor 471 and the capacitance C₉₃₀ of the capacitor 930 are correlated to the capacitance C₂₁₅ of the capacitor 215 and the capacitance C₉₁₀ of the capacitor 910. Therefore, the current-feedback signal V_I is proportional to the output current I_O of the power converter.

[0080] FIG. 8 shows a schematic diagram of the PWM circuit 500 according to the present invention. The PWM circuit 500 includes a NAND gate 511, a D flip-flop 515, an AND gate 519, a blanking circuit 520 and inverters 512 and 518. A D-input of the D flip-flop 515 is pulled high by the supply voltage V_CC. The oscillation signal PLS drives an input of the inverter 512. An output of the inverter 512 is connected to a clock-input of the D flip-flop 515 for enabling the switching signal V_PWM. An output of the D flip-flop 515 is connected to a first input of the AND gate 519. A second input of the AND gate 519 is coupled to the output of the inverter 512. The AND gate 519 outputs the switching signal V_PWM. A reset-input of the D flip-flop 515 is driven by an output of the NAND gate 511. A first input of the NAND gate 511 is supplied with the reset signal RST for cycle-by-cycle disabling the switching signal V_PWM. The second input of the NAND gate 511 is connected to an output of the blanking circuit 520 for ensuring a minimum on-time of the switching signal V_PWM once the switching signal V_PWM is enabled. The minimum on-time of the switching signal V_PWM will secure a minimum value of the discharge time T_DS, which will ensure a proper multi-sampling operation for sampling voltage signal V_AUX in the voltage-waveform detector 100. The discharge time T_DS is related to the on-period of the switching signal V_PWM. Referring to equations (1), (2), (4) and the secondary inductance L_S, which is given by equation (20), the discharge time T_DS can be expressed as equation (21),

[0081] $\begin{array}{cc}{L}_S={\left(\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\right)}^2\times L_P& \left(20\right)\\ T_{\mathrm{DS}}=\left(\frac{V_{\mathrm{IN}}}{V_O+V_F}\right)\times \frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\times T_{\mathrm{ON}}& \left(21\right)\end{array}$
where T_ON is the on-time of the switching signal V_PWM.

[0082] An input of the blanking circuit 520 is supplied with the switching signal V_PWM. When the switching signal V_PWM is enabled, the blanking circuit 520 will generate a blanking signal V_BLK to inhibit the reset of the D flip-flop 515. The blanking circuit 520 comprises a NAND gate 523, a current source 525, a capacitor 527, a transistor 526 and inverters 521 and 522. The switching signal V_PWM is supplied to an input of the inverter 521 and a first input of the NAND gate 523. The current source 525 is applied to charge the capacitor 527. The capacitor 527 is connected between a drain and a source of the transistor 526. An output of the inverter 521 turns on/off the transistor 526. An input of the inverter 522 is coupled to the capacitor 527. An output of the inverter 522 is connected to a second input of the NAND gate 523. An output of the NAND gate 523 generates the blanking signal V_BLK. The current of the current source 525 and the capacitance of the capacitor 527 determine the pulse width of the blanking signal V_BLK. The input of an inverter 518 is connected to the output of the NAND gate 523. An output of the inverter 518 generates a clear signal CLR to turn on/off switches 123, 124, 340 and 462.

[0083] FIG. 9 shows a schematic diagram of the adder 600 according to the present invention. An operational amplifier 610, transistors 620, 621, 622 and a resistor 650 develop a third V-to-I converter for generating a current I₆₂₂ in response to the ramp signal RMP. A positive input of an operational amplifier 611 is supplied with the current signal V_CS. A negative input and an output of the operational amplifier 611 are connected together to build the operational amplifier 611 as a buffer. A drain of the transistor 622 is connected to the output of the operational amplifier 611 via a resistor 651. The slope signal V_SLP is generated at the drain of the transistor 622. The slope signal V_SLP is therefore correlated to the ramp signal RMP and the current signal V_CS.

[0084] FIG. 11 shows an embodiment of a programmable capacitor, such as the first programmable capacitor 910 and the second programmable capacitor 930. The programmable capacitor comprises switching-capacitor sets connected to each other in parallel. The switching-capacitor sets are respectively formed by capacitors C₁, C₂, . . . , C_N and switches S₁,S₂, . . . S_N. The switch S₁ and the capacitor C₁ are connected in series. The switch S₂ and the capacitor C₂ are connected in series. The switch S_N and the resistor C_N are connected in series. The digital pattern code P_N. . . P₁ controls switches S₁, S₂, . . . S_N. Therefore, the capacitance of the programmable capacitor can be changed.

[0085] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.