US 9,935,190 B2Grant
Forming enhancement mode III-nitride devices
Issue Date:2018-04-03
•12 Claims
•22 Drawing Sheets
Abstract
A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.
Metadata
Assignee
- Transphorm Inc.
Inventors
- Mo Wu
- Rakesh K. Lal
- Ilan Ben-Yaacov
- Umesh Mishra
- Carl Joseph Neufeld
Application Information
Application Number:US 15/065,597
Filing Date:2016-03-09
Priority Date:2014-07-21
Art Unit:2828
Classifications
IPC:
H01L29/00H01L29/778H01L29/66H01L29/20H01L21/28H01L29/205H01L29/51H01L21/306H01L21/308H01L21/311H01L29/423H01L29/10H01L21/02
Field of Search:
H01L 21/28264H01L 21/30621H01L 21/3081H01L 21/31144H01L 29/7787H01L 29/2003H01L 29/205H01L 29/4236H01L 29/517H01L 29/518H01L 29/66462H01L 29/7783H01L 29/7786
Patent Drawings (22 sheets)
Description
Cross-Reference to Related Applications
[0001] This is a divisional of U.S. application Ser. No. 14/542,937, filed on Nov. 17, 2014, which claims priority to U.S. Provisional Application No. 62/027,126, filed on Jul. 21, 2014. The disclosures of the prior applications are considered part of and are incorporated by reference in the disclosure of this application.
Statement Regarding Federally Sponsored Research or Development
[0002] This invention was made with Government support awarded by ARPA-E [Award #DE-AR0000212]. The Government has certain tights in this invention, including the right to revoke or modify the license to manufacture if the recipient is unable to expeditiously realize practical applications.
Technical Field
[0003] This specification relates to semiconductor electronic devices, specifically III-Nitride (III-N) semiconductor devices.
Background
[0004] Most power semiconductor devices, e.g., high-voltage P-I-N diodes, and power transistors, e.g., power metal-oxide-semiconductor field-effect transistors (MOSFETs) and Insulated Gate Bipolar Transistors (IGBTs), have been typically fabricated with silicon (Si) semiconductor materials. Silicon carbide (SiC) power devices have also been used. III-N devices are attractive semiconductor devices to carry large currents and support high voltages, and provide very low on resistance, high voltage operation, and fast switching times.
[0005] Some III-N devices, e.g., high electron mobility transistors (HEMTs) and bidirectional switches (also known as four quadrant switches or FQSs), may be depletion-mode (or D-mode) or normally-on devices, e.g., devices with a negative threshold voltage. That is, the devices are in the ON state unless a sufficiently negative voltage is applied to the gate electrode relative to the source or power electrode. In many applications, in particular in power switching circuits, it is desirable to utilize enhancement-mode (or E-mode) devices, e.g., devices with a positive threshold voltage, as this can simplify the form of the signals applied by a gate-drive circuit to the device and can prevent accidental turn on of the device in case of device or circuit failure. Reliable fabrication and manufacturing of high-voltage III-N E-mode devices has proven to be very difficult. In some cases, a high-voltage III-N D-mode device and a low-voltage silicon-based E-mode device are combined together to form a hybrid device, which may achieve the same or similar output characteristics as a single high-voltage III-N E-mode device.
Summary
[0006] In a first aspect, a method for fabricating a III-N device includes forming a III-N channel layer on a substrate, forming a III-N barrier layer on the channel layer, forming an insulator layer on the barrier layer, and forming a trench in a first portion of the device. Forming the trench can comprise removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined range. Forming the trench may further include annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.
[0007] In a second aspect, a method of fabricating a device includes providing a second III-N layer on a first III-N layer, where the second layer comprises aluminum as a group-III element and the first III-N layer comprises gallium or indium but not aluminum as a group-III element, providing an insulator layer on the second III-N layer, and forming a trench in a first portion of the device. Forming the trench can comprise removing the insulator layer to expose a portion of the second III-N layer in the first portion of the device, annealing the device in a gas ambient including oxygen at an elevated temperature to oxidize the exposed portion of the second III-N layer in the first portion of the device, and removing the oxidized exposed portion of the second III-N layer and exposing a top surface of the first III-N layer in the first portion of the device.
[0008] In a third aspect, a III-N device includes a III-N material structure with a III-N channel layer and a III-N barrier layer, a source contact and a drain contact electrically coupled to the channel layer, an insulator layer on the III-N material structure, and a gate insulator at least partially in a trench, and also on a top surface of the channel layer. The trench extends though the insulator layer and into the III-N material structure, with the portion of the trench that extends into the III-N material structure having first sidewalls that are substantially more vertical than second sidewalls of the portion of the trench that is through the insulator layer. The device further includes a gate electrode deposited conformally on top of the gate insulator and at least partially in the trench, where the gate electrode is positioned between the source and drain contacts.
[0009] In a fourth aspect, a transistor includes a semiconductor material structure with a conductive channel, a source contact and a drain contact which are electrically coupled to the conductive channel, and an insulator layer on the semiconductor material structure. The transistor further includes a gate insulator on the semiconductor material structure, where the gate insulator includes an amorphous AlxSiyN film with y/x<1/3, and a gate electrode on top of the gate insulator and position between the source and drain contacts.
[0010] In a fifth aspect, a method of fabricating a nitrogen polar III-N device includes providing a III-N material structure with a second III-N layer on a first III-N layer, the second III-N layer comprising aluminum as a group-III element and the first III-N layer comprising gallium or indium but not aluminum as a group-III element, providing a masking layer on an N-face of the second III-N layer in a second portion of the device but not in a first portion of the device, such that the second III-N layer is exposed in the first portion but not the second portion of the device, annealing the device in a gas ambient including oxygen at an elevated temperature to oxidize the exposed portion of the second III-N layer in the first portion of the device; and removing the oxidized exposed portion of the second III-N layer in the first portion of the device to expose a top surface of the first III-N layer in the first portion of the device.
[0011] In a sixth aspect, a method for fabricating a III-N device includes forming a III-N channel layer on a substrate, forming a second III-N barrier layer on the channel layer, forming a III-N etch stop layer on the second III-N barrier layer, forming a first III-N barrier layer on the III-N etch stop layer, forming an insulator layer on the first III-N barrier layer, and forming a trench in a first portion of the device. Forming the trench includes removing the insulator layer in the first portion of the device, wherein a portion of the first III-N barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the portion of the first III-N barrier layer in the first portion of the device, and removing the oxidized portion of the first III-N barrier layer in the first portion of the device.
[0012] In a seventh aspect, a method of forming a III-N device includes forming a III-N channel layer on a substrate, forming a III-N barrier layer on the channel layer, forming a III-N etch stop layer on the III-N barrier layer, forming a p-type III-N layer on the III-N etch stop layer, forming a mask layer on the p-type III-N layer in a first portion of the device, and forming a trench in a second portion of the device. Forming the trench includes annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the p-type III-N layer in the first portion of the device and removing the oxidized portion of the p-type III-N layer in the first portion of the device.
[0013] The foregoing and other embodiments can each optionally include one or more of the following features, alone or in combination. A portion of the trench that is through the barrier layer can include vertical sidewalls, and a portion of the trench that is through the insulator layer can include slanted sidewalls. Forming the trench can include exposing the top surface of the channel layer in the first portion of the device. Removing the oxidized remaining portion of the barrier layer in the first portion of the device can include wet etching the oxidized remaining portion of the barrier layer. Removing the insulator layer and the part of the barrier layer in the first portion of the device can include dry etching the insulator layer and the part of the barrier layer in the first portion of the device. Wet etching can include chemically etching the III-N device in an alkaline solution. Removing the insulator layer and the part of the barrier layer in the first portion of the device can include removing the insulator layer in the first portion of the device by dry etching in a first gas ambient to expose a second top surface of the barrier layer, as well as removing the part of the barrier layer in the first portion of the device by dry etching in a second gas ambient which is different from the first gas ambient. The insulator layer can include a silicon nitride layer and the barrier layer can include an aluminum gallium nitride (AlxGa1-xN) layer, wherein the second gas ambient can include SF6 and the third gas ambient includes Cl2.
[0014] The barrier layer can include an Al-based III-N layer that can be oxidized by the annealing, and the channel layer can include a III-N layer without Aluminum (Al) that is resistant to being oxidized during the annealing. The predetermined thickness range can be from about 3 nm to 10 nm. The elevated temperature can be between 300° C. and 700° C. Forming an insulator layer can include forming a first silicon nitride layer by metal organic chemical vapor deposition (MOCVD) as the insulator layer, and fabricating the III-N device can further include forming a second silicon nitride layer by plasma enhanced chemical vapor deposition (PECVD) as an etch mask layer before forming the trench, as well as removing the etch mask layer from the insulator layer by wet etching in an acid solution after removing the oxidized remaining portion of the barrier layer in the first portion of the device. Fabricating the III-N device can also include forming a gate insulator at least partially in the trench, wherein the gate insulator is formed on the top surface of the channel layer in the first portion of the device. Forming the gate insulator can include depositing an amorphous aluminum silicon nitride (AlxSiyN) film in the trench. A thickness of the amorphous AlxSiyN film can be between 1 nm and 60 nm. A ratio of the silicon fractional composition to the Al fractional composition y/x in the AlxSiyN film is less than ⅓. Depositing the amorphous AlxSiyN film can include forming the amorphous AlxSiyN film at a growth or deposition temperature higher than 500° C. Fabricating the III-N device can include forming source and drain contacts electrically coupled to the channel layer, and forming a gate electrode on the gate insulator at least partially in the trench between the source and drain contacts. Forming the III-N barrier layer can include forming the III-N barrier layer with a higher bandgap than the channel layer, such that a conductive channel is induced in the channel layer, and forming the source and drain contacts can include forming respective ohmic contacts for the source and drain contacts that are electrically coupled to the conductive channel.
[0015] When fabricating a device, oxidizing the exposed portion of the second III-N layer can cause the second III-N layer in the first portion of the device to be oxidized all the way to an interface between the second III-N layer and the first III-N layer but does not cause any of the first III-N layer to be oxidized. Fabricating a device can also include forming an electrode in the trench. A second insulator layer can be formed prior to forming the electrode, wherein the second insulator layer is between the electrode and the top surface of the first III-N layer in the trench. The electrode can be a gate electrode, a conductive channel can be induced adjacent to an interface between the first and second III-N layers due to a compositional difference between the first and second III-N layers, and fabricating a device can further include forming a source and drain electrode, the source and drain electrodes being on opposite sides of the gate electrode and being electrically coupled to the conductive channel. The conductive channel can be depleted of mobile charge below the trench when 0V is applied to the gate electrode relative to the source electrode, but becomes populated with mobile charge when a sufficiently positive voltage is applied to the gate electrode relative to the source electrode. The electrode can include an extending portion which extends over the insulator layer towards the drain electrode. The second insulator layer can include an extending portion that is between the extending portion of the electrode and the insulator layer. Fabricating a device can also include partially removing the second III-N layer in the first portion of the device after the removing of the insulator layer in the first portion of the device but prior to the annealing of the device, causing a remaining portion of the second III-N layer in the first portion of the device to have a first thickness which is less than a second thickness of portions of the second III-N layer that are on opposite sides of the trench. The first thickness can be between 3 nm and 10 nm.
[0016] In the III-N device, the first sidewalls of the trench can be vertical and the second sidewalls of the trench can be slanted. The gate electrode can include extending portions that are outside the trench and extend towards but are separated from the source and drain contacts, respectively. The barrier layer can have a larger bandgap than the channel layer, such that a conductive channel is induced in the channel layer. The source and drain contacts can form respective ohmic contacts that are electrically coupled to the conductive channel. The conductive channel can be discontinuous in a region of the channel layer beneath the trench when 0V is applied to the gate electrode relative to the source contact, but is continuous when a voltage greater than a threshold voltage of the device is applied to the gate electrode relative to the source contact, the threshold voltage being greater than 0V. The III-N device can function as an enhancement-mode field effect transistor having the threshold voltage of more than 2V and a threshold voltage hysteresis of less than 0.5V. The gate insulator can include an amorphous AlxSiyN film. A thickness of the amorphous AlxSiyN film can be between 1 nm and 60 nm. The III-N channel layer can include a III-N layer without Aluminum (Al) and the III-N barrier layer can include an Al-based III-N layer.
[0017] In the transistor, a thickness of the amorphous AlxSiyN film can be between about 1 nm and 60 nm. The semiconductor material structure can include a III-N channel layer and a III-N barrier layer on the III-N channel layer, and wherein the III-N barrier layer has a larger bandgap than the III-N channel layer, such that the conductive channel is induced in the III-N channel layer near an interface between the III-N channel layer and the III-N barrier layer. At room temperature, a threshold voltage of the transistor can be more than 2 V and a threshold voltage hysteresis can be less than 0.5 V.
[0018] When fabricating a nitrogen polar III-N device, the top surface of the first III-N layer can be an N-face of the first III-N layer. Fabricating a nitrogen polar III-N device can also include providing a third III-N layer on an opposite side of the first III-N layer from the second III-N layer, wherein a compositional difference between the first III-N layer and the third III-N layer causes a conductive channel to be induced in the first III-N layer adjacent to an interface between the first and third III-N layers. Additionally, fabricating a nitrogen polar III-N device can include forming a gate electrode over the second portion of the device and forming a source contact electrically coupled to the conductive channel in the first portion of the device, wherein the second III-N layer is sufficiently thick to ensure that the conductive channel is depleted of mobile charge in the second portion of the device when 0V is applied to the gate electrode relative to the source contact. Prior to forming the gate electrode, the insulator layer can be removed from the second portion of the device.
[0019] Fabricating a III-N device can further include extending the trench into the first III-N barrier layer prior to the annealing of the III-N device. The extending of the trench into the first III-N barrier layer can include etching part way through the first III-N barrier layer in the first portion of the device. The III-N etch stop layer can include a III-N layer without Aluminum (Al), and the first III-N barrier layer can include an Al-based III-N layer.
[0020] As used herein, the terms III-Nitride or III-N materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula BwAlxInyGazN, where w+x+y+z is about 1 with 0≤w≤1, 0≤x≤1, 0≤y≤1, and 0≤z≤1. III-N materials, layers, or devices, can be formed or prepared by either directly growing on a suitable substrate (e.g., by metal organic chemical vapor deposition), or growing on a suitable substrate, detaching from the original substrate, and bonding to other substrates.
[0021] As used herein, two or more contacts or other items such as conductive channels or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, e.g., is about the same, at all times under any bias conditions.
[0022] As used herein, “blocking a voltage” refers to the ability of a transistor, device, or component to prevent significant current, such as current that is greater than 0.001 times the operating current during regular conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, while a transistor, device, or component is blocking a voltage that is applied across it, the total current passing through the transistor, device, or component will not be greater than 0.001 times the operating current during regular conduction. Devices with off-state currents which are larger than this value exhibit high loss and low efficiency, and are typically not suitable for many applications, especially power switching applications.
[0023] As used herein, a “high-voltage device”, e.g., a high-voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS), is an electronic device which is optimized for high-voltage applications. That is, when the device is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, or about 1200V or higher, and when the device is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, e.g., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block all voltages between 0V and at least Vmax, where Vmax is the maximum voltage that can be supplied by the circuit or power supply, and Vmax can for example be 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltage required by the application.
[0024] As used herein, a “III-N device” is a device based on III-N heterostructures. The III-N device can be designed to operate as an E-mode transistor or switch. The III-N device can be a high-voltage device suitable for high voltage applications. In such a high-voltage device, when the device is biased off (e.g., the voltage on the gate relative to the source is less than the device threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high-voltage in the application in which the device is used, which for example may be 100V, 300V, 600V, 1200V, 1700V, 2500V, or higher. When the high voltage device is biased on (e.g., the voltage on the gate relative to the source or associated power terminal is greater than the device threshold voltage), it is able to conduct substantial current with a low on-voltage (i.e., a low voltage between the source and drain terminals or between opposite power terminals). The maximum allowable on-voltage is the maximum on-state voltage that can be sustained in the application in which the device is used.
[0025] The details of one or more disclosed implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Additional features and variations may be included in the implementations as well. For example, an FQS having N-polar III-N layers can be formed by including a second gate structure between electrodes 1122 and 1124 in the device of FIG. 11G . Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.
Description of Drawings
[0026] FIG. 1 is a cross-sectional view of an example III-N device.
[0027] FIGS. 2A-2B are flow diagrams of an example process for forming the III-N device of FIG. 1 .
[0028] FIG. 3A is a flow diagram of an example process for forming a trench in the III-N device of FIG. 1 or FIG. 2A .
[0029] FIG. 3B illustrates the example process for forming the trench in FIG. 3A .
[0030] FIG. 4 shows characterization results for an amorphous AlxSiyN film and a polycrystalline AlxSiyN film.
[0031] FIG. 5 shows threshold voltage variations of III-N devices formed on a single wafer.
[0032] FIG. 6 shows characteristics of a III-N device with an amorphous AlxSiyN film as a gate insulator at room temperature.
[0033] FIG. 7 shows characteristics of a III-N device with a polycrystalline AlxSiyN film as a gate insulator at room temperature.
[0034] FIG. 8 shows OFF-state characteristics of the III-N device of FIG. 1 at an elevated temperature over a period of time.
[0035] FIG. 9 shows characteristics of the III-N device of FIG. 1 before and after being subjected to an elevated temperature.
[0036] FIG. 10 is a cross-sectional view of another example III-N device.
[0037] FIG. 11G is a cross-sectional view of an N-polar III-N device.
[0038] FIGS. 11A-11F illustrate an example process for forming the device of FIG. 11G .
[0039] FIGS. 12A-12F illustrate an example process for forming another III-N device.
[0040] FIG. 13 is a cross-sectional view of another example III-N device.
[0041] FIGS. 14A-14F illustrate an example process for forming yet another III-N device.
[0042] Like reference numbers and designations in the various drawings indicate like elements.
Detailed Description
[0043] FIG. 1 is a cross sectional view of an example III-N device 100. The III-N device 100 can be a III-N transistor or switch, and in particular a high-voltage III-N enhancement-mode field effect transistor.
[0044] The III-N device 100 includes a substrate layer 110. The substrate layer 110 can be a substrate made of, for example, Silicon (Si), Silicon Carbide (SiC), Sapphire (Al2O3), Aluminum Nitride (AlN), Gallium Nitride (GaN), or any other suitable substrate upon which III-N materials can be formed.
[0045] A buffer layer 112 is formed on the substrate layer 110. The buffer layer 112 can be a III-N buffer layer, e.g., a GaN layer, an AlxGa1-xN layer, or the like. The buffer layer 112 can be rendered insulating or substantially free of n-type mobile carriers, e.g., by including dislocations or point defects in the buffer layer 112, and/or by doping the buffer layer 112 with compensating elements, e.g., Iron (Fe), Carbon (C), and/or Magnesium (Mg). The buffer layer 112 can have a substantially uniform composition throughout the layer. In some implementations, one or more compositions vary throughout the buffer layer 112. For example, the buffer layer 112 can be graded, e.g., by grading an Al composition in the buffer layer 112. In some cases, the buffer layer 112 is substantially thicker than any of the other III-N layers in the III-N device 100.
[0046] The III-N device 100 includes a channel layer 114 formed on the buffer layer 112. The channel layer 114 can be a III-N layer, e.g., an undoped GaN layer or a slightly or unintentionally doped GaN layer. In some examples, the channel layer 114 is a III-N layer without Al composition, for example GaN or InzGa1-zN.
[0047] A barrier layer 116 is formed on the channel layer 114. The barrier layer 116 and the channel layer 114 can have different compositions or III-N materials from one another. The compositions or III-N materials are selected such that the barrier layer 116 can have a larger bandgap than the channel layer 114. In some examples, the barrier layer 116 is an Al-based III-N layer, e.g., an AlxGa1-xN layer, an AlyIn1-yN layer, or an AlInGaN layer. The channel layer can be an undoped GaN layer. The barrier layer 116 can be n-doped or can contain no significant concentration of doping impurities. In the case that the barrier layer 116 is undoped, polarization fields can exist between the channel layer 114 and the barrier layer 116, such that a fixed charge is induced at or adjacent to the interface between layers 114 and 116.
[0048] The band edge discontinuity in the conduction band of the III-N material structure, resulting from the bandgap difference and/or the difference in electron affinity between layers 114 and 116, in combination with the doping of the barrier layer 116 or introduced polarization, can induce a conductive channel 119 in the channel layer 114, e.g., near an interface between the channel layer 114 and the barrier layer 116, as illustrated in FIG. 1 . The conductive channel 119 can include a 2-dimentional electron gas (2DEG) channel, e.g., between source contact 121 and gate contact 123, as well as gate contact 123 and drain contact 122. As shown in FIG. 1 , when the device 100 is in the OFF state (i.e., the gate contact 123 is biased relative to the source contact 121 at a voltage lower than the device threshold voltage), the conductive channel 119 is depleted of mobile charge below the gate electrode 123, and so the 2DEG is discontinuous between the source contact 121 and the drain contact 122. When the device 100 is in the ON state (i.e., the gate contact 123 is biased relative to the source contact 121 at a voltage lower than the device threshold voltage), the conductive channel 119 below the gate electrode 123 is populated with mobile charge (not shown in FIG. 1 ), and the 2DEG is continuous from the source all the way to the drain. In some implementations, the source and drain contacts 121 and 122, respectively, form ohmic contacts electrically coupled to, electrically connected to, or contacting the 2DEG channel. The gate contact 123 can modulate a portion of the 2DEG channel in a gate region, e.g., directly beneath the gate contact 123.
[0049] The III-N device 100 can also include an insulator layer 118. The insulator layer 118 can be a passivation layer, preventing or suppressing dispersion by preventing or suppressing voltage fluctuations at the uppermost III-N surface. The insulator layer 118 can be made of SixNy, Al2O3, SiO2, AlxSiyN, or the like, and can be prepared by metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD), high density chemical vapor deposition, or any suitable deposition process. In a particular example, the insulator layer 118 is a Silicon Nitride (SixNy) layer formed by MOCVD.
[0050] The source contact 121, e.g., a source electrode, and the drain contact 122, e.g., a drain electrode, can be formed by metal stacks in contact with one of the III-N layers, e.g., the channel layer 114. The metal stacks can be Ti/Al/Ni/Au, Ti/Al, or the like. The source contact 121 and the drain contact 122 can be formed by metal evaporation and post-deposition annealing processes. Other ohmic contact processes can also be used.
[0051] To shape the electric field in a high-voltage-field region of the III-N device 100, a trench 124 is formed to reduce a peak electric field and increase a device breakdown voltage or threshold voltage, thereby allowing for high voltage operation. The trench 124 can also cause the device 100 to operate in enhancement mode (i.e., to be an E-mode device), The trench 124 can be formed by removing part of the insulator layer 118 and part or all of the barrier layer 116 in a trench shape. The residual damage in the channel layer, as well as the depth and shape of the trench, are crucial for achieving enhancement mode operation along with a low device on-resistance Ron, as further described below.
[0052] In some implementations, dry etching techniques, e.g., plasma etching, digital plasma etching, or reactive ion etching (RIE), are used to form a trench or recess structure. The dry etching techniques can cause ion bombardment damage, which can reduce the channel carrier mobility. These techniques also have low etching selectivity with respect to III-Nitride materials. That is, it is difficult to selectively etch one composition of III-Nitride materials without substantially etching a different composition of III-Nitride materials using these techniques. Furthermore, it can be difficult to recover a surface with ion bombardment damage. Etching selectivity can also be important for III-N epitaxy films, as each layer grown epitaxially on a substrate has thickness and composition variations from a center of a wafer to an edge of the wafer. In some cases, the dry etching techniques have little etching selectivity between a barrier layer and a channel layer. Thus, large threshold voltage variations can be caused by different etching depths.
[0053] To realize an enhancement-mode transistor using a III-N device structure, it can be important to control etching depth in the trench or recess. A device having the III-N material structure of device 100 but lacking the trench 124 typically operates in depletion mode. Including a recess or trench 124 in the III-N material structure in the gate region of the device causes the device threshold voltage to shift to a lower value. If the etching depth is not deep enough, such that the shift in threshold voltage is small, the III-N device may still remain a depletion mode device, exhibiting normally-on characteristics. If the etching depth is too deep and extends into the channel layer, current communications between the conductive channel underneath gate contact and conductive channels in the device access regions (i.e., the regions between the source and gate and between the gate and drain) can be cut off, even when the device is biased in the ON state. In this case, the III-N device may have a low current density or may not be operational in the ON state, even though normally-off E-mode operation can be realized. Although dry etching rates can be calibrated to reasonable accuracy, variations in barrier layer thickness between different wafers due to growth condition fluctuations of III-N expitaxy films, as well as variations across a single wafer, may cause low manufacturing yield.
[0054] In some implementations, as discussed in further details in FIGS. 2A-2B and FIGS. 3A-3B , a wet etching technique can be used in the formation of trench 124. Using the wet etching technique, the barrier layer 116 in the trench 124 can be completely removed and the etching can stop precisely on a top surface of the channel layer 114 in a self-aligned style. In some examples, the barrier layer 116 can be completely removed under a tolerance of barrier layer thickness fluctuations, which can improve the etch depth uniformity over the wafer and improve manufacturing yield.
[0055] Trench etch cross-sections are typically either rectangular or trapezoidal, i.e., trenches either have vertical sidewalls or sloping sidewalls, but not both. In a device such as device 100, having vertical sidewalls throughout the trench is not desirable, since conformal deposition of defect-free gate dielectric and gate metal can be challenges in III-N device structures having recesses or trenches with vertically shaped sidewalls. However, having sloped sidewalls throughout the trench, and in particular in the portion of the trench that is through the III-N material, is also not desirable because thickness variations in the barrier layer adjacent to the bottom of the trench reduces 2DEG charge density and increases resistance of the access regions in the portion of the channel directly adjacent to but not directly under the bottom of the trench. It is therefore desirable that the trench sidewalls are vertical in the barrier layer 116 but sloped in the overlying insulator layer 118.
[0056] After wet etching, as indicated in FIG. 1 , the trench 124 can have vertical sidewalls in the barrier layer 116 and slanted sidewalls in the insulator layer 118, as discussed in further details below. A top surface of the channel layer 114 is exposed in the trench 124. The trench 124 extends from the top surface of the channel layer 114 through the barrier layer 116 and the insulator layer 118 to a top surface of the insulator layer 118.
[0057] A gate insulator 120, e.g., a gate insulator layer or a gate dielectric layer, is grown or deposited conformally at least partially in the trench 124. The gate insulator 120 can be on the top surface of the channel layer 114. The gate insulator 120 can extend at least from the top surface of the channel layer 114 to the top surface of the insulator layer 118. The gate insulator 120 can also have vertical sidewalls in the barrier layer 116 and slanted sidewalls in the insulator layer 118.
[0058] The gate insulator 120 can, for example, be formed of or include Aluminum Oxide (Al2O3), Silicon Dioxide (SiO2), SixNy, or any other wide bandgap insulator. In some examples, the gate insulator 120 is an AlxSiyN layer, e.g., an amorphous AlxSiyN layer or a polycrystalline AlxSiyN layer, where x and y represent the relative fractional compositions of non-nitrogen elements in the AlxSiyN layer. That is, x/(x+y) is the percent of non-nitrogen elements in the AlxSiyN layer that are constituted by aluminum, y/(x+y) is the percent of non-nitrogen elements in the AlxSiyN layer that are constituted by silicon, and x/y is the ratio of aluminum to silicon in the AlxSiyN layer. In a particular example, as discussed in further details below, the gate insulator 120 includes an amorphous AlxSiyN film that provides high gate bias and low gate leakage. The amorphous AlxSiyN film can have a thickness of between about 1 nm and 100 nm, for example between 1 nm and 60 nm.
[0059] In some implementations, the gate insulator 120 is a ternary compound such as an AlxAyN layer, where A is an element from the fourth group of the periodic table, e.g., an amorphous AlxSiyN layer or a polycrystalline AlxSiyN layer. Gate insulator 120 could also be a wideband gap quaternary insulator such as AlxMyAzN, where M is a transition metal element, A is an element of the fourth group of the periodic table, and x, y, and z are the relative fractional compositions of non-nitrogen elements in the AlxMyAzN layer. The quaternary insulator reduces to the ternary when either y or z is equal to zero. Although amorphous films may be preferable, other mixed phase matrices could also be used.
[0060] Next, the gate contact 123, e.g., a gate electrode, is formed conformally on the gate insulator 120 at least partially in the recess 124. Similarly to the gate insulator 120, the portion of the gate contact 123 that is in the trench and adjacent to the barrier layer 116 can be oriented vertically, and the portion of the gate contact 123 that is in the trench and adjacent to the insulator layer 118 can be slanted. In some implementations, the gate contact 123 includes extending portions that are outside the trench 124 and extend towards the source contact 121 and/or the drain contact 122, respectively. The extending portions are separated from the source contact 121 and the drain contact 122, respectively. The extending portions of the gate contact 123 can function as field plates for the III-N device 100. In some examples, the extending portions of the gate contact at least partially include the slanted portions of the gate contact and can function as slant field plates, which may improve device performance.
[0061] The gate contact 123 can be formed as metal stacks, e.g., nickel/gold (Ni/Au), and can be deposited by metal evaporation or sputtering or chemical vapor deposition. The gate contact 123 may alternatively be another conductive material or material stack including one or more materials having a large work function, such as a semiconductor material having a large work function (e.g., p-type poly-silicon, indium tin oxide, or titanium nitride). A post-deposition annealing process may optionally be performed after deposition of the gate contact 123. Finally, the gate contact 123 can be used as an etch mask to etch the gate insulator 120, such that the gate insulator 120 remains directly beneath the gate contact 123 but is etched away everywhere else.
[0062] As illustrated in FIG. 1 , when 0V (or any voltage less than the device threshold voltage) is applied to the gate contact 123 relative to the source contact 121, the conductive channel 119 is discontinuous in a region of the channel layer 114 directly beneath the trench 124 in the gate region of the III-N device 100. As a consequence of the discontinuity of the conductive channel 119, the device channel between the source and drain contacts is not conductive when 0 V is applied to the gate contact 123 relative to the source contact 121, but is readily conductive when a sufficiently positive voltage, e.g., above a device threshold voltage, is applied to the gate contact 123 relative to the source contact 121. Thus, the III-device 100 can function as a high-voltage enhancement-mode device for high voltage applications. The III-N device 100 can be a transistor, a bidirectional switch or four quadrant switch (FQS), and/or any suitable semiconductor device.
[0063] FIGS. 2A-2B show an example process 200 for forming a III-N device. The process 200 can be utilized to form the III-N device 100 of FIG. 1 .
[0064] Referring to FIG. 2A , the process 200 includes forming a buffer layer on a substrate (202). The buffer layer and the substrate can be the buffer layer 112 and the substrate layer 110 of FIG. 1 , respectively. The substrate can be a silicon wafer. The buffer layer can be formed by either directly growing the buffer layer on the substrate, or alternatively by growing the buffer layer on a first substrate, detaching the buffer layer from the first substrate, and bonding the buffer layer to the substrate. As noted above, forming the buffer layer (step 202) can also include doping the buffer layer with compensating elements.
[0065] Next, a III-N channel layer is formed on the buffer layer (step 204). The III-N channel layer can be the channel layer 114 of FIG. 1 . The III-N channel layer can be an undoped III-N layer, e.g., an undoped GaN layer. In a particular example, the III-N channel layer is an undoped GaN layer and is substantially free of Al.
[0066] A III-N barrier layer is then formed on the channel layer (step 206). The III-N barrier layer can be the barrier layer 116 of FIG. 1 . The III-N barrier layer includes different composition or III-N materials from the channel layer, such that the barrier layer has a larger bandgap than the channel layer and a conductive channel, e.g., a 2DEG channel, can be induced in the channel layer. In some examples, the barrier layer is an AlxGa1-xN layer. The barrier layer can have a thickness of about 30 nm. In particular implementations, the III-N barrier layer is an AlxInyGa1-x-yN layer, where x and y are the respective aluminum and indium fractional compositions, x+y is the gallium fractional composition, 0<x≤1, 0≤y<1, and 0≤x+y<1.
[0067] Next, an insulator layer is formed on the barrier layer (step 208). The insulator layer can be the insulator layer 118 of FIG. 1 . As noted above, the insulator layer can be made of SixNy, Al2O3, SiO2, AlxSiyN, or the like, and can be deposited by MOCVD, LPCVD, PECVD, CVD, HDPCVD, sputtering, activated reactive sputtering, ALD, plasma assisted ALD, or any suitable deposition process. In a particular example, the insulator layer is a SiNx layer formed by MOCVD.
[0068] A trench is then formed to expose a top surface of the channel layer (step 210). The trench can be the trench 124 of FIG. 1 . As discussed in further details in FIGS. 3A and 3B , formation of the trench can include using a wet etching technique. After wet etching, the formed trench can have vertical sidewalls in the barrier layer 316 and slanted sidewalls in the insulator layer 318. The barrier layer can be removed in the trench region and the top surface of the channel layer 314 can be exposed in the trench. The trench can extend from the top surface of the channel layer 314 through the barrier layer 316 and the insulator layer 318 to a top surface of the insulator layer. In some examples, the conductive channel is discontinuous in a region of the channel layer directly beneath the trench when no voltages are applied to any of the device electrodes (e.g., the source, the gate, or the drain).
[0069] Referring now to FIG. 2B , a gate insulator is formed on the top surface of the channel layer (step 212). The gate insulator can be the gate insulator 120 of FIG. 1 . The gate insulator is formed conformally at least partially in the trench. The gate insulator can be in direct contact with the top surface of the channel layer without barrier material therebetween. The portion of the gate insulator contacting the barrier layer can have vertical sidewalls, and the portion of the gate insulator contacting the insulator layer can have slanted sidewalls.
[0070] In some implementations, to achieve high gate bias and low gate leakage, an amorphous aluminum silicon nitride (e.g., AlxSiyN) film is grown as the gate insulator. The III-N device with the amorphous AlxSiyN film as the gate insulator can achieve a high breakdown electrical field, low interface traps, and high temperature stability, as discussed in further details in FIGS. 6 to 9 .
[0071] The amorphous AlxSiyN film can be grown by using CVD, LPCVD, MOCVD, molecular beam epitaxy (MBE), sputter deposition, or any suitable deposition process. In some examples, the grown amorphous AlxSiyN film has a thickness of between 1 nm and 100 nm, for example between about 1 nm and 60 nm.
[0072] During formation of the AlxSiyN film, a number of growth or deposition conditions can be optimized to ensure that the resulting AlxSiyN film is amorphous (rather than polycrystalline). For example, the growth or deposition temperature, chamber pressure, and/or Si/Al ratio can be optimized to realize an amorphous AlxSiyN film. Generally, decreasing the growth or deposition temperature and increasing the Si/Al ratio tends to cause the deposited AlxSiyN film to be amorphous, rather than polycrystalline. For example, for a growth or deposition temperature of about 1000° C. or higher, the resulting AlxSiyN can be amorphous if the Si/Al ratio is about 6/94 or greater, whereas for a growth or deposition temperature of about 800° C. or higher, the resulting AlxSiyN can be amorphous if the Si/Al ratio is about 2/3 or greater. However, it has been found that increasing the growth or deposition temperature, and/or decreasing the Si/Al ratio, in an AlxSiyN gate insulator film of a III-N enhancement-mode device causes the gate leakage in the device to decrease substantially as long as the AlxSiyN is amorphous (devices with polycrystalline films have been found to exhibit substantially higher gate leakage). Hence, the deposition conditions of the AlxSiyN gate insulator film can be optimized such that a high deposition temperature and low Si/Al ratio are maintained will still achieving an amorphous film. In some implementations, the growth or deposition temperature of the amorphous AlxSiyN film is greater than 500° C., for example greater than 800° C. or greater than 900° C., and/or the ratio of the Si fractional composition to the Al fractional composition y/x is less than 2/3, for example less than 1/3, less than 1/9, or less than 7/93.
[0073] Grown AlxSiyN films can be characterized by utilizing an X-ray diffraction (XRD) grazing scan to determine whether or not any crystal grains exist. FIG. 4 shows characterization results for an amorphous AlxSiyN film and a polycrystalline AlxSiyN film. Peaks in the XRD curves indicate that the film includes at least portions which are crystalline or polycrystalline. As curve 402 shows, there are no peaks appearing in the scan of the amorphous AlxSiyN film. On the other hand, as curve 404 shows, AlN crystalline peaks 406 can be detected in the polycrystalline AlxSiyN film.
[0074] Referring back to FIG. 2B , source and drain contacts which are electrically coupled to the channel layer are then formed (step 214). The source and drain contacts can be the source contact 121 and the drain contact 122 of FIG. 1 , respectively. As noted above, the source contact and the drain contact can be formed as metal stacks, e.g., Ti/Al/Ni/Au or Ti/Al, in contact with the channel layer in the III-N device, e.g., by using metal evaporation or sputtering, and optionally performing a post-deposition annealing process. In some examples, the source and drain contacts, respectively, form ohmic contacts electrically contacting or coupled to the conductive channel, e.g., the 2DEG channel, in the channel layer. The source and drain contacts may optionally be formed prior to forming the trench.
[0075] Next, a gate electrode is formed on the gate insulator between the source and drain contacts (step 216). The gate electrode can be the gate contact 123 of FIG. 1 . As noted above, the gate electrode can be formed conformally on the gate insulator at least partially in the trench, by depositing metal stacks, e.g., nickel/gold (Ni/Au) using similar processes to those used for the source and drain contacts in step 214. The gate electrode can include vertical sidewalls in the trench adjacent to the barrier layer and slanted sidewalls in the trench adjacent to the insulator layer. In some implementations, the gate electrode includes extending portions that are outside the trench and extend towards but are separated from the source contact and the drain contact, respectively.
[0076] After deposition of the gate electrode, the gate electrode can further be used as an etch mask to etch the gate insulator, such that the gate insulator remains directly beneath the gate contact but is etched away elsewhere.
[0077] FIG. 3A shows an example process 300 for forming a trench in a III-N device. FIG. 3B illustrates structure configurations 350 of the III-N device of FIG. 3A in different steps, e.g., steps in the process 300. The trench and the III-N device can be the trench 124 and the III-N device 100 of FIG. 1 , respectively. The process 300 can be the process 210 of FIG. 2A .
[0078] After process step 208 of FIG. 2A , the III-N device structure includes a buffer layer, a channel layer, a barrier layer, and an insulator layer sequentially formed on a substrate. The substrate, the buffer layer, the channel layer, the barrier layer, and the insulator layer can be the substrate layer 110, the buffer layer 112, the channel layer 114, the barrier layer 116, and the insulator layer 118 of FIG. 1 , respectively.
[0079] The process 300 can begin with the step of forming an etch mask layer on top of the insulator layer (step 301). In some examples, a first SixNy layer grown by MOCVD is used as the insulator layer, and a second SixNy layer grown by PECVD is used as the etch mask layer. Due to different properties (e.g., density) of the films grown by the two different methods, the etch mask layer and the insulator layer can be each be etched by methods that do not substantially etch the other layer. For example, the SixNy layer formed by PECVD can be etched by a suitable wet chemical etching technique (e.g., by using a heated phosphoric acid solution), while the SixNy layer formed by MOCVD can be resistant to the same wet chemical etching technique. As such, after the etch mask layer is formed, an opening is formed in the etch mask layer for defining a trench through the underlying material. The opening can be formed, for example, by etching the etch mask layer using a heated phosphoric acid solution. Forming the opening in the etch mask layer can result in the sidewalls of the opening being slanted, as illustrated in etch mask layer 326 and insulator layer 318 in structure configuration 352 of FIG. 3B , in particular when wet etching is used to define the opening.
[0080] Next, the etch mask layer is used as a mask for removing part of the insulator layer beneath the opening to form a trench in the insulator layer (step 302). The step 302 can use any suitable etch technique to remove the part of the insulator layer. In a particular example, dry etching such as reactive-ion etching (RIE) in a gas ambient including SF6 is used to etch the SixNy in both the etch mask and the insulator layers, thereby patterning at least part of the trench and exposing the barrier layer.
[0081] Due to high etch selectivity between the insulator layer 318 (e.g., a SixNy layer) and the barrier layer 316 (e.g., an AlxGa1-xN layer), the dry etching may stop on a top surface of the barrier layer, as illustrated in structure configuration 352 of FIG. 3B . Because the opening in the etch mask layer 326 is formed having slanted sidewalls, the resulting trench that is etched through the insulator layer can also have slanted sidewalls.
[0082] The trench is then extended into the III-N materials by removing part of the barrier layer 316 (step 304). The part of the barrier layer that is removed in order to extend the trench into the III-N materials can be removed by dry etching, e.g., by using RIE etching in a gas ambient including Cl2 instead of SF6 (which was used for the insulator layer). The etching depth into the barrier layer can be controlled, e.g., by controlling etching rate and/or etching time, such that the remaining barrier layer has a particular thickness away from a top surface of the channel layer, as illustrated in structure configuration 354 of FIG. 3B . The remaining portion of the barrier layer 316 in the region in which the trench is being formed can be subsequently removed by an annealing process (step 306) followed by a wet etching process (step 308), as discussed in further detail below.
[0083] As noted above, after the trench is extended into the III-N materials by dry etching part of the barrier layer 316, a portion of the barrier layer remains beneath the trench, the remaining portion being thinner than the original thickness of the barrier layer (the original thickness being the same as the thickness of the barrier layer on either side of the trench). The remaining portion of the barrier layer in the trench region is then removed in order to extend the trench to the upper surface of the III-N channel layer 314. The following process may be used to remove the remaining portion of the III-N barrier layer without etching the III-N channel layer.
[0084] After extending the trench into the III-N materials by dry etching part of the barrier layer, the III-N device is annealed in a gas ambient including oxygen at an elevated temperature (step 306). As noted above, the channel layer can be a III-N layer which does not contain aluminum (Al) as one of the group-III elements (e.g., the channel layer can be a GaN layer). The barrier layer can be a III-N layer which includes Al as one of the group-III elements (e.g., the barrier layer can be an AlxGa1-xN layer). The annealing process can selectively oxidize the Al-containing barrier layer, without oxidizing the channel layer, as the channel layer can be resistive to oxidization due to the lack of aluminum in the layer. Referring to the structure configuration 356 of FIG. 3B , the oxidized region of the barrier layer 316 is indicated by a shaded region 362 that stops at the top surface of the channel layer 314.
[0085] The elevated temperature for annealing, as well as the remaining thickness of the barrier layer in the trench region prior to annealing, are critical parameter for high selectivity of etching between the oxidized barrier layer and the un-oxidized channel layer. The elevated annealing temperature is typically within a temperature range from about 300° C. to 700° C. In a particularly example, the elevated annealing temperature is about 500° C. In some cases, if the anneal temperature is too high, for example higher than 700° C., the channel layer will also be partially oxidized and will be etched away during the subsequent etching process, which will render the device inoperable. On the other hand, if the anneal temperature is too low, then the remaining barrier layer in the trench region may not be completely oxidized during the anneal process, which could also render the device inoperable.
[0086] In order for the trench to be etched precisely to the upper surface of the channel layer, it can also be important to ensure that, after dry etching of the barrier layer, the remaining barrier layer has a particular thickness that is within a predetermined thickness range. For example, if the initial thickness of the barrier layer prior to etching is about 30 nm, the predetermined thickness range to which the barrier layer is etched to in the trench region prior to the oxidation step can be between about 3 nm and 10 nm.
[0087] If the remaining thickness of the barrier layer prior to oxidation is smaller than the minimum predetermined thickness, e.g., smaller than 3 nm, the dry etching in step 304 can cause ion bombardment damage in the channel layer, thus damaging the device channel and worsening the performance of the device, or possibly rendering the device inoperable. Additionally, when the remaining thickness of the barrier prior to oxidation is too small, the subsequent anneal process can partially oxidize the channel layer, which is undesirable in that it could also render the device inoperable.
[0088] If the remaining thickness of the barrier layer prior to oxidation is larger than the maximum predetermined thickness, e.g., larger than 10 nm, the subsequent anneal process may not be able to oxidize all the remaining barrier layer in the trench region, such that the subsequent wet etching process can not completely remove the barrier layer from the top surface of the channel layer in the trench, which may deteriorate device performance of the III-N device.
[0089] In some implementations of the process 300, the initial thickness (i.e., the as-grown thickness) of the III-N barrier layer is within the predetermined range for which the oxidation of the III-N barrier layer stops precisely at the upper surface of the III-N channel layer. In this case, the step of dry etching the III-N barrier layer prior to annealing may be omitted, and the anneal can be performed after etching through the thickness of the insulator layer without first etching any of the III-N barrier layer.
[0090] After the anneal which oxidizes the portion of the III-N barrier layer in the trench region, the remaining oxidized portion of the barrier layer in the trench region can be removed using wet etching (step 308). The wet etching can be wet chemical etching in an alkaline solution, e.g., KOH solution or TMAH solution. A temperature of the alkaline solution bath can vary from room temperature to 100° C.
[0091] As discussed above, during wet chemical etching, alkaline solution can selectively remove the oxidized barrier layer without attacking the un-oxidized channel layer. Therefore, the remaining oxidized barrier layer can be completely removed from above the channel layer in the trench region, and the top surface of the channel layer can be exposed below the trench, as illustrated in the structure configuration 358 of FIG. 3B .
[0092] In some examples, as further illustrated in the structure configuration 358 of FIG. 3B , the trench in the barrier layer 316 has vertical sidewalls after wet etching. This is believed to be possibly due to anisotropic oxidation of the III-N barrier layer. It is believed that under the oxidation conditions previously described, the III-N materials oxidized selectively along the direction in which dislocations in the III-N materials exist. Because dislocations are formed along the direction of growth, the oxidation also occurs along the growth direction of the III-N materials, and not in a lateral direction. Hence, as illustrated in structure configuration 356, the interfaces between the oxidized portion of the barrier layer 362 and the non-oxidized portions on either side of the oxidized portion are vertical (or at least substantially more vertical than the slanted sidewalls of the trench along the insulator layer).
[0093] After the trench is formed, the etch mask layer 326 can be removed from the III-N device, e.g., by using suitable wet chemical etching technique. As noted above, the etch mask layer can be a SixNy layer formed by PECVD, different from the SixNy insulator layer formed by MOCVD. Therefore, using a suitable wet chemical etch, the etch mask layer can be removed from a top surface of the insulator layer without etching the insulator layer.
[0094] As illustrated in structure configuration 360 of FIG. 3B , the III-N device has a trench formed with vertical sidewalls in the barrier layer 316 and slanted sidewalls in the insulator layer 318. The trench extends from the top surface of the channel layer 314, through the barrier layer and the insulator layer to the top surface of the insulator layer. The III-N device can be further processed according to the process 200, e.g., steps 212, 214 and 216, in FIG. 2B to form a III-N device, e.g., a high-voltage III-N enhancement-mode field effect transistor.
[0095] FIG. 5 shows threshold voltages 500 of a set of III-N devices, i.e., a set of high-voltage III-N enhancement-mode field effect transistors, which were all formed on the same 4-inch wafer using the processes described above, such that they each had the structure illustrated in FIG. 1 The threshold voltages of the III-N devices across the 4-inch wafer are plotted as a function of the distance of the device from the center of the wafer.
[0096] It is shown that the threshold voltage of the formed III-N devices are all above 2.5 V, with a threshold voltage variation of no more than about 0.7 V across the entire wafer. Since the techniques can accurately control the etch depth of the barrier layer in the trench, e.g., by removing the barrier layer with wet chemical etching and ending up on top of the channel layer without ion bombardment damage on the channel layer, the channel electron mobility and interface quality after the gate insulator deposited on the top of the channel layer is quite uniform across the wafer, which ensures high manufacturing productivity and repeatability.
[0097] FIG. 6 shows transfer curves 600 (in log scale) of a III-N device with an amorphous AlxSiyN film as a gate insulator at room temperature, e.g., at about 300 K. The III-N device has the structure of the III-N device 100 of FIG. 1 , and was formed by techniques described above in the process 200 of FIGS. 2A-2B and the process 300 of FIGS. 3A-3B . As curve 602 shows, the transistor demonstrates enhancement-mode characteristics with a threshold voltage VTh more than 2 V (the threshold voltage is the gate-source voltage VGS at which the current begins to rise, indicating that the device is turning on). The threshold voltage hysteresis between the positive direction sweep (2) and the negative direction sweep (1) is less than 0.5 V, which indicates low density of interface traps. As curve 604 shows, an ON-state drain current density IDs is around 250 mA/mm. An OFF-state drain leakage current density IDS is about 10−8 mA/mm and the gate leakage current IGS is about 10−6 mA/mm.
[0098] FIG. 7 shows transfer curves 700 (in log scale) of a III-N device (field effect transistor) with a polycrystalline AlxSiyN film as a gate insulator at room temperature. As discussed above, with polycrystalline AlxSiyN, the transistor cannot be fully turned off because of high gate current leakage. As curve 704 shows, the gate leakage current is more than 10 mA/mm. As curve 702 shows, the transistor has a threshold voltage of about 1 V, and the drain current density is about 10 mA/mm at ON-state and 5 mA/mm at OFF-state. The gate electrode of the transistor may be easily broken down under low gate bias. As shown in FIG. 7 , the gate leakage current of the device with the polycrystalline AlxSiyN film as a gate insulator when the device was biased at a gate-source voltage of 0V was about 1 mA/mm, while the gate-leakage current of the devices with amorphous AlxSiyN gate insulator films was less than 10−6 mA/mm under the same bias conditions (as can be seen in FIG. 6 ). Hence, off state gate leakage currents in devices with amorphous AlxSiyN gate insulator films were found to be about 6 orders of magnitude lower than those in devices which had polycrystalline AlxSiyN gate insulator films but were otherwise identical.
[0099] Measurements in FIGS. 6 and 7 indicate that the III-N device with an amorphous AlxSiyN film as a gate insulator can achieve much better device performance, e.g., higher threshold voltage and lower leakage, than a III-N device with a polycrystalline AlxSiyN film as a gate insulator.
[0100] FIG. 8 shows OFF-state characteristics 800 of a III-N device at an elevated temperature over a period of time. The III-N device had the structure of the III-N device 100 of FIG. 1 , with an amorphous AlxSiyN film as a gate insulator, and was formed by techniques described above in the process 200 of FIGS. 2A-2B and the process 300 of FIGS. 3A-3B .
[0101] The III-N device was tested at OFF-state, with zero volt gate bias (e.g., VGS=0 V) and 120 V drain bias (e.g., VDS=120V) applied to the III-N device. The elevated temperature was about 400 K. Curves 802 and 804 show the OFF-state drain leakage current density and gate leakage current density stability, respectively, under the condition of high temperature (400K) drain bias stress for 1 hour. It is shown that the gate leakage current density IGS, as well as the drain leakage current density IDS, stayed stable without obvious variations. This level of stability is substantially better than any that have been achieved with other materials for the gate insulator layer.
[0102] FIG. 9 shows transfer curves 900 (in log scale) of a III-N device having an amorphous AlxSiyN film as a gate insulator before and after high temperature stress. The III-N device has the structure of the III-N device 100 of FIG. 1 , and was formed by techniques described above in the process 200 of FIGS. 2A-2B and the process 300 of FIGS. 3A-3B . The III-N device tested for the measurements of FIG. 9 was the same device tested for the measurements of FIG. 6 .
[0103] Curves 902 and 904 show that the drain current density and the gate current density before and after the device was held at a high temperature of 400 K. It is shown that there is no obvious change observed after the high temperature stress. Additionally, as curve 902 shows, the threshold voltage of the III-N device is about 3 V, the ON-state drain current density is about 100 mA/mm at ON-state, and the OFF-state drain leakage current density is about 10^−7 mA/mm. As curve 904 shows, the OFF-state gate leakage current density is less than 10^−6 mA/mm (it is about 10^−7 mA/mm). Compared to measurement results at room temperature at about 300 K in FIG. 6 , the performance of the III-N device does not change significantly with the high temperature drain bias stress.
[0104] FIG. 10 is a cross-sectional view of another III-N device 1000. Device 1000 is similar to device 100 of FIG. 1 , except that device 1000 includes two gate electrodes 1023 and 1023′ between the power electrodes 1021 and 1022. Device 1000 can be operated as a bidirectional switch (i.e., a four quadrant switch or FQS), where voltages on the first gate electrode 1023 are applied relative to the first power electrode 1021, voltages on the second gate electrode 1023′ are applied relative to the second power electrode 1022, and power electrodes 1021 and 1022 are each operated as a source and a drain of the device 1000 (depending on the polarity of the voltage across the device and/or the direction of current flow).
[0105] Layers 1010, 1012, 1014, 1016, and 1018 of device 1000 each have the same properties as respective layers 110, 112, 114, 116, and 118 of the device of FIG. 1 , and can therefore be the same materials and formed using the same methods previously described with reference to device 100 of FIG. 1 . Trenches 1024 and 1024′ can each have the same shape and properties as trench 124 in FIG. 1 , and can be formed by the same methods as those described with reference to device 100 of FIG. 1 . Gate electrodes 1023 and 1023′, as well as their respective gate insulator layers 1020 and 1020′, can each have the same shape and properties as gate insulator layers 120 in FIG. 1 , and can be formed by the same methods and/or from the same materials as those described with reference to device 100 of FIG. 1 .
[0106] A III-N device 1100, e.g., a nitrogen polar (N-polar) enhancement-mode III-N transistor, in which the III-N materials are formed in a nitrogen polar (i.e., N-polar) orientation is illustrated in FIG. 11G The device 1100 includes a series of III-N layers 1104, 1106, 1108, and 1110 formed in an N-polar or [0 0 0 −1] orientation on a substrate 1102, which can for example be a silicon substrate. That is, the N-face or [0 0 0 −1] face of the III-N material structure is on an opposite side of the III-N material structure from the substrate 1102.
[0107] III-N layer 1104 is a buffer layer formed of a material such as GaN, AlGaN, or combinations thereof. III-N layer 1106 is a first barrier layer formed of a material such as AlGaN, AlInN, or AlInGaN, III-N layer 1108 is a channel layer formed of a material such as GaN, and III-N layer 1110 is a second barrier layer formed of a material such as AlGaN, AlInN, or AlInGaN. The first barrier layer 1106 has a larger bandgap than the channel layer 1108, such that a conductive channel 1118 (e.g., a 2DEG channel) is induced in the channel layer 1108 adjacent to the interface between the channel layer 1108 and the first barrier layer 1106. The second barrier layer 1110 is over the channel layer 1108 in the gate region of the device (i.e., directly beneath the gate electrode 1120) but not over the channel layer 1108 in the device access regions on opposite sides of the gate region. The second barrier layer 1110 has a larger bandgap than the channel layer, and is sufficiently thick (e.g., at least 2 nm or at least 5 nm thick) to ensure that mobile charge is depleted from the 2DEG in the gate region of the device when 0V is applied to the gate electrode 1120 relative to the source contact 1122, but that the 2DEG is populated with mobile charge in the gate region when a sufficiently high positive voltage is applied to the gate electrode 1120 relative to the source contact 1122.
[0108] Gate insulator layer 1112, which may optionally be omitted, is disposed between the gate electrode 1120 and the second III-N barrier layer 1110. Gate insulator layer can be formed of AlxSiyN, SixNy, or the like. Source and drain contacts 1122 and 1124, respectively, electrically contact the conductive channel 1118. The source contact 1122, the drain contact 1124, and/or the gate contact 1120 are over an N-face of the III-N material structure.
[0109] A method of fabricating III-N device 1100 is illustrated in FIGS. 11A-11G First, as illustrated in FIG. 11A , layers 1104, 1106, 1108, 1110, and 1112 are grown or deposited sequentially on the substrate. In some implementations, layers 1104, 1106, 1108, 1110, and 1112 are all grown by MOCVD. In some implementations, only layers 1104, 1106, 1108, and 1110 are grown, and layer 1112 is omitted from the structure. Next, as shown in FIG. 11B , a mask layer 1114, which can for example be SixNy deposited by sputtering or PECVD, is deposited over the gate region of the device. In implementations where the gate insulator layer 1112 is included, the mask layer 1114 is then used as an etch mask for etching away the gate insulator layer 1112 on either side of the gate region (i.e., over the contact and access regions of the device), as shown in FIG. 11C . For example, the gate insulator layer 1112 on either side of the gate region can be removed by dry etching using an etch chemistry that selectively etches the material of the gate insulator layer 1112 without etching the material of the second barrier layer 1110.
[0110] Next, as shown in FIG. 11D , the device is annealed in a gas ambient including oxygen at an elevated temperature in order to oxidize the exposed portions of the second barrier layer 1110′ on either side of the gate region of the device, while the III-N material masked by the mask layer 1114 is not oxidized. As with other devices described herein, the second barrier layer 1110 can be formed of a III-N material which includes Al as one of the group-III elements (e.g., AlGaN, AlInN, or AlGaInN), while the channel layer 1108 can be formed of a III-N material which is substantially free of Al (e.g., GaN), such that the oxidation step causes all of the exposed second barrier layer material to be oxidized without oxidizing the channel layer 1108. In this case, as before, the oxidation stops precisely on the upper surface of the channel layer 1108. In some implementations, the second barrier layer 1110 has a thickness within the predetermined range that allows for the oxidation to stop precisely on the upper surface of the channel layer 1108, e.g., in the range of 3 nm to 10 nm. Although not shown in FIG. 11D , in cases where the second barrier layer 1110 is thicker than the maximum thickness of the predetermined range, the second barrier layer 1110 may be partially removed, for example by dry etching, prior to the oxidation step.
[0111] Referring to FIG. 11E , the oxidized portions 1110′ of the second barrier layer are then removed, for example using the wet etching process previously described, in order to expose an N-face of the channel layer 1108 and cause the 2DEG channel 1118 to be induced in the channel layer 1108 adjacent to the first barrier layer 1106 in the device access regions. Next, as shown in FIG. 11F , the etch mask 1114 is removed. Finally, as shown in FIG. 11G the gate electrode 1120 is formed over the gate region of the device, and the source and drain contacts 1122 and 1124, respectively, are formed on opposite sides of the gate electrode 1120.
[0112] A III-N device 1200 which is similar to that of FIG. 1 but also includes an etch stop layer and a second barrier layer is illustrated in FIG. 12F . The device 1200 includes a series of III-N layers 1212, 1214, 1230, 1228, and 1216 formed on a substrate 1210, which can for example be a silicon substrate. III-N layer 1212 is a buffer layer formed of a material such as GaN, AlGaN, or combinations thereof. III-N layer 1214 is a channel layer formed of a material such as GaN. III-N layer 1216 is a first barrier layer formed of a material such as AlGaN, AlInN, or AlInGaN. III-N layer 1228, which is directly below the first barrier layer 1216, is an etch stop layer formed of a material such as GaN. III-N layer 1230, which is between the channel layer 1214 and the etch stop layer 1228, is a second barrier layer formed of a material such as AlGaN, AlInN, or AlInGaN. Layer 1218 is an insulator layer formed of silicon nitride or the like.
[0113] As seen in FIG. 12F , device 1200 can be formed as an enhancement-mode device. That is, as further described below, the thicknesses and compositions of III-N layers 1230, 1228, and 1216 can be selected such that when 0V is applied to the gate 1223 relative to the source 1221, a conductive 2DEG channel 1219 is induced in the channel layer 1214 in the device access regions (i.e., between the source 1221 and the gate 1223 and between the drain 1222 and the gate 1223) but not in the device gate region (i.e., beneath the gate). When a voltage greater than the device threshold voltage, which for an enhancement-mode device is greater than 0V, is applied to the gate 1223 relative to the source 1221, the 2DEG channel 1219 is also induced in the device gate region in the channel layer 1214, so that the conductive channel 1219 extends all the way from the source 1221 to the drain 1222.
[0114] As further illustrated in FIG. 12F , the second barrier layer 1230 and the etch stop layer 1228 are both formed beneath the gate in the gate region of the device, but the first barrier layer 1216 is not in the gate region (e.g., directly between the gate and the portion of the channel that is modulated by the gate) of the device. The first barrier layer is only included over the device access regions on either side of the gate region. In order to ensure that 2DEG channel 1214 is depleted of charge in the gate region when 0V is applied to the gate 1223 relative to the source 1221, the second barrier layer can be made thin, for example between 0.1 nanometers and 3 nanometers or between 0.1 nanometers and 2 nanometers, and can have an aluminum composition that is less than 0.4 or less than 0.3. Forming barrier layer 1230 too thick and/or with too high an aluminum composition can cause the 2DEG 1219 to be formed in the gate region when 0V is applied to the gate relative to the drain, which would result in device 1200 being a depletion-mode device.
[0115] In order to ensure that 2DEG channel 1219 is induced in the access regions at all times, the first barrier layer 1216 can be formed sufficiently thick and with a sufficiently high aluminum concentration. For example, the first barrier layer can be thicker than 20 nanometers, for example between 20 and 50 nanometers, and have an aluminum composition greater than 0.2, for example between 0.2 and 0.5. The first barrier layer may also optionally be doped n-type.
[0116] As described in more detail below, gate 1223 is formed in a trench 1224 which is etched through the entire thickness of the first barrier layer 1216. Etch stop layer 1228 is included to ensure precision in the depth that the trench is etched. In order to effectively function as an etch stop layer, layer 1228 cannot be made too thin. However, having etch stop layer too thick can degrade the performance of the device. As such, the etch stop layer typically has a thickness of greater than 0.5 nanometers, and is more typically formed to a thickness in the range of 1 nanometer to 5 nanometers or 1 nanometer to 3 nanometers.
[0117] Insulator layer 1218 is deposited on the first barrier layer 1216 and can be formed of SixNy or the like. A gate insulator 1220, e.g., a gate insulator layer or a gate dielectric layer, is grown or deposited conformally at least partially in the trench 1224 and can be formed of AlxSiyN, SixNy, or the like. The gate insulator 1220 can be on the top surface of the etch stop layer 1228 in the gate region of the device. The gate insulator 1220 can extend at least from the top surface of the etch stop layer 1228 to the top surface of the insulator layer 1218. The gate insulator 1220 can also have vertical sidewalls in the barrier layer 1216 and slanted sidewalls in the insulator layer 1218. The gate electrode 1223 is deposited on the gate insulator 1220. The source and drain contacts 1221 and 1222, respectively, electrically contact the conductive channel 1219.
[0118] A method of fabricating III-N device 1200 is illustrated in FIGS. 12A-12F . First, as illustrated in FIG. 12A , layers 1212, 1214, 1230, 1228, 1216, and 1218 are grown or deposited sequentially on the substrate 1210. In some implementations, layers 1212, 1214, 1230, 1228, 1216, and 1218 are all grown by MOCVD. A mask layer 1226, which can for example be SixNy deposited by sputtering or PECVD, is deposited over the insulator layer 1218. The mask 1226 and insulator 1218 are dry etched in a gate region of the device, and a trench 1224 is formed to a top surface of the first barrier layer 1216. Next, as shown in FIG. 12B , a portion of the first barrier layer 1216 is dry etched away, extending the trench 1224 part way through the first barrier layer.
[0119] The device is then annealed in a gas ambient including oxygen at an elevated temperature in order to oxidize the exposed portions of the first barrier layer 1216 while the III-N material masked by the mask layer 1226 is not oxidized, as shown in FIG. 12C . As with other devices described herein, the first barrier layer 1216 can be formed of a M-N material which includes Al as one of the group-III elements (e.g., AlGaN, AlInN, or AlGaInN), while etch stop layer 1228 can be formed of a III-N material which is substantially free of Al (e.g., GaN), such that the oxidation step causes all of the exposed first barrier layer material to be oxidized, indicated by 1262, without oxidizing the etch stop layer 1228. In some implementations, after the trench 1224 is etched part way through the first barrier layer 1216 but prior to the oxidation step, the first barrier layer 1216 has a thickness beneath the trench 1224 that is within the predetermined range that allows for the oxidation to stop precisely on the upper surface of the etch stop layer 1228, e.g., in the range of 3 nm to 10 nm. In other implementations, the oxidation step is performed without the trench being etched into the first barrier layer 1216, so that the first barrier layer 1216 has the same thickness inside and outside the trench region prior to oxidation, and this entire thickness of the first barrier layer 1216 in the trench region is oxidized. Additionally, in some implementations, the second barrier layer 1230 is partially oxidized via diffusion through the etch stop layer 1228, which can occur in cases where the etch stop layer 1228 is made very thin.
[0120] Next, as illustrated in FIG. 12D , the oxidized portions 1262 of the first barrier layer are removed, for example using the wet etching process previously described, thereby extending the trench 1224 through the remainder of the first barrier layer 1216 to the upper surface of the etch stop layer 1228. Then, as illustrated in FIG. 12E , mask layer 1226 is removed. Finally, as shown in FIG. 12F , source and drain contacts 1221 and 1222, respectively, are formed on opposite sides of the trench 1224, the gate insulator layer 1220 is formed in the trench 1224 in the gate region of the device, and the gate electrode 1223 is formed over the gate insulator 1220.
[0121] Prior to deposition of the gate insulator layer 1220 and the gate electrode 1223, the etch stop layer 1228 may optionally also be etched away in the gate region of the device, thereby extending the trench 1224 (labeled 1224′ in FIG. 13 ) to the upper surface of the second barrier layer 1230. The resulting structure 1300 is shown in FIG. 13 .
[0122] Another III-N device 1400 is illustrated in FIG. 14F . The device 1400 includes a series of III-N layers 1412, 1414, 1440, 1428, and 1442 formed on a substrate 1410, which can for example be a silicon substrate. III-N layer 1412 is a buffer layer formed of a material such as GaN, AlGaN, or combinations thereof. III-N layer 1414 is a channel layer formed of a material such as GaN. III-N layer 1440 is a barrier layer formed of a material such as AlGaN, AlInN, or AlInGaN. III-N layer 1428, which is directly above the barrier layer 1440, is an etch stop layer formed of a material such as GaN. III-N layer 1442, which is above the etch stop layer 1428, is doped p-type and formed of a material such as p-AlGaN. Layer 1444 is an insulator or passivation layer formed of silicon nitride or the like.
[0123] As seen in FIG. 14F , device 1400 can be formed as an enhancement-mode device. That is, as further described below, the thicknesses and compositions of III-N layers 1440 and 1428 can be selected such that when 0V is applied to the gate 1423 relative to the source 1421, a conductive 2DEG channel 1419 is induced in the channel layer 1414 in the device access regions (i.e., between the source 1421 and the gate 1423 and between the drain 1422 and the gate 1423) but not in the device gate region (i.e., beneath the gate 1423). When a voltage greater than the device threshold voltage, which for an enhancement-mode device is greater than 0V, is applied to the gate 1423 relative to the source 1421, the 2DEG channel 1419 is also induced in the device gate region in the channel layer 1414, so that the conductive channel 1419 extends all the way from the source 1421 to the drain 1422.
[0124] As further illustrated in FIG. 14F , the barrier layer 1440 and the etch stop layer 1428 are both formed beneath the gate in the gate region of the device (e.g., directly between the gate and the portion of the channel that is modulated by the gate), as well as in the device access regions on either side of the gate region. In order to ensure that 2DEG channel 1419 is induced in the access regions at all times, the barrier layer 1440 can be formed sufficiently thick and with a sufficiently high aluminum concentration. For example, the barrier layer can be thicker than 20 nanometers, for example between 20 and 50 nanometers, and have an aluminum composition greater than 0.2, for example between 0.2 and 0.5. The barrier layer may also optionally be doped n-type. Forming barrier layer 1440 too thick and/or with too high an aluminum composition can cause the 2DEG 1419 to be formed in the gate region when 0V is applied to the gate relative to the drain, which would result in device 1400 being a depletion-mode device.
[0125] In order to ensure that 2DEG channel 1419 is not induced in the gate region when 0V or a negative voltage is applied to the gate 1423 relative to the source 1421, p-type layer 1442 is formed beneath gate 1423 to deplete the 2DEG channel 1419 within the gate region. The thickness and p-type doping level in the p-type layer 1442, as well as its composition, is selected to ensure that the 2DEG channel 1419 is depleted in the device gate region when 0V is applied to the gate 1423 relative to the source 1421. For example, the p-type doping level may be greater than 1018 cm−3, greater than 1019 cm−3, or greater than 1020 cm−3, and the thickness may be greater than 1 nm, greater than 5 nm, or greater than 10 nm. Furthermore, as described below, p-type layer 1442 can be a III-Nitride layer which contains aluminum (Al), for example AlGaN, AlInN, or AlInGaN, in order to enable reproducible fabrication of the device 1400.
[0126] As described in more detail below, gate 1423 is formed on p-type layer 1442, and p-type layer 1442 is etched away in the device access regions. Etch stop layer 1428 is included to ensure precision in the depth of the etch which removes the p-type layer 1442 in the access regions. In order to effectively function as an etch stop layer, layer 1428 cannot be made too thin. However, having etch stop layer 1428 too thick can degrade the performance of the device. As such, the etch stop layer typically has a thickness of greater than 0.5 nanometers, and is more typically formed to a thickness in the range of 1 nanometer to 5 nanometers or 1 nanometer to 3 nanometers. The same materials, compositions, and thicknesses used for etch stop layer 1228 in device 1200 (FIG. 12F ) may also be used for etch stop layer 1428.
[0127] Insulator layer 1444 is deposited on the etch stop layer 1428 and can be formed of SixNy or the like. The source and drain contacts 1421 and 1422, respectively, electrically contact the conductive channel 1419.
[0128] A method of fabricating III-N device 1400 is illustrated in FIGS. 14A-14F . First, as illustrated in FIG. 14A , layers 1412, 1414, 1440, 1428, and 1442 are grown or deposited sequentially on the substrate 1410. In some implementations, layers 1412, 1414, 1440, 1428, and 1442 are all grown by MOCVD. A mask layer 1426, which can for example be SixNy deposited by sputtering or PECVD, is deposited on a portion of the p-type layer 1442 in a gate region of the device. Next, as shown in FIG. 14B , a portion of the p-type layer 1442 is dry etched in the access regions of the device, such that the thickness of p-type layer 1442 is less in the access regions than in the gate region.
[0129] The device is then annealed in a gas ambient including oxygen at an elevated temperature in order to oxidize the exposed portions of the p-type layer 1442 while the III-N material masked by the mask layer 1426 is not oxidized, as shown in FIG. 14C . As with other devices described herein, the barrier layer 1440 can be formed of a III-N material which includes Al as one of the group-III elements (e.g., AlGaN, AlInN, or AlGaInN), while etch stop layer 1428 can be formed of a III-N material which is substantially free of Al (e.g., GaN or InGaN), such that the oxidation step causes all of the exposed p-type layer 1442 to be oxidized, indicated by 1462, without oxidizing the etch stop layer 1428. In some implementations, after the p-type layer 1442 is etched part way through but prior to the oxidation step, the p-type layer has a thickness in the device access regions that is within the predetermined range that allows for the oxidation to stop precisely on the upper surface of etch stop layer 1428, e.g., in the range of 3 nm to 10 nm. Additionally, in some implementations, barrier layer 1440 is partially oxidized via diffusion through etch stop layer 1428, which can occur in cases where etch stop layer 1428 is made very thin. In still other implementations, the step of partially etching the p-type layer 1442 prior to oxidation (shown in FIG. 14B ) is omitted. That is, the p-type layer 1442 may be made sufficiently thin, for example between 3 nm and 10 nm thick, so that the entire thickness of the exposed portions of layer 1442 may be readily oxidized without needing to first be thinned.
[0130] Next, as illustrated in FIG. 14D , the oxidized portions 1462 of p-AlGaN layer 1442 are removed, for example using the wet etching process previously described, thereby exposing etch stop layer 1428 in the device access regions. Then, as illustrated in FIG. 14E , mask layer 1426 is removed. Finally, as shown in FIG. 14F , source and drain contacts 1421 and 1422, respectively, are formed on opposite sides of gate region, insulator layer 1444 is formed on the remaining exposed etch stop layer 1428, and the gate electrode 1423 is formed over the p-type layer 1442. In some implementations, insulator layer 1444 can be formed prior to forming source and drain contacts 1421 and 1422, respectively. Although not shown in FIGS. 14D-14F , prior to removing the mask layer 1426, the etch stop layer 1428 may also be removed in the device access regions, such that in the final device, the p-type layer 1442 and etch stop layer 1428 are in the gate region of the device (i.e., beneath the gate) but not in the device access regions on either side of the gate region.
[0131] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. For example, the III-N layer structures and gate structures shown for the HEMT devices of FIGS. 11G 12F, 13, and 14 can also be utilized to form a bidirectional switch such as that shown in FIG. 10 . Features shown in each of the implementations may be used independently or in combination with one another. Accordingly, other implementations are within the scope of the following claims.
Claims
The invention claimed is:
1. A III-N device, comprising:
a III-N material structure comprising a III-N channel layer and a III-N barrier layer;
a source contact and a drain contact electrically coupled to the channel layer;
an insulator layer on the III-N material structure;
a gate insulator at least partially in a first trench, the first trench extending through the insulator layer and into the III-N material structure, a portion of the trench that extends into the III-N material structure having first sidewalls that are substantially more vertical than second sidewalls of the portion of the trench that is through the insulator layer, the gate insulator being on a top surface of the channel layer; and
a first gate electrode deposited conformally on top of the gate insulator and at least partially in the first trench, the first gate electrode being positioned between the source and drain contacts;
a second trench between the first gate electrode and the drain contact; and
a second gate electrode at least partially in the second trench.
2. The III-N device of claim 1, wherein the first sidewalls of the trench are vertical and the second sidewalls of the trench are slanted.
3. The III-N device of claim 1, wherein the gate electrode includes extending portions that are outside the trench and extend towards but are separated from the source and drain contacts, respectively.
4. The III-N device of claim 1, wherein the barrier layer has a larger bandgap than the channel layer, such that a conductive channel is induced in the channel layer.
5. The III-N device of claim 4, wherein the source and drain contacts form respective ohmic contacts that are electrically coupled to the conductive channel.
6. The III-N device of claim 5, wherein the conductive channel is discontinuous in a region of the channel layer beneath the trench when 0V is applied to the gate electrode relative to the source contact, but is continuous when a voltage greater a threshold voltage of the device is applied to the gate electrode relative to the source contact, the threshold voltage being greater than 0V.
7. The III-N device of claim 6, wherein the III-N device functions as an enhancement-mode field effect transistor, the threshold voltage of the transistor is more than 2 V, and a threshold voltage hysteresis of the transistor is less than 0.5 V.
8. The III-N device of claim 1, wherein the gate insulator is an amorphous film comprising N and at least one of Al and Si.
9. The III-N device of claim 8, wherein a thickness of the amorphous film is between 1 nm and 60 nm.
10. The III-N device of claim 1, wherein the III-N channel layer includes a III-N layer without Aluminum (Al) and the III-N barrier layer includes an Al-based III-N layer.
11. The III-N device of claim 1, wherein the gate insulator is an amorphous film comprising Al and Si.
12. The III-N device of claim 11, wherein a ratio of the silicon fractional composition to the aluminum fractional composition in the amorphous film is less than ⅓.
Patent Citations (311)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4300091(A) | 1981-11-01 | Schade, Jr. | Applicant |
| US4532439(A) | 1985-07-01 | Koike | Applicant |
| US4645562(A) | 1987-02-01 | Liao et al. | Applicant |
| US4665508(A) | 1987-05-01 | Chang | Applicant |
| US4728826(A) | 1988-03-01 | Einzinger et al. | Applicant |
| US4821093(A) | 1989-04-01 | Iafrate et al. | Applicant |
| US4914489(A) | 1990-04-01 | Awano | Applicant |
| US5051618(A) | 1991-09-01 | Lou | Applicant |
| US5329147(A) | 1994-07-01 | Vo et al. | Applicant |
| US5618384(A) | 1997-04-01 | Chan et al. | Applicant |
| US5646069(A) | 1997-07-01 | Jelloian et al. | Applicant |
| US5663091(A) | 1997-09-01 | Yen et al. | Applicant |
| US5705847(A) | 1998-01-01 | Kashiwa et al. | Applicant |
| US5714393(A) | 1998-02-01 | Wild et al. | Applicant |
| US5909103(A) | 1999-06-01 | Williams | Applicant |
| US5998810(A) | 1999-12-01 | Hatano et al. | Applicant |
| US6008684(A) | 1999-12-01 | Ker et al. | Applicant |
| US6097046(A) | 2000-08-01 | Plumton | Applicant |
| US6100571(A) | 2000-08-01 | Mizuta et al. | Applicant |
| US6292500(B1) | 2001-09-01 | Kouchi et al. | Applicant |
| US6307220(B1) | 2001-10-01 | Yamazaki | Applicant |
| US6316793(B1) | 2001-11-01 | Sheppard et al. | Applicant |
| US6373082(B1) | 2002-04-01 | Ohno et al. | Applicant |
| US6429468(B1) | 2002-08-01 | Hsu et al. | Applicant |
| US6475889(B1) | 2002-11-01 | Ring | Applicant |
| US6486502(B1) | 2002-11-01 | Sheppard et al. | Applicant |
| US6504235(B2) | 2003-01-01 | Schmitz et al. | Applicant |
| US6515303(B2) | 2003-02-01 | Ring | Applicant |
| US6548333(B2) | 2003-04-01 | Smith | Applicant |
| US6552373(B2) | 2003-04-01 | Ando et al. | Applicant |
| US6580101(B2) | 2003-06-01 | Yoshida | Applicant |
| US6583454(B2) | 2003-06-01 | Sheppard et al. | Applicant |
| US6586781(B2) | 2003-07-01 | Wu et al. | Applicant |
| US6624452(B2) | 2003-09-01 | Yu et al. | Applicant |
| US6633195(B2) | 2003-10-01 | Baudelot et al. | Applicant |
| US6649497(B2) | 2003-11-01 | Ring | Applicant |
| US6727531(B1) | 2004-04-01 | Redwing et al. | Applicant |
| US6746938(B2) | 2004-06-01 | Uchiyama et al. | Applicant |
| US6777278(B2) | 2004-08-01 | Smith | Applicant |
| US6849882(B2) | 2005-02-01 | Chavarkar et al. | Applicant |
| US6867078(B1) | 2005-03-01 | Green et al. | Applicant |
| US6914273(B2) | 2005-07-01 | Ren et al. | Applicant |
| US6946739(B2) | 2005-09-01 | Ring | Applicant |
| US6979863(B2) | 2005-12-01 | Ryu | Applicant |
| US6982204(B2) | 2006-01-01 | Saxler et al. | Applicant |
| US7030428(B2) | 2006-04-01 | Saxler | Applicant |
| US7038252(B2) | 2006-05-01 | Saito et al. | Applicant |
| US7045404(B2) | 2006-05-01 | Sheppard et al. | Applicant |
| US7053413(B2) | 2006-05-01 | D'Evelyn et al. | Applicant |
| US7071498(B2) | 2006-07-01 | Johnson et al. | Applicant |
| US7078743(B2) | 2006-07-01 | Murata et al. | Applicant |
| US7084475(B2) | 2006-08-01 | Shelton et al. | Applicant |
| US7109552(B2) | 2006-09-01 | Wu | Applicant |
| US7125786(B2) | 2006-10-01 | Ring et al. | Applicant |
| US7126212(B2) | 2006-10-01 | Enquist et al. | Applicant |
| US7161194(B2) | 2007-01-01 | Parikh et al. | Applicant |
| US7169634(B2) | 2007-01-01 | Zhao et al. | Applicant |
| US7170111(B2) | 2007-01-01 | Saxler | Applicant |
| US7199640(B2) | 2007-04-01 | De Cremoux et al. | Applicant |
| US7217960(B2) | 2007-05-01 | Ueno et al. | Applicant |
| US7230284(B2) | 2007-06-01 | Parikh et al. | Applicant |
| US7238560(B2) | 2007-07-01 | Sheppard et al. | Applicant |
| US7250641(B2) | 2007-07-01 | Saito et al. | Applicant |
| US7253454(B2) | 2007-08-01 | Saxler | Applicant |
| US7265399(B2) | 2007-09-01 | Sriram et al. | Applicant |
| US7268375(B2) | 2007-09-01 | Shur et al. | Applicant |
| US7304331(B2) | 2007-12-01 | Saito et al. | Applicant |
| US7321132(B2) | 2008-01-01 | Robinson et al. | Applicant |
| US7326971(B2) | 2008-02-01 | Harris et al. | Applicant |
| US7332795(B2) | 2008-02-01 | Smith et al. | Applicant |
| US7364988(B2) | 2008-04-01 | Harris et al. | Applicant |
| US7375407(B2) | 2008-05-01 | Yanagihara et al. | Applicant |
| US7382001(B2) | 2008-06-01 | Beach | Applicant |
| US7388236(B2) | 2008-06-01 | Wu et al. | Applicant |
| US7419892(B2) | 2008-09-01 | Sheppard et al. | Applicant |
| US7429534(B2) | 2008-09-01 | Gaska et al. | Applicant |
| US7432142(B2) | 2008-10-01 | Saxler et al. | Applicant |
| US7436001(B2) | 2008-10-01 | Lee et al. | Applicant |
| US7449730(B2) | 2008-11-01 | Kuraguchi | Applicant |
| US7456443(B2) | 2008-11-01 | Saxler et al. | Applicant |
| US7465967(B2) | 2008-12-01 | Smith et al. | Applicant |
| US7465997(B2) | 2008-12-01 | Kinzer et al. | Applicant |
| US7482788(B2) | 2009-01-01 | Yang | Applicant |
| US7488992(B2) | 2009-02-01 | Robinson | Applicant |
| US7501669(B2) | 2009-03-01 | Parikh et al. | Applicant |
| US7501670(B2) | 2009-03-01 | Murphy | Applicant |
| US7508014(B2) | 2009-03-01 | Tanimoto | Applicant |
| US7544963(B2) | 2009-06-01 | Saxler | Applicant |
| US7547925(B2) | 2009-06-01 | Wong et al. | Applicant |
| US7548112(B2) | 2009-06-01 | Sheppard | Applicant |
| US7550781(B2) | 2009-06-01 | Kinzer et al. | Applicant |
| US7550783(B2) | 2009-06-01 | Wu et al. | Applicant |
| US7550784(B2) | 2009-06-01 | Saxler et al. | Applicant |
| US7566580(B2) | 2009-07-01 | Keller et al. | Applicant |
| US7566918(B2) | 2009-07-01 | Wu et al. | Applicant |
| US7573078(B2) | 2009-08-01 | Wu et al. | Applicant |
| US7592211(B2) | 2009-09-01 | Sheppard et al. | Applicant |
| US7598108(B2) | 2009-10-01 | Li et al. | Applicant |
| US7601993(B2) | 2009-10-01 | Hoshi et al. | Applicant |
| US7605017(B2) | 2009-10-01 | Hayashi et al. | Applicant |
| US7612363(B2) | 2009-11-01 | Takeda et al. | Applicant |
| US7612390(B2) | 2009-11-01 | Saxler et al. | Applicant |
| US7615774(B2) | 2009-11-01 | Saxler | Applicant |
| US7629627(B2) | 2009-12-01 | Mil'shtein et al. | Applicant |
| US7638818(B2) | 2009-12-01 | Wu et al. | Applicant |
| US7655962(B2) | 2010-02-01 | Simin et al. | Applicant |
| US7678628(B2) | 2010-03-01 | Sheppard et al. | Applicant |
| US7692263(B2) | 2010-04-01 | Wu et al. | Applicant |
| US7700973(B2) | 2010-04-01 | Shen et al. | Applicant |
| US7709269(B2) | 2010-05-01 | Smith et al. | Applicant |
| US7709859(B2) | 2010-05-01 | Smith et al. | Applicant |
| US7714360(B2) | 2010-05-01 | Otsuka et al. | Applicant |
| US7723739(B2) | 2010-05-01 | Takano et al. | Applicant |
| US7728356(B2) | 2010-06-01 | Suh et al. | Applicant |
| US7745851(B2) | 2010-06-01 | Harris | Applicant |
| US7755108(B2) | 2010-07-01 | Kuraguchi | Applicant |
| US7759699(B2) | 2010-07-01 | Beach | Applicant |
| US7759700(B2) | 2010-07-01 | Ueno et al. | Applicant |
| US7777252(B2) | 2010-08-01 | Sugimoto et al. | Applicant |
| US7777254(B2) | 2010-08-01 | Sato | Applicant |
| US7795622(B2) | 2010-09-01 | Kikkawa et al. | Applicant |
| US7795642(B2) | 2010-09-01 | Suh et al. | Applicant |
| US7811872(B2) | 2010-10-01 | Hoshi et al. | Applicant |
| US7812369(B2) | 2010-10-01 | Chini et al. | Applicant |
| US7834380(B2) | 2010-11-01 | Ueda et al. | Applicant |
| US7851825(B2) | 2010-12-01 | Suh et al. | Applicant |
| US7855401(B2) | 2010-12-01 | Sheppard et al. | Applicant |
| US7859014(B2) | 2010-12-01 | Nakayama et al. | Applicant |
| US7859020(B2) | 2010-12-01 | Kikkawa et al. | Applicant |
| US7859021(B2) | 2010-12-01 | Kaneko | Applicant |
| US7875537(B2) | 2011-01-01 | Suvorov et al. | Applicant |
| US7875907(B2) | 2011-01-01 | Honea et al. | Applicant |
| US7875910(B2) | 2011-01-01 | Sheppard et al. | Applicant |
| US7875914(B2) | 2011-01-01 | Sheppard | Applicant |
| US7884394(B2) | 2011-02-01 | Wu et al. | Applicant |
| US7884395(B2) | 2011-02-01 | Saito | Applicant |
| US7892974(B2) | 2011-02-01 | Ring et al. | Applicant |
| US7893424(B2) | 2011-02-01 | Eichler et al. | Applicant |
| US7893500(B2) | 2011-02-01 | Wu et al. | Applicant |
| US7898004(B2) | 2011-03-01 | Wu et al. | Applicant |
| US7901994(B2) | 2011-03-01 | Saxler et al. | Applicant |
| US7906799(B2) | 2011-03-01 | Sheppard et al. | Applicant |
| US7915643(B2) | 2011-03-01 | Suh et al. | Applicant |
| US7915644(B2) | 2011-03-01 | Wu et al. | Applicant |
| US7919791(B2) | 2011-04-01 | Flynn et al. | Applicant |
| US7928475(B2) | 2011-04-01 | Parikh et al. | Applicant |
| US7932539(B2) | 2011-04-01 | Chen et al. | Applicant |
| US7935985(B2) | 2011-05-01 | Mishra et al. | Applicant |
| US7939391(B2) | 2011-05-01 | Suh et al. | Applicant |
| US7948011(B2) | 2011-05-01 | Rajan et al. | Applicant |
| US7955918(B2) | 2011-06-01 | Wu et al. | Applicant |
| US7955984(B2) | 2011-06-01 | Ohki | Applicant |
| US7956383(B2) | 2011-06-01 | Kuroda et al. | Applicant |
| US7960756(B2) | 2011-06-01 | Sheppard et al. | Applicant |
| US7961482(B2) | 2011-06-01 | Ribarich | Applicant |
| US7965126(B2) | 2011-06-01 | Honea et al. | Applicant |
| US7973335(B2) | 2011-07-01 | Okamoto et al. | Applicant |
| US7982242(B2) | 2011-07-01 | Goto | Applicant |
| US7985986(B2) | 2011-07-01 | Heikman et al. | Applicant |
| US7985987(B2) | 2011-07-01 | Kaneko | Applicant |
| US8039352(B2) | 2011-10-01 | Mishra et al. | Applicant |
| US8044380(B2) | 2011-10-01 | Lee | Applicant |
| US8049252(B2) | 2011-11-01 | Smith et al. | Applicant |
| US8076698(B2) | 2011-12-01 | Ueda et al. | Applicant |
| US8076699(B2) | 2011-12-01 | Chen et al. | Applicant |
| US8093606(B2) | 2012-01-01 | Sonobe et al. | Applicant |
| US8110425(B2) | 2012-02-01 | Yun | Applicant |
| US8114717(B2) | 2012-02-01 | Palacios et al. | Applicant |
| US8153515(B2) | 2012-04-01 | Saxler | Applicant |
| US8174048(B2) | 2012-05-01 | Beach | Applicant |
| US8178900(B2) | 2012-05-01 | Kurachi et al. | Applicant |
| US8223458(B2) | 2012-07-01 | Mochizuki et al. | Applicant |
| US8237196(B2) | 2012-08-01 | Saito | Applicant |
| US8237198(B2) | 2012-08-01 | Wu et al. | Applicant |
| US8264003(B2) | 2012-09-01 | Herman | Applicant |
| US8361816(B2) | 2013-01-01 | Lee et al. | Applicant |
| US8363437(B2) | 2013-01-01 | Wang et al. | Applicant |
| US8389975(B2) | 2013-03-01 | Kikuchi et al. | Applicant |
| US8389977(B2) | 2013-03-01 | Chu et al. | Applicant |
| US8390000(B2) | 2013-03-01 | Chu et al. | Applicant |
| US8404042(B2) | 2013-03-01 | Mizuhara et al. | Applicant |
| US8431960(B2) | 2013-04-01 | Beach et al. | Applicant |
| US8455885(B2) | 2013-06-01 | Keller et al. | Applicant |
| US8471267(B2) | 2013-06-01 | Hayashi et al. | Applicant |
| US8476125(B2) | 2013-07-01 | Khan et al. | Applicant |
| US8492779(B2) | 2013-07-01 | Lee | Applicant |
| US8502323(B2) | 2013-08-01 | Chen | Applicant |
| US8519438(B2) | 2013-08-01 | Mishra et al. | Applicant |
| US8525231(B2) | 2013-09-01 | Park et al. | Applicant |
| US8530904(B2) | 2013-09-01 | Treu et al. | Applicant |
| US8598937(B2) | 2013-12-01 | Lal et al. | Applicant |
| US8603880(B2) | 2013-12-01 | Yamada | Applicant |
| US8614460(B2) | 2013-12-01 | Matsushita | Applicant |
| US8652948(B2) | 2014-02-01 | Horie et al. | Applicant |
| US8674407(B2) | 2014-03-01 | Ando et al. | Applicant |
| US8698198(B2) | 2014-04-01 | Kuraguchi | Applicant |
| US8716141(B2) | 2014-05-01 | Dora et al. | Applicant |
| US8742460(B2) | 2014-06-01 | Mishra et al. | Applicant |
| US8772832(B2) | 2014-07-01 | Boutros | Applicant |
| US8785305(B2) | 2014-07-01 | Ramdani | Applicant |
| US8803246(B2) | 2014-08-01 | Wu et al. | Applicant |
| US2003/0006437(A1) | 2003-01-01 | Mizuta et al. | Applicant |
| US2003/0030056(A1) | 2003-02-01 | Callaway, Jr. | Applicant |
| US2004/0119067(A1) | 2004-06-01 | Weeks, Jr. et al. | Applicant |
| US2005/0133816(A1) | 2005-06-01 | Fan et al. | Applicant |
| US2005/0189559(A1) | 2005-09-01 | Saito et al. | Applicant |
| US2006/0076677(A1) | 2006-04-01 | Daubenspeck et al. | Applicant |
| US2006/0145189(A1) | 2006-07-01 | Beach | Applicant |
| US2006/0189109(A1) | 2006-08-01 | Fitzgerald | Applicant |
| US2006/0202272(A1) | 2006-09-01 | Wu et al. | Applicant |
| US2006/0226442(A1) | 2006-10-01 | Zhang et al. | Applicant |
| US2007/0018199(A1) | 2007-01-01 | Sheppard et al. | Applicant |
| US2007/0045670(A1) | 2007-03-01 | Kuraguchi | Applicant |
| US2007/0128743(A1) | 2007-06-01 | Huang et al. | Applicant |
| US2007/0131968(A1) | 2007-06-01 | Morita et al. | Applicant |
| US2007/0145417(A1) | 2007-06-01 | Brar et al. | Applicant |
| US2007/0205433(A1) | 2007-09-01 | Parikh et al. | Applicant |
| US2007/0210329(A1) | 2007-09-01 | Goto | Applicant |
| US2007/0228477(A1) | 2007-10-01 | Suzuki et al. | Applicant |
| US2007/0249119(A1) | 2007-10-01 | Saito | Applicant |
| US2007/0295985(A1) | 2007-12-01 | Weeks, Jr. et al. | Applicant |
| US2008/0073670(A1) | 2008-03-01 | Yang et al. | Applicant |
| US2008/0272397(A1) | 2008-11-01 | Koudymov et al. | Applicant |
| US2008/0308813(A1) | 2008-12-01 | Suh et al. | Applicant |
| US2009/0045438(A1) | 2009-02-01 | Inoue et al. | Applicant |
| US2009/0050936(A1) | 2009-02-01 | Oka | Applicant |
| US2009/0072269(A1) | 2009-03-01 | Suh et al. | Applicant |
| US2009/0075455(A1) | 2009-03-01 | Mishra | Applicant |
| US2009/0085065(A1) | 2009-04-01 | Mishra et al. | Applicant |
| US2009/0140262(A1) | 2009-06-01 | Ohki et al. | Applicant |
| US2010/0044752(A1) | 2010-02-01 | Marui | Applicant |
| US2010/0065923(A1) | 2010-03-01 | Charles et al. | Applicant |
| US2010/0133506(A1) | 2010-06-01 | Nakanishi et al. | Applicant |
| US2010/0203234(A1) | 2010-08-01 | Anderson et al. | Applicant |
| US2010/0219445(A1) | 2010-09-01 | Yokoyama et al. | Applicant |
| US2011/0012110(A1) | 2011-01-01 | Sazawa et al. | Applicant |
| US2011/0127604(A1) | 2011-06-01 | Sato | Applicant |
| US2012/0217512(A1) | 2012-08-01 | Renaud | Applicant |
| US2012/0235160(A1) | 2012-09-01 | Heikman | Examiner |
| US2012/0267637(A1) | 2012-10-01 | Jeon et al. | Applicant |
| US2013/0056744(A1) | 2013-03-01 | Mishra et al. | Applicant |
| US2013/0292698(A1) | 2013-11-01 | Then et al. | Applicant |
| US2013/0313561(A1) | 2013-11-01 | Suh | Applicant |
| US2013/0328061(A1) | 2013-12-01 | Chu et al. | Applicant |
| US2014/0084346(A1) | 2014-03-01 | Tajiri | Applicant |
| US2014/0099757(A1) | 2014-04-01 | Parikh et al. | Applicant |
| US2014/0264370(A1) | 2014-09-01 | Keller et al. | Applicant |
| US2014/0264455(A1) | 2014-09-01 | Keller et al. | Applicant |
| US2016/0020313(A1) | 2016-01-01 | Wu et al. | Applicant |
| CN1596477 | 2005-03-01 | Applicant | |
| CN1748320 | 2006-03-01 | Applicant | |
| CN101107713 | 2008-01-01 | Applicant | |
| CN101312207 | 2008-11-01 | Applicant | |
| CN101897029 | 2010-11-01 | Applicant | |
| CN102017160 | 2011-04-01 | Applicant | |
| CN103477543 | 2013-12-01 | Applicant | |
| CN103493206 | 2014-01-01 | Applicant | |
| EP1998376 | 2008-12-01 | Applicant | |
| EP2188842 | 2010-05-01 | Applicant | |
| JP9-306926 | 1997-11-01 | Applicant | |
| JP11-224950 | 1999-08-01 | Applicant | |
| JP2000-058871 | 2000-02-01 | Applicant | |
| JP2003-229566 | 2003-08-01 | Applicant | |
| JP2003-244943 | 2003-08-01 | Applicant | |
| JP2004-253620 | 2004-09-01 | Applicant | |
| JP2004-260114 | 2004-09-01 | Applicant | |
| JP2006-032749 | 2006-02-01 | Applicant | |
| JP2006-033723 | 2006-02-01 | Applicant | |
| JP2007-036218 | 2007-02-01 | Applicant | |
| JP2007-505501 | 2007-03-01 | Applicant | |
| JP2007-215331 | 2007-08-01 | Applicant | |
| JP2008-091699 | 2008-04-01 | Applicant | |
| JP2008-199771 | 2008-08-01 | Applicant | |
| JP2008-243848 | 2008-10-01 | Applicant | |
| JP2009-503815 | 2009-01-01 | Applicant | |
| JP2009-054807 | 2009-03-01 | Examiner | |
| JP2009-524242 | 2009-06-01 | Applicant | |
| JP2010-087076 | 2010-04-01 | Applicant | |
| JP2010-525023 | 2010-07-01 | Applicant | |
| JP2010-539712 | 2010-12-01 | Applicant | |
| KR2011-0033584 | 2011-03-01 | Applicant | |
| TW200924068 | 2009-06-01 | Applicant | |
| TW200924201 | 2009-06-01 | Applicant | |
| TW200947703 | 2009-11-01 | Applicant | |
| TW201010076 | 2010-03-01 | Applicant | |
| TW201027759 | 2010-07-01 | Applicant | |
| TW201027912 | 2010-07-01 | Applicant | |
| TW201036155 | 2010-10-01 | Applicant | |
| TW201322443 | 2013-06-01 | Applicant | |
| WO2004/070791 | 2004-08-01 | Applicant | |
| WO2004/098060 | 2004-11-01 | Applicant | |
| WO2005/036749 | 2005-04-01 | Applicant | |
| WO2005/070007 | 2005-08-01 | Applicant | |
| WO2005/070009 | 2005-08-01 | Applicant | |
| WO2006/114883 | 2006-11-01 | Applicant | |
| WO2007/077666 | 2007-07-01 | Applicant | |
| WO2007/108404 | 2007-09-01 | Applicant | |
| WO2008/120094 | 2008-10-01 | Applicant | |
| WO2009/036181 | 2009-03-01 | Applicant | |
| WO2009/036266 | 2009-03-01 | Applicant | |
| WO2009/039028 | 2009-03-01 | Applicant | |
| WO2009/039041 | 2009-03-01 | Applicant | |
| WO2009/076076 | 2009-06-01 | Applicant | |
| WO2009/132039 | 2009-10-01 | Applicant | |
| WO2010/039463 | 2010-04-01 | Applicant | |
| WO2010/068554 | 2010-06-01 | Applicant | |
| WO2010/090885 | 2010-08-01 | Applicant | |
| WO2010/132587 | 2010-11-01 | Applicant | |
| WO2011/031431 | 2011-03-01 | Applicant | |
| WO2011/072027 | 2011-06-01 | Applicant | |
| WO2013/052833 | 2013-04-01 | Applicant |
Non-Patent Literature (108)
- Authorized officer Chung Keun Lee, International Search Report and Written Opinion in PCT/US2008/076030, dated Mar. 23, 2009, 10 pages.Applicant
- Authorized officer Yolaine Cussac, International Preliminary Report on Patentability in PCT/US2008/076030, dated Mar. 25, 2010, 5 pages.Applicant
- Authorized officer Chung Keun Lee, International Search Report and Written Opinion in PCT/US2008/076079, dated Mar. 20, 2009, 11 pages.Applicant
- Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2008/076079, dated Apr. 1, 2010, 6 pages.Applicant
- Authorized officer Keon Hyeong Kim, International Search Report and Written Opinion in PCT/US2008/076160 dated Mar. 18, 2009, 11 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2008/076160, dated Mar. 25, 2010, 6 pages.Applicant
- Authorized officer Chung Keun Lee, International Search Report and Written Opinion in PCT/US2008/076199, dated Mar. 24, 2009, 11 pages.Applicant
- Authorized officer Dorothée Mülhausen, International Preliminary Report on Patentability in PCT/US2008/076199, dated Apr. 1, 2010, 6 pages.Applicant
- Authorized officer Keon Hyeong Kim, International Search Report and Written Opinion in PCT/US2008/085031, dated Jun. 24, 2009, 11 pages.Applicant
- Authorized officer Yolaine Cussac, International Preliminary Report on Patentability in PCT/US2008/085031, dated Jun. 24, 2010, 6 pages.Applicant
- Authorized officer Tae Hoon Kim, International Search Report and Written Opinion in PCT/US2009/041304, dated Dec. 18, 2009, 13 pages.Applicant
- Authorized officer Dorothée Mülhausen, International Preliminary Report on Patentability, in PCT/US2009/041304, dated Nov. 4, 2010, 8 pages.Applicant
- Authorized officer Sung Hee Kim, International Search Report and the Written Opinion in PCT/US2009/057554, dated May 10, 2010, 13 pages.Applicant
- Authorized Officer Gijsbertus Beijer, International Preliminary Report on Patentability in PCT/US2009/057554, dated Mar. 29, 2011, 7 pages.Applicant
- Authorized officer Cheon Whan Cho, International Search Report and Written Opinion in PCT/US2009/066647, dated Jul. 1, 2010, 16 pages.Applicant
- Authorized officer Athina Nikitas-Etienne, International Preliminary Report on Patentability in PCT/US2009/066647, dated Jun. 23, 2011, 12 pages.Applicant
- Authorized officer Sung Chan Chung, International Search Report and Written Opinion for PCT/US2010/021824, dated Aug. 23, 2010, 9 pages.Applicant
- Authorized officer Beate Giffo-Schmitt, International Preliminary Report on Patentability in PCT/US2010/021824, dated Aug. 18, 2011, 6 pages.Applicant
- Authorized officer Sang Ho Lee, International Search Report and Written Opinion in PCT/US2010/034579, dated Dec. 24, 2010, 9 pages.Applicant
- Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2010/034579, dated Nov. 24, 2011, 7 pages.Applicant
- Authorized officer Jeongmin Choi, International Search Report and Written Opinion in PCT/US2010/046193, dated Apr. 26, 2011, 13 pages.Applicant
- Authorized officer Philippe Bécamel, International Preliminary Report on Patentability in PCT/US2010/046193, dated Mar. 8, 2012, 10 pages.Applicant
- Authorized officer Sang Ho Lee, International Search Report and Written Opinion in PCT/US2010/059486, dated Jul. 26, 2011, 9 pages.Applicant
- Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2010/059486, dated Jun. 21, 2012, 6 pages.Applicant
- Authorized officer Kwan Sik Sul, International Search Report and Written Opinion in PCT/US2011/063975, dated May 18, 2012, 8 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2011/063975, dated Jun. 27, 2013, 5 pages.Applicant
- Authorized officer Sang-Taek Kim, International Search Report and Written Opinion in PCT/US2011/061407, dated May 22, 2012, 10 pages.Applicant
- Authorized officer Lingfei Bai, International Preliminary Report on Patentability in PCT/US2011/061407, dated Jun. 6, 2013, 7 pages.Applicant
- Authorized officer Kwan Sik Sul, International Search Report and Written Opinion in PCT/US2012/023160, dated May 24, 2012, 9 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2012/023160, dated Aug. 15, 2013, 6 pages.Applicant
- Authorized officer Jeongmin Choi, International Search Report and Written Opinion in PCT/US2012/027146, dated Sep. 24, 2012, 12 pages.Applicant
- Authorized officer Athina Nickitas-Etienne, International Preliminary Report on Patentability in PCT/US2012/027146, dated Sep. 19, 2013, 9 pages.Applicant
- Authorized officer Tae Hoon Kim, International Search Report and Written Opinion in PCT/US2013/035837, dated Jul. 30, 2013, 9 pages.Applicant
- Authorized officer Agnès Wittmann-Regis, International Preliminary Report on Patentability in PCT/US2013/035837, dated Oct. 23, 2014, 6 pages.Applicant
- Authorized officer Sang Won Choi, International Search Report and Written Opinion in PCT/US2013/048275, dated Oct. 14, 2013, 17 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2013/048275, dated Jan. 8, 2015, 14 pages.Applicant
- Authorized officer Hye Lyun Park, International Search Report and Written Opinion in PCT/US2013/050914, dated Oct. 18, 2013, 11 pages.Applicant
- Authorized officer Yukari Nakamura, International Preliminary Report on Patentability in PCT/US2013/050914, dated Jan. 29, 2015, 8 pages.Applicant
- Authorized officer Sang Won Choi, International Search Report and Written Opinion in PCT/US2013/024470, dated May 27, 2013, 12 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2013/024470, dated Aug. 14, 2014, 9 pages.Applicant
- Authorized officer June Young Son, International Search Report and Written Opinion in PCT/US2014/016298, dated May 23, 2014, 15 pages.Applicant
- Authorized officer Kihwan Moon, International Preliminary Report on Patentability in PCT/US2014/016298, dated Aug. 27, 2015, 12 pages.Applicant
- Authorized officer Tae Hoon Kim, International Search Report and Written Opinion in PCT/US2014/027523, dated Jul. 30, 2014, 14 pages.Applicant
- Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2014/027523, dated Sep. 24, 2015, 11 pages.Applicant
- Authorized officer June Young Son, International Search Report and Written Opinion in PCT/US2014/024191, dated Aug. 7, 2014, 11 pages.Applicant
- Authorized officer Kihwan Moon, International Preliminary Report on Patentability in PCT/US2014/024191, dated Sep. 24, 2015, 8 pages.Applicant
- Authorized officer June Young Son, International Search Report and Written Opinion in PCT/US2014/046030, dated Oct. 21, 2014, 12 pages.Applicant
- European Search Report in Application No. 10 81 5813.0, dated Mar. 12, 2013, 9 pages.Applicant
- Search Report and Action in TW Application No. 098132132, dated Dec. 6, 2012, 8 pages.Applicant
- Search Report and Action in TW Application No. 098141930, dated Jul. 10, 2014, 7 pages.Applicant
- Chinese First Office Action for Application No. 200880120050.6, dated Aug. 2, 2011, 10 pages.Applicant
- Chinese First Office Action for Application No. 200980114639.X, dated May 14, 2012, 13 pages.Applicant
- Ando et al., “10-W/mm A1GaN—GaN HFET with a Field Modulating Plate,” IEEE Electron Device Letters, 2003, 24(5):289-291.Applicant
- Arulkumaran et al., “Enhancement of Breakdown Voltage by AlN Buffer Layer Thickness in AlGaN/GaN High-electron-mobility Transistors on 4 in. Diameter Silicon,” Applied Physics Letters, 2005, 86:123503-1-3.Applicant
- Arulkumaran et al. “Surface Passivation Effects on AlGaN/GaN High-Electron-Mobility Transistors with SiO2, Si3N4, and Silicon Oxynitride,” Applied Physics Letters, 2004, 84(4):613-615.Applicant
- Barnett and Shinn, “Plastic and Elastic Properties of Compositionally Modulated Thin Films,” Annu. Rev. Mater. Sci., 1994, 24:481-511.Applicant
- Chen et al., “High-performance AlGaN/GaN Lateral Field-effect Rectifiers Compatible with High Electron Mobility Transistors,” Applied Physics Letters, 2008, 92, 253501-1-3.Applicant
- Cheng et al., “Flat GaN Epitaxial Layers Grown on Si(111) by Metalorganic Vapor Phase Epitaxy Using Step-graded AlGaN Intermediate Layers,” Journal of Electronic Materials, 2006, 35(4):592-598.Applicant
- Coffie, “Characterizing and Suppressing DC-to-RF Dispersion in AlGaN/GaN High Electron Mobility Transistors,” 2003, PhD Thesis, University of California, Santa Barbara, 169 pages.Applicant
- Coffie et al., “Unpassivated p-GaN/AlGaN/GaN HEMTs with 7.1 W/mm at 10 GhZ,” Electronic Letters, 2003, 39(19):1419-1420.Applicant
- Chu et al., “1200-V Normally Off GaN-on-Si Field-effect Transistors with Low Dynamic On-Resistance,” IEEE Electron Device Letters, 2011, 32(5):632-634.Applicant
- Dora et al., “High Breakdown Voltage Achieved on AlGaN/GaN HEMTs with Integrated Slant Field Plates,” IEEE Electron Device Letters, 2006, 27(9):713-715.Applicant
- Dora et al., “ZrO2 Gate Dielectrics Produced by Ultraviolet Ozone Oxidation for GaN and AlGaN/GaN Transistors,” J. Vac. Sci. Technol. B, 2006, 24(2)575-581.Applicant
- Dora, “Understanding Material and Process Limits for High Breakdown Voltage AlGaN/GaN HEMTs,” PhD Thesis, University of California, Santa Barbara, Mar. 2006, 157 pages.Applicant
- Fanciulli et al., “Structural and Electrical Properties of HfO2 Films Grown by Atomic Layer Deposition on Si, Ge, GaAs and GaN,” Mat. Res. Soc. Symp. Proc., 2004, vol. 786, 6 pages.Applicant
- Green et al., “The Effect of Surface Passivation on the Microwave Characteristics of Undoped AlGaN/GaN HEMT's,” IEEE Electron Device Letters, 2000, 21(6):268 270.Applicant
- Gu et al., “AlGaN/GaN MOS Transistors using Crystalline ZrO2 as Gate Dielectric,” Proceedings of SPIE, 2007, vol. 6473, 64730S-1-8.Applicant
- Higashiwaki et al. “AlGaN/GaN Heterostructure Field-Effect Transistors on 4H—SiC Substrates with Current-Gain Cutoff Frequency of 190 GHz,” Applied Physics Express, 2008, 021103-1-3.Applicant
- Hwang et al., “Effects of a Molecular Beam Epitaxy Grown A1N Passivation Layer on AlGaN/GaN Heterojunction Field Effect Transistors,” Solid-State Electronics, 2004, 48:363-366.Applicant
- Im et al., “Normally Off GaN MOSFET Based on AlGaN/GaN Heterostructure with Extremely High 2DEG Density Grown on Silicon Substrate,” IEEE Electron Device Letters, 2010, 31(3):192-194.Applicant
- Karmalkar and Mishra, “Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using a Field Plate,” IEEE Transactions on Electron Devices, 2001, 48(8):1515-1521.Applicant
- Karmalkar and Mishra, “Very High Voltage AlGaN/GaN High Electron Mobility Transistors Using a Field Plate Deposited on a Stepped Insulator,” Solid-State Electronics, 2001, 45:1645-1652.Applicant
- Keller et al., “GaN-GaN Junctions with Ultrathin A1N Interlayers: Expanding Heterojunction Design,” Applied Physics Letters, 2002, 80(23):4387-4389.Applicant
- Khan et al., “AlGaN/GaN Metal Oxide Semiconductor Heterostructure Field Effect Transistor,” IEEE Electron Device Letters, 2000, 21(2):63-65.Applicant
- Kim, “Process Development and Device Characteristics of AlGaN/GaN HEMTs for High Frequency Applications,” PhD Thesis, University of Illinois at Urbana-Champaign, 2007, 120 pages.Applicant
- Kumar et al., “High Transconductance Enhancement-mode AlGaN/GaN HEMTs on SiC Substrate,” Electronics Letters, 2003, 39(24):1758-1760.Applicant
- Kuraguchi et al., “Normally-off GaN-MISFET with Well-controlled Threshold Voltage,” Phys. Stats. Sol., 2007, 204(6):2010-2013.Applicant
- Lanford et al., “Recessed-gate Enhancement-mode GaN HEMT with High Threshold Voltage,” Electronic Letters, 2005, 41(7):449-450.Applicant
- Lee et al., “Self-aligned Process for Emitter- and Base-regrowth GaN HBTs and BJTs,” Solid-State Electronics, 2001, 45:243-247.Applicant
- Marchand et al., “Metalorganic Chemical Vapor Deposition on GaN on Si(111): Stress Control and Application to Filed-effect Transistors,” Journal of Applied Physics, 2001, 89(12):7846-7851.Applicant
- Mishra et al., “AlGaN/GaN HEMTs—An Overview of Device Operation and Applications,” Proceedings of the IEEE, 2002, 90(6):1022-1031.Applicant
- Nanjo et al., “Remarkable Breakdown Voltage Enhancement in AlGaN Channel High Electron Mobility Transistors,” Applied Physics Letters 92 (2008), 3 pages.Applicant
- Napierala et al., “Selective GaN Epitaxy on Si(111) Substrates Using Porous Aluminum Oxide Buffer Layers,” Journal of the Electrochemical Society, 2006. 153(2):G125-G127, 4 pages.Applicant
- Oka and Nozawa, “AlGaN/GaN Recessed MIS-gate HFET with High-threshold-voltage Normally-off Operation for Power Electronics Applications,” IEEE Electron Device Letters, 2008, 29(7):668-670.Applicant
- Palacios et al., “AlGaN/GaN HEMTs with an InGaN-based Back-barrier,” Device Research Conference Digest, 2005, DRC '05 63rd, pp. 181-182.Applicant
- Palacios et al., “AlGaN/GaN High Electron Mobility Transistors with InGaN Back-Barriers,” IEEE Electron Device Letters, 2006, 27(1):13-15.Applicant
- Palacios et al., “Nitride-based High Electron Mobility Transistors with a GaN Spacer,” Applied Physics Letters, 2006, 89:073508-1-3.Applicant
- Pei et al., “Effect of Dielectric Thickness on Power Performance of AlGaN/GaN HEMTs,” IEEE Electron Device Letters, 2009, 30(4):313-315.Applicant
- Tracy Frost, “Planar, Low Switching Loss, Gallium Nitride Devices for Power Conversion Applications,” SBIR N121-090 (Navy), 2012, 3 pages.Applicant
- Rajan et al., “Advanced Transistor Structures Based on N-face GaN,” 32M International Symposium on Compound Semiconductors (ISCS), Sep. 18-22, 2005, Europa-Park Rust, Germany, 2 pages.Applicant
- Reiher et al., “Efficient Stress Relief in GaN Heteroepitaxy on Si(111) Using Low-temperature A1N Interlayers,” Journal of Crystal Growth, 2003, 248:563-567.Applicant
- Saito et al., “Recessed-gate Structure Approach Toward Normally Off High-voltage AlGaN/GaN HEMT for Power Electronics Applications,” IEEE Transactions on Electron Device, 2006, 53(2):356-362.Applicant
- Shelton et al., “Selective Area Growth and Characterization of AlGaN/GaN Heterojunction Bipolar Transistors by Metalorganic Chemical Vapor Deposition,” IEEE Transactions on Electron Devices, 2001, 48(3):490-494.Applicant
- Shen, “Advanced Polarization-based Design of AlGaN/GaN HEMTs,” Jun. 2004, PhD Thesis, University of California, Santa Barbara, 192 pages.Applicant
- Sugiura et al., “Enhancement-mode n-channel GaN MOSFETs Fabricated on p-GaN Using HfO2 as Gate Oxide,” Electronics Letters, 2007, vol. 43, No. 17, 2 pages.Applicant
- Suh et al. “High-Breakdown Enhancement-mode AlGaN/GaN HEMTs with Integrated Slant Field-Plate,” Electron Devices Meeting, 2006, IEDM '06 International, 3 pages.Applicant
- Tipirneni et al. “Silicon Dioxide-encapsulated High-Voltage AlGaN/GaN HFETs for Power-Switching Applications,” IEEE Electron Device Letters, 2007, 28(9):784-786.Applicant
- Vetury et al., “Direct Measurement of Gate Depletion in High Breakdown (405V) Al/GaN/GaN Heterostructure Field Effect Transistors,” IEDM 98, 1998, pp. 55-58.Applicant
- Wang et al., “Comparison of the Effect of Gate Dielectric Layer on 2DEG Carrier Concentration in Strained AlGaN/GaN Heterostructure,” Mater. Res. Soc. Symp. Proc., 2007, vol. 831, 6 pages.Applicant
- Wang et al “Enhancement-mode Si3N4/AlGaN/GaN MISHFETs,” IEEE Electron Device Letters, 2006, 27(10):793-795.Applicant
- Wu, “AlGaN/GaN Microwave Power High-Mobility Transistors,” PhD Thesis, University of California, Santa Barbara, Jul. 1997, 134 pages.Applicant
- Wu et al., “A 97.8% Efficient GaN HEMT Boost Converter with 300-W Output Power at 1 MHz,” Electronic Device Letters, 2008, IEEE, 29(8):824-826.Applicant
- Yoshida, “AlGan/GaN Power FET,” Furukawa Review, 2002, 21:7-11.Applicant
- Zhang, “High Voltage GaN HEMTs with Low On-resistance for Switching Applications,” PhD Thesis, University of California, Santa Barbara, Sep. 2002, 166 pages.Applicant
- Zhanghong Content, Shanghai Institute of Metallurgy, Chinese Academy of Sciences, “Two-Dimensional Electron Gas and High Electron Mobility Transistor (HEMT),” Dec. 31, 1984, 17 pages.Applicant
- Authorized officer Agnès Wittmann-Regis, International Preliminary Report on Patentability in PCT/US2014/046030, dated Jan. 28, 2016, 9 pages.Applicant
- Authorized officer Kihwan Moon, International Preliminary Report on Patentability in PCT/US2015/041199, dated Feb. 2, 2017, 12 pages.Applicant
- Authorized officer Sang Won Choi, International Search Report and Written Opinion in PCT/US2015/041199, dated Apr. 5, 2016, 15 pages.Applicant