Method and system for down-converting and up-converting an electromagnetic signal, and transforms for same

[0002] This application is a continuation-in-part of U.S. application Ser. No. 09/550,644, filed Apr. 14, 2000, which is a continuation-in-part of U.S. application Ser. No. 09/521,879, filed Mar. 9, 2000 (now abandon), which is a continuation-in-part of pending U.S. application Ser. No. 09/293,342, filed Apr. 16, 1999, which is a continuation-in-part application of U.S. application Ser. No. 09/176,022, filed Oct. 21, 1998 (now U.S. Pat. No. 6,061,551), all of which are herein incorporated by reference in their entireties, and this application claims the benefit of U.S. Provisional Application No. 60/199,141, filed Apr. 24, 2000, all of which are herein incorporated by reference in their entireties.

[0003] The following patents and patent applications of common assignee are related to the present application, and are herein incorporated by reference in their entireties:

[0004] U.S. Pat. No. 6,091,940, entitled “Method and System for Frequency Up-Conversion,” filed Oct. 21, 1998 and issued Jul. 18, 2000.

[0005] U.S. Pat. No. 6,049,706, entitled “Integrated Frequency Translation And Selectivity,” filed Oct. 21, 1998 and issued Apr. 11, 2000.

[0006] U.S. Non-Provisional Application No. 09/525,615, entitled “Method, System, and Apparatus for Balanced Frequency Up-Conversion of a Baseband Signal,” filed Mar. 14, 2000.

[0007] Not applicable.

[0008] 1. Field of the Invention

[0009] The present invention relates generally to the down-conversion and up-conversion of an electromagnetic signal using a universal frequency translation module.

[0010] 2. Related Art

[0011] Various communication components exist for performing frequency down-conversion, frequency up-conversion, and filtering. Also, schemes exist for signal reception in the face of potential jamming signals.

[0012] The invention shall be described with reference to the accompanying figures, wherein:

[0013] FIG. 1A is a block diagram of a universal frequency translation (UFT) module according to an embodiment of the invention.

[0014] FIG. 1B is a more detailed diagram of a universal frequency translation (UFT) module according to an embodiment of the invention.

[0015] FIG. 1C illustrates a UFT module used in a universal frequency down-conversion (UFD) module according to an embodiment of the invention.

[0016] FIG. 1D illustrates a UFT module used in a universal frequency up-conversion (TFU) module according to an embodiment of the invention.

[0017] FIG. 2 is a block diagram of a universal frequency translation (UFT) module according to an alternative embodiment of the invention.

[0018] FIGS. 3A and 3G are example aliasing modules according to embodiments of the invention.

[0019] FIGS. 3B-3F are example waveforms used to describe the operation of the aliasing modules of FIGS. 3A and 3G.

[0020] FIG. 4 illustrates an energy transfer system with an optional energy transfer signal module according to an embodiment of the invention.

[0021] FIG. 5 illustrates an example aperture generator.

[0022] FIG. 6A illustrates an example aperture generator.

[0023] FIG. 6B illustrates an oscillator according to an embodiment of the present invention.

[0024] FIGS. 7A-B illustrate example aperture generators.

[0025] FIG. 8 illustrates an aliasing module with input and output impedance match according to an embodiment of the invention.

[0026] FIG. 9 illustrates an example energy transfer module with a switch module and a reactive storage module according to an embodiment of the invention.

[0027] FIG. 10 is a block diagram of a universal frequency up-conversion (UFU) module according to an embodiment of the invention.

[0028] FIG. 11 is a more detailed diagram of a universal frequency up-conversion (UFU) module according to an embodiment of the invention.

[0029] FIG. 12 is a block diagram of a universal frequency up-conversion (UFU) module according to an alternative embodiment of the invention.

[0030] FIGS. 13A-13I illustrate example waveforms used to describe the operation of the UTFU module.

[0031] FIG. 14 illustrates a unified down-converting and filtering (UDF) module according to an embodiment of the invention.

[0032] FIG. 15 illustrates an exemplary I/Q modulation embodiment of a receiver according to the invention.

[0033] FIGS. 16-17 illustrate exemplary block diagrams of a transmitter operating in an I/Q modulation mode, according to embodiments of the invention.

[0034] FIG. 18 illustrates a block diagram of a transceiver implementation according to an embodiment of the present invention.

[0035] FIG. 19 illustrates a method for down-converting an electromagnetic signal according to an embodiment of the present invention using a matched filtering/correlating operation.

[0036] FIG. 20 illustrates a matched filtering/correlating processor according to an embodiment of the present invention.

[0037] FIG. 21 illustrates a method for down-converting an electromagnetic signal according to an embodiment of the present invention using a finite time integrating operation.

[0038] FIG. 22 illustrates a finite time integrating processor according to an embodiment of the present invention.

[0039] FIG. 23 illustrates a method for down-converting an electromagnetic signal according to an embodiment of the present invention using an RC processing operation.

[0040] FIG. 24 illustrates an RC processor according to an embodiment of the present invention.

[0041] FIG. 25 illustrates an example pulse train.

[0042] FIG. 26 illustrates combining a pulse train of energy signals to produce a power signal according to an embodiment of the invention.

[0043] FIG. 27 illustrates an example piecewise linear reconstruction of a sine wave.

[0044] FIG. 28 illustrates how certain portions of a carrier signal or sine waveform are selected for processing according to an embodiment of the present invention.

[0045] FIG. 29 illustrates an example double sideband large carrier AM waveform.

[0046] FIG. 30 illustrates a block diagram of an example optimum processor system.

[0047] FIG. 31 illustrates the frequency response of an optimum processor according to an embodiment of the present invention.

[0048] FIG. 32 illustrates example frequency responses for a processor at various apertures.

[0049] FIG. 33 illustrates differences between the transform of an ideal impulse response (half sine) and a rectangular sample aperture.

[0050] FIGS. 34-35 illustrates an example processor embodiment according to the present invention.

[0051] FIGS. 36A-B illustrate example impulse responses of a matched filter processor and a finite time integrator.

[0052] FIG. 37 illustrates a basic circuit for an RC processor according to an embodiment of the present invention.

[0053] FIGS. 38-39 illustrate example plots of voltage signals.

[0054] FIGS. 40-42 illustrate the various characteristics of a processor according to an embodiment of the present invention.

[0055] FIGS. 43-45 illustrate example processor embodiments according to the present invention.

[0056] FIG. 46 illustrates the relationship between beta and the output charge of a processor according to an embodiment of the present invention.

[0057] FIG. 47A illustrates an RC processor according to an embodiment of the present invention coupled to a load resistance.

[0058] FIG. 47B illustrates an example implementation of the present invention.

[0059] FIG. 47C illustrates an example charge/discharge timing diagram according to an embodiment of the present invention.

[0060] FIG. 47D illustrates example energy transfer pulses according to an embodiment of the present invention.

[0061] FIG. 48 illustrates example performance characteristics of an embodiment of the present invention.

[0062] FIG. 49A illustrates example performance characteristics of an embodiment of the present invention.

[0063] FIG. 49B illustrates example waveforms for elementary matched filters.

[0064] FIG. 49C illustrates a waveform for an embodiment of a UFT subharmonic matched filter of the present invention.

[0065] FIG. 49D illustrates example embodiments of complex matched filter/correlator processor.

[0066] FIG. 49E illustrates an embodiment of a complex matched filter/correlator processor of the present invention.

[0067] FIG. 49F illustrates an embodiment of the decomposition of a non-ideal correlator alignment into an ideally aligned UFT correlator component of the present invention.

[0068] FIGS. 50A-50B illustrate example processor waveforms according to an embodiment of the present invention.

[0069] FIG. 51 illustrates the Fourier transforms of example waveforms waveforms according to an embodiment of the present invention.

[0070] FIGS. 52-53 illustrates actual waveforms from an embodiment of the present invention.

[0071] FIG. 54 illustrates a relationship between an example UFT waveform and an example carrier waveform.

[0072] FIG. 55 illustrates example impulse samplers having various apertures.

[0073] FIG. 56 illustrates the allingment of sample apertures according to an embodiment of the present invention.

[0074] FIG. 57 illustrates an ideal aperture according to an embodiment of the present invention.

[0075] FIG. 58 illustrates the relationship of a step function and delta functions.

[0076] FIG. 59 illustrates an embodiment of a receiver with bandpass filter for complex down-converting of the present invention.

[0077] FIG. 60 illustrates Fourier transforms used to analyze a clock embodiment in accordance with the present invention.

[0078] FIG. 61 illustrates an acquistion and hold processor according to an embodiment of the present invention.

[0079] FIGS. 62-63 illustrate frequency representations of transforms according to an embodiment of the present invention.

[0080] FIG. 64 illustrates an example clock generator.

[0081] FIG. 65 illustrates the down-conversion of an electromagnetic signal according to an embodiment of the present invention.

[0082] FIG. 66 illustrates a receiver according to an embodiment of the present invention.

[0083] FIG. 67 illustrates a vector modulator according to an embodiment of the present invention.

[0084] FIG. 68 illustrates example waveforms for the vector modulator of FIG. 67.

[0085] FIG. 69 illustrates an exemplary I/Q modulation receiver, according to an embodiment of the present invention.

[0086] FIG. 70 illustrates a I/Q modulation control signal generator, according to an embodiment of the present invention.

[0087] FIG. 71 illustrates example waveforms related to the I/Q modulation control signal generator of FIG. 70.

[0088] FIG. 72 illustrates example control signal waveforms overlaid upon an example input RF signal.

[0089] FIG. 73 illustrates a I/Q modulation receiver circuit diagram, according to an embodiment of the present invention.

[0090] FIGS. 74-84 illustrate example waveforms related to a receiver implemented in accordance with the present invention.

[0091] FIG. 85 illustrates a single channel receiver, according to an embodiment of the present invention.

[0092] FIG. 86 illustrates exemplary waveforms associated with quad aperture implementations of the receiver of FIG. 153, according to embodiments of the present invention.

[0093] FIG. 87 illustrates a high-level example UFT module radio architecture, according to an embodiment of the present invention.

[0094] FIG. 88 illustrates wireless design considerations.

[0095] FIG. 89 illustrates noise figure calculations based on RMS voltage and current noise specifications.

[0096] FIG. 90A illustrates an example differential input, differential output receiver configuration, according to an embodiment of the present invention.

[0097] FIG. 90B illustrates a example receiver implementation, configured as an I-phase channel, according to an embodiment of the present invention.

[0098] FIG. 90C illustrates example waveforms related to the receiver of FIG. 90B.

[0099] FIG. 90D illustrates an example re-radiation frequency spectrum related to the receiver of FIG. 90B, according to an embodiment of the present invention.

[0100] FIG. 90E illustrates an example re-radiation frequency spectral plot related to the receiver of FIG. 90B, according to an embodiment of the present invention.

[0101] FIG. 90F illustrates example impulse sampling of an input signal.

[0102] FIG. 90G illustrates example impulse sampling of an input signal in a environment with more noise relative to that of FIG. 90F.

[0103] FIG. 91 illustrates an example integrated circuit conceptual schematic, according to an embodiment of the present invention.

[0104] FIG. 92 illustrates an example receiver circuit architecture, according to an embodiment of the present invention.

[0105] FIG. 93 illustrates example waveforms related to the receiver of FIG. 92, according to an embodiment of the present invention.

[0106] FIG. 94 illustrates DC equations, according to an embodiment of the present invention.

[0107] FIG. 95 illustrates an example receiver circuit, according to an embodiment of the present invention.

[0108] FIG. 96 illustrates example waveforms related to the receiver of FIG. 95.

[0109] FIG. 97 illustrates an example receiver circuit, according to an embodiment of the present invention.

[0110] FIGS. 98 and 99 illustrate example waveforms related to the receiver of FIG. 97.

[0111] FIGS. 100-102 illustrate equations and information related to charge transfer.

[0112] FIG. 103 illustrates a graph related to the equations of FIG. 102.

[0113] FIG. 104 illustrates example control signal waveforms and an example input signal waveform, according to embodiments of the present invention.

[0114] FIG. 105 illustrates an example differential output receiver, according to an embodiment of the present invention.

[0115] FIG. 106 illustrates example waveforms related to the receiver of FIG. 105.

[0116] FIG. 107 illustrates an example transmitter circuit, according to an embodiment of the present invention.

[0117] FIG. 108 illustrates example waveforms related to the transmitter of FIG. 107.

[0118] FIG. 109 illustrates an example frequency spectrum related to the transmitter of FIG. 107.

[0119] FIG. 110 illustrates an intersection of frequency selectivity and frequency translation, according to an embodiment of the present invention.

[0120] FIG. 111 illustrates a multiple criteria, one solution aspect of the present invention.

[0121] FIG. 112 illustrates an example complementary FET switch structure, according to an embodiment of the present invention.

[0122] FIG. 113 illustrates example waveforms related to the complementary FET switch structure of FIG. 112.

[0123] FIG. 114 illustrates an example differential configuration, according to an embodiment of the present invention.

[0124] FIG. 115 illustrates an example receiver implementing clock spreading, according to an embodiment of the present invention.

[0125] FIG. 116 illustrates example waveforms related to the receiver of FIG. 115.

[0126] FIG. 117 illustrates waveforms related to the receiver of FIG. 115 implemented without clock spreading, according to an embodiment of the present invention.

[0127] FIG. 118 illustrates an example recovered I/Q waveforms, according to an embodiment of the present invention.

[0128] FIG. 119 illustrates an example CMOS implementation, according to an embodiment of the present invention.

[0129] FIG. 120 illustrates an example LO gain stage of FIG. 119 at a gate level, according to an embodiment of the present invention.

[0130] FIG. 121 illustrates an example LO gain stage of FIG. 119 at a transistor level, according to an embodiment of the present invention.

[0131] FIG. 122 illustrates an example pulse generator of FIG. 119 at a gate level, according to an embodiment of the present invention.

[0132] FIG. 123 illustrates an example pulse generator of FIG. 119 at a transistor level, according to an embodiment of the present invention.

[0133] FIG. 124 illustrates an example power gain block of FIG. 119 at a gate level, according to an embodiment of the present invention.

[0134] FIG. 125 illustrates an example power gain block of FIG. 119 at a transistor level, according to an embodiment of the present invention.

[0135] FIG. 126 illustrates an example switch of FIG. 119 at a transistor level, according to an embodiment of the present invention.

[0136] FIG. 127 illustrates an example CMOS “hot clock” block diagram, according to an embodiment of the present invention.

[0137] FIG. 128 illustrates an example positive pulse generator of FIG. 127 at a gate level, according to an embodiment of the present invention.

[0138] FIG. 129 illustrates an example positive pulse generator of FIG. 127 at a transistor level, according to an embodiment of the present invention.

[0139] FIG. 130 illustrates pulse width error effect for ½ cycle.

[0140] FIG. 131 illustrates an example single-ended receiver circuit implementation, according to an embodiment of the present invention.

[0141] FIG. 132 illustrates an example single-ended receiver circuit implementation, according to an embodiment of the present invention.

[0142] FIG. 133 illustrates an example full differential receiver circuit implementation, according to an embodiment of the present invention.

[0143] FIG. 134 illustrates an example full differential receiver implementation, according to an embodiment of the present invention.

[0144] FIG. 135 illustrates an example single-ended receiver implementation, according to an embodiment of the present invention.

[0145] FIG. 136 illustrates a plot of loss in sensitivity vs. clock phase deviation, according to an example embodiment of the present invention.

[0146] FIGS. 137 and 138 illustrate example 802.11 WLAN receiver/transmitter implementations, according to embodiments of the present invention.

[0147] FIG. 139 illustrates 802.11 requirements in relation to embodiments of the present invention.

[0148] FIG. 140 illustrates an example doubler implementation for phase noise cancellation, according to an embodiment of the present invention.

[0149] FIG. 141 illustrates an example doubler implementation for phase noise cancellation, according to an embodiment of the present invention.

[0150] FIG. 142 illustrates a example bipolar sampling aperture, according to an embodiment of the present invention.

[0151] FIG. 143 illustrates an example diversity receiver, according to an embodiment of the present invention.

[0152] FIG. 144 illustrates an example equalizer implementation, according to an embodiment of the present invention.

[0153] FIG. 145 illustrates an example multiple aperture receiver using two apertures, according to an embodiment of the present invention.

[0154] FIG. 146 illustrates exemplary waveforms related to the multiple aperture receiver of FIG. 145, according to an embodiment of the present invention.

[0155] FIG. 147 illustrates an example multiple aperture receiver using three apertures, according to an embodiment of the present invention.

[0156] FIG. 148 illustrates exemplary waveforms related to the multiple aperture receiver of FIG. 147, according to an embodiment of the present invention.

[0157] FIG. 149 illustrates an example multiple aperture transmitter, according to an embodiment of the present invention.

[0158] FIG. 150 illustrates example frequency spectrums related to the transmitter of FIG. 149.

[0159] FIG. 151 illustrates an example output waveform in a double aperture implementation of the transmitter of FIG. 149.

[0160] FIG. 152 illustrates an example output waveform in a single aperture implementation of the transmitter of FIG. 149.

[0161] FIG. 153 illustrates an example multiple aperture receiver implementation, according to an embodiment of the present invention.

[0162] FIG. 154 illustrates exemplary waveforms in a single aperture implementation of the receiver of FIG. 153, according to an embodiment of the present invention.

[0163] FIG. 155 illustrates exemplary waveforms in a dual aperture implementation of the receiver of FIG. 153, according to an embodiment of the present invention.

[0164] FIG. 156 illustrates exemplary waveforms in a triple aperture implementation of the receiver of FIG. 153, according to an embodiment of the present invention.

[0165] FIG. 157 illustrates exemplary waveforms in quad aperture implementations of the receiver of FIG. 153, according to embodiments of the present invention.

[0166] FIGS. 158 and 159 illustrate the amplitude and pulse width modulated transmitter according to embodiments of the present invention.

[0167] FIGS. 160A-160D, 161 and 162 illustrate example signal diagrams associated with the amplitude and pulse width modulated transmitter according to embodiments of the present invention.

[0168] FIG. 163 shows an embodiment of a receiver block diagram to recover the amplitude or pulse width modulated information.

[0169] FIGS. 164A-164G illustrates example signal diagrams associated with a waveform generator according to embodiments of the present invention.

[0170] FIGS. 165-167 are example schematic diagrams illustrating various circuits employed in the receiver of FIG. 163.

[0171] FIGS. 168-171 illustrate time and frequency domain diagrams of alternative transmitter output waveforms.

[0172] FIGS. 172 and 173 illustrate differential receivers in accord with embodiments of the present invention.

[0173] FIGS. 174 and 175 illustrate time and frequency domains for a narrow bandwidth/constant carrier signal in accord with an embodiment of the present invention.

[0174] 1. Introduction

[0175] 2. Universal Frequency Translation

[0176] 2.1 Frequency Down-Conversion

[0177] 2.2 Optional Energy Transfer Signal Module

[0178] 2.3 Impedance Matching

[0179] 2.4 Frequency Up-Conversion

[0180] 2.5 Enhanced Signal Reception

[0181] 2.6 Unified Down-Conversion and Filtering

[0182] 3. Example Embodiments of the Invention

[0183] 3.1 Receiver Embodiments

[0184] 3.3.1. In-Phase/Quadrature-Phase (I/Q) Modulation Mode Receiver Embodiments

[0185] 3.1.2. Other Receiver Embodiments

[0186] 3.2. Transmitter Embodiments

[0187] 3.2.1. In-Phase/Quadrature-Phase (I/Q) Modulation Mode Transmitter Embodiments

[0188] 3.3.2. Other Transmitter Embodiments

[0189] 3.3. Transceiver Embodiments

[0190] 3.4. Other Embodiments

[0191] 4. Mathematical Description of the Present Invention

[0192] 4.1 Overview

[0193] 4.2. High Level Description of a Matched Filtering/Correlating Characterization/Embodiment of the Invention

[0194] 4.3. High Level Description of a Finite Time Integrating Characterization/ Embodiment of the Invention

[0195] 4.4. High Level Description of an RC Processing Characterization/ Embodiment of the Invention

[0196] 4.5. Representation of a Power Signal as a Sum of Energy Signals

[0197] 4.5.1. De-Composition of a Sine Wave into an Energy Signal Representation

[0198] 4.5.2. Decomposition of Sine Waveforms

[0199] 4.6 Matched Filtering/Correlating Characterization/Embodiment

[0200] 4.6.1 Time Domain Description

[0201] 4.6.2 Frequency Domain Description

[0202] 4.7. Finite Time Integrating Characterization/Embodiment

[0203] 4.8 RC Processing Characterization/Embodiment

[0204] 4.9 Charge Transfer and Correlation

[0205] 4.10 Load Resistor Consideration

[0206] 4.11. Signal-To-Noise Ratio Comparison of the Various Embodiments

[0207] 4.12. Carrier Offset and Phase Skew Characteristics of Embodiments of the Present Invention

[0208] 4.13. Multiple Aperture Embodiments of the Present Invention

[0209] 4.14. Mathematical Transform Describing Embodiments of the Present Invention

[0210] 4.14.1 Overview

[0211] 4.14.2 The Kernel for Embodiments of the Invention

[0212] 4.14.3 Waveform Information Extraction

[0213] 4.15. Proof Statement for UFT Complex Downconverter Embodiment of the Present Invention

[0214] 4.16. Acquisition and Hold Processor Embodiment

[0215] 4.17. Comparison of the UFT Transform to the Fourier Sine and Cosine Transforms

[0216] 4.18. Conversion, Fourier Transform, and Sampling Clock Considerations

[0217] 4.19. Phase Noise Multiplication

[0218] 4.20. AM-PM Conversion and Phase Noise

[0219] 4.21. Pulse Accumulation and System Time Constant

[0220] 4.21.1 Pulse Accumulation

[0221] 4.21.2. Pulse Accumulation by Correlation

[0222] 4.22. Energy Budget Considerations

[0223] 4.23. Energy Storage Networks

[0224] 4.24 Impedance Matching

[0225] 4.25 Time Domain Analysis

[0226] 4.26 Complex Passband Waveform Generation Using the Present Invention Cores

[0227] 4.27. Example Embodiments of the Invention

[0228] 4.27.1. Example I/Q Modulation Receiver Embodiment

[0229] 4.27.2 Example I/Q Modulation Control Signal Generator Embodiments

[0230] 4.27.3 Detailed Example I/Q Modulation Receiver Embodiment with Exemplary Waveforms

[0231] 4.27.4 Example Single Channel Receiver Embodiment

[0232] 4.27.5 Example Automatic Gain Control (AGC) Embodiment

[0233] 4.27.6 Other Example Embodiments

[0234] 5. Architectural Features of the Invention

[0235] 6. Additional Benefits of the Invention

[0236] 6.1 Compared to an Impulse Sampler

[0237] 6.2 Linearity

[0238] 6.3 Optimal Power Transfer into a Scalable Output Impedance

[0239] 6.4 System Integration

[0240] 6.5. Fundamental or Sub-Harmonic Operation

[0241] 6.6. Frequency Multiplication and Signal Gain

[0242] 6.7. Controlled Aperture Sub-Harmonic Matched Filter Features

[0243] 6.71. Non-Negligible Aperture

[0244] 6.7.2 Bandwidth

[0245] 6.7.3 Architectural Advantages of a Universal Frequency Down-Converter

[0246] 6.7.4. Complimentary FET Switch Advantages

[0247] 6.7.5. Differential Configuration Characteristics

[0248] 6.7.6. Clock Spreading Characteristics

[0249] 6.7.7. Controlled Aperture Sub Harmonic Matched Filter Principles

[0250] 6.7.8. Effects of Pulse Width Variation

[0251] 6.8. Conventional Systems

[0252] 6.8.1. Heterodyne Systems

[0253] 6.8.2. Mobile Wireless Devices

[0254] 6.9. Phase Noise Cancellation

[0255] 6.10. Multiplexed UFD

[0256] 6.11. Sampling Apertures

[0257] 6.12. Diversity Reception and Equalizers

[0258] 7. Conclusions

[0259] 8. Glossary of Terms

[0260] 9. Conclusion

[0261] 1. Introduction

[0262] The present invention is directed to the down-conversion and up-conversion of an electromagnetic signal using a universal frequency translation (UFT) module, transforms for same, and applications thereof. The systems described herein each may include one or more receivers, transmitters, and transceivers. According to embodiments of the invention, at least some of these receivers, transmitters, and transceivers are implemented using universal frequency translation (UFT) modules. The UFT modules perform frequency translation operations. Embodiments of the present invention incorporating various applications of the UFT module are described below.

[0263] Systems that transmit and receive EM signals using UFT modules exhibit multiple advantages. These advantages include, but are not limited to, lower power consumption, longer power source life, fewer parts, lower cost, less tuning, and more effective signal transmission and reception. These systems can receive and transmit signals across a broad frequency range. The structure and operation of embodiments of the UFT module, and various applications of the same are described in detail in the following sections, and in the referenced documents.

[0264] 2. Universal Frequency Translation

[0265] The present invention is related to frequency translation, and applications of same. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and filtering, and combinations and applications of same.

[0266] FIG. 1A illustrates a universal frequency translation (UFT) module 102 according to embodiments of the invention. (The UFT module is also sometimes called a universal frequency translator, or a universal translator.)

[0267] As indicated by the example of FIG. 1A, some embodiments of the UFT module 102 include three ports (nodes), designated in FIG. 1A as Port 1, Port 2, and Port 3. Other UTF embodiments include other than three ports.

[0268] Generally, the UFT module 102 (perhaps in combination with other components) operates to generate an output signal from an input signal, where the frequency of the output signal differs from the frequency of the input signal. In other words, the UFT module 102 (and perhaps other components) operates to generate the output signal from the input signal by translating the frequency (and perhaps other characteristics) of the input signal to the frequency (and perhaps other characteristics) of the output signal.

[0269] An example embodiment of the UFT module 103 is generally illustrated in FIG. 1B. Generally, the UFT module 103 includes a switch 106 controlled by a control signal 108. The switch 106 is said to be a controlled switch.

[0270] As noted above, some UFT embodiments include other than three *ports. For example, and without limitation, FIG. 2 illustrates an example UFT module 202. The example UFT module 202 includes a diode 204 having two ports, designated as Port 1 and Port 2/3. This embodiment does not include a third port, as indicated by the dotted line around the “Port 3” label.

[0271] The UFT module is a very powerful and flexible device. Its flexibility is illustrated, in part, by the wide range of applications in which it can be used. Its power is illustrated, in part, by the usefulness and performance of such applications.

[0272] For example, a UFT module 115 can be used in a universal frequency down-conversion (UFD) module 114, an example of which is shown in FIG. 1C. In this capacity, the UFT module 115 frequency down-converts an input signal to an output signal.

[0273] As another example, as shown in FIG. 1D, a UFT module 117 can be used in a universal frequency up-conversion (UFU) module 116. In this capacity, the UFT module 117 frequency up-converts an input signal to an output signal.

[0274] These and other applications of the UFT module are described below. Additional applications of the UFT module will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. In some applications, the UFT module is a required component. In other applications, the UFT module is an optional component.

[0275] 2.1 Frequency Down-Conversion

[0276] The present invention is directed to systems and methods of universal frequency down-conversion, and applications of same.

[0277] In particular, the following discussion describes down-converting using a Universal Frequency Translation Module. The down-conversion of an EM signal by aliasing the EM signal at an aliasing rate is fully described in U.S. Pat. No. 6,061,551 entitled “Method and System for Down-Converting Electromagnetic Signals,” assigned to the assignee of the present invention, the full disclosure of which is incorporated herein by reference. A relevant portion of the above-mentioned patent is summarized below to describe down-converting an input signal to produce a down-converted signal that exists at a lower frequency or a baseband signal. The frequency translation aspects of the invention are further described in other documents referenced above, such as application Ser. No. 09/550,644, entitled “Method and System for Down-converting an Electromagnetic Signal, and Transforms for Same, and Aperture Relationships.”

[0278] FIG. 3A illustrates an aliasing module 300 for down-conversion using a universal frequency translation (UFT) module 302 which down-converts an EM input signal 304. In particular embodiments, aliasing module 300 includes a switch 308 and a capacitor 310 (or integrator). (In embodiments, the UFT module is considered to include the switch and integrator.) The electronic alignment of the circuit components is flexible. That is, in one implementation, the switch 308 is in series with input signal 304 and capacitor 310 is shunted to ground (although it may be other than ground in configurations such as differential mode). In a second implementation (see FIG. 3G), the capacitor 310 is in series with the input signal 304 and the switch 308 is shunted to ground (although it may be other than ground in configurations such as differential mode). Aliasing module 300 with UFT module 302 can be tailored to down-convert a wide variety of electromagnetic signals using aliasing frequencies that are well below the frequencies of the EM input signal 304.

[0279] In one implementation, aliasing module 300 down-converts the input signal 304 to an intermediate frequency (IF) signal. In another implementation, the aliasing module 300 down-converts the input signal 304 to a demodulated baseband signal. In yet another implementation, the input signal 304 is a frequency modulated (FM) signal, and the aliasing module 300 down-converts it to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal. Each of the above implementations is described below.

[0280] In an embodiment, the control signal 306 includes a train of pulses that repeat at an aliasing rate that is equal to, or less than, twice the frequency of the input signal 304. In this embodiment, the control signal 306 is referred to herein as an aliasing signal because it is below the Nyquist rate for the frequency of the input signal 304. Preferably, the frequency of control signal 306 is much less than the input signal 304.

[0281] A train of pulses 318 as shown in FIG. 3D controls the switch 308 to alias the input signal 304 with the control signal 306 to generate a down-converted output signal 312. More specifically, in an embodiment, switch 308 closes on a first edge of each pulse 320 of FIG. 3D and opens on a second edge of each pulse. When the switch 308 is closed, the input signal 304 is coupled to the capacitor 310, and charge is transferred from the input signal to the capacitor 310. The charge stored during successive pulses forms down-converted output signal 312.

[0282] Exemplary waveforms are shown in FIGS. 3B-3F.

[0283] FIG. 3B illustrates an analog amplitude modulated (AM) carrier signal 314 that is an example of input signal 304. For illustrative purposes, in FIG. 3C, an analog AM carrier signal portion 316 illustrates a portion of the analog AM carrier signal 314 on an expanded time scale. The analog AM carrier signal portion 316 illustrates the analog AM carrier signal 314 from time to to time t₁.

[0284] FIG. 3D illustrates an exemplary aliasing signal 318 that is an example of control signal 306. Aliasing signal 318 is on approximately the same time scale as the analog AM carrier signal portion 316. In the example shown in FIG. 3D, the aliasing signal 318 includes a train of pulses 320 having negligible apertures that tend towards zero (the invention is not limited to this embodiment, as discussed below). The pulse aperture may also be referred to as the pulse width as will be understood by those skilled in the art(s). The pulses 320 repeat at an aliasing rate, or pulse repetition rate of aliasing signal 318. The aliasing rate is determined as described below, and further described in U.S. Pat. No. 6,061,551 entitled “Method and System for Down-Converting Electromagnetic Signals.”

[0285] As noted above, the train of pulses 320 (i.e., control signal 306) control the switch 308 to alias the analog AM carrier signal 316 (i.e., input signal 304) at the aliasing rate of the aliasing signal 318. Specifically, in this embodiment, the switch 308 closes on a first edge of each pulse and opens on a second edge of each pulse. When the switch 308 is closed, input signal 304 is coupled to the capacitor 310, and charge is transferred from the input signal 304 to the capacitor 310. The charge transferred during a pulse is referred to herein as an under-sample. Exemplary under-samples 322 form down-converted signal portion 324 (FIG. 3E) that corresponds to the analog AM carrier signal portion 316 (FIG. 3C) and the train of pulses 320 (FIG. 3D). The charge stored during successive under-samples of AM carrier signal 314 form the down-converted signal 324 (FIG. 3E) that is an example of down-converted output signal 312 (FIG. 3A). In FIG. 3F, a demodulated baseband signal 326 represents the demodulated baseband signal 324 after filtering on a compressed time scale. As illustrated, down-converted signal 326 has substantially the same “amplitude envelope” as AM carrier signal 314. Therefore, FIGS. 3B-3F illustrate down-conversion of AM carrier signal 314.

[0286] The waveforms shown in FIGS. 3B-3F are discussed herein for illustrative purposes only, and are not limiting. Additional exemplary time domain and frequency domain drawings, and exemplary methods and systems of the invention relating thereto, are disclosed in U.S. Pat. No. 6,061,551 entitled “Method and System for Down-Converting Electromagnetic Signals.”

[0287] The aliasing rate of control signal 306 determines whether the input signal 304 is down-converted to an IF signal, down-converted to a demodulated baseband signal, or down-converted from an FM signal to a PM or an AM signal. Generally, relationships between the input signal 304, the aliasing rate of the control signal 306, and the down-converted output signal 312 are illustrated below:

[0288] (Freq. of input signal 304)=n•(Freq. of control signal 306)±(Freq. of down-converted output signal 312)

[0289] For the examples contained herein, only the “+” condition will be discussed. Example values of n include, but are not limited to, n={0.5, 1, 2, 3, 4, . . . }.

[0290] When the aliasing rate of control signal 306 is off-set from the frequency of input signal 304, or off-set from a harmonic or sub-harmonic thereof, input signal 304 is down-converted to an IF signal. This is because the under-sampling pulses occur at different phases of subsequent cycles of input signal 304. As a result, the under-samples form a lower frequency oscillating pattern. If the input signal 304 includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the down-converted IF signal. For example, to down-convert a 901 MHZ input signal to a 1 MHZ IF signal, the frequency of the control signal 306 would be calculated as follows:

[0291] (Freq_input−Freq_IF)/n=Freq_control

[0292] (901 MHZ−1 MHZ)/n=900/n

[0293] For n={0.5, 1, 2, 3, 4, . . . }, the frequency of the control signal 306 would be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc.

[0294] Exemplary time domain and frequency domain drawings, illustrating down-conversion of analog and digital AM, PM and FM signals to IF signals, and exemplary methods and systems thereof, are disclosed in U.S. Pat. No. 6,061,551 entitled “Method and System for Down-Converting Electromagnetic Signals.”

[0295] Alternatively, when the aliasing rate of the control signal 306 is substantially equal to the frequency of the input signal 304, or substantially equal to a harmonic or sub-harmonic thereof, input signal 304 is directly down-converted to a demodulated baseband signal. This is because, without modulation, the under-sampling pulses occur at the same point of subsequent cycles of the input signal 304. As a result, the under-samples form a constant output baseband signal. If the input signal 304 includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the demodulated baseband signal. For example, to directly down-convert a 900 MHZ input signal to a demodulated baseband signal (i.e., zero IF), the frequency of the control signal 306 would be calculated as follows:

[0296] (Freq_input−Freq_IF)/n=Freq_control

[0297] (900 MHZ−0 MHZ)/n=900 MHZ/n

[0298] For n={0.5, 1, 2, 3, 4, . . . }, the frequency of the control signal 306 should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc.

[0299] Exemplary time domain and frequency domain drawings, illustrating direct down-conversion of analog and digital AM and PM signals to demodulated baseband signals, and exemplary methods and systems thereof, are disclosed in U.S. Pat. No. 6,061,551 entitled “Method and System for Down-Converting Electromagnetic Signals.”

[0300] Alternatively, to down-convert an input FM signal to a non-FM signal, a frequency within the FM bandwidth must be down-converted to baseband (i.e., zero IF). As an example, to down-convert a frequency shift keying (FSK) signal (a sub-set of FM) to a phase shift keying (PSK) signal (a subset of PM), the mid-point between a lower frequency F₁and an upper frequency F₂(that is, [(F₁+F₂)÷2]) of the FSK signal is down-converted to zero IF.

[0301] For example, to down-convert an FSK signal having F₁equal to 899 MHZ and F₂equal to 901 MHZ, to a PSK signal, the aliasing rate of the control signal 306 would be calculated as follows:

[0302] Frequency of the input=(F₁+F₂)÷2

[0303] =(899 MHZ+901 MHZ)÷2

[0304] =900 MHZ

[0305] Frequency of the down-converted signal=0 (i.e., baseband)

[0306] (Freq_input−Freq_IF)/n=Freq_control(900 MHZ−0 MHZ)/n=900 MHZ/n

[0307] For n={0.5, 1, 2, 3, 4 . . . }, the frequency of the control signal 306 should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc. The frequency of the down-converted PSK signal is substantially equal to one half the difference between the lower frequency F₁and the upper frequency F₂.

[0308] As another example, to down-convert a FSK signal to an amplitude shift keying (ASK) signal (a subset of AM), either the lower frequency F₁or the upper frequency F₂of the FSK signal is down-converted to zero IF. For example, to down-convert an FSK signal having F₁equal to 900 MHZ and F₂equal to 901 MHZ, to an ASK signal, the aliasing rate of the control signal 306 should be substantially equal to:

[0309] (900 MHZ−0 MHZ)/n=900 MHZ/n, or

[0310] (901 MHZ−0 MHZ)/n=901 MHZ/n.

[0311] For the former case of 900 MHZ/n, and for n={0.5, 1, 2, 3, 4, . . . }, the frequency of the control signal 306 should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc. For the latter case of 901 MHZ, and for n={0.5, 1, 2, 3, 4, . . . }, the frequency of the control signal 306 should be substantially equal to 1.802 GHz, 901 MHZ, 450.5 MHZ, 300.333 MHZ, 225.25 MHZ, etc. The frequency of the down-converted AM signal is substantially equal to the difference between the lower frequency F₁and the upper frequency F₂(i.e., 1 MHZ).

[0312] Exemplary time domain and frequency domain drawings, illustrating down-conversion of FM signals to non-FM signals, and exemplary methods and systems thereof, are disclosed in U.S. Pat. No. 6,061,551 entitled “Method and System for Down-Converting Electromagnetic Signals.”

[0313] In an embodiment, the pulses of the control signal 306 have negligible apertures that tend towards zero. This makes the UFT module 302 a high input impedance device. This configuration is useful for situations where minimal disturbance of the input signal may be desired.

[0314] In another embodiment, the pulses of the control signal 306 have non-negligible apertures that tend away from zero. This makes the UFT module 302 a lower input impedance device. This allows the lower input impedance of the UFT module 302 to be substantially matched with a source impedance of the input signal 304. This also improves the energy transfer from the input signal 304 to the down-converted output signal 312, and hence the efficiency and signal to noise (s/n) ratio of UFT module 302.

[0315] Exemplary systems and methods for generating and optimizing the control signal 306, and for otherwise improving energy transfer and s/n ratio, are disclosed in U.S. Pat. No. 6,061,551 entitled “Method and System for Down-Converting Electromagnetic Signals.”

[0316] When the pulses of the control signal 306 have non-negligible apertures, the aliasing module 300 is referred to interchangeably herein as an energy transfer module or a gated transfer module, and the control signal 306 is referred to as an energy transfer signal. Exemplary systems and methods for generating and optimizing the control signal 306 and for otherwise improving energy transfer and/or signal to noise ratio in an energy transfer module are described below.

[0317] 2.2 Optional Energy Transfer Signal Module

[0318] FIG. 4 illustrates an energy transfer system 401 that includes an optional energy transfer signal module 408, which can perform any of a variety of functions or combinations of functions including, but not limited to, generating the energy transfer signal 406.

[0319] In an embodiment, the optional energy transfer signal module 408 includes an aperture generator, an example of which is illustrated in FIG. 5 as an aperture generator 502. The aperture generator 502 generates non-negligible aperture pulses 508 from an input signal 412. The input signal 412 can be any type of periodic signal, including, but not limited to, a sinusoid, a square wave, a saw-tooth wave, etc. Systems for generating the input signal 412 are described below.

[0320] The width or aperture of the pulses 508 is determined by delay through the branch 506 of the aperture generator 502. Generally, as the desired pulse width increases, the difficulty in meeting the requirements of the aperture generator 502 decrease (i.e., the aperture generator is easier to implement). In other words, to generate non-negligible aperture pulses for a given EM input frequency, the components utilized in the example aperture generator 502 do not require reaction times as fast as those that are required in an under-sampling system operating with the same EM input frequency.

[0321] The example logic and implementation shown in the aperture generator 502 are provided for illustrative purposes only, and are not limiting. The actual logic employed can take many forms. The example aperture generator 502 includes an optional inverter 510, which is shown for polarity consistency with other examples provided herein.

[0322] An example implementation of the aperture generator 502 is illustrated in FIG. 6A. Additional examples of aperture generation logic are provided in FIGS. 7A and 7B. FIG. 7A illustrates a rising edge pulse generator 702, which generates pulses 508 on rising edges of the input signal 412. FIG. 7B illustrates a falling edge pulse generator 704, which generates pulses 508 on falling edges of the input signal 412.

[0323] In an embodiment, the input signal 412 is generated externally of the energy transfer signal module 408, as illustrated in FIG. 4. Alternatively, the input signal 412 is generated internally by the energy transfer signal module 408. The input signal 412 can be generated by an oscillator, as illustrated in FIG. 6B by an oscillator 602. The oscillator 602 can be internal to the energy transfer signal module 408 or external to the energy transfer signal module 408. The oscillator 602 can be external to the energy transfer system 401. The output of the oscillator 602 may be any periodic waveform.

[0324] The type of down-conversion performed by the energy transfer system 401 depends upon the aliasing rate of the energy transfer signal 406, which is determined by the frequency of the pulses 508. The frequency of the pulses 508 is determined by the frequency of the input signal 412.

[0325] The optional energy transfer signal module 408 can be implemented in hardware, software, firmware, or any combination thereof.

[0326] 2.3 Impedance Matching

[0327] The energy transfer module 300 described in reference to FIG. 3A, above, has input and output impedances generally defined by (1) the duty cycle of the switch module (i.e., UFT 302), and (2) the impedance of the storage module (e.g., capacitor 310), at the frequencies of interest (e.g. at the EM input, and intermediate/baseband frequencies).

[0328] Starting with an aperture width of approximately ½ the period of the EM signal being down-converted as an example embodiment, this aperture width (e.g. the “closed time”) can be decreased (or increased). As the aperture width is decreased, the characteristic impedance at the input and the output of the energy transfer module increases. Alternatively, as the aperture width increases from ½ the period of the EM signal being down-converted, the impedance of the energy transfer module decreases.

[0329] One of the steps in determining the characteristic input impedance of the energy transfer module could be to measure its value. In an embodiment, the energy transfer module's characteristic input impedance is 300 ohms. An impedance matching circuit can be utilized to efficiently couple an input EM signal that has a source impedance of, for example, 50 ohms, with the energy transfer module's impedance of, for example, 300 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary impedance directly or the use of an impedance match circuit as described below.

[0330] Referring to FIG. 8, a specific example embodiment using an RF signal as an input, assuming that the impedance 812 is a relatively low impedance of approximately 50 Ohms, for example, and the input impedance 816 is approximately 300 Ohms, an initial configuration for the input impedance match module 806 can include an inductor 906 and a capacitor 908, configured as shown in FIG. 9. The configuration of the inductor 906 and the capacitor 908 is a possible configuration when going from a low impedance to a high impedance. Inductor 906 and the capacitor 908 constitute an L match, the calculation of the values which is well known to those skilled in the relevant arts.

[0331] The output characteristic impedance can be impedance matched to take into consideration the desired output frequencies. One of the steps in determining the characteristic output impedance of the energy transfer module could be to measure its value. Balancing the very low impedance of the storage module at the input EM frequency, the storage module should have an impedance at the desired output frequencies that is preferably greater than or equal to the load that is intended to be driven (for example, in an embodiment, storage module impedance at a desired 1 MHz output frequency is 2K ohm and the desired load to be driven is 50 ohms). An additional benefit of impedance matching is that filtering of unwanted signals can also be accomplished with the same components.

[0332] In an embodiment, the energy transfer module's characteristic output impedance is 2K ohms. An impedance matching circuit can be utilized to efficiently couple the down-converted signal with an output impedance of, for example, 2K ohms, to a load of, for example, 50 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary load impedance directly or the use of an impedance match circuit as described below.

[0333] When matching from a high impedance to a low impedance, a capacitor 914 and an inductor 916 can be configured as shown in FIG. 9. The capacitor 914 and the inductor 916 constitute an L match, the calculation of the component values being well known to those skilled in the relevant arts.

[0334] The configuration of the input impedance match module 806 and the output impedance match module 808 are considered to be initial starting points for impedance matching, in accordance with embodiments of the present invention. In some situations, the initial designs may be suitable without further optimization. In other situations, the initial designs can be optimized in accordance with other various design criteria and considerations.

[0335] As other optional optimizing structures and/or components are utilized, their affect on the characteristic impedance of the energy transfer module should be taken into account in the match along with their own original criteria.

[0336] 2.4 Frequency Up-Conversion

[0337] The present invention is directed to systems and methods of frequency up-conversion, and applications of same.

[0338] An example frequency up-conversion system 1000 is illustrated in FIG. 10. The frequency up-conversion system 1000 is now described.

[0339] An input signal 1002 (designated as “Control Signal” in FIG. 10) is accepted by a switch module 1004. For purposes of example only, assume that the input signal 1002 is a FM input signal 1306, an example of which is shown in FIG. 13C. FM input signal 1306 may have been generated by modulating information signal 1302 onto oscillating signal 1304 (FIGS. 13A and 13B). It should be understood that the invention is not limited to this embodiment. The information signal 1302 can be analog, digital, or any combination thereof, and any modulation scheme can be used.

[0340] The output of switch module 1004 is a harmonically rich signal 1006, shown for example in FIG. 13D as a harmonically rich signal 1308. The harmonically rich signal 1308 has a continuous and periodic waveform.

[0341] FIG. 13E is an expanded view of two sections of harmonically rich signal 1308, section 1310 and section 1312. The harmonically rich signal 1308 may be a rectangular wave, such as a square wave or a pulse (although, the invention is not limited to this embodiment). For ease of discussion, the term “rectangular waveform” is used to refer to waveforms that are substantially rectangular. In a similar manner, the term “square wave” refers to those waveforms that are substantially square and it is not the intent of the present invention that a perfect square wave be generated or needed.

[0342] Harmonically rich signal 1308 is comprised of a plurality of sinusoidal waves whose frequencies are integer multiples of the fundamental frequency of the waveform of the harmonically rich signal 1308. These sinusoidal waves are referred to as the harmonics of the underlying waveform, and the fundamental frequency is referred to as the first harmonic. FIG. 13F and FIG. 13G show separately the sinusoidal components making up the first, third, and fifth harmonics of section 1310 and section 1312. (Note that in theory there may be an infinite number of harmonics; in this example, because harmonically rich signal 1308 is shown as a square wave, there are only odd harmonics). Three harmonics are shown simultaneously (but not summed) in FIG. 13H.

[0343] The relative amplitudes of the harmonics are generally a function of the relative widths of the pulses of harmonically rich signal 1006 and the period of the fundamental frequency, and can be determined by doing a Fourier analysis of harmonically rich signal 1006. According to an embodiment of the invention, the input signal 1306 may be shaped to ensure that the amplitude of the desired harmonic is sufficient for its intended use (e.g., transmission).

[0344] An optional filter 1008 filters out any undesired frequencies (harmonics), and outputs an electromagnetic (EM) signal at the desired harmonic frequency or frequencies as an output signal 1010, shown for example as a filtered output signal 1314 in FIG. 13I.

[0345] FIG. 11 illustrates an example universal frequency up-conversion (UFU) module 1101. The UFU module 1101 includes an example switch module 1004, which comprises a bias signal 1102, a resistor or impedance 1104, a universal frequency translator (UFT) 1150, and a ground 1108. The UFT 1150 includes a switch 1106. The input signal 1002 (designated as “Control Signal” in FIG. 11) controls the switch 1106 in the UFT 1150, and causes it to close and open. Harmonically rich signal 1006 is generated at a node 1105 located between the resistor or impedance 1104 and the switch 1106.

[0346] Also in FIG. 11, it can be seen that an example optional filter 1008 is comprised of a capacitor 1110 and an inductor 1112 shunted to a ground 1114. The filter is designed to filter out the undesired harmonics of harmonically rich signal 1006.

[0347] The invention is not limited to the UFU embodiment shown in FIG. 11.

[0348] For example, in an alternate embodiment shown in FIG. 12, an unshaped input signal 1201 is routed to a pulse shaping module 1202. The pulse shaping module 1202 modifies the unshaped input signal 1201 to generate a (modified) input signal 1002 (designated as the “Control Signal” in FIG. 12). The input signal 1002 is routed to the switch module 1004, which operates in the manner described above. Also, the filter 1008 of FIG. 12 operates in the manner described above.

[0349] The purpose of the pulse shaping module 1202 is to define the pulse width of the input signal 1002. Recall that the input signal 1002 controls the opening and closing of the switch 1106 in switch module 1004. During such operation, the pulse width of the input signal 1002 establishes the pulse width of the harmonically rich signal 1006. As stated above, the relative amplitudes of the harmonics of the harmonically rich signal 1006 are a function of at least the pulse width of the harmonically rich signal 1006. As such, the pulse width of the input signal 1002 contributes to setting the relative amplitudes of the harmonics of harmonically rich signal 1006.

[0350] Further details of up-conversion as described in this section are presented in U.S. Pat. No. 6,091,940, entitled “Method and System for Frequency Up-Conversion,” incorporated herein by reference in its entirety.

[0351] 2.5 Enhanced Signal Reception

[0352] The present invention is directed to systems and methods of enhanced signal reception (ESR), and applications of same, which are described in the above-referenced U.S. Pat. No. 6,061,555, entitled “Method and System for Ensuring Reception of a Communications Signal,” incorporated herein by reference in its entirety.

[0353] 2.6 Unified Down-Conversion and Filtering

[0354] The present invention is directed to systems and methods of unified down-conversion and filtering (UDF), and applications of same.

[0355] In particular, the present invention includes a unified down-converting and filtering (UDF) module that performs frequency selectivity and frequency translation in a unified (i.e., integrated) manner. By operating in this manner, the invention achieves high frequency selectivity prior to frequency translation (the invention is not limited to this embodiment). The invention achieves high frequency selectivity at substantially any frequency, including but not limited to RF (radio frequency) and greater frequencies. It should be understood that the invention is not limited to this example of RF and greater frequencies. The invention is intended, adapted, and capable of working with lower than radio frequencies.

[0356] FIG. 14 is a conceptual block diagram of a UDF module 1402 according to an embodiment of the present invention. The UDF module 1402 performs at least frequency translation and frequency selectivity.

[0357] The effect achieved by the UDF module 1402 is to perform the frequency selectivity operation prior to the performance of the frequency translation operation. Thus, the UDF module 1402 effectively performs input filtering.

[0358] According to embodiments of the present invention, such input filtering involves a relatively narrow bandwidth. For example, such input filtering may represent channel select filtering, where the filter bandwidth may be, for example, 50 KHz to 150 KHz. It should be understood, however, that the invention is not limited to these frequencies. The invention is intended, adapted, and capable of achieving filter bandwidths of less than and greater than these values.

[0359] In embodiments of the invention, input signals 1404 received by the UDF module 1402 are at radio frequencies. The UDF module 1402 effectively operates to input filter these RF input signals 1404. Specifically, in these embodiments, the UDF module 1402 effectively performs input, channel select filtering of the RF input signal 1404. Accordingly, the invention achieves high selectivity at high frequencies.

[0360] The UDF module 1402 effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof.

[0361] Conceptually, the UDF module 1402 includes a frequency translator 1408. The frequency translator 1408 conceptually represents that portion of the UDF module 1402 that performs frequency translation (down conversion).

[0362] The UDF module 1402 also conceptually includes an apparent input filter 1406 (also sometimes called an input filtering emulator). Conceptually, the apparent input filter 1406 represents that portion of the UDF module 1402 that performs input filtering.

[0363] In practice, the input filtering operation performed by the UDF module 1402 is integrated with the frequency translation operation. The input filtering operation can be viewed as being performed concurrently with the frequency translation operation. This is a reason why the input filter 1406 is herein referred to as an “apparent” input filter 1406.

[0364] The UDF module 1402 of the present invention includes a number of advantages. For example, high selectivity at high frequencies is realizable using the UDF module 1402. This feature of the invention is evident by the high Q factors that are attainable. For example, and without limitation, the UDF module 1402 can be designed with a filter center frequency f_con the order of 900 MHZ, and a filter bandwidth on the order of 50 KHz. This represents a Q of 18,000 (Q is equal to the center frequency divided by the bandwidth).

[0365] It should be understood that the invention is not limited to filters with high Q factors. The filters contemplated by the present invention may have lesser or greater Qs, depending on the application, design, and/or implementation. Also, the scope of the invention includes filters where Q factor as discussed herein is not applicable.

[0366] The invention exhibits additional advantages. For example, the filtering center frequency f_cof the UDF module 1402 can be electrically adjusted, either statically or dynamically.

[0367] Also, the UDF module 1402 can be designed to amplify input signals.

[0368] Further, the UDF module 1402 can be implemented without large resistors, capacitors, or inductors. Also, the UDF module 1402 does not require that tight tolerances be maintained on the values of its individual components, i.e., its resistors, capacitors, inductors, etc. As a result, the architecture of the UDF module 1402 is friendly to integrated circuit design techniques and processes.

[0369] The features and advantages exhibited by the UDF module 1402 are achieved at least in part by adopting a new technological paradigm with respect to frequency selectivity and translation. Specifically, according to the present invention, the UDF module 1402 performs the frequency selectivity operation and the frequency translation operation as a single, unified (integrated) operation. According to the invention, operations relating to frequency translation also contribute to the performance of frequency selectivity, and vice versa.

[0370] According to embodiments of the present invention, the UDF module generates an output signal from an input signal using samples/instances of the input signal and/or samples/instances of the output signal.

[0371] More particularly, first, the input signal is under-sampled. This input sample includes information (such as amplitude, phase, etc.) representative of the input signal existing at the time the sample was taken.

[0372] As described further below, the effect of repetitively performing this step is to translate the frequency (that is, down-convert) of the input signal to a desired lower frequency, such as an intermediate frequency (IF) or baseband.

[0373] Next, the input sample is held (that is, delayed).

[0374] Then, one or more delayed input samples (some of which may have been scaled) are combined with one or more delayed instances of the output signal (some of which may have been scaled) to generate a current instance of the output signal.

[0375] Thus, according to a preferred embodiment of the invention, the output signal is generated from prior samples/instances of the input signal and/or the output signal. (It is noted that, in some embodiments of the invention, current samples/instances of the input signal and/or the output signal may be used to generate current instances of the output signal.). By operating in this manner, the UDF module 1402 preferably performs input filtering and frequency down-conversion in a unified manner.

[0376] Further details of unified down-conversion and filtering as described in this section are presented in U.S. Pat. No. 6,049,706, entitled “Integrated Frequency Translation And Selectivity,” filed Oct. 21, 1998, and incorporated herein by reference in its entirety.

[0377] 3. Example Embodiments of the Invention

[0378] As noted above, the UFT module of the present invention is a very powerful and flexible device. Its flexibility is illustrated, in part, by the wide range of applications and combinations in which it can be used. Its power is illustrated, in part, by the usefulness and performance of such applications and combinations.

[0379] Such applications and combinations include, for example and without limitation, applications/combinations comprising and/or involving one or more of: (1) frequency translation; (2) frequency down-conversion; (3) frequency up-conversion; (4) receiving; (5) transmitting; (6) filtering; and/or (7) signal transmission and reception in environments containing potentially jamming signals. Example receiver and transmitter embodiments implemented using the UFT module of the present invention are set forth below.

[0380] 3.1 Receiver Embodiments

[0381] In embodiments, a receiver according to the invention includes an aliasing module for down-conversion that uses a universal frequency translation (UFT) module to down-convert an EM input signal. For example, in embodiments, the receiver includes the aliasing module 300 described above, in reference to FIG. 3A or FIG. 3G. As described in more detail above, the aliasing module 300 may be used to down-convert an EM input signal to an intermediate frequency (IF) signal or a demodulated baseband signal.

[0382] In alternate embodiments, the receiver may include the energy transfer system 401, including energy transfer module 404, described above, in reference to FIG. 4. As described in more detail above, the energy transfer system 401 may be used to down-convert an EM signal to an intermediate frequency (IF) signal or a demodulated baseband signal. As also described above, the energy transfer system 401 may include an optional energy transfer signal module 408, which can perform any of a variety of functions or combinations of functions including, but not limited to, generating the energy transfer signal 406 of various aperture widths.

[0383] In further embodiments of the present invention, the receiver may include the impedance matching circuits and/or techniques described in herein for optimizing the energy transfer system of the receiver.

[0384] 3.3.1. In-Phase/Quadrature-Phase (I/Q) Modulation Mode Receiver Embodiments

[0385] FIG. 15 illustrates an exemplary I/Q modulation mode embodiment of a receiver 1502, according to an embodiment of the present invention. This I/Q modulation mode embodiment is described herein for purposes of illustration, and not limitation. Alternate I/Q modulation mode embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein), as well as embodiments of other modulation modes, will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

[0386] Receiver 1502 comprises an I/Q modulation mode receiver 1738, a first optional amplifier 1516, a first optional filter 1518, a second optional amplifier 1520, and a second optional filter 1522.

[0387] I/Q modulation mode receiver 1538 comprises an oscillator 1506, a first UFD module 1508, a second UFD module 1510, a first UFT module 1512, a second UFT module 1514, and a phase shifter 1524.

[0388] Oscillator 1506 provides an oscillating signal used by both first UFD module 1508 and second UFD module 1510 via the phase shifter 1524. Oscillator 1506 generates an “I” oscillating signal 1526.

[0389] “I” oscillating signal 1526 is input to first UFD module 1508. First UFD module 1508 comprises at least one UFT module 1512. First UFD module 1508 frequency down-converts and demodulates received signal 1504 to down-converted “I” signal 1530 according to “I” oscillating signal 1526.

[0390] Phase shifter 1524 receives “I” oscillating signal 1526, and outputs “Q” oscillating signal 1528, which is a replica of “I” oscillating signal 1526 shifted preferably by 90 degrees.

[0391] Second UFD module 1510 inputs “Q” oscillating signal 1528. Second UFD module 1510 comprises at least one UFT module 1514. Second UFD module 1510 frequency down-converts and demodulates received signal 1504 to down-converted “Q” signal 1532 according to “Q” oscillating signal 1528.

[0392] Down-converted “I” signal 1530 is optionally amplified by first optional amplifier 1516 and optionally filtered by first optional filter 1518, and a first information output signal 1534 is output.

[0393] Down-converted “Q” signal 1532 is optionally amplified by second optional amplifier 1520 and optionally filtered by second optional filter 1522, and a second information output signal 1536 is output.

[0394] In the embodiment depicted in FIG. 15, first information output signal 1534 and second information output signal 1536 comprise a down-converted baseband signal. In embodiments, first information output signal 1534 and second information output signal 1536 are individually received and processed by related system components. Alternatively, first information output signal 1534 and second information output signal 1536 are recombined into a single signal before being received and processed by related system components.

[0395] Alternate configurations for I/Q modulation mode receiver 1538 will be apparent to persons skilled in the relevant art(s) from the teachings herein. For instance, an alternate embodiment exists wherein phase shifter 1524 is coupled between received signal 1504 and UFD module 1510, instead of the configuration described above. This and other such I/Q modulation mode receiver embodiments will be apparent to persons skilled in the relevant art(s) based upon the teachings herein, and are within the scope of the present invention.

[0396] 3.1.2. Other Receiver Embodiments

[0397] The receiver embodiments described above are provided for purposes of illustration. These embodiments are not intended to limit the invention. Alternate embodiments, differing slightly or substantially from those described herein, will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternate embodiments include, but are not limited to, down-converting different combinations of modulation techniques in an “I/Q” mode. Other embodiments include those shown in the documents referenced above, including but not limited to U.S. patent application Ser. Nos. 09/525,615 and 09/550,644. Such alternate embodiments fall within the scope and spirit of the present invention.

[0398] For example, other receiver embodiments may down-convert signals that have been modulated with other modulation techniques. These would be apparent to one skilled in the relevant art(s) based on the teachings disclosed herein, and include, but are not limited to, amplitude modulation (AM), frequency modulation (FM), pulse width modulation, quadrature amplitude modulation (QAM), quadrature phase-shift keying (QPSK), time division multiple access (TDMA), frequency division multiple access (FDMA), code division multiple access (CDMA), down-converting a signal with two forms of modulation embedding thereon, and combinations thereof.

[0399] 3.2. Transmitter Embodiments

[0400] The following discussion describes frequency up-converting signals transmitted according to the present invention, using a Universal Frequency Up-conversion Module. Frequency up-conversion of an EM signal is described above, and is more fully described in U.S. Pat. No. 6,091,940 entitled “Method and System for Frequency Up-Conversion,” filed Oct. 21, 1998 and issued Jul. 18, 2000, the full disclosure of which is incorporated herein by reference in its entirety, as well as in the other documents referenced above (see, for example, U.S. patent application Ser. No. 09/525,615).

[0401] Exemplary embodiments of a transmitter according to the invention are described below. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

[0402] In embodiments, the transmitter includes a universal frequency up-conversion (UFU) module for frequency up-converting an input signal. For example, in embodiments, the system transmitter includes the UFU module 1000, the UFU module 1101, or the UFU module 1290 as described, above, in reference to FIGS. 10, 11 and 12, respectively. In further embodiments, the UFU module is used to both modulate and up-convert an input signal.

[0403] 3.2.1. In-Phase/Quadrature-Phase (I/Q) Modulation Mode Transmitter Embodiments

[0404] In FIG. 16, an I/Q modulation mode transmitter embodiment is presented. In this embodiment, two information signals are accepted. An in-phase signal (“I”) is modulated such that its phase varies as a function of one of the information signals, and a quadrature-phase signal (“Q”) is modulated such that its phase varies as a function of the other information signal. The two modulated signals are combined to form an “I/Q” modulated signal and transmitted. In this manner, for instance, two separate information signals could be transmitted in a single signal simultaneously. Other uses for this type of modulation would be apparent to persons skilled in the relevant art(s).

[0405] FIG. 16 illustrates an exemplary block diagram of a transmitter 1602 in an I/Q modulation mode. In FIG. 16, a baseband signal comprises two signals, first information signal 1612 and second information signal 1614. Transmitter 1602 comprises an I/Q transmitter 1604 and an optional amplifier 1606. I/Q transmitter 1604 comprises at least one UFT module 1610. I/Q transmitter 1604 provides I/Q modulation to first information signal 1612 and second information signal 1614, outputting I/Q output signal 1616. Optional amplifier 1606 optionally amplifies I/Q output signal 1616, outputting up-converted signal 1618.

[0406] FIG. 17 illustrates a more detailed circuit block diagram for I/Q transmitter 1604. I/Q transmitter 1604 is described herein for purposes of illustration, and not limitation. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.

[0407] I/Q transmitter 1604 comprises a first UFU module 1702, a second UFU module 1704, an oscillator 1706, a phase shifter 1708, a summer 1710, a first UFT module 1712, a second UFT module 1714, a first phase modulator 1728, and a second phase modulator 1730.

[0408] Oscillator 1706 generates an “I”-oscillating signal 1716.

[0409] A first information signal 1612 is input to first phase modulator 1728. The “I”-oscillating signal 1716 is modulated by first information signal 1612 in the first phase modulator 1728, thereby producing an “I”-modulated signal 1720.

[0410] First UFU module 1702 inputs “I”-modulated signal 1720, and generates a harmonically rich “I” signal 1724 with a continuous and periodic wave form.

[0411] The phase of “I”-oscillating signal 1716 is shifted by phase shifter 1708 to create “Q”-oscillating signal 1718. Phase shifter 1708 preferably shifts the phase of “I”-oscillating signal 1716 by 90 degrees.

[0412] A second information signal 1614 is input to second phase modulator 1730. “Q”-oscillating signal 1718 is modulated by second information signal 1614 in second phase modulator 1730, thereby producing a “Q” modulated signal 1722.

[0413] Second UFU module 1704 inputs “Q” modulated signal 1722, and generates a harmonically rich “Q”0 signal 1726, with a continuous and periodic waveform.

[0414] Harmonically rich “I” signal 1724 and harmonically rich “Q” signal 1726 are preferably rectangular waves, such as square waves or pulses (although the invention is not limited to this embodiment), and are comprised of pluralities of sinusoidal waves whose frequencies are integer multiples of the fundamental frequency of the waveforms. These sinusoidal waves are referred to as the harmonics of the underlying waveforms, and a Fourier analysis will determine the amplitude of each harmonic.

[0415] Harmonically rich “I” signal 1724 and harmonically rich “Q” signal 1726 are combined by summer 1710 to create harmonically rich “I/Q” signal 1734. Summers are well known to persons skilled in the relevant art(s).

[0416] Optional filter 1732 filters out the undesired harmonic frequencies, and outputs an I/Q output signal 1616 at the desired harmonic frequency or frequencies.

[0417] It will be apparent to persons skilled in the relevant art(s) that an alternative embodiment exists wherein the harmonically rich “I” signal 1724 and the harmonically rich “Q” signal 1726 may be filtered before they are summed, and further, another alternative embodiment exists wherein “I”-modulated signal 1720 and “Q”-modulated signal 1722 may be summed to create an “I/Q”-modulated signal before being routed to a switch module. Other “I/Q”-modulation embodiments will be apparent to persons skilled in the relevant art(s) based upon the teachings herein, and are within the scope of the present invention. Further details pertaining to an I/Q modulation mode transmitter are provided in co-pending U.S. Pat. No. 6,091,940 entitled “Method and System for Frequency Up-Conversion,” filed Oct. 21, 1998 and issued Jul. 18, 2000, which is incorporated herein by reference in its entirety.

[0418] 3.3.2. Other Transmitter Embodiments

[0419] The transmitter embodiments described above are provided for purposes of illustration. These embodiments are not intended to limit the invention. Alternate embodiments, differing slightly or substantially from those described herein, will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternate embodiments include, but are not limited to, combinations of modulation techniques in an “I/Q” mode. Such embodiments also include those described in the documents referenced above, such as U.S. patent application Ser. Nos. 09/525,615 and 09/550,644. Such alternate embodiments fall within the scope and spirit of the present invention.

[0420] For example, other transmitter embodiments may utilize other modulation techniques. These would be apparent to one skilled in the relevant art(s) based on the teachings disclosed herein, and include, but are not limited to, amplitude modulation (AM), frequency modulation (FM), pulse width modulation, quadrature amplitude modulation (QAM), quadrature phase-shift keying (QPSK), time division multiple access (TDMA), frequency division multiple access (FDMA), code division multiple access (CDMA), embedding two forms of modulation onto a signal for up-conversion, etc., and combinations thereof.

[0421] 3.3. Transceiver Embodiments

[0422] As discussed above, embodiments of the invention include a transceiver unit, rather than a separate receiver and transmitter. Furthermore, the invention is directed to any of the applications described herein in combination with any of the transceiver embodiments described herein.

[0423] An exemplary embodiment of a transceiver system 1800 of the present invention is illustrated in FIG. 18.

[0424] Transceiver 1802 frequency down-converts first EM signal 1808 received by antenna 1806, and outputs down-converted baseband signal 1812. Transceiver 1802 comprises at least one UFT module 1804 at least for frequency down-conversion.

[0425] Transceiver 1802 inputs baseband signal 1814. Transceiver 1802 frequency up-converts baseband signal 1814. UFT module 1804 provides at least for frequency up-conversion. In alternate embodiments, UFT module 1804 only supports frequency down-conversion, and at least one additional UFT module provides for frequency up-conversion. The up-converted signal is output by transceiver 1802, and transmitted by antenna 1806 as second EM signal 1810.

[0426] First and second EM signals 1808 and 1810 may be of substantially the same frequency, or of different frequencies. First and second EM signals 1808 and 1810 may have been modulated using the same technique, or may have been modulated by different techniques.

[0427] Further example embodiments of receiver/transmitter systems applicable to the present invention may be found in U.S. Pat. No. 6,091,940 entitled “Method and System for Frequency Up-Conversion,” incorporated by reference in its entirety.

[0428] These example embodiments and other alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the example embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the referenced teachings and the teachings contained herein, and are within the scope and spirit of the present invention. The invention is intended and adapted to include such alternate embodiments.

[0429] 3.4. Other Embodiments

[0430] The embodiments described above are provided for purposes of illustration. These embodiments are not intended to limit the invention. Alternate embodiments, differing slightly or substantially from those described herein, will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternate embodiments fall within the scope and spirit of the present invention.

[0431] 4. Mathematical Description of the Present Invention

[0432] As described and illustrated in the preceding sections and sub-sections, embodiments of the present invention down-convert and up-convert electromagnetic signals. In this section, matched filter theory, sampling theory, and frequency domain techniques, as well as other theories and techniques that would be known to persons skilled in the relevant art, are used to further describe the present invention. In particular, the concepts and principles of these theories and techniques are used to describe the present invention's waveform processing.

[0433] As will be apparent to persons skilled in the relevant arts based on the teachings contained herein, the description of the present invention contained herein is a unique and specific application of matched filter theory, sampling theory, and frequency domain techniques. It is not taught or suggested in the present literature. Therefore, a new transform has been developed, based on matched filter theory, sampling theory, and frequency domain techniques, to describe the present invention. This new transform is described below and referred to herein as the UFT transform.

[0434] It is noted that the following describes embodiments of the invention, and it is provided for illustrative purposes. The invention is not limited to the descriptions and embodiments described below. It is also noted that characterizations such as “optimal,” “sub-optimal,” “maximum,” “minimum,” “ideal,” “non-ideal,” and the like, contained herein, denote relative relationships.

[0435] 4.1 Overview

[0436] Embodiments of the present invention down-convert an electromagnetic signal by repeatedly performing a matched filtering or correlating operation on a received carrier signal. Embodiments of the invention operate on or near approximate half cycles (e.g., ½, 1½, 2½, etc.) of the received signal. The results of each matched filtering/correlating process are accumulated, for example using a capacitive storage device, and used to form a down-converted version of the electromagnetic signal. In accordance with embodiments of the invention, the matched filtering/correlating process can be performed at a sub-harmonic or fundamental rate.

[0437] Operating on an electromagnetic signal with a matched filtering/correlating process or processor produces enhanced (and in some cases the best possible) signal-to-noise ration (SNR) for the processed waveform. A matched filtering/correlating process also preserves the energy of the electromagnetic signal and transfers it through the processor.

[0438] Since it is not always practical to design a matched filtering/correlating processor with passive networks, the sub-sections that follow also describe how to implement the present invention using a finite time integrating operation and an RC processing operation. These embodiments of the present invention are very practical and can be implemented using existing technologies, for example but not limited to CMOS technology.

[0439] 4.2. High Level Description of a Matched Filtering/Correlating Characterization/Embodiment of the Invention

[0440] In order to understand how embodiments of the present invention operate, it is useful to keep in mind the fact that such embodiments do not operate by trying to emulate an ideal impulse sampler. Rather, the present invention operates by accumulating the energy of a carrier signal and using the accumulated energy to produce the same or substantially the same result that would be obtained by an ideal impulse sampler, if such a device could be built. Stated more simply, embodiments of the present invention recursively determine a voltage or current value for approximate half cycles (e.g., ½, 1½, 2½, etc.) of a carrier signal, typically at a sub-harmonic rate, and use the determined voltage or current values to form a down-converted version of an electromagnetic signal. The quality of the down-converted electromagnetic signal is a function of how efficiently the various embodiments of the present invention are able to accumulate the energy of the approximate half cycles of the carrier signal.

[0441] Ideally, some embodiments of the present invention accumulate all of the available energy contained in each approximate half cycle of the carrier signal operated upon. This embodiment is generally referred to herein as a matched filtering/correlating process or processor. As described in detail below, a matched filtering/correlating processor is able to transfer substantially all of the energy contained in a half cycle of the carrier signal through the processor for use in determining, for example, a peak or an average voltage value of the carrier signal. This embodiment of the present invention produces enhanced (and in some cases the best possible) signal-to-noise ration (SNR), as described in the sub-sections below.

[0442] FIG. 19 illustrates an example method 1900 for down-converting an electromagnetic signal using a matched filtering/correlating operation. Method 1900 starts at step 1910.

[0443] In step 1910, a matched filtering/correlating operation is performed on a portion of a carrier signal. For example, a match filtering/correlating operation can be performed on a 900 MHz RF signal, which typically comprises a 900 MHz sinusoid having noise signals and information signals superimposed on it. Many different types of signals can be operated upon in step 1910, however, and the invention is not limited to operating on a 900 MHz RF signal. In embodiments, Method 1900 operates on approximate half cycles of the carrier signal.

[0444] In an embodiment of the invention, step 1910 comprises the step of convolving an approximate half cycle of the carrier signal with a representation of itself in order to efficiently acquire the energy of the approximate half cycle of the carrier signal. As described elsewhere herein, other embodiments use other means for efficiently acquiring the energy of the approximate half cycle of the carrier signal. The matched filtering/correlating operation can be performed on any approximate half cycle of the carrier signal (although the invention is not limited to this), as described in detail in the sub-sections below.

[0445] In step 1920, the result of the matched filtering/correlating operation in step 1910 is accumulated, preferably in an energy storage device. In an embodiment of the present invention, a capacitive storage devise is used to store a portion of the energy of an approximate half cycle of the carrier signal.

[0446] Steps 1910 and 1920 are repeated for additional half cycles of the carrier signal. In an embodiment of the present invention, steps 1910 and 1920 are normally performed at a sub-harmonic rate of the carrier signal, for example at a third sub-harmonic rate. In another embodiment, steps 1910 and 1920 are repeated at an offset of a sub-harmonic rate of the carrier signal.

[0447] In step 1930, a down-converted signal is output. In embodiments, the results of steps 1910 and 1920 are passed on to a reconstruction filter or an interpolation filter.

[0448] FIG. 20 illustrates an example gated matched filtering/correlating system 2000, which can be used to implement method 1900. Ideally, in an embodiment, an impulse response of matched filtering/correlating system 2000 is identical to the modulated carrier signal, S_i(t), to be processed. As can be seen in FIG. 20, system 2000 comprises a multiplying module 2002, a switching module 2004, and an integrating module 2006.

[0449] System 2000 can be thought of as a convolution processor. System 2000 multiplies the modulated carrier signal, S_i(t), by a representation of itself, S_i(t-τ), using multiplication model 2002. The output of multiplication module 2002 is then gated by switching module 2004 to integrating module 2006. As .can be seen in FIG. 20, switching module 2004 is controlled by a windowing function, u(t)−u(t-T_A). The length of the windowing function aperture is T_A, which is in an embodiment equal to an approximate half cycle of the carrier signal. Switching module 2004 in an embodiment ensures that approximate half cycles of the carrier signal are normally operated upon at a sub-harmonic rate. In an embodiment shown in FIG. 72, preprocessing is used to select a portion of the carrier signal to be operated upon in accordance with the present invention. In an embodiment of system 2000, the received carrier signal is operated on at an off-set of a sub-harmonic rate of the carrier signal. Integration module 2006 integrates the gated output of multiplication module 2002 and passes on its result, S₀(t). This embodiment of the present invention is described in more detail in subsequent sub-sections.

[0450] As will be apparent to persons skilled in the relevant arts given the discussion herein, the present invention is not a traditional realization of a matched filter/correlator.

[0451] 4.3. High Level Description of a Finite Time Integrating Characterization/Embodiment of the Invention

[0452] As described herein, in some embodiments, a matched filter/correlator embodiment according to the present invention provides maximum energy transfer and maximum SNR. A matched filter/correlator embodiment, however, might not always provide an optimum solution for all applications. For example, a matched filter/correlator embodiment might be too expensive or too complicated to implement for some applications. In such instances, other embodiments according to the present invention may provide acceptable results at a substantially lower cost, using less complex circuitry. The invention is directed to those embodiments as well.

[0453] As described herein in subsequent sub-sections, a gated matched filter/correlator processor can be approximated by a processor whose impulse response is a step function having a duration substantially equal to the time interval defined for the waveform, typically a half cycle of the electromagnetic signal, and an integrator. Such an approximation of a gated matched filter/correlator is generally referred to as a finite time integrator. A finite time integrator in accordance with an embodiment of the present invention can be implemented with, for example, a switching device controlled by a train of pulses having apertures substantially equal to the time interval defined for the waveform. The energy transfer and SNR of a finite time integrator implemented in accordance with an embodiment of the present invention is nearly that of a gated matched filter/correlator, but without having to tailor the matched filter/correlator for a particular type of electromagnetic signal. As described in sub-section 6, a finite time integrator embodiment according to the present invention can provide a SNR result that differs from the result of matched filter/correlator embodiment by only 0.91 dB.

[0454] FIG. 21 illustrates an example method 2100 for down-converting an electromagnetic signal using a matched filtering/correlating operation. Method 2100 starts at step 2110.

[0455] In step 2110, a matched filtering/correlating operation is performed on a portion of a carrier signal. For example, a match filtering/correlating operation can be performed on a 900 MHz RF signal, which typically comprises a 900 MHz sinusoid having noise signals and information signals superimposed on it. Many different types of signals can be operated upon in step 2110, however, and the invention is not limited to operating on a 900 MHz RF signal. In embodiments, Method 2100 operates on approximate half cycles of the carrier signal.

[0456] In an embodiment of the invention, step 2110 comprises the step of convolving an approximate half cycle of the carrier signal with a representation of itself in order to efficiently acquire the energy of the approximate half cycle of the carrier signal. As described elsewhere herein, other embodiments use other means for efficiently acquiring the energy of the approximate half cycle of the carrier signal. The matched filtering/correlating operation can be performed on any approximate half cycle of the carrier signal (although the invention is not limited to this), as described in detail in the sub-sections below.

[0457] In step 2120, the result of the matched filtering/correlating operation in step 2110 is accumulated, preferably in an energy storage device. In an embodiment of the present invention, a capacitive storage devise is used to store a portion of the energy of an approximate half cycle of the carrier signal.

[0458] Steps 2110 and 2120 are repeated for additional half cycles of the carrier signal. In one embodiment of the present invention, steps 2110 and 2120 are performed at a sub-harmonic rate of the carrier signal. In another embodiment, steps 2110 and 2120 are repeated at an off-set of a sub-harmonic rate of the carrier signal.

[0459] In step 2130, a down-converted signal is output. In embodiments, the results of steps 2110 and 2120 are passed on to a reconstruction filter or an interpolation filter.

[0460] FIG. 22 illustrates an example finite time integrating system 2200, which can be used to implement method 2100. Finite time integrating system 2200 has an impulse response that is approximately rectangular, as further described in sub-section 4. As can be seen in FIG. 22, system 2200 comprises a switching module 2202 and an integrating module 2204.

[0461] Switching module 2202 is controlled by a windowing function, u(t)−u(t-T_A). The length of the windowing function aperture is T_A, which is equal to an approximate half cycle of the received carrier signal, S_i(t). Switching module 2202 ensures that approximate half cycles of the carrier signal can be operated upon at a sub-harmonic rate. In an embodiment of system 2200, the received carrier signal is operated on at an off-set of a sub-harmonic rate of the carrier signal.

[0462] Integration module 2204 integrates the output of switching module 2202 and passes on its result, S₀(t). This embodiment of the present invention is described in more detail in sub-section 4 below.

[0463] 4.4. High Level Description of an RC Processing Characterization/Embodiment of the Invention

[0464] The prior sub-section describes how a gated matched filter/correlator can be approximated with a finite time integrator. This sub-section describes how the integrator portion of the finite time integrator can be approximated with a resistor/capacitor (RC) processor. This embodiment of the present invention is generally referred to herein as an RC processor, and it can be very inexpensive to implement. Additionally, the RC processor embodiment according to the present invention can be implemented using only passive circuit devices, and it can be implemented, for example, using existing CMOS technology. This RC processor embodiment, shown in FIG. 24, utilizes a very low cost integrator or capacitor as a memory across the aperture or switching module. If the capacitor is suitably chosen for this embodiment, the performance of the RC processor approaches that of the matched filter/correlator embodiments described herein.

[0465] FIG. 23 illustrates an example method 2300 for down-converting an electromagnetic signal using a matched filtering/correlating operation. Method 2300 starts at step 2310.

[0466] In step 2310, a matched filtering/correlating operation is performed on a portion of a carrier signal. For example, a match filtering/correlating operation can be performed on a 900 MHz RF signal, which typically comprises a 900 MHz sinusoid having noise signals and information signals superimposed on it. Many different types of signals can be operated upon in step 2310, however, and the invention is not limited to operating on a 900 MHz RF signal. In embodiments, Method 2300 operates on approximate half cycles of the carrier signal.

[0467] In an embodiment of the invention, step 2310 comprises the step of convolving an approximate half cycle of the carrier signal with a representation of itself in order to efficiently acquire the energy of the approximate half cycle of the carrier signal. As described elsewhere herein, other embodiments use other means for efficiently acquiring the energy of the approximate half cycle of the carrier signal. The matched filtering/correlating operation can be performed on any approximate half cycle of the carrier signal (although the invention is not limited to this), as described in detail in the sub-sections below.

[0468] In step 2320, the result of the matched filtering/correlating operation in step 2310 is accumulated, preferably in an energy storage device. In an embodiment of the present invention, a capacitive storage devise is used to store a portion of the energy of an approximate half cycle of the carrier signal.

[0469] Steps 2310 and 2320 are repeated for additional half cycles of the carrier signal. In an embodiment of the present invention, steps 2310 and 2320 are normally performed at a sub-harmonic rate of the carrier signal, for example at a third sub-harmonic rate. In another embodiment, steps 2310 and 2320 are repeated at an offset of a sub-harmonic rate of the carrier signal.

[0470] In step 2330, a down-converted signal is output. In embodiments, the results of steps 2310 and 2320 are passed on to a reconstruction filter or an interpolation fiter.

[0471] FIG. 24 illustrates an example RC processing system 2400, which can be used to implement method 2300. As can be seen in FIG. 24, system 2400 comprises a source resistance 2402, a switching module 2404, and a capacitance 2406. Source resistance 2402 is a lumped sum resistance.

[0472] Switching module 2404 is controlled by a windowing function, u(t)−u(t-T_A). The length of the windowing function aperture is T_A, which is equal to an approximate half cycle of the received carrier signal, S_i(t). Switching module 2404 ensures that approximate half cycles of the carrier signal are normally processed at a sub-harmonic rate. In an embodiment of system 2400, the received carrier signal is processed on at an off-set of a sub-harmonic rate of the carrier signal.

[0473] Capacitor 2406 integrates the output of switching module 2404 and vaccumulates the energy of the processed portions of the received carrier signal. RC processor 2400 also passes on its result, S₀(t), to subsequent circuitry for further processing. This embodiment of the present invention is described in more detail in subsequent sub-sections.

[0474] It is noted that the implementations of the invention presented above are provided for illustrative purposes. Other implementations will be apparent to persons skilled in the art based on the herein teachings, and the invention is directed to such implementations.

[0475] 4.5. Representation of a Power Signal as a Sum of Energy Signals

[0476] This sub-section describes how a power signal can be represented as a sum of energy signals. The detailed mathematical descriptions in the sub-sections below use both Fourier transform analysis and Fourier series analysis to describe embodiments of the present invention. Fourier transform analysis typically is used to describe energy signals while Fourier series analysis is used to describe power signals. In a strict mathematical sense, Fourier transforms do not exist for power signals. It is occasionally mathematically convenient, however, to analyze certain repeating or periodic power signals using Fourier transform analysis.

[0477] Both Fourier series analysis and Fourier transform analysis can be used to describe periodic waveforms with pulse like structure. For example, consider the ideal impulse sampling train in EQ. (1). $\begin{array}{cc}x\left(t\right)=\sum _{m=-\infty }^{\infty }\delta \left(t-{\mathrm{mT}}_s\right)& \text{EQ. (1)}\end{array}$

[0478] Suppose that this sampling train is convolved (in the time domain) with a particular waveform s(t), which is of finite duration T_A. Hence s(t) is an energy waveform. Then: $\begin{array}{cc}s\left(t\right)*x\left(t\right)=\sum _{m=-\infty }^{\infty }\delta \left(t-{\mathrm{mT}}_s\right)*s\left(t\right)& \text{EQ. (2)}\\ =\sum _{m=-\infty }^{\infty }s\left(t-{\mathrm{mT}}_s\right)& \text{EQ. (3)}\end{array}$

[0479] The above equation is a well known form of the sampler equation for arbitrary pulse shapes which may be of finite time duration rather than impulse-like. The sampler equation possesses a Fourier transform on a term-by-term basis because each separate is an energy waveform.

[0480] Applying the convolution theorem and a term-by-term Fourier transform yields: $\begin{array}{cc}\widetilde{𝒥}\left\{s\left(t\right)*x\left(t\right)\right\}\underset{\_}{\Delta }\widetilde{𝒥}\left\{\sum _{m=-\infty }^{\infty }\right\}\delta \left(t-{\mathrm{mT}}_s\right)s\left(f\right)=\sum _{m=-\infty }^{\infty }{T}_s^{-1}\delta \left(f-\frac{m}{T_s}\right)S\left(\frac{n}{T_s}\right)& \text{EQ. (4)}\end{array}$

[0481] where f_s=T_s⁻¹. In this manner the Fourier transform may be derived for a train of pulses of arbitrary time domain definition provided that each pulse is of finite time duration and each pulse in the train is identical to the next. If the pulses are not deterministic then techniques viable for stochastic signal analysis may be required. It is therefore possible to represent the periodic signal, which is a power signal, by an infinite linear sum of finite duration energy signals. If the power signal is of infinite time duration, an infinite number of energy waveforms are required to create the desired representation.

[0482] FIG. 25 illustrates a pulse train 2502. Each pulse of pulse deterministic train 2502, for example pulse 2504, is an energy signal.

[0483] FIG. 26 illustrates one heuristic method based on superposition for combining pulses to form pulse deterministic train 2502.

[0484] The method of FIG. 26 shows how a power signal can be obtained from a linear piece-wise continuous sum of energy signals.

[0485] 4.5.1. De-Composition of a Sine Wave into an Energy Signal Representation

[0486] The heuristic discussion presented in the previous section can be applied to the piecewise linear reconstruction of a sine wave function or carrier. FIG. 27 illustrates a simple way to view such a construction.

[0487] Using the previously developed equations, the waveform y(t) can be represented by: $\begin{array}{cc}\sin \left({\omega }_{c}t+\phi \right){|}_{t=0}^{\mathrm{mT}}=\sum _{l=0}^{m=\mathrm{even}}\sin \left({\omega }_{c}t+\phi \right)[u\left(t\right)-u\left(t-\frac{T_c}{2}\right)]*\delta \left(t-l·\frac{T_s}{2}\right)+\sum _{k=1}^{m=\mathrm{odd}}\sin \left({\omega }_{c}t+\phi \right)\left[u\left(t-\frac{T_c}{2}\right)-u\left(t-\frac{3T_c}{2}\right)\right]*\delta \left(t-k\frac{T_s}{2}\right)& \text{EQ. (5)}\end{array}$

[0488] and y(t) can be rewritten as: $\begin{array}{cc}y\left(t\right)=\sum _{l=0}^{m,\mathrm{even}}\left[u\left(t-\frac{{\mathrm{lT}}_s}{2}\right)-u\left(t-\frac{{\mathrm{lT}}_s}{2}-\frac{T_c}{2}\right)\right]·\sin \left({\omega }_c\left(t-\frac{{\mathrm{lT}}_s}{2}\right)+\phi \right)+\sum _{k=1}^{m,\mathrm{odd}}\left[u\left(t-{\mathrm{kT}}_s\right)-u\left(t-{\mathrm{kT}}_s\right)\right]·\sin \left({\omega }_c\left(t-{\mathrm{kT}}_s-\frac{T_c}{2}\right)\right)\sin \left({\omega }_c\left(t-{\mathrm{kT}}_s\right)+\phi \right)& \text{EQ. (6)}\end{array}$

[0489] In general, T_sis usually integrally related to T_c. That is, the sampling interval T_sdivided by T_cusually results in an integer, which further reduces the above equation. The unit step functions are employed to carve out the portion of a sine function applicable for positive pulses and negative pulse, respectively. The point is a power signal may be viewed as an infinite linear sum of energy signals.

[0490] 4.5.2. Decomposition of Sine Waveforms

[0491] FIG. 28 illustrates how portions of a carrier signal or sine waveform are selected for processing according to embodiments of the present invention. Embodiments of the present invention operate recursively, at a sub-harmonic rate, on a carrier signal (i.e., sine wave waveform). FIG. 28 shows the case where there is synchronism in phase and frequency between the clock of the present invention and the carrier signal. This sub-section, as well as the previous sub-sections, illustrates the fact that each half-sine segment of a carrier signal can be viewed as an energy signal, and may be partitioned from the carrier or power signal by a gating process.

[0492] 4.6 Matched Filtering/Correlating Characterization/Embodiment

[0493] 4.6.1 Time Domain Description

[0494] Embodiments of the present invention are interpreted as a specific implementation of a matched filter and a restricted Fourier sine or cosine transform. The matched filter of such embodiments is not a traditional realization of a matched filter designed to extract information at the data bandwidth. Rather, the correlation properties of the filter of the embodiments exploit specific attributes of bandpass waveforms to efficiently down convert signals from RF. A controlled aperture specifically designed to the bandpass waveform is used. In addition, the matched filter operation of embodiments of the present invention is applied recursively to the bandpass signal at a rate sub-harmonically related to the carrier frequency. Each matched filtered result or correlation of embodiments of the present invention is retained and accumulated to provide an initial condition for subsequent recursions of the correlator. This accumulation is approximated as a zero order data hold filter.

[0495] An attribute of bandpass waveforms is that they inherently possess time domain structure, which can be compared to sampling processes. For example, FIG. 29 illustrates a double sideband large carrier AM waveform 2902, with a dashed reference 2904 and black sample dots 2906. Each half sine above or below the dashed reference 2904 can represent a finite duration pulse that possesses information impressed on the carrier by the modulation process.

[0496] Sampled systems attempt to extract information in the envelope, at the black sample dots 2906, if possible. The sample times illustrated by the black sample dots 2906 are shown here at optimum sampling times.

[0497] Difficulties arise when the bandpass waveform is at RF. Then sampling is difficult because of sample rate, sample aperture, and aperture uncertainty. When the traditional sampler acquires, the aperture and aperture uncertainty must be minimized such that the number associated with the acquired waveform value possesses great accuracy at a particular instant in time with minimum variance. Sample rate can be reduced by sampling sub-harmonically. However, precisely controlling a minimized aperture makes the process very difficult, if not impossible, at RF.

[0498] In FIG. 29, the area under a half-sine cycle 2908 is illustrated with hatched marks. In accordance with embodiments of the present invention, instead of obtaining a sample of a single waveform voltage value, energy in the hatched area is acquired. By acquiring energy in the hatched area, the effects of aperture uncertainty can be minimized. Moreover, the waveform itself possesses the sampling information between the half sine zero crossings. This is true because the total energy of the hatched area is proportional to the peak of the modulated half sine peak. This is illustrated by EQ. (7), below. All that remains is to extract that latent information. In embodiments, the underlying theory for optimal extractions of the energy is in fact matched filter theory. $\begin{array}{cc}{E}_A={\int }_{-\infty }^{\infty }{S_i\left(t\right)}^{2}dt=2A^2{\int }_0^{\frac{T_A}{2}}{\left(\sin \left(2\pi ft\right)\right)}^{2}dt=\frac{A^2{T}_A}{2}& \text{EQ. (7)}\end{array}$  E_A=A²π/2 for the case of ω_c=1

[0499] f_A=T_A⁻¹=2f_c

[0500] T_c=T_A/2

[0501] T_c=f_c⁻¹=ω_c/2π

[0502] Historically, an optimization figure of merit is signal-to-noise ratio (SNR) at the system output. FIG. 30 illustrates a block diagram of an example optimum processor system 3002, which considers additive white Gaussian noise (AWGN). The general theory described herein can be extended to systems operating in the presence of colored noise as well.

[0503] Although an RF carrier with modulated information is typically a power signal, the analysis which follows considers the power signal to be a piece-wise construct of sequential energy signals where each energy waveform is a half sine pulse (single aperture) or multiple sine pulses (see sub-section 2 above). Hence, theorems related to finite time observations, Fourier transforms, etc., may be applied throughout.

[0504] Analysis begins with the assumption that a filtering process can improve SNR. No other assumptions are necessary except that the system is casual and linear. The analysis determines the optimum processor for SNR enhancement and maximum energy transfer.

[0505] The output of the system is given by the convolution integral illustrated in EQ. (8): $\begin{array}{cc}{S}_0\left(t\right)={\int }_0^{\infty }h\left(\tau \right)S_i\left(t-\tau \right)d\tau & \text{EQ. (8)}\end{array}$

[0506] where h(τ) is the unknown impulse response of the optimum processor.

[0507] The output noise variance is found from EQ. (9): $\begin{array}{cc}{\sigma }_0^2=N_0{\int }_0^{\infty }{h}^2\left(\tau \right)d\tau \left(\mathrm{Single}\mathrm{sided}\mathrm{noise}\mathrm{PSD}\right)& \text{EQ. (9)}\end{array}$

[0508] The signal to noise ratio at time t₀is given by EQ. (10): $\begin{array}{cc}\frac{S_0^2\left(t_0\right)}{{\sigma }_0^2}=\frac{{\left[{\int }_0^{\infty }h\left(\tau \right)S_i\left(t_0-\tau \right)d\tau \right]}^2}{N_0{\int }_0^{\infty }{h}^2\left(\tau \right)d\tau }& \text{EQ. (10)}\end{array}$

[0509] The Schwarz inequality theorem may be used to maximize the above ratio by recognizing, in EQ. (11), that: $\begin{array}{cc}\frac{S_0^2\left(t_0\right)}{{\sigma }_0^2}\le \frac{{\int }_0^{\infty }{h}^2\left(\tau \right){\int }_0^{\infty }{S}_i^2\left(t_0-\tau \right)d\tau }{N_0{\int }_0^{\infty }{h}^2\left(\tau \right)d\tau }& \text{EQ. (11)}\end{array}$

[0510] The maximum SNR occurs for the case of equality in EQ. (11), which yields EQ. (12): $\begin{array}{cc}\left|\frac{S_0^2\left(t_0\right)}{{\sigma }_0^2}\right|\max =\frac{1}{N_0}{\int }_0^{\infty }{S}_i^2\left(t_0-\tau \right)d\tau & \text{EQ. (12)}\end{array}$

[0511] In general therefore:

[0512] h(τ)=kS_i(t₀−τ)u(τ)  EQ. (13)

[0513] where u(τ) is added as a statement of causality and k is an arbitrary gain constant. Since, in general, the original waveform S_i(t) can be considered as an energy signal (single half sine for the present case), it is important to add the consideration of t₀, a specific observation time. That is, an impulse response for an optimum processor may not be optimal for all time. This is due to the fact that an impulse response for realizable systems operating on energy signals will typically die out over time. Hence, the signal at t₀is said to possess the maximum SNR.

[0514] This can be verified by maximizing EQ. (12) in general. $\begin{array}{cc}\left(\frac{d}{dt}\right)\frac{S_0^2\left(t\right)}{{\sigma }_0^2}=0& \text{EQ. (14)}\end{array}$

[0515] It is of some interest to rewrite EQ. (12) by a change of variable, substituting t=t₀−τ. This yields: $\begin{array}{cc}k{\int }_0^{\infty }{S}_i^2\left(t_0-\tau \right)d\tau =k{\int }_{-\infty }^{t_0}{S}_i^2\left(t\right)dt& \text{EQ. (15)}\end{array}$

[0516] This is the energy of the waveform up to time t₀. After t₀, the energy falls off again due to the finite impulse response nature of the processor. EQ. (15) is of great importance because it reveals an often useful form of a matched filter known as a correlator. That is, the matched filter may be implemented by multiplying the subject waveform by itself over the time interval defined for the waveform, and then integrated. In this realization the maximum output occurs when the waveform and its optimal processor aperture are exactly overlapped for t₀=T_a. It should also be evident from the matched filter equivalency stated in EQ. (15) that the maximum SNR solution also preserves the maximum energy transfer of the desired waveform through the processor. This may be proven using the Parseval and/or Rayliegh energy theorems. EQ. (15) relates directly to Parseval's theorem.

[0517] 4.6.2 Frequency Domain Description

[0518] The previous sub-section derived an optimal processor from the time domain point-of-view according to embodiments of the invention. In an embodiment, the present invention is defined to correlate with a finite time duration half-sine pulse (T_Awide), which is a portion of the carrier signal. The aperture portion of this correlation is represented herein. Fourier transforms may be applied to obtain a frequency domain representation for h(t). This result is shown below.

[0519] H(f)=kS_i*(f)e^−j2πft  EQ. (16)

[0520] Letting jω=j2πf and t₀=T_A, we can write the following EQ. (17) for FIGS. 31 and 32. $\begin{array}{cc}H\left(j\omega \right)=\frac{2}{T_A}{e}^{-j\omega T_A/2}\sin \frac{\left(\omega T_A/2\right)}{\omega T_A/2}H\left(j\omega \right)=\frac{2}{T_A}{e}^{-\mathrm{j\omega }{T}_A/2}\sin \frac{\left(\omega T_A/2\right)}{\omega T_A/2}& \text{EQ. (17)}\end{array}$

[0521] The frequency domain representation in FIG. 31 represents the response of an optimum processor according to embodiments. FIG. 32 illustrates responses of processors that use parameters different than T_A. For t₀<<T_A, the frequency domain response possesses too wide a bandwidth which captures too little of the main lobe of desired energy with respect to out of band noise power. Conversely, when t₀>>T_A, the energy transfer from the signal's main lobe is very inefficient. Therefore, proper selection of T_Ais key for implementation efficiency.

[0522] Another simple but useful observation is gleaned from EQ. (15) and Rayleigh's Energy Theorem for Fourier transforms, as illustrated by EQ. (18). $\begin{array}{cc}E={\int }_{-\infty }^{\infty }{\left|S_1\left(t\right)\right|}^{2}dt={\int }_{-\infty }^{\infty }{\left|H\left(f\right)\right|}^{2}df& \text{EQ. (18)}\end{array}$

[0523] EQ. (18) verifies that the transform of the optimal filter of various embodiments should substantially match the transform of the specific pulse, which is being processed, for efficient energy transfer.

[0524] FIG. 33 illustrates the slight differences between the transform of an ideal impulse response (half sine) (Plot 3302) and a rectangular sample aperture (Plot 3304) according to an embodiment of the invention. Even though they are not perfectly matched, the correlation is quite good. Plot 3302 is a plot of the normalized Fourier transform for an ideal half sine impulse response. Plot 3304 is a plot of the normalized Fourier transform for a rectangular sampling aperture (finite time integrator) according to the invention. In circuit embodiments of the invention, finite rise and fall times shape the aperture to quasi-Gaussian. Plot 3306, a plot of the normalized Fourier transform for a CMOS sampling aperture (with natural process shaping) according to the invention, illustrates a pulse from a CMOS circuit embodiment of the invention designed specifically to the T_A=1 criteria for the carrier half sine. As can be seen in FIG. 33, its correlation is excellent. Channel resistances can increase non-linearity for the shaped aperture in CMOS, however, so that only part of the maximum possible shaping benefit is realized.

[0525] 4.7. Finite Time Integrating Characterization/Embodiment

[0526] It is not always practical to design the matched filter with passive networks. Sometimes the waveform correlation of S_i(t) is also cumbersome to generate exactly. However, a single aperture realization of embodiments of the present invention is practical, even in CMOS, with certain concessions.

[0527] Consider FIGS. 34 and 35, which illustrate an optimum single aperture realization of embodiments of the present invention using sub harmonic sampling (3rd harmonic) and a processor 3510 according to such embodiments. Ideally over the aperture of interest, T_A, a half sine impulse response or waveform is used to operate on the original gated S_i(t). Suppose for ease of implementation, however, that a rectangular impulse response is used, as illustrated by FIGS. 36A and 36B. The Fourier transform of this processor still overlaps the Fourier transform for the original pulse S_i(t) with similar nulls, as shown in FIG. 33, when the aperture is implemented using available CMOS technology (hardware). A perfect finite time integrator has a response that has different null locations, but it still has a very desirable SNR. Although the Fourier correlation is not perfect, it is still quite good. Furthermore, it can be implemented using a simple switch that lets the half sine through in order to charge a capacitor, which acquires the total energy of the half sine at t₀≅T_A.

[0528] Applying EQ. (17) for both the matched filter and non-matched filter embodiments yields:

[0529] Optimal Matched Filter Embodiment Result $E_{\mathrm{A0}}={\int }_0^{T_A}{S}_i^2\left(t\right)dt=\frac{A^2{T}_A}{2}$  E_A0=A²π for ω_c=1; and

[0530] Finite Time Integrator Embodiment Result $E_{\mathrm{AS0}}={\left({\int }_0^{T_A}A·S\left(t\right)\right)}^{2}dt={\left(\frac{2T_{A}A}{\pi }\right)}^2$  E_AS0=(2 kA)²for ω_c=1

[0531] It turns out in practice that realizable apertures are not perfectly rectangular and do possess a finite rise and fall time. In particular, they become triangular or nearly sinusoidal for very high frequency implementations. Thus, the finite time integrating processor result tends toward the matched filtering/correlating processor result when the aperture becomes sine-like, if the processor possesses constant impedance across the aperture duration. Even though the matched filter/correlator response produces a lower output value at T_A, it yields a higher SNR by a factor of 0.9 dB, as further illustrated below in sub-section 6.

[0532] 4.8 RC Processing Characterization/Embodiment

[0533] Sometimes a precise matched filter is difficult to construct, particularly if the pulse shape is complex. Often, such complexities are avoided in favor of suitable approximations, which preserve the essential features. The single aperture realization of embodiments of the present invention is usually implemented conceptually as a first order approximation to a matched filter where the pulse shape being matched is a half-sine pulse. As shown in above, in embodiments, the matched filter is applied recursively to a carrier waveform. The time varying matched filter output correlation contains information modulated onto the carrier. If many such matched filter correlation samples are extracted, the original information modulated onto the carrier is recovered.

[0534] A baseband filter, matched or otherwise, may be applied to the recovered information to optimally process the signal at baseband. The present invention should not be confused with this optimal baseband processing. Rather embodiments of the present invention are applied on a time microscopic basis on the order of the time scale of a carrier cycle.

[0535] FIG. 37 illustrates a basic circuit 3702 that can be used to describe an example RC processor according to embodiments of the present invention. Circuit 3702 comprises a switch 3704. The switch 3704 is closed on a T_Abasis in order to sample V_i(t). In the analysis that follows, the transfer function and impulse response are derived for circuit 3702.

[0536] The switch 3704 functions as a sampler, which possesses multiplier attributes. Heviside's operator is used to model the switch function. The operator is multiplied in the impulse response, thus rendering it essential to the matched filtering/correlating process.

[0537] In the analysis that follows, only one aperture event is considered. That is, the impulse response of the circuit is considered to be isolated aperture-to-aperture, except for the initial value inherited from the previous aperture.

[0538] For circuit 3702, shown in FIG. 37: $\begin{array}{cc}{V}_0\left(t\right)=\frac{1}{C}\int i\left(t\right)dt& \text{EQ. (19)}\\ i\left(t\right)=\frac{V_i\left(t\right)\left[u\left(t\right)-u\left(t-T_A\right)\right]-V_0\left(t\right)}{R}& \text{EQ. (20)}\\ V_0\left(t\right)=\int \frac{V_i\left(t\right)\left[u\left(t\right)-\left(t-T_A\right)\right]-V_0\left(t\right)}{\mathrm{RC}}dt& \text{EQ. (21)}\\ V_0\left(t\right)+\int \frac{V_0\left(t\right)}{\mathrm{RC}}dt=\int \frac{V_i\left(t\right)\left[u\left(t\right)-u\left(t-T_A\right)\right]}{\mathrm{RC}}dt& \text{EQ. (22)}\end{array}$

[0539] EQ. (22) represents the integro-differential equation for circuit 3702. The right hand side of EQ. (22) represents the correlation between the input waveform V_i(t) and a rectangular window over the period T_A.

[0540] The Laplace transform of EQ. (22) is: $\begin{array}{cc}\begin{array}{c}\mathrm{initial}\mathrm{condition}\mathrm{initial}\mathrm{condition}\\ //\\ ––\\ \swarrow \swarrow \\ V_0\left(s\right)\left(1+\frac{1}{\mathrm{sRC}}\right)+\frac{v_0\left(0\right)}{\mathrm{sRC}}=V_i\left(s\right)\left(\frac{1-e^{-{\mathrm{sT}}_A}}{s^2\mathrm{RC}}\right)+\frac{V_i\left(0\right)}{\mathrm{sRC}}\end{array}& \mathrm{EQ}.\left(23\right)\end{array}$

[0541] Consider that the initial condition equal to zero, then: $\begin{array}{cc}H\left(s\right)=\frac{V_0\left(s\right)}{V_i\left(s\right)}={\mathrm{RC}}^{-1}·\left(\frac{1-e^{-{\mathrm{sT}}_A}}{s}\right)·\left(\frac{1}{s+{\left(\mathrm{RC}\right)}^{-1}}\right)& \text{EQ. (24)}\\ \therefore h\left(t\right)=\left(\frac{e^{\frac{t}{-\mathrm{RC}}}}{\mathrm{RC}}\right)\left[u\left(t\right)-u\left(t-T_A\right)\right]& \mathrm{EQ}.\left(25\right)\end{array}$

[0542] Suppose that $V_i\left(t\right)=A\sin \left(2\pi \frac{f_A}{2}t+\phi \right),$

[0543] as illustrated in FIG. 38, where f_A=T_A⁻¹and φ is an arbitrary phase shift. (FIG. 38 also shows h(t).) Note in FIG. 38 that h(t) is not ideally a sine pulse. However, the cross correlation of h(t) and V_i(t) can still be quite good if RC is properly selected. This is the optimization, which is required in order to approximate a matched filter result (namely SNR optimization given h(t) and V_i(t)).

[0544] V₀(t)=V_i(t)*h(t)=Asin(πf_At)*h(t); 0≦t≦T_A  EQ. (26)

[0545] $\begin{array}{cc}{V}_0\left(t\right)={\int }_0^{\infty }\sin \left(\pi f_A\left(t-\tau \right)\right)\frac{e^{\frac{-\tau }{RC}}}{RC}d\tau & \mathrm{EQ}.\left(27\right)\end{array}$

[0546] By a change of variables; $\begin{array}{cc}{V}_0\left(t\right)={\int }_{-\infty }^{i}A\sin \left(\pi f_A\tau +\phi \right)·\frac{e^{\frac{-\left(t-\tau \right)}{RC}}}{RC}\left[u\left(t-\tau \right)-u\left(t-\tau -T_A\right)\right]d\tau where{f}_A\underset{\_}{\Delta }2f=T_A^{-1}\therefore V_0\left(t\right)=\frac{A}{1+{\left(\pi f_{A}RC\right)}^2}\left(-\pi f_{A}t+\phi \right)+\sin (\pi f_{A}t+\phi )-A{e}^{\frac{-t}{RC}}(\sin \phi -\frac{{\left(\pi f_{A}RC\right)}^2}{1+{\left(\pi f_{A}RC\right)}^2}·\sin \phi -\frac{\pi f_{A}RC}{1+{\left(\pi f_{A}RC\right)}^2}·\cos \phi )0\le t\le T_A{V}_0\left(t\right)=\left[\frac{1}{1+{\left(RC\pi f_A\right)}^2}\right]\left(\sin \left(\pi f_{A}t\right)-\pi f_{A}RC·\cos \left(\pi f_{A}t\right)+\pi f_{A}RC·e^{\frac{-t}{RC}}\right)0\le t\le T_A,& \mathrm{EQ}.\left(28\right)\end{array}$

[0547] φ=0

[0548] Notice that the differential equation solution provides for carrier phase skew, φ. It is not necessary to calculate the convolution beyond T_Asince the gating function restricts the impulse response length.

[0549] FIG. 39 illustrates the response V₀(t). The output may peak just before T_A(depending on the RC value) because the example RC processor is not a perfect matched filtering/correlating processor, but rather an approximation. FIG. 40 illustrates that the maximum of the function occurs at t≅0.75T_A, for a β=2.6, which can be verified by evaluating: $\begin{array}{cc}\frac{\partial }{\partial t}{V}_0\left(t\right)=0& \mathrm{EQ}.\left(29\right)\end{array}$

[0550] Solving the differential equation for V₀(t) permits an optimization of β=(RC)⁻¹for maximization of V₀.

[0551] FIG. 41 illustrates a spread of values for beta. In embodiments, the peak β occurs at approximately β≅2.6. FIG. 41 illustrates a family of output responses for processors according to embodiments of the present invention having different beta values. In embodiments, the definition used for optimality to obtain β=2.6 is the highest value of signal obtained at the cutoff instant, T_A. Other criteria can be applied, particularly for multiple pulse accumulation and SNR consideration.

[0552] In embodiments, one might be tempted to increase β and cutoff earlier (i.e., arbitrarily reduce T_A). However, this does not necessarily always lead to enhanced SNR, and it reduces charge transfer in the process. It can also create impedance matching concerns, and possibly make it necessary to have a high-speed buffer. That is, reducing T_Aand C is shown below to decrease SNR. Nevertheless, some gain might be achieved by reducing T_Ato 0.75 for β=2.6, if maximum voltage is the goal.

[0553] In embodiments, in order to maximize SNR, consider the following. The power in white noise can be found from: $\begin{array}{cc}{\sigma }^2=N_0{\int }_0^{\infty }{h}^2\left(\lambda \right)d\lambda {\sigma }^2=N_0{\int }_0^{\infty }\left(\frac{e^{\frac{-2\lambda }{R{C}^2}}}{RC}\right)\left(u\left(t\right)-u\left(\lambda -T_A\right)\right)d\lambda \left(\mathrm{Single}\mathrm{sided}\mathrm{noise}\mathrm{PSD}\right)& \mathrm{EQ}.\left(30\right)\\ {\sigma }^2=\frac{\beta N_0\left(1-e^{-2\beta N_0{T}_A}\right)}{2}@T_A& \mathrm{EQ}.\left(31\right)\\ \beta ={\left(RC\right)}^{-1}& \mathrm{EQ}.\left(32\right)\end{array}$

[0554] Notice that σ²is a function of RC.

[0555] The signal power is calculated from: $\begin{array}{cc}{\left(V_0\left(t\right)\right)}^2={\left(\frac{1}{1+{\left({\beta }^{-1}\pi f_A\right)}^2}\right)}^2{\left(\sin \left(\pi f_{A}t\right)-{\beta }^{-1}\pi f_A·\cos \left(\pi f_{A}t\right)+{\beta }^{-1}\pi f_A{e}^{-\beta t}\right)}^2& \mathrm{EQ}.\left(33\right)\end{array}$

[0556] Hence, the SNR at T_Ais given by: $\begin{array}{cc}\frac{{\left(V_0\left(t\right)\right)}^2}{{\sigma }^2}{|}_{t=T_A}=\frac{2}{\beta N_0\left(1-e^{-2\beta N_0{T}_A}\right)}{\left(\frac{1}{1+{\left({\beta }^{-1}\pi f_A\right)}^2}\right)}^2{\left({\beta }^{-1}\pi f_A+{\beta }^{-1}\pi f_A{e}^{-\beta T_A}\right)}^2& \mathrm{EQ}.\left(34\right)\end{array}$

[0557] Maximizing the SNR requires solving: $\begin{array}{cc}\frac{\partial }{\partial \beta }\left(\frac{{V_0\left(t\right)}^2}{{\sigma }^2}\right)=0& \mathrm{EQ}.\left(35\right)\end{array}$

[0558] Solving the SNR_maxnumerically yields β values that are ever decreasing but with a diminishing rate of return.

[0559] As can be seen in FIG. 42, in embodiments, β=2.6 for the maximum voltage response, which corresponds to a normalized SNR relative to an ideal matched filter of 0.431. However, in embodiments, selecting a β of {fraction (1/10)} the β, which optimizes voltage, produces a superior normalized SNR of 0.805 (about 80.5% efficiency) This is a gain in SNR performance of about 2.7 dB.

[0560] In certain embodiments, it turns out that for an ideal matched filter the optimum sampling point corresponding to correlator peak is precisely T_A. However, in embodiments, for the RC processor, the peak output of occurs at approximately 0.75 T_Afor large β (i.e., β=2.6). That is because the impulse response is not perfectly matched to the carrier signal. However, as β is reduced significantly, the RC processor response approaches the efficiency of the finite time integrating processor response in terms of SNR performance. As β is lowered, the optimal SNR point occurs closer to T_A, which simplifies design greatly. Embodiments of the present invention provides excellent energy accumulation over T_Afor low β, particularly when simplicity is valued.

[0561] 4.9 Charge Transfer and Correlation

[0562] The basic equation for charge transfer is: $\begin{array}{cc}\frac{dq}{dt}=C\frac{dv}{dt},\left(\mathrm{assuming}C\mathrm{constant}\mathrm{over}\mathrm{time}\right)q=\mathrm{CV}& \mathrm{EQ}.\left(36\right)\end{array}$

[0563] Similarly the energy u stored by a capacitor can be found from: $\begin{array}{cc}u={\int }_0^q\frac{q_x}{C}d{q}_x=\frac{q^2}{2C}& \mathrm{EQ}.\left(37\right)\end{array}$

[0564] From EQs. (36) and (37): $\begin{array}{cc}u=\frac{C{v}^2}{2}& \mathrm{EQ}.\left(38\right)\end{array}$

[0565] Thus, the charge stored by a capacitor is proportional to the voltage across the capacitor, and the energy stored by the capacitor is proportional to the square of the charge or the voltage. Hence, by transferring charge, voltage and energy are also transferred. If little charge is transferred, little energy is transferred, and a proportionally small voltage results unless C is lowered.

[0566] The law of conversation of charge is an extension of the law of the conservation of energy. EQ. (36) illustrates that if a finite amount of charge must be transferred in an infinitesimally short amount of time then the voltage, and hence voltage squared, tends toward infinity. The situation becomes even more troubling when resistance is added to the equation. Furthermore, $\begin{array}{cc}{V}_c=\frac{1}{C}{\int }_0^{T_A}idt& \mathrm{EQ}.\left(39\right)\end{array}$

[0567] This implies an infinite amount of current must be supplied to create the infinite voltage if T_Ais infinitesimally small. Clearly, such a situation is impractical, especially for a device without gain.

[0568] In most radio systems, the antenna produces a small amount of power available for the first conversion, even with amplification from an LNA. Hence, if a finite voltage and current restriction do apply to the front end of a radio then a conversion device, which is an impulse sampler, must by definition possess infinite gain. This would not be practical for a switch. What is usually approximated in practice is a fast sample time, charging a small capacitor, then holding the value acquired by a hold amplifier, which preserves the voltage from sample to sample.

[0569] The analysis that follows shows that given a finite amount of time for energy transfer through a conversion device, the impulse response of the ideal processor, which transfers energy to a capacitor when the input voltage source is a sinusoidal carrier and possesses a finite source impedance, is represented by embodiments of the present invention. If a significant amount of energy can be transferred in the sampling process then the tolerance on the charging capacitor can be reduced, and the requirement for a hold amplifier is significantly reduced or even eliminated.

[0570] In embodiments, the maximum amount of energy available over a half sine pulse can be found from: $\begin{array}{cc}u={\int }_0^{T_A}{S}_i^2\left(t\right)dt=\frac{A^2{T}_A}{2}\left(A^2\pi /2\mathrm{fo}r{\omega }_c=1\right)& \mathrm{EQ}.\left(40\right)\end{array}$

[0571] This points to a correlation processor or matched filter processor. If energy is of interest then a useful processor, which transfers all of the half sine energy, is revealed in EQ. (39), where T_Ais an aperture equivalent to the half sine pulse. In embodiments, EQ. (40) provides the clue to an optimal processor.

[0572] Consider the following equation sequence. $\begin{array}{cc}{\int }_0^{\infty }h\left(\tau \right)S_i\left(t-\tau \right)d\tau \Rightarrow {\int }_0^{T_A}k{S}_i^2\left(T_A-\tau \right)d\tau \Rightarrow {\int }_{-0}^{T_A}{S}_i^2\left(t\right)dt& \mathrm{EQ}.\left(41\right)\end{array}$

[0573] where h(τ)=S_i(T_A-τ) and t=T_A-τ.

[0574] This is the matched filter equation with the far most right hand side revealing a correlator implementation, which is obtained by a change of variables as indicated. The matched filter proof for h(τ)=S_i(T_A-τ) is provided below. Note that the correlator form of the matched filter is exactly a statement of the desired signal energy. Therefore a matched filter/correlator accomplishes acquisition of all the energy available across a finite duration aperture. Such a matched filter/correlator can be implemented as shown in FIG. 43.

[0575] In embodiments, when optimally configured, the example matched filter/correlator of FIG. 43 operates in synchronism with the half sine pulse S_i(t) over the aperture T_A. Phase skewing and phase roll will occur for clock frequencies, which are imprecise. Such imprecision can be compensated for by a carrier recovery loop, such as a Costas Loop. A Costas Loop can develop the control for the acquisition clock, which also serves as a sub-harmonic carrier. However, phase skew and non-conherency does not invalidate the optimal form of the processor provided that the frequency or phase errors are small, relative to T⁻¹_A. Non-coherent and differentially coherent processors may extract energy from both I and Q with a complex correlation operation followed by a rectifier or phase calculator. It has been shown that phase skew does not alter the optimum SNR processor formulation. The energy which is not transferred to I is transferred to Q and vice versa when phase skew exists. This is an example processor for a finite duration sample window with finite gain sampling function, where energy or charge is the desired output.

[0576] A matched filter/correlator embodiment according to the present invention might be too expensive and complicated to build for some applications. In such cases, however, other processes and processors according to embodiments of the invention can be used. The approximation to the matched filter/correlator embodiment shown in FIG. 44 is just one embodiment that can be used in such instances. The finite time integrator embodiment of FIG. 44 requires only a switch and an integrator. Sub-section 6 below shows that this embodiment of the present invention has only a 0.91 dB difference in SNR compared to the matched filter/correlator embodiment.

[0577] Another very low cost and easy to build embodiment of the present invention is the RC processor. This embodiment, shown in FIG. 45, utilizes a very low cost integrator or capacitor as a memory across the aperture. If C is suitable chosen for this embodiment, its performance approaches that of the matched filter/correlator embodiment, shown in FIG. 43. Notice the inclusion of the source impedance, R, along with the switch and capacitor. This simple embodiment nevertheless can approximate the optimum energy transfer of the matched filter/correlator embodiment if properly designed.

[0578] When maximum charge is transferred, the voltage across the capacitor 4504 in FIG. 45 is maximized over the aperture period for a specific RC combination.

[0579] Using EQs. (36) and (39) yields: $\begin{array}{cc}q=C·\frac{1}{C}{\int }_0^{T_A}{i}_{c}dt& \mathrm{EQ}.\left(42\right)\end{array}$

[0580] If it is accepted that an infinite amplitude impulse with zero time duration is not available or practical, due to physical parameters of capacitors like ESR, inductance and breakdown voltages, as well as currents, then EQ. (42) reveals the following important considerations for embodiments of the invention:

[0581] The transferred charge, q, is influenced by the amount of time available for transferring the charge;

[0582] The transferred charge, q, is proportional to the current available for charging the energy storage device; and

[0583] Maximization of charge, q, is a function of i_c, C, and T_A.

[0584] Therefore, it can be shown that for embodiments: $\begin{array}{cc}{q}_{\max }=C{v}_{\max }={C\left[\frac{1}{C}{\int }_0^{T_A}{i}_{c}dt\right]}_{\max }& \mathrm{EQ}.\left(43\right)\end{array}$

[0585] The impulse response for the RC processing network was found in sub-section 5.2 below to be; $\begin{array}{cc}h\left(t\right)=\frac{e^{\frac{-\tau }{RC}}}{RC}\left[u\left(\tau \right)-u\left(\tau -T_A\right)\right]& \mathrm{EQ}.\left(44\right)\end{array}$

[0586] Suppose that T_Ais constrained to be less than or equal to ½ cycle of the carrier period. Then, for a synchronous forcing function, the voltage across a capacitor is given by EQ. (45). $\begin{array}{cc}{V}_0\left(t\right)={\int }_{-\infty }^t\sin \left(\pi f_A\tau \right)·\frac{e-\frac{\left(t-\tau \right)}{RC}}{RC}d\tau & \mathrm{EQ}.\left(45\right)\end{array}$

[0587] Maximizing the charge, q, requires maximizing EQ. (28) with respect to t and β. $\begin{array}{cc}\frac{{\partial }^2{V}_0\left(t\right)}{\partial t\partial \beta }=0& \mathrm{EQ}.\left(46\right)\end{array}$

[0588] It is easier, however, to set R=1, T_A=1, A=1, f_A=T_A⁻¹and then calculate q=cV₀from the previous equations by recognizing that $q=\frac{{\beta }^{-1}}{R}{V}_0=c{V}_0,$

[0589] which produces a normalized response.

[0590] FIG. 46 illustrates that increasing C is preferred in embodiments of the invention. It can be seen in FIG. 46 that as C increases (i.e., as β decreases) the charge transfer also increases. This is what is to be expected based on the optimum SNR solution. Hence, for embodiments of the present invention, an optimal SNR design results in optimal charge transfer. As C is increased, bandwidth considerations should be taken into account.

[0591] In embodiments, EQ. (40) establishes T_Aas the entire half sine for an optimal processor. However, in embodiments, optimizing jointly for t and β reveals that the RC processor response creates an output across the energy storage capacitor that peaks for t_max≅0.75 T_A, and β_max≅2.6, when the forcing function to the network is a half sine pulse.

[0592] In embodiments, if the capacitor of the RC processor embodiment is replaced by an ideal integrator then t_max→T_A.

[0593] βT_A≅1.95  EQ. (47)

[0594] where β=(RC)⁻¹

[0595] For example, for a 2.45 GHz signal and a source impedance of 50 Ω, EQ. (47) above suggests the use of a capacitor of ≅2 pf. This is the value of capacitor for the aperture selected, which permits the optimum voltage peak for a single pulse accumulation. For practical realization of the present invention, the capacitance calculated by EQ. (47) is a minimum capacitance. SNR is not considered optimized at βT_A≅1.95. As shown earlier, a smaller β yields better SNR and better charge transfer. In embodiments, as discussed below, it turns out that charge can also be optimized if multiple apertures are used for collecting the charge.

[0596] In embodiments, for the ideal matched filter/correlator approximation, βT_Ais constant and equivalent for both consideration of optimum SNR and optimum charge transfer, and charge is accumulated over many apertures for most practical designs. Consider the following example, β=0.25, and T_A=1. Thus βT_A=0.25. At 2.45 GHz, with R=50 Ω, C can be calculated from: $\begin{array}{cc}C\geqq \frac{T_A}{R\left(\mathrm{.25}\right)}\ge 16.3\mathrm{pf}& \mathrm{EQ}.\left(48\right)\end{array}$

[0597] The charge accumulates over several apertures, and SNR is simultaneously optimized melding the best of two features of the present invention. Checking CV for βT_A≅1.95 vs. βT_A=0.25 confirms that charge is optimized for the latter.

[0598] 4.10 Load Resistor Consideration

[0599] The general forms of the differential equation and transfer function, described above, for embodiments of the present invention are the same as for a case involving a load resistor, R_L, applied across capacitor, C. FIG. 47A illustrates an example RC processor embodiment 4702 of the present invention having a load resistance 4704 across a capacitance 4706.

[0600] Consider RC processing embodiment 4702 (without initial conditions).

[0601] EQ. (24) becomes: $\begin{array}{cc}H\left(s\right)=\frac{1-e^{-{\mathrm{sT}}_A}}{s}\left(\frac{1}{\mathrm{sCR}+k}\right)& \text{EQ. (49)}\\ k=\left(\frac{R}{R_L}+1\right)& \text{EQ. (50)}\\ h\left(t\right)=\left(\frac{e^{-\frac{t·k}{\mathrm{RC}}}}{\mathrm{RC}}\right)\left[u\left(t\right)-\left(t-T_A\right)\right]& \text{EQ. (51)}\end{array}$

[0602] It should be clear that R_L4704, and therefore k, accelerate the exponential decay cycle. $\begin{array}{cc}{V}_0\left(t\right)={\int }_{-\infty }^t\sin \left(\pi f_a\tau \right)·\frac{e^{-\frac{k\left(t-\tau \right)}{\mathrm{RC}}}}{\mathrm{RC}}d\tau & \text{EQ. (52)}\\ V_0\left(t\right)=\left(\frac{1}{k^2+{\left(\pi f_A\right)}^2}\right)\left[k·\sin \left(\pi f_{A}t\right)-\pi f_A\mathrm{RC}·\cos \left(\pi f_{A}t\right)+\mathrm{RC}{e}^{-\frac{\mathrm{kt}}{\mathrm{RC}}}\right]0\le t\le T_A& \text{EQ. (53)}\end{array}$

[0603] This result is valid only over the acquisition aperture. After the switch is opened, the final voltage that occurred at the sampling instance t≅T_Abecomes an initial condition for a discharge cycle across R_L4704. The discharge cycle possesses the following response: $\begin{array}{cc}{V}_D=\frac{V_A·e^{-\frac{t}{R_{L}C}}}{R_{L}C}u\left(t-T_A\right)\left(\mathrm{single}\mathrm{event}\mathrm{discharge}\right)& \text{EQ. (54)}\end{array}$