Digital FM Demodulation Apparatus Demodulating Sampled Digital FM Modulated Wave

1. Field of the Invention

The present invention relates to a digital FM demodulation apparatus demodulating FM modulated waves, and particularly to a digital FM demodulation apparatus performing digital sampling at a high frequency.

2. Description of the Background Art

While an FM modulated wave has been demodulated conventionally by an analog FM demodulation apparatus, an FM demodulation apparatus has been developed with a digital circuit which has been made more functional due to advances in semiconductor technology.

A conventional digital FM demodulation apparatus performs digital FM demodulation in an arc tangent system, description of which will hereinafter be described.

An FM modulated wave y(t) is described by:

where .phi.(t) is a carrier phase. The carrier phase .phi.(t) should satisfy the following relation with a demodulated wave Y(t):

The above equation shows change of an instantaneous frequency .omega. of the carrier in the vicinity of .omega..sub.c according to Y(t).

Considering the carrier, as two components A and B orthogonal to each other, the following equation is obtained:

From the equations (2) and (3), the demodulated wave Y(t) is described by the following:

With a hardware structured according to the above equations, a digital FM demodulation apparatus in an arc tangent system can be implemented.

FIG. 7 is a block diagram of a conventional digital FM demodulation apparatus in accordance with the above-described system. As shown in FIG. 7, the digital FM demodulation apparatus includes a sampling circuit 11, a 90.degree. phase splitter 12, an arithmetic circuit 13, and a differentiating circuit 14. 90.degree. phase splitter 12 splits an FM modulated wave y(t) sampled by sampling circuit 11 into a component A with respect to 0.degree. and a component B with respect to 90.degree. to provide the same to arithmetic circuit 13. Arithmetic circuit 13 includes a table ROM (Read Only Memory) in which a value of atan(B/A) to be defined by the components A and B of the FM modulated wave y(t) has been written. Arithmetic circuit 13 reads out the value of atan (B/A) to be defined by the components A and B, i.e. a carrier phase .phi.(t), from the table ROM to provide the same to differentiating circuit 14. Arithmetic circuit 13 does not carry out an operation of atan (B/A), but only reads out a value from the table ROM. Accordingly, the processing requires less time, which will scarcely cause delay. Differentiating circuit 14 differentiates the input carrier phase .phi.(t) to provide a demodulated wave Y(t), and FM demodulation is thus completed.

FIG. 8 is a detailed block diagram showing 90.degree. phase splitter 12 in the digital FM demodulation apparatus. Since the circuit shown in FIG. 8 is a phase circuit employing Hilbert transform constituted of delay, multiplication, and addition and subtraction, various delay circuits, multiplier circuits, and adder-subtractor circuits are required, causing large scale and long delay time of the circuit.

An object of the present invention is to provide a digital FM demodulation apparatus of small circuit scale and short delay time.

The digital FM demodulation apparatus of the present invention includes a sampling unit for sampling an FM modulated wave at predetermined intervals, a frequency specifying unit for specifying a frequency at the time of sampling based on a plurality of the sampled values obtained by the sampling unit, and a demodulated value specifying unit for specifying a demodulated value based on the specified frequency by the frequency specifying unit.

Digital demodulation, therefore, can be carried out with a simple structure in which a simple operation is performed for a plurality of sampled data to provide a demodulated value based on the data. Accordingly, a conventional 90.degree. phase splitter and a conventional differentiating circuit are not required, which enables a smaller circuit scale. In addition, simplicity of each processing enables reduced delay time.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram functionally showing a digital FM demodulation apparatus in accordance with one embodiment of the present invention.

FIG. 2 is a block diagram of the digital FM demodulation apparatus in accordance with one embodiment of the present invention.

FIG. 3 is a graph showing sampling processing of an FM modulated wave.

FIG. 4 is a graph showing the relation between an instantaneous frequency of an FM modulated wave and a luminance signal level.

FIG. 5 is a flow chart showing a correction operation.

FIG. 6 is a diagram showing an address having data stored.

FIG. 7 is a block diagram of a conventional digital FM demodulation apparatus.

FIG. 8 is a block diagram of the 90.degree. phase splitter.

The digital FM demodulation apparatus in accordance with one embodiment of the present invention will hereinafter be described with the drawings.

In FIG. 1, the digital FM demodulation apparatus includes a sampling unit 1, a frequency specifying unit 2, and a demodulated value specifying unit 3. Sampling unit 1 is externally supplied with an FM modulated wave y(t), and samples a value of the FM modulated wave y(t) at each sampling to provide the value to frequency specifying unit 2. Frequency specifying unit 2 calculates an instantaneous frequency of the FM modulated wave y(t) at the time of sampling based on the input sampled values. Demodulated value specifying unit 3 calculates a demodulated value at the instantaneous frequency to. Through these operations digital FM demodulation is performed.

Description will now be made on the case where a video luminance signal FM modulated by an analog VTR is to be demodulated. Specifically, an FM modulated video luminance signal is to be sampled at 28.63 MHz as 10-bit digital data, FM demodulated, and converted into 12-bit luminance signal digital data.

In FIG. 2, the digital FM demodulation apparatus includes a sampling circuit 4, a CPU (Center Processing Unit) 5, and a table ROM 6. An FM modulated video luminance signal is sampled at a sampling frequency of 28.63 MHz by sampling circuit 4, and provided to CPU 5 as 10-bit digital data. CPU 5 performs a prescribed program to calculate an instantaneous frequency at sampling based on the sampled digital data.

Description will now be made on a method of calculating an instantaneous frequency based on sampled values. As shown in FIG. 3, when an FM modulated wave is sampled at a sampling interval T, respective sampled data values Y.sub.t-T, Y.sub.t, and Y.sub.t+T at time t-T, t, and t+T are described as follows:

where A, f, and .theta. are an amplitude, an instantaneous frequency, an initial phase of y.sub.t at the time t, respectively.

From the equations (5) (6), and (6) (7), the following equations are provided, respectively:

Provided that .alpha.=2.pi.ft+.theta., and .beta.=2.pi.fT, the equations (8) and (9) are described as follows:

From the equations (10) and (11), the following equation is provided:

where .beta.=2.pi.fT. An instantaneous frequency f.sub.t at the time t, therefore, is given by:

The instantaneous frequency f.sub.t at the time t can thus be obtained from the sampled value y.sub.t and the preceding and succeeding sampled values y.sub.t-T and y.sub.t+T.

In accordance with the above-described method, CPU 5 performs a prescribed program, stores the sampled values y.sub.t-T, y.sub.t, and y.sub.t+T, and calculates a value (y.sub.t-T +y.sub.t+T)/2. After calculation, CPU 5 provides the calculated value and the sampled value y.sub.t to table ROM 6 to designate an address in table ROM 6.

Table ROM 6 has an address region including the upper ten bits and the lower ten bits, and a data region of 12 bits. The value (y.sub.t-T +y.sub.t+T)/2 provided from CPU 5 corresponds to the upper address, while the value y.sub.t corresponds to the lower address. In the data region corresponding to this address, a demodulated value for the instantaneous frequency f.sub.t obtained by substituting (y.sub.t-T y.sub.t+T)/2 and y.sub.t for the equation (13) is stored.

Description will be now given on how a demodulated value is obtained. In FIG. 4, the instantaneous frequency f is converted into 10-bit data, and the luminance signal level y.sub.t is converted into 12-bit data. The FM modulated wave is set to have the center frequency of 4.8 MHz. The frequency difference of 0.6 MHz corresponds to a luminance signal level of 500, and a luminance signal level of -500 corresponds to a horizontal synchronization level of the luminance signal. The above relation is described by:

Therefore, the luminance signal level Y.sub.t can be obtained by substituting the instantaneous frequency f.sub.t for the equation (14). According to this transform, the luminance signal shown in the left side of FIG. 4 can be provided.

Since luminance signal level data corresponding to data (address) provided from CPU 5 is stored in table ROM 6, the luminance signal level data can be obtained instantaneously with least delay time.

Description will now be made, with reference to the flow chart of FIG. 5, on a method of correcting data where a sampled value does not satisfy prescribed conditions because of noise on an input FM modulated wave or some other reasons which cause disturbances in the input FM modulated wave.

At step S1, CPU 5 reads a prescribed program, and receives a sampled value y.sub.t of an FM modulated wave by sampling circuit 4.

At step S2, CPU 5 determines whether an absolute value of y.sub.t is larger than a prescribed value L. If y.sub.t is small, operation error in subsequent processing will be large. The value L should be, therefore, set to a value so as to make operation error smaller, and not to affect a response speed. When .vertline.y.sub.t .vertline. is larger than the value L, the routine proceeds to step S3, and continues usual processing. When .vertline.y.sub.t .vertline. is smaller than the value L, the routine proceeds to step S7, where CPU 5 provides the luminance signal level y.sub.t-1 precedingly provided.

As is realized from the equation (13), ](y.sub.t-T +y.sub.t+T)/2y.sub.t .vertline. should not be more than one, in other words, .vertline.y.sub.t-T +y.sub.t+T .vertline. should not be more than .vertline.2y.sub.t .vertline.; otherwise, the sampled value might be detected incorrectly because of noise and factors causing disturbance in the FM modulated wave. In such a case, the incorrect data is corrected according to this conditional expression. Specifically, when .vertline.y.sub.t-T +y.sub.t+T .vertline. is larger than .vertline.2y.sub.t .vertline., the data is determined to be incorrect, and the routine proceeds to step S8. At step S8, y.sub.t is provided to the upper address, and (y.sub.t-T +y.sub.t+T)/2 is provided to the lower address, so that respective data values are stored in the address region of table ROM 6, as shown in FIG. 6(b). When .vertline.y.sub.t-T m+y.sub.t+T .vertline. is not more than .vertline.2y.sub.t .vertline., detected data is determined to be correct, and the routine proceeds to step S4. At step S4, (y.sub.t-T +y.sub.t+T)/2 is provided to the upper address, and y.sub.t is provided to the lower address, so that respective data values are stored in the address region of table ROM 6, as shown in FIG. 6(a).

After termination of processing in steps S4 and S8, the routine proceeds to step S5. At step S5, CPU 5 reads a demodulated value stored in the designated address in table ROM 6, and provides the same as the luminance signal level Y.sub.t.

Through the above process, digital FM demodulation operation with less operation error and without incorrect detection can be realized.

In the above method, determination is made as to whether .vertline.y.sub.t-T +y.sub.t+T .vertline. is not more than ]2y.sub.t ], so that address and dataregions for the case where .vertline.y.sub.t-T +y.sub.t+T .vertline. is larger than .vertline.2y.sub.t .vertline. are not required. Accordingly, since the capacity of table ROM 6 having 20-bit address and 12-bit data can be halved, reduction in the capacity of the ROM can also be implemented.

Although operational processing is performed by CPU 5 in the above embodiment, it may be carried out with a digital circuit in a hardware manner, so that higher operation speed, and thus digital FM demodulation at a higher speed can be implemented.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.