Digital FM Demodulating Apparatus

1. Field of the Invention

This invention relates to a digital FM demodulating apparatus and, more particularly, to a digital FM demodulating apparatus used in a VTR.

2. Description of the Related Art

As is well known, a conventional digital FM demodulating apparatus, e.g., a digital FM demodulating apparatus used in a VTR (viedo tape recorder) is arranged as shown in FIG. 1. That is, an input video signal is supplied to recording signal processor 12 consisting of an FM modulator and the like. An output from processor 12 is supplied as a digital FM signal to input terminal 16 of digital FM demodulating apparatus 14. The digital FM signal, e.g., signal Asin .theta. is supplied to phase shift circuit 18 to be divided into digital FM signal Asin .theta. and signal Acos .theta. which is phase-shifted from signal Asin .theta. through 90.degree.. Thereafter, signals Asin .theta. Acos .theta. are supplied to absolute value circuits 20 and 22 to be converted into absolute value signals .vertline.Asin .theta..vertline. and .vertline.Acos .theta..vertline., respectively. Then, divider 24 performs the following division using the absolute value signals:

Division result .vertline.tan .theta..vertline. obtained by divider 24 is address data of ROM (read-only memory) 26 which stores a tan.sup.-1 conversion table. For this reason, ROM 26 outputs phase data .theta. falling within the range of 0 to .pi./2. Data .theta. is supplied to phase expanding circuit 28 to be converted into phase data .theta.' falling within the range of -.pi. to .pi. on the basis of a pair of digital FM signals Asin .theta. and Acos .theta. output from circuit 18.

Thereafter, data .theta.' is supplied to differentiating circuit 30 comprising delay circuit 30a for delaying one cycle of a sampling clock of input digital FM signal Asin .theta. and subtracter 30b, thereby performing the following calculation:

As a result, signal data (d.theta.'/dt) obtained by differentiating data .theta.' by time t is output from output terminal 32.

In the conventional digital FM demodulating apparatus having the above arrangement, however, if signal Asin .theta. is represented by an 8-bit complement of 2, an address of ROM 26 requires 21 bits in order to set precision at the output side of ROM 26 to correspond to 11 bits. For this reason, the capacity of ROM 26 must be:

That is, the scale of ROM 26 is increased to complicate and enlarge its arrangement. In addition, since ROM 26 is enlarged, its cost is also increased to pose a problem of economical disadvantage.

It is, therefore, an object of the present invention to provide a digital FM demodulating apparatus which is economically advantageous because a capacity of a memory for performing tan.sup.-1 conversion is decreased to reduce a cost of the memory.

According to an aspect of the present invention, there is provided a digital FM demodulating apparatus comprising: generating means for generating a pair of digital FM signals having a phase difference of 90.degree. on the basis of an input digital FM signal; delay means for delaying the pair of digital FM signals generated by the generating means by a predetermine time period; calculating means for calculating data such that a result of synthesis of outputs from the generating means and the delay means becomes a value obtained by differentiating a phase component of the input digital FM signal by a time; and converting means for performing tan.sup.-1 conversion in accordance with the output data from the calculating means in order to obtain the phase component of the input digital FM signal.

These and other features and advantages of the present invention will become more apparent from the following detailed description of exemplary embodiment as illustrated in the accompanying drawings in which:

FIG. 1 is a block diagram showing an arrangement of a digital FM demodulating apparatus of a prior art;

FIG. 2 is a block diagram showing an arrangement of a digital FM demodulating apparatus according to the present invention;

FIG. 3 is a schematic view showing an arrangement of an operational circuit shown in FIG. 2;

FIG. 4 is a graph showing input/output characteristics of tan.sup.-1 conversion schematically showing stored contents of a ROM shown in FIG. 2; and

FIG. 5 is a schematic view showing another arrangement of the operational circuit shown in FIG. 2.

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 shows an arrangement of a digital FM demodulating apparatus used in a VTR, in which an input video signal is converted into a predetermined signal by recording signal processor 12 comprising an FM modulator and the like. The converted signal, e.g., digital FM signal Asin .theta. is supplied to input terminal 16 of digital FM demodulating apparatus 34. Signal Asin .theta. supplied to terminal 16 is supplied to phase shift circuit 18. Circuit 18 divides signal Asin .theta. into digital FM signal Asin .theta..sub.2 and digital FM signal Acos .theta..sub.2 which is phase-shifted from signal Asin .theta..sub.2 through 90.degree. and outputs the signals. A pair of signals Asin .theta..sub.2 and Acos .theta..sub.2 are supplied to registers 38 and 36, respectively, and then to operational circuit 40. Registers 36 and 38 are driven by a clock having the same frequency as a sampling frequency of signal Asin .theta. and can delay input signals Acos .theta..sub.2 and Asin .theta..sub.2 by one cycle of the clock. In this manner, registers 36 and 38 generate and output digital FM signals A'cos .theta..sub.1 and A'sin .theta..sub.1 to operational circuit 40.

On the basis of four input signals Asin .theta..sub.2, Acos .theta..sub.2, A'sin .theta..sub.1 and A'cos .theta..sub.1, operational circuit 40 calculates data by which a result of tan.sup.-1 conversion becomes a value (d.theta./dt) obtained differentiating phase component .theta. of signal Asin .theta. input to terminal 16 by time t.

Output data calculated by operational circuit 40 is supplied to ROM 42 which stores a tan.sup.-1 conversion table so as to be used as its address data. By this address data, signal data (d.theta./dt) obtained by differentiating the phase component of signal Asin .theta. by a time is output from output terminal 32.

Operational circuit 40 is arranged as shown in FIG. 3. That is, signals Asin .theta..sub.2 and Acos .theta..sub.2 from phase shift circuit 18 are supplied to divider 40a, and signals A'sin .theta..sub.1 and A'cos .theta..sub.1 delayed by registers 38 and 36 are supplied to divider 40b. Calculation results of dividers 40a and 40b are supplied to subtracter 40c and multiplier 40d, respectively. An output from multiplier 40d is added with "1" by adder 40e and then supplied to divider 40f. This "1" corresponds to "1" in the denominator of the right-side term of equation (2) which will be given later. An output from subtracter 40c is supplied to divider 40f so that division is performed between the outputs from subtracter 40c and adder 40e. As a result, .DELTA..theta.=.theta..sub.2 -.theta..sub.1 is output from divider 40f to ROM 42.

As described above, the signal data (d.theta./dt) which is to be finally obtained from terminal 32 of demodulating apparatus 34 is given by the following equation:

In order to obtain .theta..sub.2 -.theta..sub.1 (=.DELTA..theta.), the right-hand side of equation (1) is rewritten as follows:

In this case, the contents in { } of equation (2) represent the input of ROM 42, i.e., the output data from operational circuit 40. x.sub.1 and x.sub.2 are given as follows:

Therefore, referring to FIG. 3, equations (3) and (4) are substituted in equation (2) to obtain the following equation: ##EQU1## In this case, the contents in { } of equation (5) represent the input data of ROM 42, i.e., the output data from operational circuit 40.

On the basis of four input signals Asin .theta..sub.2, Acos .theta..sub.2, A'sin .theta..sub.1 and A'cos .theta..sub.1, operational circuit 40 calculates the right-hand side of equation (5) by the respective calculator components shown in FIG. 3. As a result, the output data from operational circuit 40 is supplied to ROM 42, so that ROM 42 generates data by which the result of tan.sup.-1 conversion becomes the value (d.theta./dt) obtained by differentiating phase component .theta. of signal Asin .theta. by time t.

By using the output data from calculator 40 as the address data of ROM 42 which stores the tan.sup.-1 conversion table, the signal data (d.theta./dt) obtained by differentiating the phase component of signal Asin .theta. supplied to terminal 16 can be output from terminal 32.

FIG. 4 shows the contents of the tan.sup.-1 conversion table stored in ROM 42 in correspondence with an inverse tangent curve. In FIG. 4, the ordinate represents address data at the input side of ROM 42; and the abscissa, those at its output side. In practice, numerical values are stored.

According to the arrangement of the above embodiment, if, for example, a frequency component of signal Asin .theta. supplied to terminal 16 is less than 1/8 of the sampling frequency, the signal data (d.theta./dt) finally obtained from ROM 42, i.e., terminal 32 falls within the following range:

For this reason, the tan.sup.-1 conversion table to be stored in ROM 42 need only correspond to the range from 0 to .pi./4 of phase .theta. of input signal Asin .theta.. Therefore, the capacity of ROM 42 can be decreased smaller than those of conventional ROMs. In addition, a cost can be reduced by this decrease in the capacity of the ROM, resulting in an economical advantage.

For example, in order to obtain output precision of ten bits of ROM 42, the address (input side) of ROM 42 need only have 11 bits. For this reason, the capacity of ROM 42 is calculated to be:

That is, the capacity of ROM 42 can be reduced to about 1/10 those of the conventional ROMs.

FIG. 5 shows a modification 40' of operational circuit 40 shown in FIG. 2. As is shown in this figure, circuit 40' comprises multipliers 40g, 40h, 40i and 40j, subtractors 40k and 40l, and divider 40m. Signal Asin .theta..sub.2 output by phase shift circuit 18 is supplied to multipliers 40h and 40. Signal Acos .theta..sub.2, also output by circuit 18, is supplied to multipliers 40g and 40j. Signal A'sin .theta..sub.1, which has been delayed by register 38, is input to multipliers 40g and 40h. Signal A'cos .theta..sub.1, which has been delayed by register 36, is input to multipliers 40i and 40j. The products, which multipliers 40g and 40i have made, are supplied to subtractor 40k, whereas the products, which multipliers 40h and 40j have made, are supplied to subtractor 40l. The differences, which subtractors 40k and 40l have obtained, are output to divider 40m, which divides the difference output by subtractor 40k by the difference output by subtractor 40l, thus providing .DELTA..theta. (=.theta..sub.2 -.theta..sub.1). The value, .DELTA..theta., thus obtained, is output from divider 40m to ROM 42.