I/Q Quadraphase Modulator Circuit

This invention relates to I/Q quadraphase modulator electrical circuits.

Quadraphase modulator/circuits for digital communication systems are known. For example, the HPMX-2001 is a silicon monolithic quadraphase shift keyed modulator with a typical local oscillator (LO) operating frequency range of DC-2000 MHz and typical I/Q bandwidth of DC-700 MHz. Such devices are useful for, among other things, digital cellular radio, RF data links, vector generators, AM modulators, and single sideband mixers. Typical I/Q modulator performance of this and similar chips is limited by the quadrature quality of the LO signals. Quadrature phase errors occur due to process variations, circuit component mismatch and circuit parasitics. In addition, it is difficult to make accurate broad band quadrature phase shifters. Phase errors in the I and Q LO signals in complex vector modulators, for example, limit sideband suppression critical to meeting system specifications for ADC (IS-54) and GSM digital cellular phone transmitters.

An object of the invention is a quadraphase modulator circuit having improved performance.

Another object of the invention is a quadraphase modulator circuit which is substantially insensitive to phase errors in the quadrature LO signals.

In accordance with one aspect of the invention, the quadraphase modulator circuit comprises two Gilbert cell type of multipliers each of which comprises top ports and bottom ports. Sum and difference, limited, quadrature, differential signals are applied to the top ports of the Gilbert cell multipliers. The result is to make the circuit less sensitive to LO phase errors and thus to improve sideband (image) rejection over the conventional circuit typically using one Gilbert cell multiplier.

The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and specific objects attained by its use, reference should be had to the accompanying drawings and descriptive matter in which there are illustrated and described the preferred embodiments of the invention.

FIG. 1 is a circuit schematic of a conventional Gilbert cell multiplier;

FIG. 2 is a schematic circuit showing equivalence of a differential pair;

FIG. 3 is a circuit schematic of one form of quadraphase modulator circuit in accordance with the invention;

FIG. 4 is a circuit schematic of another form of quadraphase modulator circuit in accordance with the invention.

Gilbert cell multipliers are known. See, for example, Pg. 593 of "Analog Integrated Circuits" by Gray and Meyer, published 1977 by Wiley. A Gilbert cell multiplier is a modification of an emitter-coupled cell, which allows four-quadrant multiplication in an IC balanced multiplier system. FIG. 1 shows a typical Gilbert cell multiplier circuit 10, which is characterized by the series connection of an emitter-coupled transistor pair Q1, Q2, designated 11, with two cross-coupled, emitter-coupled pairs Q3, Q4, and Q5, Q6, designated 12, and 13, respectively. Two top ports 16, 17 for LO signals and two bottom ports 18, 19 for RF signals are provided. The referenced book also provides a detailed explanation for the operation of such multipliers, which is hereby incorporated by reference, but those details need not be repeated here to understand the present invention. Note that the LO signals are applied such that the positive signal goes to both outer transistors, Q3, Q6, of each pair, and the negative signal goes to both inner transistors, Q4, Q5, of each pair.

For simplicity, each of the transistor pairs can be and are replaced by a block 20, so that the circuit fragment depicted at the left in FIG. 2 is the equivalent of the circuit fragment at the right, referred to herein as a differential pair. Thus, the block 20 corresponds to each of the transistor pairs 11, 12, and 13.

FIG. 3 shows one form of quadraphase modulator circuit in accordance with the invention, the same reference numerals designating the same elements. This differs from the circuit of FIG. 1 in that two identical Gilbert cell multipliers 21, 22 are provided, each of which, except for the signal connections, is identical to the circuit 10 of FIG. 1. In the FIG. 3 circuit, to the ports 30, 31 of the bottom differential pair at the left are supplied positive and negative I (inphase) signals, designated VI. To the ports 32, 33 of the bottom differential pair at the right are supplied positive and negative Q (quadraphase) signals, designated VQ. To the top ports 34, 35 of the left differential pair at the left are supplied positive and negative signals, designated V1. To the top ports 36, 37 of the left differential pair at the right are supplied positive and negative signals, designated V2. To the top ports 38, 39 of the right differential pair at the left are supplied positive and negative signals, designated V3. To the top ports 40, 41 of the right differential pair at the right are supplied positive and negative signals, designated V4. The circuitry 45 above the Gilbert cells provides positive and negative outputs designated Vout. This corresponds to a summation function, also described below.

In accordance with the invention, the V1, V2, V3 and V4 signals are defined as:

where.omega..sub.1 is the LO frequency.

These signals are supplied as the quadrature outputs from a conventional IC phase shifter to which are input the positive and negative LO signals corresponding to those supplied to the upper ports of the Gilbert cell multiplier of FIG. 1. Equations (1) through (4) give the sum and difference terms of the quadrature LO terms. It can be demonstrated that, even though phase error terms are introduced to Eq.'s (1) through (4), the unique properties of the modulator architecture of the invention inherently corrects those errors, where the quadrature LO signals contain only phase errors. Thus, the amplitudes of the quadrature LO signals should be maintained substantially equal. This is achieved by means of limiting amplifiers which are part of the quadrature phase shift network circuitry, as shown in FIG. 4, explained below.

To explain the operation of the circuit of the invention, the modulation waveforms are examined. V1, V2, V3 and V4 are sufficiently large in amplitude (>5V.sub.T) to switch the upper differential pairs of the quadraphase multipliers on/off. Due to the limiting action of V1 through V4 switching several V.sub.T, the Fourier series expansion can be used on the modulation (pairs V1,V2 and V3,V4) port and on the linear port signals (differential V.sub.1 and V.sub.Q) of the quadraphase multiplier, assuming that V1 through V4 are large enough in amplitude to multiply the differential V.sub.1 and V.sub.Q input signals by +1 and -1 alternately.

The collector currents of multiplier 21 and multiplier 22 are summed together to produce upper/lower sideband cancellation depending on the phasing (+/-180.degree.) of the output currents.

The output of the quadraphase multiplier is ##EQU1## and K.sub.3 =K.sub.3 =K is the magnitude of the gain of the multiplier from the small signal input to the output.

Let

and

Substituting Eq.'s (8) and (9) into Eq. (5) yields

where

Applying trigonometric identities to Eq. (10) gives

Looking only at terms near .omega..sub.1 (all other higher terms are filtered) yields

Using

Substituting Eq.'s (14) and (15) into Eq. (13) produces

Collecting like terms provides

which is the lower sideband term, .omega..sub.1 t-.omega..sub.m t, as is desired and where

and A is the input amplitude of the I and Q differential input signals and K is the small signal multiplier gain.

This demonstrates that by the unique application of quadrature LO signals to the Gilbert cell pair, even with phase errors present, complete sideband cancellation can be achieved independent of the quadrature LO phase quality. In practical applications, phase errors up to +/-10.degree. cause no significant level of the undesired (canceled) sideband.

FIG. 4 shows one form of circuit embodying the invention. The Gilbert cell multipliers 21, 22 and their outputs 45 correspond to the FIG. 3 circuit. I and IN correspond to +VI and -VI in FIG. 3. "N" and "/" represent the opposite phase signal, sometimes shown as a bar over the symbol. Q and QN correspond to +VQ and -VQ of FIG. 3. LO and LON correspond to the normal quadrature LO signals. These input signals in FIG. 4 are amplified by a limiting amplifier 50 and inputted to a conventional 90.degree. phase shifter 51 whose outputs, quadrature sin and sin/, and cos and cos/ signals, are again amplified in limiting amplifiers 53, 54, and supplied as inputs to the multipliers 21 and 22 as shown to correspond to the signals V1-V4 defined above. Thus, V1=sin-cos.backslash.=sin+cos; V2=cos-sin.backslash.=cos+sin; V3=sin-cos=sin-cos; V4=cos.backslash.-sin.backslash.=sin-cos. The outputs at 45 are summed in a conventional summer 55, from whose output are obtained the desired signals OUT and OUTN. Used as a modulator, the output would be the quadrature LO signals modulated by the signals VI and VQ.

It will be understood that the invention is not limited to the specific circuitry of FIG. 4, and other ways of producing the desired sum and difference, limited, quadrature differential signals to be supplied to the pair of Gilbert cell multipliers as described above are considered to be within the scope of the invention.

While the invention has been described in connection with preferred embodiments, it will be understood that modifications thereof within the principles outlined above will be evident to those skilled in the art and thus the invention is not limited to the preferred embodiments but is intended to encompass such modifications.