Multiple-Input Four-Quadrant Multiplier

1. Field of the Invention

The present invention relates to a four-quadrant multiplier with more than two signal inputs for multiplying an input signal by several other input signals such that the results of the separate multiplications appear added together at its output terminal.

Multipliers of this type are advantageously employed, for example, for modulating various signals on the same carrier or for detecting already modulated signals with different frequencies on the same carrier.

2. Description of the Prior Art

Four-quadrant multipliers with two linear signal inputs are described along with their mode of operation on pages 6-9 to 6-16 of Data-Acquisition Handbook 1984, Vol. 1: Integrated Circuits (Analog Devices, Inc.), on page 227 ff., Section 11.41, of U. Tietze and Ch. Schenk, "Halbleiterschaltungstechnik," 5th ed. (1980), etc. These known multipliers are based on what is called a Gilbert cell.

FIG. 1 illustrates a prior art circuit as identified above. Two transistors T1 and T2 and two other transistors T3 and T3 constitute two pairs of differential amplifiers with directly connected emitters. The collector of transistor T1 is connected to the collector of transistor T3 and, by way of a resistor R1, to a supply potential Uv, creating a signal-output terminal +z. The collector of transistor T2 is analogously connected to the collector of transistor T4 and, by way of another resistor R2, to supply potential Uv, creating another signal-output terminal -z. The two signal-output terminals together supply a symmetrical output signal. Since the emitters of transistors T1 and T2 and of transistors T3 and T4 are interconnected with no negative-feedback resistor, the bases of these transistors do not constitute a linear signal-input terminal. To provide a linear signal-input terminal, the base of transistor T1 is connected to the base of transistor T4 and to the collector of a fifth transistor T5 and by way of a diode D1 to a source of current, specifically a third resistor R3, the other terminal of which is at supply potential Uv. The base of transistor T2 is analogously connected to the base of transistor T3, to the collector of a sixth transistor T6, and by way of a second diode D2 to resistor R3, the source of current. The emitters of transistor T5 and transistor T6 are either interconnected by way of a resistor and connected by way of a separate source of current to reference potential or, as illustrated in FIG. 1, interconnected by way of a fourth resistor Rx1 and a fifth resistor Rx2, with the junction between them connected by way of a source I1 of constant current to reference potential (mass). The base of transistor T6 accordingly constitutes one input terminal +x and the base of transistor T5 another input terminal -x of the multiplier. It is possible to introduce a symmetrical input signal through input terminals +x and -x in that the multiplier's transmission properties are linear in relation to this signal input. The emitters of transistors T1 and T2 are connected to the collector of a seventh transistor T7. The emitters of transistors T3 and T4 are connected to the collector of an eighth transistor T8. The emitters of transistors T7 and T8 are interconnected by way of a coupling resistor Ry. The emitter of seventh transistor T7 is connected to reference potential by way of another source I2 of constant current, and the emitter of transistor T8 to reference potential by way of a third source I3 of constant current. The base of seventh transistor T7 constitutes the third input terminal +y and the base of transistor T8 the fourth input terminal -y of the multiplier. It is possible to introduce a symmetrical input signal through input terminals +y and -y in that the multiplier's transmission properties are linear in relation to this signal input as well due to the negative feedback represented by coupling resistor Ry.

Circuits of the above described type are especially appropriate for multiplying at least one digital input signal by another input signal. To obtain a similar multiplier with more than two signal-input terminals, whereby one input signal can be multiplied by several other input signals and the individual results added, it would be possible to connect the corresponding number of known multipliers. This known approach would, however, have drawbacks that would be particularly apparent when the multiplier was used as a detector or modulator.

Although transistors or diodes manufactured in a single step on one chip are generally similar, the slight difference in large-signal behavior, the wide difference between the amplification factors, etc. of the different transistors results in different direct-current voltage offsets in the individual amplification stages, especially when many transistors are connected together, and the individual signal-input terminals in the overall multiplier circuit are variously weighted. Since the direct-current voltage offset already creates problems in such circuits, the superposition of several different direct-current voltage offsets would be particularly detrimental.

Other drawbacks encountered in such known prior art circuits are that they occupy a lot of the surface of the chip and that potentially deleterious track capacities can occur at high frequencies.

The present invention describes a multiplier for multiplying an input signal by several other input signals with the results of the separate multiplications appearing added together at its output terminal, such that the aforementioned disadvantages of the prior art are either eliminated or are substantially decreased.

This invention is described in detail with reference to the drawings wherein:

FIG. 1 illustrates a multiplier of the prior art.

FIG. 2 illustrates a block diagram of the technique of the present invention which is appropriate for processing square or digital signals.

FIG. 3 illustrates a preferred embodiment of the present invention.

Circuit components that have the same or similar function are labeled with the same or a similar reference number in FIGS. 1, 2, and 3. The mode of operation of the circuits illustrated in FIGS. 2 and 3 is operationally similar to that of the described prior art circuit illustrated in FIG. 1, but includes the hereinafter disclosed improvements.

The particular advantage of the circuit in accordance with the present invention is that transistors T1, T2, T3, and T4, which are present in a similar activating circuit in the form of a Gilbert cell, are designed for this special application as multiple-emitter transistors. Thus, the expenditure for circuitry and the chip surface occupied in accordance with the invention is only a little greater than in the case of single-stage multipliers.

The input signal applied to input terminals +x and -x is multiplicatively mixed or multiplied in the linear-activation range with the signals at terminals +y1 & -y1, +y2 & -y2, etc. as is known. Since the collector currents from transistors T1, T2, T3, and T4 always contain the sum of their emitter currents, the individual multiplication products are presented added together at signal-output terminals +z & -z.

Whether the product of the input signal supplied to input terminal +x & -x and of another input signal supplied to another signal-input terminal is added to or subtracted from the products of the input signals applied to input terminal +x & -x and to the remaining signal-input terminals depends only on the mathematical sign of the particular input signal. The input terminals can be interchanged to reverse the sign.

The circuit illustrated in FIG. 3 is especially suitable for applications wherein the transmission behavior of the multiplier should be linear in relation to separate input terminals. This type of transmission behavior is ensured in particular with respect to input terminals +y1 & -y1, +y2 & -y2, etc. by the negative feedback comprising coupling resistors Ry1, Ry2, etc.

Whether the emitters of transistors T5, T6, T7, T8, T71, T81, T72, T82, etc. are each connected by way of a resistor Ry1 etc. to the emitter of the corresponding transistor and by way of a particular source of current to reference potential or whether the emitters are interconnected by way of a series of two resistors Rx1, Rx2, etc., with only the junctions between the resistors connected by way of source of constant current to reference potential is irrelevant to the circuitry in accordance with the invention. As will be evident from pages 64 and 65 of U. Tietze and Ch. Schenk, "Halbleiter-Schaltungstechnik," 4th ed. (1978), the two versions are equivalent. Their effects differ only in that, when there are two sources of current and one resistor per pair of emitters, the resistor carries no current when inactive, so that varying the amplification does not affect rest potential. Which embodiment of the circuit is employed accordingly depends on the specific conditions and is not critical in the case of monolithic integrated circuit.

When signal-input terminals +y & -y, +y1 & -y1, etc. are to be supplied with square-wave signals, the multiplier illustrated in FIG. 2 is particularly advantageously applicable.

It is often sufficient to make sources Is21, Is22, . . . , Is31, Is32, etc. conventional sources of constant current that engage and disengage in accordance with the particular signal level. If the current-input terminal of these sources Is 21 etc. of variable current is the collector of a transistor Tx, the emitter of which is connected to another potential, especially reference potential, and simultaneously to the emitter of another transistor Ty, and the base of which is connected to the base and to the collector of transistor Ty to create a control input terminal for the source, whereby the control input terminal is connected to supply potential Uv by way of a resistor Rv, the control input terminal of this type of current source can be directly activated by the output from a logic gate, especially an I.sup.2 L gate G1, G2, etc.

To keep the edges of the square-wave signal clean, one inverting input terminal -y1, -y2, etc. can be activated by the output signal from a logic gate G1, G2, etc. and one non-inverting input terminal +y1, +y2, etc. by an output signal that is the inverse of that output signal.