Complementary Symmetry FET Frequency Converter Circuits

This invention relates to frequency converter circuits using field-effect transistors (FET's) as may be used, for example, in superheterodyne signal receiving systems.

A frequency converter translates the frequency components of an input signal in the frequency domain so as to translate the input signal from one part of the frequency spectrum to another. In superheterodyne radio and television receivers, a frequency converter is used to change the frequency of the received radio frequency (RF) signal to a fixed intermediate frequency (IF) signal.

A frequency converter comprises an oscillator and a mixer. Typically, the mixer includes a non-linear device such as a diode or a transistor. The oscillator signal and the incoming RF signal are applied as inputs to the mixer. The two input signals beat (or heterodyne) within the mixer to produce a signal which, in addition to having signal components at the frequency of the input signals, has numerous sum and difference frequencies.

The output circuit of the mixer is provided with a tuned circuit for selecting only one beat frequency, i.e., the predetermined IF frequency. By tuning the local oscillator frequency, the output frequency of the mixer is kept constant for all values of received signal frequency.

It is known to use a dual gate FET transistor as a mixer. For example, see Solid State Devices Manual, SC-16, 1975, published by RCA Corporation, Solid State Division. The mixer circuit shown in FIG. 455, page 373 of the above-referenced manual employs a dual gate FET transistor wherein the RF input signal is applied to one gate and the oscillator signal is applied to the other gate. In a similar manner, two individual FET transistors of the same conductivity type with their conduction channels connected in series, may be employed as a mixer. However, such circuit configurations require a substantial number of peripheral components, particulary resistors, for proper operation.

Mixer circuits using complementary symmetry FET transistors have been disclosed in U.S. Pat. Nos. 4,032,851 and 4,090,139, both of which are issued to the present inventor and assigned to RCA Corporation. The mixer circuits shown in the above-referenced patents are of the type in which a separate oscillator would have to be employed. In contrast, circuits of the present invention are embodied in frequency converter circuits, i.e., mixer circuits of the self-oscillating type (also known as an autodyne frequency converter) wherein a separate oscillator is not required.

Frequency converters of the present invention comprise first and second FET transistors of opposite conductivity type to perform respective oscillator and mixer functions. The conduction channel of the first FET transistor is connected in series with the conduction channel of the second FET transistor. The first FET transistor is arranged as an oscillator by providing feedback from one of its drain and source electrodes to the gate electrode thereof. The second FET transistor is arranged as a mixer by coupling an input signal to the gate electrode thereof. Sum and difference beat frequencies are available at a circuit node at the interconnection of the conduction channels of the first and second FET transistors.

FIGS. 1, 2, 3 and 4 are schematic diagrams each illustrating a frequency converter embodying the present invention.

FIG. 1a illustrates a varactor diode tuning circuit for adjusting the frequency of the tuned circuits shown in FIG. 1.

In FIG. 1, a frequency converter 6 is used as part of a superheterodyne receiving system. The frequency converter 6 receives an RF input signal from signal source 4 at terminals 12 and 14 and translates the RF signal frequency to an IF signal frequency. The output of frequency converter 6 at terminals 16 and 18 is connected to an IF amplifier stage 8.

The frequency converter 6 comprises P-channel FET transistor P1 and N-channel FET transistor N1 having respective complementary conductivity characteristics, capacitors C1, C2, C3, C4, C5 and C6, transformers L1 and L3 and inductors L2 and L4. The respective source-to-drain conduction channels of transistors P1 and N1 are connected in series across an operating potential. Particularly, the source electrode of transistor P1 is connected to a relatively positive operating potential V+, while the source electrode of transistor N1 is connected to a relatively negative potential, in this case shown as ground potential. The respective drain electrodes of transistors P1 and N1 are connected to circuit node A.

Capacitor C1 and the secondary winding of transformer L1 form a first parallel-resonant circuit at a frequency f.sub.1 connected between the gate electrode of transistor N1 and ground potential through capacitor C6. Capacitor C6 is a bypass capacitor forming a low impedance path to ground potential in the range of input frequencies of interest. Capacitor C2 and inductor L2 form a second parallel-resonant circuit at a frequency f.sub.2 connected between node A and the gate electrode of transistor P1. Capacitor C3 and the primary winding of inductor L3 form a third parallel-resonant circuit connected between ground potential and circuit node A via capacitor C4. Coupling capacitor C4 isolates circuit node A from ground with respect to dc, but provides a low impedance path for AC signal components in the range of output IF signal frequencies of interest. Capacitors C1, C2 and C3 are shown as variable capacitors. Generally, capacitor C3 is adjusted to correspond to a fixed IF frequency, while C1 and C2 are varied according to the desired frequency of the received RF input signal.

Quiescent operating potentials are established for transistors P1 and N1 by direct coupled feedback paths from point A to the respective gate electrodes thereof. Specifically, point A is dc connected through inductor L2 to the gate electrode of P1. Point A is also dc connected via a portion of inductor L2, and inductors L4 and L1 to the gate electrode of N1. Inductor L4 is a radio frequency choke to reduce interaction between the input circuit L1, C1 and the oscillator circuit L2, C2. The gate electrode of transistors N1 and P1 are therefore biased with similar gate-to-source dc potentials for common-source operation. Assuming that transistors P1 and N1 have complementary conductivity characteristics, node A is at a dc potential equal to V+/2 under quiescent operating conditions.

In operation, the second parallel-resonant circuit C2, L2, provides a drain-to-gate feedback path so as to form an oscillator in conjunction with transistor P1. The frequency of oscillation, f.sub.2, is determined by the parallel-resonant circuit components, C2, L2, at which frequency the drain-to-gate feedback provides 180.degree. phase shift. The current flowing through the conduction channel of transistor P1 is therefore modulated at frequency f.sub.2 causing a corresponding modulation of the potential at node A.

At the same time, an RF signal input at terminals 12 and 14 of the primary winding of transformer L1 appears across the first parallel-resonant circuit formed by capacitor C1 and the secondary winding of transformer L1. Capacitor C1 and the secondary winding of transformer L1 are tuned to the input frequency, f.sub.1. Since the voltage across C1 and L1 appears across the gate-to-source electrode of transistor N1 (due to bypass capacitor C6), the current flowing through the conduction channel of transistor N1 is modulated at frequency f.sub.1. This causes the potential at node A to be modulated at frequency f.sub.1 via the conduction channel of transistor N1 to ground potential.

Since the conduction channels of transistors P1 and N1 are connected in series, the oscillator signal and the RF input signal beat, or heterodyne, against each other. As a result, the signal at node A includes, among other components, two sideband frequencies of interest, namely f.sub.1 plus f.sub.2, and f.sub.1 minus f.sub.2. The desired IF output signal is selected by the third parallel-resonant tuned circuit comprising capacitor C3 and the primary winding of transformer L3. The secondary winding of transformer L3 provides the output signal at terminals 16 and 18 to the successive IF stage 8.

Also, the value of the bypass capacitor C5 is chosen so that C5 presents a low impedance path to the input and oscillator signals at frequencies f.sub.1 and f.sub.2 and the IF signal frequency of interest.

Note that no resistors are required for the operation or the quiescent biasing of the circuit of FIG. 1. Furthermore, since transistor P1 acts as an oscillator, no separate oscillator is required. The use of FET transistors, as compared to bipolar transistors, provides several advantages. Complementary FET transistors are readily integrated on a common substrate. FET transistors also provide high input impedance, square law operating characteristics, and the capability of operating over a wide dynamic range of input signal voltages.

Various substitutions may be made for the tuned circuit elements in the circuit shown in FIG. 1. For example, the parallel resonant output circuit C3, L3, which is tuned to the IF signal frequency may be a series-resonant tuned circuit or a Pi network.

The variable capacitors C1, C2 which determine the respective input signal frequency and oscillator signal frequency may be implemented with varactor diodes. A circuit employing a varactor diode which may be used as a substitution for capacitor C2 is shown in FIG. 1a. The varactor diode 7 is connected in series with a fixed capacitor 5. A tuning control 11 is connected via a large range value resistor 9 so as to provide reverse-bias dc voltage across the varactor diode 7. The value of the reverse-bias dc voltage across the varactor diode 7 determines the value of the varactor diode capacitance and therefore determines the frequency of the oscillator signal f.sub.2. Varactor circuits similar to that shown in FIG. 1a can replace any of the variable capacitors shown in FIGS. 1, 2, 3, or 4.

FIG. 2 shows an alternate embodiment of the present invention. In FIG. 2, as compared to FIG. 1, the operational functions of transistors P1 and N1 are reversed. That is, transistor N1 and its associated parallel-resonant tuned circuit C22, L22 form the oscillator, whereas transistor P1 and its associated parallel-resonant tuned circuit C11, L11 form the input signal amplifier and mixer.

FIG. 3 shows another embodiment of the present invention employing a crystal controlled oscillator to improve oscillator frequency stability. A Pi-type network comprising capacitors C7 and C8, crystal 20, and resistor R3 provides the requisite drain-to-gate feedback for transistor P1 necessary for oscillation. Input signal amplification and the mixing functions are performed by transistor N1.

The frequency converter of FIG. 3 provides a fixed oscillator frequency for conveniently tuning a receiver to a predetermined frequency. Such circuits are also useful in broadband frequency converters for translating a band frequencies across the frequency spectrum.

A quiescient operating point is established through resistors R1 and R2 which provide respective dc connections between the drain and gate electrodes of transistors P1 and N1. Specifically, node A is connected to the gate electrode of transistor P1 via resistor R2. Node A is also connected to the gate electrode of transistor N1 via the primary winding of transformer L3, resistor R1, and the secondary winding of transformer L1. Capacitor C4 serves to block a dc path from node A to ground, while providing a low impedance path to ground for AC signal components selected by the IF tuned circuit C3, L3 at the output IF frequency of interest.

Yet another embodiment of a frequency converter in accordance with the present invention is shown in FIG. 4.

Inductor L2 and capacitor C2 form a parallel-resonant circuit connected at one terminal thereof to the positive operating potential V+. Coupling capacitor C9 connects the other terminal of the parallel-resonant circuit L3,C2 to the gate electrode of transistor P1. The source electrode of transistor P1 is connected to a top point on inductor L2.

Quiescent bias is established via resistors R4 and R5. Node A is dc connected to the gate electrode of transistor P1 via the primary winding of transformer L3 and resistor R5. Node A is also dc connected to the gate electrode of transistor N1 via the primary winding of transformer L3, resistor R4, and the secondary winding of transformer L1.

In operation, the source current of transistor P1 flows through a portion of the inductor L2. Such arrangement provides feedback between the channel current of transistor P1 and the gate electrode thereof through capacitor C9. Oscillations are thus sustained at a frequency determined by the parallel-resonant tuned circuit L2, C2. As before, the voltage at node A is simultaneously modulated at the frequency of the oscillator (by transistor P1) and the frequency of the input signal (by transistor N1). The desired IF output signal frequency is selected by the parallel-resonant tuned circuit comprising capacitor C3 and the primary winding of transformer L3.

Note that the conduction channel of transistor P1 is connected between the oscillator parallel-resonant circuit L2, C2 and the output IF resonant circuit L3, C3. Compare the circuit of FIG. 1 wherein the oscillator parallel-resonant circuit L2, C2 and the output IF resonant circuit L3, C3 are connected via capacitor C4. In the arrangement of FIG. 4, the separation provided by the conduction channel of transistor P1 reduces the frequency interaction between the variable frequency oscillator circuit L2, C2 and the fixed frequency IF circuit, L3, C3.