US 9,634,100 B2Grant
Semiconductor devices with integrated hole collectors
Issue Date:2017-04-25
•8 Claims
•12 Drawing Sheets
Abstract
Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.
Metadata
Assignee
- Transphorm Inc.
Inventors
- Umesh Mishra
- Srabanti Chowdhury
- Ilan Ben-Yaacov
Application Information
Application Number:US 14/934,565
Filing Date:2015-11-06
Priority Date:2012-06-27
Art Unit:2815
Classifications
IPC:
H01L31/0328H01L29/40H01L29/778H01L29/06H01L29/20H01L29/207H01L29/78H01L29/423
Field of Search:
H01L 29/2003H01L 29/402H01L 29/7786
Patent Drawings (12 sheets)
Description
Cross-Reference to Related Application
[0001] This is a divisional application of U.S. application Ser. No. 13/535,094, filed on Jun. 27, 2012, the disclosure of which is hereby incorporated by reference in its entirety.
Technical Field
[0002] Semiconductor electronic devices and components, in particular nitride-based transistors and diodes with improved reliability, are described.
Background
[0003] To date, most transistors used in power electronic applications have typically been fabricated with silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs). While Si power devices are inexpensive, they suffer from a number of disadvantages, including relatively low switching speeds and high levels of electrical noise. More recently, silicon carbide (SiC) power devices have been considered due to their superior properties. III-Nitride or III-N semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates to carry large currents, support high voltages, and to provide very low on-resistance and fast switching times.
[0004] FIGS. 1A and 1B illustrate a plan view and a cross-sectional view, respectively, of a III-N transistor of the prior art having source electrode 14, drain electrode 15, gate electrode 13, and access regions 23 and 24. As used herein, the “access regions” of a transistor refer to the two regions between the source and gate electrodes, and between the gate and drain electrodes of the transistor, i.e., regions 23 and 24, respectively, in FIGS. 1A and 1B . Region 23, the access region on the source side of the gate, is typically referred to as the source access region, and region 24, the access region on the drain side of the gate, is typically referred to as the drain access region. As used herein, the “gate region” 31 of a transistor refers to the portion of the transistor between the two access regions 23 and 24 in FIGS. 1A and 1B .
[0005] While numerous III-N transistors and diodes have been demonstrated, improvements in device reliability are still necessary in order to enable large scale manufacturing and more widespread adoption of these devices. In particular, in III-N devices configured to support high voltages and/or large currents, large electric fields present in the device during operation can lead to deleterious effects such as threshold voltage shifts and breakdown, as well as other effects that degrade device performance or otherwise render the device inoperable. Device structures that reduce such degradation and improve device reliability are therefore desirable.
Summary
[0006] Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the gate, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes. In some cases, the hole collector regions are capable of conducting holes but not electrons.
[0007] In one aspect, a transistor device comprising a source, a gate, and a drain is described. The transistor device includes a semiconductor material which includes a gate region between the source and the drain, and a plurality of channel access regions in the semiconductor material between the source and the gate, and between the drain and the gate, respectively. The transistor device further includes a channel in the semiconductor material and an insulating material over the semiconductor material, the insulating material having a first portion over the gate region and a second portion over at least one of the plurality of channel access regions, with a thickness of the first portion being less than a thickness of the second portion. The transistor device also includes one or more hole collector regions at least partially in the gate region of the semiconductor material. Furthermore, the insulating material is between the gate and the semiconductor material and prevents the gate from contacting the semiconductor material in the gate region.
[0008] In another aspect, a transistor device is described. The transistor device includes an electrode, a semiconductor material which includes a gate region between two channel access regions, a channel in the semiconductor material, an insulating material over the semiconductor material, and a hole collector region in the semiconductor material below the electrode. The insulating material is between the electrode and the hole collector region and prevents the electrode from contacting the hole collector region, and at least a portion of the insulating material that is between the electrode and the hole collector region is sufficiently thin to allow holes generated during device operation to be collected by the electrode.
[0009] In yet another aspect, a transistor device is described. The transistor device includes a gate and a III-N semiconductor material which includes a gate region beneath the gate, the gate region including a first portion having a first area and a second portion having a second area. The transistor device further includes a channel in the III-N semiconductor material and an insulating material over the III-N semiconductor material. The insulating material is over the first portion of the gate region but not over the second portion of the gate region, the gate contacts the III-N semiconductor material in the second portion of the gate region but not in the first portion of the gate region, and the first area is greater than the second area.
[0010] In still another aspect, a transistor device is described. The transistor device includes a III-N semiconductor material layer, an insulating layer over the III-N semiconductor material layer, a source, a gate, a drain, and a gate region beneath the gate. The insulating layer is between the gate and the III-N semiconductor material layer in a first portion of the gate region, with the first portion of the gate region having a first area. Furthermore, the insulating layer includes one or more apertures, the one or more apertures being in a second portion of the gate region, the second portion of the gate region having a second area. The first area is greater than the second area.
[0011] In yet another aspect, a transistor device is described. The transistor device includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a channel in the semiconductor material, an insulating material between the gate and the semiconductor material, and a field plate over the insulating material. An electrically conductive portion extending from the source or from the field plate contacts the semiconductor material, and the transistor device is an enhancement-mode transistor.
[0012] In still another aspect, a transistor device is described. The transistor device includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a channel in the semiconductor material, an insulating material between the gate and the semiconductor material, a field plate over the insulating material, an electrically conductive portion electrically connected to the source or to the field plate, and a hole collector region in the gate region of the semiconductor material. A resistance between the electrically conductive portion and the hole collector region is less than a resistance between the gate and the hole collector region.
[0013] In yet another aspect, a transistor device is described. The transistor device includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a channel in the semiconductor material, an insulating material between the gate and the semiconductor material, a field plate over the insulating material, an electrically conductive portion electrically connected to the source or to the field plate, and a doped portion at least partially in the gate region of the semiconductor material. A resistance to hole current flow between the electrically conductive portion and the doped portion is less than a resistance to hole current flow between the gate and the doped portion.
[0014] In still another aspect, a transistor device is described. The transistor device includes a gate and a III-N semiconductor material which includes a gate region beneath the gate, the gate region including a first portion having a first area and a second portion having a second area. The transistor device further includes a channel in the III-N semiconductor material and an insulating material over the first and second portions of the gate region. The insulating material is thicker over the first portion of the gate region than over the second portion of the gate region, and the first area is greater than the second area.
[0015] In yet another aspect, a transistor device is described. The transistor device includes a source, a gate, a drain, a semiconductor material which includes a gate region adjacent to the gate, a channel in the semiconductor material, and one or more doped regions at least partially in the gate region of the semiconductor material. The transistor device is configured to block at least 480V for 500 hours or more when a gate-source voltage less than a device threshold voltage is applied to the transistor device.
[0016] In still another aspect, a method of forming a transistor device is described. The method includes providing a III-N semiconductor material and forming a source, a gate, and a drain on the III-N semiconductor material, where the III-N semiconductor material includes a gate region between the source and the drain and a plurality of channel access regions between the source and the gate, and between the drain and the gate, respectively. The method further includes doping a portion of the III-N semiconductor material, wherein the portion is at least partially in the gate region, and forming an insulating material over the III-N semiconductor material, the insulating material having a first portion over the gate region and a second portion over at least one of the plurality of channel access regions, a thickness of the first portion being less than a thickness of the second portion. The insulating material is between the gate and the semiconductor material and prevents the gate from contacting the semiconductor material in the gate region.
[0017] For all transistor devices and methods described herein, one or more of the following may be applicable. The first portion of the insulating material can be sufficiently thin to allow holes generated during device operation to be collected by the gate. The first portion of the insulating material can be sufficiently thin to allow holes generated during device operation to be transported out of the semiconductor material through the gate. The device can include at least two hole collector regions in the gate region of the semiconductor material. The hole collector region can contains dopants, and the dopants can be selected from the group consisting of Mg, Al, and Fe. The device can be a III-N transistor, a high-voltage device, and/or a field-effect transistor.
[0018] The insulating material can comprise a first insulating material layer and a second insulating material layer. The second portion of the insulating material can include both the first and second insulating material layers, and the first portion of the insulating material can include the first insulating material layer but not the second insulating material layer. The insulating material can be over an entirety of the one or more hole collector regions. The one or more hole collector regions can be configured to conduct substantial hole current but not substantial electron current. The maximum hole current density that the one or more hole collector regions are configured to conduct can be at least 100 times the maximum electron current density that the one or more hole collector regions are configured to conduct.
[0019] The portion of the insulating material that is between the electrode and the hole collector region is sufficiently thin to allow holes generated during device operation to be transported out of the semiconductor material through the electrode. The electrode can be a gate, and the transistor can further comprise a source and a drain. The portion of the insulating material that is between the electrode and the hole collector region can be a first portion, the insulating material comprising a second portion between the gate and the drain, with the first portion being thinner than the second portion. The insulating material can prevent the electrode from contacting the semiconductor material. The semiconductor material can include a III-N material. The hole collector region can contain dopants, which can be selected from the group consisting of Mg, Al, and Fe.
[0020] The first area can be at least two times, at least four times, or at least ten times the second area. The III-N semiconductor material can include one or more hole collector regions in the gate region of the III-N semiconductor material, and the one or more hole collector regions can be at least partially in the second portion of the gate region. The transistor can further comprising a source and a drain on opposite sides of the gate, and a plurality of channel access regions in the III-N semiconductor material between the source and the gate, and between the drain and the gate, respectively. A portion of the insulating material that is over at least one of the plurality of access regions can be thicker than a portion of the insulating material that is over the first portion of the gate region. The insulating material over the first portion of the gate region can be between the gate and the III-N semiconductor material. The insulating material can include a first insulating material and a second insulating material. The transistor can further include a source and a drain on opposite sides of the gate, and a plurality of channel access regions in the III-N semiconductor material between the source and the gate, and between the drain and the gate, respectively. The insulating material that is over at least one of the plurality of access regions can include both the first and second insulating materials, and the insulating material that is over the first portion of the gate region can include the first insulating material but not the second insulating material. The second portion of the gate region can include a plurality of portions, and the second area is a total area of the plurality of portions.
[0021] At least one of the gate, the source, and the drain can be at least partially in at least one of the one or more apertures. At least one of the gate, the source, and the drain can contact the III-N semiconductor material layer in the second portion of the gate region. The insulating material can prevent the gate from contacting the semiconductor material in the gate region. The field plate can be electrically connected to the source. In operation, the channel may not be conductive when 0V is applied to the gate relative to the source and a voltage greater than 0V is applied to the drain relative to the source, but can be conductive when a switching voltage greater than a device threshold voltage is applied to the gate relative to the source. The transistor device can further include a hole collector region in the gate region of the semiconductor material, wherein the electrically conductive portion contacts the hole collector region. In a first mode of operation, the transistor device can be operable to block a positive voltage applied to the drain relative to the source when 0V is applied to the gate relative to the source, and in a second mode of operation, the device can be operable to conduct current from the source to the drain when 0V is applied to the gate relative to the source and the drain is at a negative voltage relative to the source. The contact between the electrically conductive portion and the hole collector region can have a turn-on voltage, wherein the turn-on voltage is sufficiently large to prevent substantial current from flowing through the contact between the electrically conductive portion and the hole collector region during the second mode of operation. The semiconductor material can include a III-N channel layer and a III-N barrier layer, the channel being in the III-N channel layer adjacent to the III-N barrier layer.
[0022] The electrically conductive portion can extend towards the hole collector region without contacting the hole collector region. A separation between the electrically conductive portion and the hole collector region can be less than or equal to a separation between the gate and the hole collector region. The insulating material can prevent the gate from contacting the semiconductor material in the gate region. The device can be an enhancement-mode transistor. A threshold voltage of the transistor device may not be substantially altered after the blocking of at least 480V for 500 hours or more.
[0023] Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages. Compared to some conventional semiconductor devices, the devices described herein can have improved reliability, longer lifespan, or both. For example, the devices described herein can be operable after blocking at least 480V for 500 hours or more, or 1000 hours or more, with a gate-source voltage less than the device threshold voltage applied to the transistor device.
Description of Drawings
[0024] FIG. 1A is a plan view of a prior art III-Nitride device.
[0025] FIG. 1B is a cross-sectional view of the device of FIG. 1A .
[0026] FIG. 2 is a plan view of a device according to this specification.
[0027] FIG. 3 is a cross-section through the cut 3-3 of the device of FIG. 2 .
[0028] FIG. 4 is a cross-section through the cut 4-4 of the device of FIG. 2 .
[0029] FIG. 5 is a plan view of another device according to this specification.
[0030] FIG. 6 is a cross-section through the cut 6-6 of the device of FIG. 5 .
[0031] FIG. 7 is a cross-section through the cut 7-7 of the device of FIG. 5 .
[0032] FIG. 8 is a plan view of yet another device according to this specification.
[0033] FIG. 9 is a cross-section through the cut 8-8 of the device of FIG. 8 .
[0034] FIG. 10 is a cross-section through the cut 9-9 of the device of FIG. 8 .
[0035] FIG. 11 is a cross-section through the cut 9-9 of an alternative implementation of the device of FIG. 8 .
[0036] Like reference symbols in the various drawings indicate like elements.
Detailed Description
[0037] Described herein are III-Nitride (i.e., III-N) semiconductor devices that include integrated hole collectors or hole collector regions. The hole collectors are configured to collect holes generated in the device during operation, for example holes generated during high voltage and/or high current operation, and facilitate the removal of the holes from active regions within the device. The generation of holes in the devices can lead to threshold voltage shifts, reduction in device reliability, and other undesirable effects. Thus, collection and removal of the holes may be necessary for reliable operation of the devices.
[0038] As used herein, the terms III-Nitride or III-N materials, layers, devices, structures, etc., refer to a material, device, or structure comprised of a compound semiconductor material according to the stoichiometric formula BwAlxInyGazN, where w+x+y+z is about 1, and w, x, y, and z are each greater than or equal to zero and less than or equal to 1. In a III-Nitride or III-N device, the conductive channel can be partially or entirely contained within a III-N material layer.
[0039] FIGS. 2-4 illustrate an exemplary III-N transistor device, i.e., a III-N high electron mobility transistor (HEMT), which includes one or more hole collector regions which are at least partially below the transistor gate. FIG. 2 is a plan view (top view) of the device, FIG. 3 is a cross-sectional view along dashed line 3 in FIG. 2 , and FIG. 4 is a cross-sectional view along dashed line 4 in FIG. 2 . The transistor is a unipolar device; that is, electrical current flowing through the device is dominated by current of a single carrier type. In the example illustrated in FIGS. 2-4 , the current passing through the device channel is predominantly an electron current. Alternatively, unipolar transistors for which channel current is predominantly a hole current are possible as well, although such devices would include electron collector regions in place of the hole collector regions described herein. While the current through the transistor of FIGS. 2-4 is predominantly an electron current, holes can be generated in the device III-N material layers during device operation, in particular during times when the device is operated under high voltage and/or high current conditions.
[0040] The transistor of FIGS. 2-4 includes hole collector regions 20, 21, and 22 (best seen in FIG. 2 ) between the source 14 and the drain 15. The hole collector regions are configured to collect the holes that are generated in the transistor during operation. Optionally, the hole collector regions can also be configured to increase or maximize the short-circuit survival time of the transistor by reducing or minimizing the maximum channel current (short-circuit current) Imax that can flow through the device, while maintaining an acceptably low on-resistance. In applications in which the hole collector regions also serve to limit the maximum channel current that can flow through the device, the hole collector regions may need to at least be under the side of the gate 16 that is closest to the source 14. That is, the hole collector regions can each include a first portion which is in the source access region 23 and a second portion which is in the gate region 31, as illustrated in FIG. 2 . Optionally, as also illustrated in FIG. 2 , the hole collector regions can also extend into the drain access region 24; that is, they can include a third portion which is in the drain access region 24. In devices with shorter gate lengths, having the hole collector regions 20-22 extend into the drain access region 24 can result in the device being more easily manufacturable.
[0041] As shown in the cross-sectional views of FIGS. 3 and 4 , the transistor device includes a substrate 10 (which may optionally be omitted), a semiconductor material structure 32, and a conductive channel 19, such as a two-dimensional electron gas (2DEG), in the semiconductor material structure 32. The semiconductor material structure 32 includes a III-N channel layer 11 and a III-N barrier layer 12, where the compositions of layers 11 and 12 are selected to induce a 2DEG in the III-N channel layer 11 near the interface between the III-N channel layer 11 and the III-N barrier layer 12. The transistor further includes an insulating material 36, which includes a first insulating material layer 35 and a second insulating material layer 33. Alternatively, insulating material layers could be formed of the same insulating material, such that together they constitute a single material layer. The first insulating material layer 35 includes a gate insulator portion 17 in the gate region 31 beneath the gate 16 of the device, while the second insulating material layer 33 is in access regions 23 and 24 of the device. The transistor also includes a source 14, a drain 15, a gate 16, and a field plate 28. The gate 16 and field plate 28 are shown to be directly connected and together form electrode 29. However, they can alternatively be isolated from one another, such that they are not directly connected.
[0042] The slant field plate 28 shown in FIGS. 2-4 is formed of the same conducting material as the gate contact 16. Examples of such conducting materials are Ni, Pt, poly-silicon, Al, Ti, Au, or combinations thereof. Field plates can be used in semiconductor devices, such as transistors, to shape the electric field in the high-field region of the device in such a way that reduces the peak electric field and increases the device breakdown voltage, thereby allowing for higher voltage operation. A field plate does not necessarily need to be formed of the same material as the gate, and it does not necessarily need to be connected to the gate; in some cases, it can be connected to the source, the drain, an electrical ground or a DC voltage source. Insulating material layer 33 (shown in FIGS. 3-4 ) at least partially defines the geometry of the gate and field plate structures. In the implementation shown in FIG. 3 , for example, the insulating material layer 33 includes a slanted edge 34 on the drain side of the gate, and the field plate 28 is on top of and contacting slanted edge 34. Hence the field plate 28 is a “slant field plate”. The slanted edge 34 includes at least a substantial portion which is at a non-perpendicular angle to a main surface of the semiconductor material structure 32. Alternative field plate structures to a slant field plate may also be used.
[0043] The transistor in FIGS. 2-4 is a lateral device, having source and drain electrodes 14 and 15, respectively, on the same side of the semiconductor material structure 32. However, the transistor could be modified to be a vertical device, in which the drain 15 is on an opposite side of the semiconductor material structure 32 from the source. The device may further be any type of field effect transistor, and can be an enhancement-mode device (threshold voltage >0V), a depletion-mode device (threshold voltage <0V), a high-voltage device, or any combination of these devices. The device can be a III-polar (III-face) device, an N-polar (N-face) device, a non-polar, or a semipolar device. A Ga-face, III-face, or III-polar III-N device can include III-N materials grown with a group III-face or [0 0 0 1] face on an opposite side of the III-N materials from the growth substrate, or can include source, gate, and/or drain electrodes on a group III-face or [0 0 0 1] face of the III-N materials. A nitrogen-face, N-face, or N-polar III-N device can include III-N materials grown with an N-face or [0 0 0 1 bar] face on an opposite side of the III-N materials from the growth substrate, or can include source, gate, and/or drain electrodes on an N-face or [0 0 0 1 bar] face of the III-N materials.
[0044] Most conventional III-N high electron mobility transistors (HEMTs) and related transistor devices are normally on, i.e., have a negative threshold voltage, which means that they can conduct current when zero voltage is applied to the gate relative to the source. These devices with negative threshold voltages are known as depletion-mode (D-mode) devices. It can be preferable in some power electronics applications to have normally-off devices, i.e., devices with positive threshold voltages, that cannot conduct current when the gate and the source are at the same voltage, in order to avoid damage to the device or to other circuit components by preventing accidental turn-on of the device. Normally-off devices are commonly referred to as enhancement-mode (E-mode) devices. While the device illustrated in FIGS. 2-4 is a depletion-mode transistor, the structure could be modified to form an enhancement-mode transistor. For example, III-N barrier layer 12 could be recessed in the gate region 31, such that the 2DEG channel 19 is depleted of electrons in the gate region 31 at zero gate bias (relative to the source) but is not depleted when a sufficiently high positive voltage is applied to the gate 16 relative to the source 14.
[0045] As used herein, a “high-voltage device”, such as a high-voltage transistor, is an electronic device which is optimized for high-voltage switching applications. That is, when the transistor is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, about 1200V or higher, or about 1700V or higher, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, i.e., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block any voltage between 0V and at least Vmax, where Vmax is the maximum voltage that could be supplied by the circuit or power supply. In some implementations, a high-voltage device can block any voltage between 0V and at least 2*Vmax.
[0046] When a semiconductor device such as a transistor is operated in the off state, large electric fields may be present in the material layers, especially when the device is used in high-voltage applications. These large electric fields can result in the creation of holes, such as by impact ionization, in regions in which these electric fields are large. The holes, which have a positive electrical charge, migrate within the device structure towards regions of low electric potential (i.e., low voltage). The presence of these positively charged holes can lead to shifts in the device threshold voltage, increase in electron injection across the gate insulator, reduced reliability, and other undesirable effects. Hence, it is desirable to minimize or eliminate the effects of these holes.
[0047] Referring back to FIG. 2 , hole collector regions 20-22 are regions through which holes generated during device operation are collected. These holes can be passed to the gate 16 after being collected. Regions 20-22 can be doped, such as with Al, Mg, or Fe ions, for example by ion-implantation, and may be p-type, nominally p-type, or electrically insulating. As seen in FIG. 4 , regions 20-22 can extend through the channel region, thereby forming a break in the 2DEG channel 19. Regions 20-22 may be capable of conducting substantial hole currents, but not substantial electron currents. That is, in some implementations the maximum hole current density that can be conducted through regions 20-22 is at least 100 times the maximum electron current density that can be conducted through regions 20-22.
[0048] Hole collector regions 20-22 can be placed in regions of high electric field, or in the vicinity of regions of high electric fields, within the device. Since holes may be generated in regions where high electric fields exist during device operation, placing a hole collector region near the region where the holes are generated can improve hole collection efficiency. Examples of regions that typically have high electric fields (i.e., fields that are substantially larger, for example more than 10 times larger, than the average field in the vicinity of the source, gate, and drain electrodes) during device operation include the regions between the gate and the drain electrode, particularly near the drain-side edge of the gate electrode, or near or beneath the gate or a field plate.
[0049] Hole collector regions 20-22 can also be placed in regions of low voltage or low electric potential, or in the vicinity of regions of low voltage or low electric potential. Since holes are drawn towards regions of low voltage or low electric potential, placing a hole collector region near where the holes are drawn to can improve hole collection efficiency. Examples of regions that are typically at low voltage or low electric potential during device operation include regions near or beneath the source electrode, the regions near or beneath the gate electrode, regions near or beneath any of the device field plates, or the regions between the source and the gate electrode. In some cases, regions in the device that are a low electric potential during device operation are also regions that have a high electric field.
[0050] Once the holes approach or are incident upon the hole collector regions 20-22, they can be drawn away from the vicinity of the channel or other active regions of the device. For example, in some implementations, the holes can recombine with electrons near to or within the hole collector regions 20-22. In other implementations, a metal electrode, for example a portion of the gate or source, is connected to the surface of a hole collector region, the electrode being at a sufficiently low or negative voltage in order to carry the holes away through the electrode as an electrical current. Since the gate 16 and source 14 are typically at a low or negative voltage when the transistor is in the off state, the voltage on the gate or source may be sufficient to draw the holes away from the vicinity of the device channel or other active regions.
[0051] In order for the holes generated during device operation to pass from the hole collector regions 20-22 to the gate 16, it can be necessary for the gate metal 16 to electrically contact at least a portion of the regions 20-22. For example, the gate metal can directly contact the semiconductor material in regions 20-22. Alternatively, as seen in FIG. 4 , portion 17 of insulating material 36 (that is, the portion of insulating material 36 that is directly below the gate 16 in the gate region 31) can be sufficiently thin to allow holes collected in regions 20-22 to pass through portion 17 and into the gate 16, although the portions of insulating material 36 that are in or over the access regions 23 and 24 can be made thicker. In this case, at least a portion of each hole collector region 20-22 may need to be in the gate region 31.
[0052] In some implementations, keeping portion 17 of insulating material 36 less than 500 nanometers allows holes to be collected by the gate, while in other implementations portion 17 must be thinner than 100 nanometers, 70 nanometers, 50 nanometers, or 30 nanometers. The maximum thickness that region 17 can be made for which the gate 16 is operable to collect holes may depend on the particular material selected for portion 17 of insulating material 36. Typical examples of gate insulators that can be used for portion 17 of insulating material 36 include silicon nitride, silicon oxide, silicon dioxide, or aluminum nitride, although other dielectric materials may be used as well. In some implementations, the semiconductor material structure includes or is formed of III-N materials, and the device is a III-N device, such as a III-N transistor or FET. For example, channel layer 11 can be GaN and barrier layer 12 can be AlxGa1-xN.
[0053] Although not shown in FIGS. 2-4 , in some implementations the portion of the gate insulator 17 that is directly above the hole collector region 20-22 (e.g., the portion of gate insulator 17 shown in FIG. 4 ) can be thinned so that its thickness is less than that of the portion of the gate insulator 17 in the remaining parts of the device (e.g., the portion of gate insulator 17 shown in FIG. 3 ). This can allow for the gate insulator directly above the hole collector regions 20-22 to be thin enough to facilitate hole collection by the gate 16, while at the same time maintaining a thicker gate insulator directly over regions in which the device 2DEG channel is present, which can result in a reduction in gate leakage.
[0054] The separation between hole collector regions (labeled Wsep in FIG. 2 ) and the width of the hole collector regions (labeled Wh-c in FIG. 2 ), relative to the source width (labeled Wsource in FIG. 2 ) of the device, determine the maximum current level of the device. That is, if a device which is identical to that of FIGS. 2-4 but lacking the hole collector regions 20-22 has a maximum current level Jo, the maximum current level of the device of FIGS. 2-4 will equal I0*(Wsource−/Wh-c)/Wsource (where ΣWh-c is the sum of the widths of all the hole collector regions). Hence, for a given hole collector width Wh-c, if a higher maximum current level is desired, Wsep should be made larger, whereas for a smaller maximum current level Wsep should be made smaller. However, if Wsep is made too large, then holes generated directly in between adjacent hole collector regions may not be collected efficiently during device operation. Hence, the separation between hole collector regions cannot be made too large.
[0055] A set of III-N transistor devices such as the one illustrated in FIGS. 2-4 were fabricated with a gate length of 4 microns, a 28 nanometer thick SiN gate insulator, a hole collector region width Wh-c equal to 2 microns, and a hole collector separation width Wsep equal to 8 microns. The hole collector regions 20-22 were formed by ion-implanting aluminum (Al) ions into the III-N material layers. When the devices were subjected to conditions in which the gate-source voltage VGS was set to −30V (such that the devices were in the OFF state, since the gate-source voltage was less than the device threshold voltage), the drain-source voltage VDS was set to 480V (such that the devices were blocking 480V), and the ambient temperature was kept at room temperature (about 25° C.), most of the devices survived (i.e., were still operable) after 500 or more hours under the above conditions, and over half of the devices exhibited an off-state current density smaller than 10−4 mA/mm, indicating that the threshold voltages of these devices had not shifted substantially. Additionally, over 40% of the devices exhibited an off-state current density smaller than 10−4 mA/mm after 1000 hours under the above conditions. This result was unexpected and indicated that inclusion of the hole collector regions did in fact substantially improve the reliability of the devices. Furthermore, for a set of devices having a gate length of 1 micron, a hole collector region width Wh-c equal to 5 microns, and a hole collector separation width Wsep equal to 15 microns, at least 90% of the devices survived and exhibited an off-state current density smaller than 10−4 mA/mm after 1000 hours under the above conditions.
[0056] The above results indicated that a hole collector region separation of 15 microns or less, and/or a ratio Wh-c/(Wh-c+Wsep) of 0.2 or larger could result in the efficient collection of holes from the device during operation. Additional tests have indicated that a hole collector region separation of 30 microns or less, and/or a ratio Wh-c/(Wh-c+Wsep) of 0.05 or larger can in many cases result in the efficient collection of holes from the device during operation.
[0057] FIGS. 5-7 illustrate another transistor device for which holes generated during operation can be collected by the gate 16. FIG. 5 is a plan view (top view) of the device, FIG. 6 is a cross-sectional view along dashed line 6 in FIG. 5 , and FIG. 7 is a cross-sectional view of the device along dashed line 7 in FIG. 5 . The transistor of FIGS. 5-7 is similar to that of FIGS. 2-4 , except that hole collector regions 20-22 in the semiconductor material, shown in FIG. 2 , are omitted in the device of FIGS. 5-7 . Instead, holes generated during device operation are transported into and collected by the gate 16 in portions 25 where the gate insulator 35 is removed and the gate 16 directly contacts and forms a Schottky contact with the underlying semiconductor material, as further described below.
[0058] In some III-N transistors, in particular those used in high power or high voltage switching applications, a gate insulator is incorporated between the gate and the underlying semiconductor material in order to reduce gate leakage and/or to prevent premature breakdown of the device. The gate insulator is typically over the entire gate region of the semiconductor layers, with the gate over the gate insulator, such that the gate does not directly contact the underlying semiconductor material. However, in some transistors in which holes are generated during operation, inclusion of a gate insulator which prevents the gate from directly contacting the underlying semiconductor material can also prevent the gate from being able to collect the holes, which can result in device instability and other deleterious effects.
[0059] As seen in the transistor of FIGS. 6-7 , insulating material 36, which includes both insulating material layers 35 and 33, includes a portion 17 which is underneath the gate 16, i.e., between the gate 16 and the semiconductor material 32. Hence portion 17 acts as a gate insulator, as described above. However, as seen in FIGS. 5-6 , the gate region 31 also includes a portion or plurality of portions 25 in which the gate insulator 17 is removed or is not included, and the gate 16 directly contacts and forms a Schottky contact with the underlying semiconductor material 32 in portions 25. Hence, holes generated during operation of the transistor can be collected by the gate in portions 25 of the gate region 31.
[0060] While increasing the area of portions 25 can improve efficiency of hole collection, it may also lead to unacceptably high gate-drain leakage currents. The maximum amount of gate-drain leakage that can be tolerated, which at least partially determines the maximum total area of portions 25, depends on the particular application in which the transistor is used. For example, in some applications, sufficiently small leakage currents are achieved when the total area of the gate region outside of portions 25 is greater than the total area of portions 25. However, in applications in which only very small gate-drain leakage currents can be tolerated, the ratio of the total area of the gate region outside of portions 25 to the total area of portions 25 may need to be larger. For example, the total area of the gate region outside of portions 25 can be at least 2 times, at least 4 times, or at least 10 times that of the total area of portions 25.
[0061] Optionally, the transistor of FIGS. 5-7 may also include hole collector regions in the semiconductor material (not shown), with properties similar to or the same as hole collector regions 20-22 in FIGS. 2-4 . When hole collector regions are used, they can be at least partially in or under portion 25 of the gate region, such that the portion of the gate 16 that directly contacts the semiconductor material 32 also directly contacts the hole collector regions in the semiconductor material.
[0062] In an alternative implementation to that shown in FIGS. 5-7 , portions 25 can include a thin gate insulator layer between the gate 16 and the underlying semiconductor material layers. For example, referring to FIG. 6 , region 25 can include a layer of material 35 between the gate 16 and III-N barrier layer 12, where the thickness of material layer 35 is smaller in region 25 than in the remainder of the gate region 31. The gate insulator material in region 25 can be thin enough to allow for holes to be collected by the gate 16, while at the same time being thick enough to keep gate-drain leakage currents at a sufficiently low level.
[0063] Another transistor device for which holes generated during operation can be collected by the gate 16 is illustrated in FIGS. 8-10 . FIG. 8 is a plan view (top view) of the device, FIG. 9 is a cross-sectional view of the device along dashed line 8 in FIG. 8 , and FIG. 10 is a cross-sectional view of the device along dashed line 9 in FIG. 8 . In the device of FIGS. 8-10 , holes are transported out of the semiconductor material 32 and collected through electrically conductive portions 40, which extend downwards from field plate 28 in regions 42 (best seen in FIGS. 8 and 10 ). As shown, electrically conductive portion 40 is electrically connected to the source 14 and to the field plate 28, resulting in holes being collected by the source 14 and/or field plate 28, and not by the gate 16.
[0064] Similarly to the transistors of previous implementations, the transistor of FIGS. 8-10 includes a III-N material structure 32 which includes a III-N channel layer 11 and a III-N barrier layer 12. The transistor also optionally includes a substrate 10 upon which the III-N material structure 32 is grown or deposited. The transistor may also be an enhancement-mode device. As seen in FIG. 9 , a recess formed in the III-N barrier layer 12 beneath the gate electrode causes the conductive 2DEG channel 19 to be depleted of electrons in the gate region 31 when zero volts is applied to the gate 16 relative to the source 14, such that the device is in the off state. A sufficiently large positive voltage must be applied to the gate 16 relative to the source 14 to induce charge in the portion of the channel in the gate region, in order to turn the device on. Alternatively, the transistor can be made to be an E-mode device through alternative designs, for example by including a p-type III-N layer directly on the III-N barrier layer below the gate 16 in the gate region 31.
[0065] Referring to FIGS. 9 and 10 , a gate insulator layer 44 is included in the gate region 31 between the gate electrode 16 and the III-N semiconductor material structure 32. The gate insulator layer 44 may optionally also extend to and at least partially cover the semiconductor material in the access regions 23 and 24, as shown. After depositing the gate 16 on the gate insulator layer 44, an additional insulator layer 43 is deposited over the gate 16 and over the gate insulator layer 44, as shown.
[0066] As seen in FIGS. 8 and 10 , the field plate 28 is directly on the additional insulator layer 43 and is electrically connected to the source 14 by conductive extending portions 41. The additional insulator layer 43 separates the field plate 28 from the gate 16 and prevents the field plate 28 and the gate 16 from being electrically connected, thereby ensuring that the gate 16 and the field plate 28 are electrically isolated from one another. As used herein, two or more contacts or other elements such as conductive layers or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting so that the electric potential at each of the contacts or other elements will be similar, e.g., about the same or substantially the same, during operation. As used herein, elements which are not electrically connected are said to be “electrically isolated”. Electrically isolated elements, although not maintained at substantially the same potential at all times, can be capacitively or inductively coupled.
[0067] Still referring to FIGS. 8 and 10 , gate 16 covers the entire gate region 31 of the III-N material structure 32 except in regions 42, in which the gate 16 is removed or is not included. Electrically conductive portions 40, which are electrically connected to the source 14 and to the field plate 28, extend downwards through the gate insulator layer 44 and contact the III-N material structure 32 in regions 42. Optionally, as illustrated in FIG. 10 , a hole collector region 20 can also be included in the III-N material structure 32 in region 42. In applications in which the hole collector region also serves to limit the maximum channel current that can flow through the device, the hole collector region may need to at least be under the side of the gate 16 that is closest to the source 14. That is, the hole collector region can include a first portion which is in the source access region 23 and a second portion which is in the gate region 31, as illustrated in FIGS. 10 and 11 . While not shown in FIGS. 10 and 11 , the hole collector region 20 can also extend into the drain access region 24; that is, it can include a third portion which is in the drain access region 24. In devices with shorter gate lengths, having the hole collector region 20 extend into the drain access region 24 can result in the device being more easily manufacturable.
[0068] As illustrated in FIG. 11 , in an alternative configuration to that shown in FIG. 10 , the electrically conductive portion 40 may only extend partially through the gate insulator layer 44, such that the separation between the electrically conductive portion 40 and the III-N material structure 32 is less than or equal to the separation between the gate 16 and the III-N material structure 32. In this case, the resistance between the electrically conductive portion 40 and the hole collector region 20 can be less than the resistance between the gate 16 and the hole collector region 20, resulting in holes being collected by the source 14 rather than by the gate 16. In particular, the resistance to hole current flow between the electrically conductive portion 40 and the hole collector region 20 can be less than the resistance to hole current flow between the gate 16 and the hole collector region 20. An alternative way to ensure that holes are collected by the source 14 rather than by the gate 16 is to design the structure of FIGS. 10 and 11 such that the resistance (e.g., the total resistance and/or the resistance to hole current flow) between the hole collector region 20 and either the source 14 or field plate 28 is less than the resistance between the hole collector region 20 and the gate 16.
[0069] In some applications in which the transistor devices of FIGS. 2-11 are used, the transistor is operated in several different modes. For example, when the transistor is used as one of the switches in a half-bridge circuit configuration, at some times, the transistor is operated in a first mode in which the gate of the transistor is biased relative to the source at a voltage lower than the device threshold voltage (for example 0V if the transistor is an enhancement-mode transistor), the drain is biased at a high positive voltage relative to the source, and the transistor blocks the positive voltage applied to the drain relative to the source. At other times, the transistor is operated in a second mode in which the device conducts current from the source to the drain when the gate of the transistor is biased relative to the source at a voltage lower than the device threshold voltage (for example 0V if the transistor is an enhancement-mode transistor), and the drain is at a negative voltage relative to the source. This second mode of operation is often referred to as the “reverse-conduction mode” or “diode mode”. At still other times, the transistor is operated in a third mode in which the device conducts current from the drain to the source when the gate of the transistor is biased relative to the source at a voltage higher than the device threshold voltage, and the drain is at a positive voltage relative to the source. This third mode is typically referred to as “standard conduction mode”.
[0070] As used herein, the term “blocking a voltage” refers to the ability of a transistor, diode, device, or component to prevent significant current, e.g., current that is greater than 0.001 times the average operating current during regular on-state conduction, from flowing through the transistor, diode, device, or component when a voltage is applied across the transistor, diode, device, or component. In other words, while a transistor, diode, device, or component is blocking a voltage that is applied across it, the total current passing through the transistor, diode, device, or component will not be greater than 0.001 times the average operating current during regular on-state conduction.
[0071] When the transistor is operated in standard conduction mode, all substantial current flows from the drain to the source (i.e., electrons flow from the source to the drain) directly through the entire length of the 2DEG channel. In the case of diode mode operation (i.e., the second mode of operation), it may be preferable that all substantial current also flow from the source to the drain (i.e., electrons flow from the drain to the source) through the entire length of the 2DEG channel, as this can reduce switching losses. In the case of the transistor of FIGS. 8-10 , a diode may be formed between the hole collector region 20 and semiconductor material between the hole collector region 20 and the drain 15. During the first and third modes of operation described above, the diode is reverse biased. However, during the second mode of operation, when the drain 15 is at a lower voltage than the source, the diode becomes forward biased. If the turn-on voltage of the diode is too low (i.e., lower than the source-drain voltage required to conduct the total current through the entire length of the channel), then the diode turns on, resulting in at least some substantial source-drain current flowing from the source to the drain through electrically conductive portion 40. This would result in the diode switching from off to on during operation, which can result in undesirable effects such as increased switching losses during operation. As such, it is typically preferable to design the hole collector region 20 such that the diode has a turn-on voltage which is sufficiently large to prevent substantial current from flowing through the contact between the electrically conductive portion 40 and the hole collector region 20 during the second mode of operation. Increasing the turn-on voltage can be achieved in a number of ways, for example by choosing a metal for electrically conductive portion 40 with a large work function, or by performing a treatment to the surface of the III-N material on which the electrically conductive portion 40 is deposited on and contacts.
[0072] In all implementations described herein, hole collector regions can have the following properties. They can be regions in which the semiconductor material is etched, in some cases at least through the device channel. In this case, a metal electrode or a portion of the source or gate metal may electrically contact at least a portion of the semiconductor surface which was exposed by the etch. Alternatively, they can be doped regions (for example doped by ion implantation) in the semiconductor material, where the implanted regions can extend through the channel region, thereby forming a break in the device channel. Doped regions such as ion implanted regions may be capable of conducting substantial hole, but not substantial electron currents. For example they can be p-type or nominally p-type regions.
[0073] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. For example, in devices in which the electrode (or portion of the electrode) which collects holes is separated from the underlying III-N materials by an insulating layer (for example, the devices shown in FIGS. 2-4 and 11 ), it may be preferable to select an insulator layer for which the valence band edge in the insulator layer is higher than that in the III-N barrier layer at the interface between the insulator layer and the barrier layer. Such a configuration can result in more efficient collection of holes. Alternatively, efficient collection of holes may still be possible in structures where the valence band edge in the insulator layer is lower than that in the III-N barrier layer at the interface between the insulator layer and the barrier layer, provided the valence band discontinuity at this interface is less than 2 electron-volts. Accordingly, other implementations are within the scope of the following claims.
Claims
The invention claimed is:
1. A transistor device, comprising:
a source, a gate, and a drain;
a semiconductor material which includes a gate region between the source and the drain;
a channel in the semiconductor material;
an insulating material between the gate and the semiconductor material; and
a field plate over the insulating material;
wherein an electrically conductive portion extending from the source or from the field plate contacts the semiconductor material in the gate region; and
wherein the transistor device is an enhancement-mode transistor.
2. The transistor device of claim 1, wherein the insulating material prevents the gate from contacting the semiconductor material in the gate region.
3. The transistor device of claim 1, wherein the field plate is electrically connected to the source.
4. The transistor device of claim 1, wherein in operation, the channel is not conductive when 0V is applied to the gate relative to the source and a voltage greater than 0V is applied to the drain relative to the source, but is conductive when a switching voltage greater than a device threshold voltage is applied to the gate relative to the source.
5. The transistor device of claim 1, further comprising a hole collector region in the gate region of the semiconductor material, wherein the electrically conductive portion contacts the hole collector region.
6. The transistor device of claim 5, wherein in a first mode of operation, the device is operable to block a positive voltage applied to the drain relative to the source when 0V is applied to the gate relative to the source, and in a second mode of operation, the device is operable to conduct current from the source to the drain when 0V is applied to the gate relative to the source and the drain is at a negative voltage relative to the source.
7. The transistor device of claim 6, the contact between the electrically conductive portion and the hole collector region having a turn-on voltage, wherein the turn-on voltage is sufficiently large to prevent substantial current from flowing through the contact between the electrically conductive portion and the hole collector region during the second mode of operation.
8. The transistor device of claim 1, wherein the semiconductor material includes a III-N channel layer and a III-N barrier layer, the channel being in the III-N channel layer adjacent to the III-N barrier layer.
Patent Citations (278)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4300091(A) | 1981-11-01 | Schade, Jr. | Applicant |
| US4645562(A) | 1987-02-01 | Liao et al. | Applicant |
| US4728826(A) | 1988-03-01 | Einzinger et al. | Applicant |
| US4821093(A) | 1989-04-01 | Iafrate et al. | Applicant |
| US4914489(A) | 1990-04-01 | Awano | Applicant |
| US5051618(A) | 1991-09-01 | Lou | Applicant |
| US5329147(A) | 1994-07-01 | Vo et al. | Applicant |
| US5618384(A) | 1997-04-01 | Chan et al. | Applicant |
| US5646069(A) | 1997-07-01 | Jelloian et al. | Applicant |
| US5663091(A) | 1997-09-01 | Yen et al. | Applicant |
| US5705847(A) | 1998-01-01 | Kashiwa et al. | Applicant |
| US5714393(A) | 1998-02-01 | Wild et al. | Applicant |
| US5909103(A) | 1999-06-01 | Williams | Applicant |
| US5998810(A) | 1999-12-01 | Hatano et al. | Applicant |
| US6008684(A) | 1999-12-01 | Ker et al. | Applicant |
| US6097046(A) | 2000-08-01 | Plumton | Applicant |
| US6100571(A) | 2000-08-01 | Mizuta et al. | Applicant |
| US6307220(B1) | 2001-10-01 | Yamazaki | Applicant |
| US6316793(B1) | 2001-11-01 | Sheppard et al. | Applicant |
| US6373082(B1) | 2002-04-01 | Ohno et al. | Applicant |
| US6475889(B1) | 2002-11-01 | Ring | Applicant |
| US6486502(B1) | 2002-11-01 | Sheppard et al. | Applicant |
| US6504235(B2) | 2003-01-01 | Schmitz et al. | Applicant |
| US6515303(B2) | 2003-02-01 | Ring | Applicant |
| US6548333(B2) | 2003-04-01 | Smith | Applicant |
| US6583454(B2) | 2003-06-01 | Sheppard et al. | Applicant |
| US6586781(B2) | 2003-07-01 | Wu et al. | Applicant |
| US6649497(B2) | 2003-11-01 | Ring | Applicant |
| US6727531(B1) | 2004-04-01 | Redwing et al. | Applicant |
| US6777278(B2) | 2004-08-01 | Smith | Applicant |
| US6849882(B2) | 2005-02-01 | Chavarkar et al. | Applicant |
| US6867078(B1) | 2005-03-01 | Green et al. | Applicant |
| US6946739(B2) | 2005-09-01 | Ring | Applicant |
| US6979863(B2) | 2005-12-01 | Ryu | Applicant |
| US6982204(B2) | 2006-01-01 | Saxler et al. | Applicant |
| US7030428(B2) | 2006-04-01 | Saxler | Applicant |
| US7045404(B2) | 2006-05-01 | Sheppard et al. | Applicant |
| US7071498(B2) | 2006-07-01 | Johnson et al. | Applicant |
| US7084475(B2) | 2006-08-01 | Shelton et al. | Applicant |
| US7125786(B2) | 2006-10-01 | Ring et al. | Applicant |
| US7126212(B2) | 2006-10-01 | Enquist et al. | Applicant |
| US7161194(B2) | 2007-01-01 | Parikh et al. | Applicant |
| US7170111(B2) | 2007-01-01 | Saxler | Applicant |
| US7230284(B2) | 2007-06-01 | Parikh et al. | Applicant |
| US7238560(B2) | 2007-07-01 | Sheppard et al. | Applicant |
| US7253454(B2) | 2007-08-01 | Saxler | Applicant |
| US7265399(B2) | 2007-09-01 | Sriram et al. | Applicant |
| US7268375(B2) | 2007-09-01 | Shur et al. | Applicant |
| US7304331(B2) | 2007-12-01 | Saito et al. | Applicant |
| US7321132(B2) | 2008-01-01 | Robinson et al. | Applicant |
| US7326971(B2) | 2008-02-01 | Harris et al. | Applicant |
| US7332795(B2) | 2008-02-01 | Smith et al. | Applicant |
| US7364988(B2) | 2008-04-01 | Harris et al. | Applicant |
| US7388236(B2) | 2008-06-01 | Wu et al. | Applicant |
| US7419892(B2) | 2008-09-01 | Sheppard et al. | Applicant |
| US7432142(B2) | 2008-10-01 | Saxler et al. | Applicant |
| US7449730(B2) | 2008-11-01 | Kuraguchi | Applicant |
| US7456443(B2) | 2008-11-01 | Saxler et al. | Applicant |
| US7465967(B2) | 2008-12-01 | Smith et al. | Applicant |
| US7501669(B2) | 2009-03-01 | Parikh et al. | Applicant |
| US7544963(B2) | 2009-06-01 | Saxler | Applicant |
| US7547925(B2) | 2009-06-01 | Wong et al. | Applicant |
| US7548112(B2) | 2009-06-01 | Sheppard | Applicant |
| US7550783(B2) | 2009-06-01 | Wu et al. | Applicant |
| US7550784(B2) | 2009-06-01 | Saxler et al. | Applicant |
| US7566918(B2) | 2009-07-01 | Wu et al. | Applicant |
| US7573078(B2) | 2009-08-01 | Wu et al. | Applicant |
| US7592211(B2) | 2009-09-01 | Sheppard et al. | Applicant |
| US7598108(B2) | 2009-10-01 | Li et al. | Applicant |
| US7612390(B2) | 2009-11-01 | Saxler et al. | Applicant |
| US7615774(B2) | 2009-11-01 | Saxler | Applicant |
| US7638818(B2) | 2009-12-01 | Wu et al. | Applicant |
| US7678628(B2) | 2010-03-01 | Sheppard et al. | Applicant |
| US7692263(B2) | 2010-04-01 | Wu et al. | Applicant |
| US7709269(B2) | 2010-05-01 | Smith et al. | Applicant |
| US7709859(B2) | 2010-05-01 | Smith et al. | Applicant |
| US7714360(B2) | 2010-05-01 | Otsuka et al. | Applicant |
| US7745851(B2) | 2010-06-01 | Harris | Applicant |
| US7755108(B2) | 2010-07-01 | Kuraguchi | Applicant |
| US7759700(B2) | 2010-07-01 | Ueno et al. | Applicant |
| US7777252(B2) | 2010-08-01 | Sugimoto et al. | Applicant |
| US7777254(B2) | 2010-08-01 | Sato | Applicant |
| US7795642(B2) | 2010-09-01 | Suh et al. | Applicant |
| US7812369(B2) | 2010-10-01 | Chini et al. | Applicant |
| US7855401(B2) | 2010-12-01 | Sheppard et al. | Applicant |
| US7875537(B2) | 2011-01-01 | Suvorov et al. | Applicant |
| US7875914(B2) | 2011-01-01 | Sheppard | Applicant |
| US7884395(B2) | 2011-02-01 | Saito | Applicant |
| US7892974(B2) | 2011-02-01 | Ring et al. | Applicant |
| US7893500(B2) | 2011-02-01 | Wu et al. | Applicant |
| US7898004(B2) | 2011-03-01 | Wu et al. | Applicant |
| US7901994(B2) | 2011-03-01 | Saxler et al. | Applicant |
| US7906799(B2) | 2011-03-01 | Sheppard et al. | Applicant |
| US7915643(B2) | 2011-03-01 | Suh et al. | Applicant |
| US7915644(B2) | 2011-03-01 | Wu et al. | Applicant |
| US7919791(B2) | 2011-04-01 | Flynn et al. | Applicant |
| US7928475(B2) | 2011-04-01 | Parikh et al. | Applicant |
| US7955918(B2) | 2011-06-01 | Wu et al. | Applicant |
| US7955984(B2) | 2011-06-01 | Ohki | Applicant |
| US7960756(B2) | 2011-06-01 | Sheppard et al. | Applicant |
| US7965126(B2) | 2011-06-01 | Honea et al. | Applicant |
| US7985986(B2) | 2011-07-01 | Heikman et al. | Applicant |
| US8049252(B2) | 2011-11-01 | Smith et al. | Applicant |
| US8519438(B2) | 2013-08-01 | Mishra et al. | Applicant |
| US8525231(B2) | 2013-09-01 | Park et al. | Applicant |
| US2001/0032999(A1) | 2001-10-01 | Yoshida | Applicant |
| US2001/0040247(A1) | 2001-11-01 | Ando et al. | Applicant |
| US2002/0036287(A1) | 2002-03-01 | Yu et al. | Applicant |
| US2002/0121648(A1) | 2002-09-01 | Hsu et al. | Applicant |
| US2002/0163042(A1) | 2002-11-01 | Yamazaki et al. | Applicant |
| US2002/0167023(A1) | 2002-11-01 | Chavarkar et al. | Applicant |
| US2003/0003724(A1) | 2003-01-01 | Uchiyama et al. | Applicant |
| US2003/0006437(A1) | 2003-01-01 | Mizuta et al. | Applicant |
| US2003/0020092(A1) | 2003-01-01 | Parikh et al. | Applicant |
| US2004/0041169(A1) | 2004-03-01 | Ren et al. | Applicant |
| US2004/0061129(A1) | 2004-04-01 | Saxler et al. | Applicant |
| US2004/0164347(A1) | 2004-08-01 | Zhao et al. | Applicant |
| US2005/0001235(A1) | 2005-01-01 | Murata et al. | Applicant |
| US2005/0077541(A1) | 2005-04-01 | Shen et al. | Applicant |
| US2005/0133816(A1) | 2005-06-01 | Fan et al. | Applicant |
| US2005/0189561(A1) | 2005-09-01 | Kinzer et al. | Applicant |
| US2005/0189562(A1) | 2005-09-01 | Kinzer et al. | Applicant |
| US2005/0194612(A1) | 2005-09-01 | Beach | Applicant |
| US2005/0253168(A1) | 2005-11-01 | Wu et al. | Applicant |
| US2005/0274977(A1) | 2005-12-01 | Saito et al. | Applicant |
| US2006/0011915(A1) | 2006-01-01 | Saito et al. | Applicant |
| US2006/0043499(A1) | 2006-03-01 | De Cremoux et al. | Applicant |
| US2006/0060871(A1) | 2006-03-01 | Beach | Applicant |
| US2006/0076677(A1) | 2006-04-01 | Daubenspeck et al. | Applicant |
| US2006/0102929(A1) | 2006-05-01 | Okamoto et al. | Applicant |
| US2006/0108602(A1) | 2006-05-01 | Tanimoto | Applicant |
| US2006/0108605(A1) | 2006-05-01 | Yanagihara et al. | Applicant |
| US2006/0121682(A1) | 2006-06-01 | Saxler | Applicant |
| US2006/0124962(A1) | 2006-06-01 | Ueda et al. | Applicant |
| US2006/0157729(A1) | 2006-07-01 | Ueno et al. | Applicant |
| US2006/0186422(A1) | 2006-08-01 | Gaska et al. | Applicant |
| US2006/0189109(A1) | 2006-08-01 | Fitzgerald | Applicant |
| US2006/0202272(A1) | 2006-09-01 | Wu et al. | Applicant |
| US2006/0220063(A1) | 2006-10-01 | Kurachi et al. | Applicant |
| US2006/0226442(A1) | 2006-10-01 | Zhang et al. | Applicant |
| US2006/0255364(A1) | 2006-11-01 | Saxler et al. | Applicant |
| US2006/0289901(A1) | 2006-12-01 | Sheppard et al. | Applicant |
| US2007/0007547(A1) | 2007-01-01 | Beach | Applicant |
| US2007/0018187(A1) | 2007-01-01 | Lee et al. | Applicant |
| US2007/0018199(A1) | 2007-01-01 | Sheppard et al. | Applicant |
| US2007/0018210(A1) | 2007-01-01 | Sheppard | Applicant |
| US2007/0045670(A1) | 2007-03-01 | Kuraguchi | Applicant |
| US2007/0080672(A1) | 2007-04-01 | Yang | Applicant |
| US2007/0128743(A1) | 2007-06-01 | Huang et al. | Applicant |
| US2007/0131968(A1) | 2007-06-01 | Morita et al. | Applicant |
| US2007/0132037(A1) | 2007-06-01 | Hoshi et al. | Applicant |
| US2007/0134834(A1) | 2007-06-01 | Lee et al. | Applicant |
| US2007/0145390(A1) | 2007-06-01 | Kuraguchi | Applicant |
| US2007/0145417(A1) | 2007-06-01 | Brar et al. | Applicant |
| US2007/0158692(A1) | 2007-07-01 | Nakayama et al. | Applicant |
| US2007/0164315(A1) | 2007-07-01 | Smith et al. | Applicant |
| US2007/0164322(A1) | 2007-07-01 | Smith et al. | Applicant |
| US2007/0194354(A1) | 2007-08-01 | Wu et al. | Applicant |
| US2007/0205433(A1) | 2007-09-01 | Parikh et al. | Applicant |
| US2007/0210329(A1) | 2007-09-01 | Goto | Applicant |
| US2007/0215899(A1) | 2007-09-01 | Herman | Applicant |
| US2007/0224710(A1) | 2007-09-01 | Palacios et al. | Applicant |
| US2007/0228477(A1) | 2007-10-01 | Suzuki et al. | Applicant |
| US2007/0241368(A1) | 2007-10-01 | Mil'shtein et al. | Applicant |
| US2007/0249119(A1) | 2007-10-01 | Saito | Applicant |
| US2007/0278518(A1) | 2007-12-01 | Chen et al. | Applicant |
| US2007/0295985(A1) | 2007-12-01 | Weeks, Jr. et al. | Applicant |
| US2008/0073670(A1) | 2008-03-01 | Yang et al. | Applicant |
| US2008/0093626(A1) | 2008-04-01 | Kuraguchi | Applicant |
| US2008/0121876(A1) | 2008-05-01 | Otsuka et al. | Applicant |
| US2008/0121933(A1) | 2008-05-01 | Hayashi et al. | Applicant |
| US2008/0157121(A1) | 2008-07-01 | Ohki | Applicant |
| US2008/0173944(A1) | 2008-07-01 | Coronel et al. | Applicant |
| US2008/0203430(A1) | 2008-08-01 | Simin et al. | Applicant |
| US2008/0230784(A1) | 2008-09-01 | Murphy | Applicant |
| US2008/0237606(A1) | 2008-10-01 | Kikkawa et al. | Applicant |
| US2008/0237640(A1) | 2008-10-01 | Mishra et al. | Applicant |
| US2008/0274574(A1) | 2008-11-01 | Yun | Applicant |
| US2008/0283844(A1) | 2008-11-01 | Hoshi et al. | Applicant |
| US2008/0296618(A1) | 2008-12-01 | Suh et al. | Applicant |
| US2008/0308813(A1) | 2008-12-01 | Suh et al. | Applicant |
| US2009/0001409(A1) | 2009-01-01 | Takano et al. | Applicant |
| US2009/0032820(A1) | 2009-02-01 | Chen | Applicant |
| US2009/0032879(A1) | 2009-02-01 | Kuraguchi | Applicant |
| US2009/0045438(A1) | 2009-02-01 | Inoue et al. | Applicant |
| US2009/0050936(A1) | 2009-02-01 | Oka | Applicant |
| US2009/0065810(A1) | 2009-03-01 | Honea et al. | Applicant |
| US2009/0072240(A1) | 2009-03-01 | Suh et al. | Applicant |
| US2009/0072269(A1) | 2009-03-01 | Suh et al. | Applicant |
| US2009/0072272(A1) | 2009-03-01 | Suh et al. | Applicant |
| US2009/0075455(A1) | 2009-03-01 | Mishra | Applicant |
| US2009/0085065(A1) | 2009-04-01 | Mishra et al. | Applicant |
| US2009/0121775(A1) | 2009-05-01 | Ueda et al. | Applicant |
| US2009/0140262(A1) | 2009-06-01 | Ohki et al. | Applicant |
| US2009/0152613(A1) | 2009-06-01 | Kim | Applicant |
| US2009/0201072(A1) | 2009-08-01 | Honea et al. | Applicant |
| US2009/0218598(A1) | 2009-09-01 | Goto | Applicant |
| US2009/0267078(A1) | 2009-10-01 | Mishra et al. | Applicant |
| US2010/0019225(A1) | 2010-01-01 | Lee | Applicant |
| US2010/0019279(A1) | 2010-01-01 | Chen et al. | Applicant |
| US2010/0065923(A1) | 2010-03-01 | Charles et al. | Applicant |
| US2010/0067275(A1) | 2010-03-01 | Wang et al. | Applicant |
| US2010/0133506(A1) | 2010-06-01 | Nakanishi et al. | Applicant |
| US2010/0140660(A1) | 2010-06-01 | Wu et al. | Applicant |
| US2010/0201439(A1) | 2010-08-01 | Wu et al. | Applicant |
| US2010/0203234(A1) | 2010-08-01 | Anderson et al. | Applicant |
| US2010/0219445(A1) | 2010-09-01 | Yokoyama et al. | Applicant |
| US2010/0244087(A1) | 2010-09-01 | Horie et al. | Applicant |
| US2010/0264461(A1) | 2010-10-01 | Rajan et al. | Applicant |
| US2010/0288998(A1) | 2010-11-01 | Kikuchi et al. | Applicant |
| US2011/0006346(A1) | 2011-01-01 | Ando et al. | Applicant |
| US2011/0012110(A1) | 2011-01-01 | Sazawa et al. | Applicant |
| US2011/0049526(A1) | 2011-03-01 | Chu et al. | Applicant |
| US2011/0249359(A1) | 2011-10-01 | Mochizuki et al. | Applicant |
| US2012/0126287(A1) | 2012-05-01 | Aoki | Examiner |
| US2012/0168822(A1) | 2012-07-01 | Matsushita | Applicant |
| US2012/0193638(A1) | 2012-08-01 | Keller et al. | Applicant |
| US2012/0211760(A1) | 2012-08-01 | Yamada | Applicant |
| US2012/0211800(A1) | 2012-08-01 | Boutros | Applicant |
| US2012/0217512(A1) | 2012-08-01 | Renaud | Applicant |
| US2012/0218783(A1) | 2012-08-01 | Imada | Examiner |
| US2012/0267639(A1) | 2012-10-01 | Jeon | Examiner |
| US2012/0315445(A1) | 2012-12-01 | Mizuhara et al. | Applicant |
| US2013/0292699(A1) | 2013-11-01 | Ueno | Examiner |
| US2013/0328061(A1) | 2013-12-01 | Chu et al. | Applicant |
| US2014/0001557(A1) | 2014-01-01 | Mishra et al. | Applicant |
| US2014/0084346(A1) | 2014-03-01 | Tajiri | Applicant |
| CN1748320 | 2006-03-01 | Applicant | |
| CN101107713 | 2008-01-01 | Applicant | |
| CN101312207 | 2008-11-01 | Applicant | |
| CN101897029 | 2010-11-01 | Applicant | |
| CN102017160 | 2011-04-01 | Applicant | |
| CN103477543 | 2013-12-01 | Applicant | |
| CN103493206 | 2014-01-01 | Applicant | |
| EP1998376 | 2008-12-01 | Applicant | |
| EP2188842 | 2010-05-01 | Applicant | |
| JP11-224950 | 1999-08-01 | Applicant | |
| JP2000-058871 | 2000-02-01 | Applicant | |
| JP2003-229566 | 2003-08-01 | Applicant | |
| JP2003-244943 | 2003-08-01 | Applicant | |
| JP2004-260114 | 2004-09-01 | Applicant | |
| JP2006-032749 | 2006-02-01 | Applicant | |
| JP2006-033723 | 2006-02-01 | Applicant | |
| JP2007-036218 | 2007-02-01 | Applicant | |
| JP2007-215331 | 2007-08-01 | Applicant | |
| JP2008-199771 | 2008-08-01 | Applicant | |
| JP2010-087076 | 2010-04-01 | Applicant | |
| JP2010-539712 | 2010-12-01 | Applicant | |
| KR10-0847306 | 2008-07-01 | Applicant | |
| TW200924068 | 2009-06-01 | Applicant | |
| TW200924201 | 2009-06-01 | Applicant | |
| TW200947703 | 2009-11-01 | Applicant | |
| TW201010076 | 2010-03-01 | Applicant | |
| TW201027759 | 2010-07-01 | Applicant | |
| TW201027912 | 2010-07-01 | Applicant | |
| TW201036155 | 2010-10-01 | Applicant | |
| TW201322443 | 2013-06-01 | Applicant | |
| WO2004/070791 | 2004-08-01 | Applicant | |
| WO2004/098060 | 2004-11-01 | Applicant | |
| WO2005/070007 | 2005-08-01 | Applicant | |
| WO2005/070009 | 2005-08-01 | Applicant | |
| WO2006/114883 | 2006-11-01 | Applicant | |
| WO2007/077666 | 2007-07-01 | Applicant | |
| WO2007/108404 | 2007-09-01 | Applicant | |
| WO2008/120094 | 2008-10-01 | Applicant | |
| WO2009/036181 | 2009-03-01 | Applicant | |
| WO2009/036266 | 2009-03-01 | Applicant | |
| WO2009/039028 | 2009-03-01 | Applicant | |
| WO2009/039041 | 2009-03-01 | Applicant | |
| WO2009/076076 | 2009-06-01 | Applicant | |
| WO2009/132039 | 2009-10-01 | Applicant | |
| WO2010/039463 | 2010-04-01 | Applicant | |
| WO2010/068554 | 2010-06-01 | Applicant | |
| WO2010/090885 | 2010-08-01 | Applicant | |
| WO2010/132587 | 2010-11-01 | Applicant | |
| WO2011/031431 | 2011-03-01 | Applicant | |
| WO2011/072027 | 2011-06-01 | Applicant | |
| WO2013/052833 | 2013-04-01 | Applicant |
Non-Patent Literature (97)
- Authorized officer Chung Keun Lee, International Search Report and Written Opinion in PCT/US2008/076030, mailed Mar. 23, 2009, 10 pages.Applicant
- Authorized officer Yolaine Cussac, International Preliminary Report on Patentability in PCT/US2008/076030, Mar. 25, 2010, 5 pages.Applicant
- Authorized officer Chung Keun Lee, International Search Report and Written Opinion in PCT/US2008/076079, mailed Mar. 20, 2009, 11 pages.Applicant
- Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2008/076079, mailed Apr. 1, 2010, 6 pages.Applicant
- Authorized officer Keon Hyeong Kim, International Search Report and Written Opinion in PCT/US2008/076160 mailed Mar. 18, 2009, 11 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2008/076160, mailed Mar. 25, 2010, 6 pages.Applicant
- Authorized officer Chung Keun Lee, International Search Report and Written Opinion in PCT/US2008/076199, mailed Mar. 24, 2009, 11 pages.Applicant
- Authorized officer Dorothée Mülhausen, International Preliminary Report on Patentability in PCT/US2008/076199, mailed Apr. 1, 2010, 6 pages.Applicant
- Authorized officer Keon Hyeong Kim, International Search Report and Written Opinion in PCT/US2008/085031, mailed Jun. 24, 2009, 11 pages.Applicant
- Authorized officer Yolaine Cussac, International Preliminary Report on Patentability in PCT/US2008/085031, mailed Jun. 24, 2010, 6 pages.Applicant
- Authorized officer Tae Hoon Kim, International Search Report and Written Opinion in PCT/US2009/041304, mailed Dec. 18, 2009, 13 pages.Applicant
- Authorized officer Dorothée Mülhausen, International Preliminary Report on Patentability, in PCT/US2009/041304, mailed Nov. 4, 2010, 8 pages.Applicant
- Authorized officer Sung Hee Kim, International Search Report and the Written Opinion in PCT/US2009/057554, mailed May 10, 2010, 13 pages.Applicant
- Authorized Officer Gijsbertus Beijer, International Preliminary Report on Patentability in PCT/US2009/057554, mailed Mar. 29, 2011, 7 pages.Applicant
- Authorized officer Cheon Whan Cho, International Search Report and Written Opinion in PCT/US2009/066647, mailed Jul. 1, 2010, 16 pages.Applicant
- Authorized officer Athina Nikitas-Etienne, International Preliminary Report on Patentability in PCT/US2009/066647, mailed Jun. 23, 2011, 12 pages.Applicant
- Authorized officer Sung Chan Chung, International Search Report and Written Opinion for PCT/US2010/021824, mailed Aug. 23, 2010, 9 pages.Applicant
- Authorized officer Beate Giffo-Schmitt, International Preliminary Report on Patentability in PCT/US2010/021824, mailed Aug. 18, 2011, 6 pages.Applicant
- Authorized officer Sang Ho Lee, International Search Report and Written Opinion in PCT/US2010/034579, mailed Dec. 24, 2010, 9 pages.Applicant
- Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2010/034579, mailed Nov. 24, 2011, 7 pages.Applicant
- Authorized officer Jeongmin Choi, International Search Report and Written Opinion in PCT/US2010/046193, mailed Apr. 26, 2011, 13 pages.Applicant
- Authorized officer Philippe Bécamel, International Preliminary Report on Patentability in PCT/US2010/046193, mailed Mar. 8, 2012, 10 pages.Applicant
- Authorized officer Sang Ho Lee, International Search Report and Written Opinion in PCT/US2010/059486, mailed Jul. 26, 2011, 9 pages.Applicant
- Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2010/059486, mailed Jun. 21, 2012, 6 pages.Applicant
- Authorized officer Kwan Sik Sul, International Search Report and Written Opinion in PCT/US2011/063975, mailed May 18, 2012, 8 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2011/063975, mailed Jun. 27, 2013, 5 pages.Applicant
- Authorized officer Sang-Taek Kim, International Search Report and Written Opinion in PCT/US2011/061407, mailed May 22, 2012, 10 pages.Applicant
- Authorized officer Lingfei Bai, International Preliminary Report on Patentability in PCT/US2011/061407, mailed Jun. 6, 2013, 7 pages.Applicant
- Authorized officer Kwan Sik Sul, International Search Report and Written Opinion in PCT/US2012/023160, mailed May 24, 2012, 9 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2012/023160, mailed Aug. 15, 2013, 6 pages.Applicant
- Authorized officer Jeongmin Choi, International Search Report and Written Opinion in PCT/US2012/027146, mailed Sep. 24, 2012, 12 pages.Applicant
- Authorized officer Athina Nickitas-Etienne, International Preliminary Report on Patentability in PCT/US2012/027146, mailed Sep. 19, 2013, 9 pages.Applicant
- Authorized officer Tae Hoon Kim, International Search Report and Written Opinion in PCT/US2013/035837, mailed Jul. 30, 2013, 9 pages.Applicant
- Authorized officer Sang Won Choi, International Search Report and Written Opinion in PCT/US2013/048275, mailed Oct. 14, 2013, 17 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2013/048275, mailed Jan. 8, 2015, 14 pages.Applicant
- Authorized officer Hye Lyun Park, International Search Report and Written Opinion in PCT/US2013/050914, mailed Oct. 18, 2013, 11 pages.Applicant
- European Search Report in Application No. 10 81 5813.0, mailed Mar. 12, 2013, 9 pages.Applicant
- Search Report and Action in TW Application No. 098132132, issued Dec. 6, 2012, 8 pages.Applicant
- Chinese First Office Action for Application No. 200880120050.6, Aug. 2, 2011, 10 pages.Applicant
- Chinese First Office Action for Application No. 200980114639.X, May 14, 2012, 13 pages.Applicant
- Ando et al., “10-W/mm AlGaN—GaN HFET with a Field Modulating Plate,” IEEE Electron Device Letters, 2003, 24(5):289-291.Applicant
- Arulkumaran et al. “Surface Passivation Effects on AlGaN/GaN High-Electron-Mobility Transistors with SiO2, Si3N4, and Silicon Oxynitride,” Applied Physics Letters, 2004, 84(4):613-615.Applicant
- Chen et al., “High-performance AlGaN/GaN Lateral Field-effect Rectifiers Compatible with High Electron Mobility Transistors,” Applied Physics Letters, 2008, 92, 253501-1-3.Applicant
- Coffie, “Characterizing and Suppressing DC-to-RF Dispersion in AlGaN/GaN High Electron Mobility Transistors,” 2003, PhD Thesis, University of California, Santa Barbara, 169 pages.Applicant
- Coffie et al., “Unpassivated p-GaN/AlGaN/GaN HEMTs with 7.1 W/mm at 10 GhZ,” Electronic Letters, 2003, 39(19):1419-1420.Applicant
- Chu et al., “1200-V Normally off GaN-on-Si Field-effect Transistors with Low Dynamic on-Resistance,” IEEE Electron Device Letters, 2011, 32(5):632-634.Applicant
- Dora et al., “High Breakdown Voltage Achieved on AlGaN/GaN HEMTs with Integrated Slant Field Plates,” IEEE Electron Device Letters, 2006, 27(9):713-715.Applicant
- Dora et al., “ZrO2 Gate Dielectrics Produced by Ultraviolet Ozone Oxidation for GaN and AlGaN/GaN Transistors,” J. Vac. Sci. TechnoI. B, 2006, 24(2)575-581.Applicant
- Dora, “Understanding Material and Process Limits for High Breakdown Voltage AlGaN/GaN HEMTs,” PhD Thesis, University of California, Santa Barbara, Mar. 2006, 157 pages.Applicant
- Fanciulli et al., “Structural and Electrical Properties of HfO2 Films Grown by Atomic Layer Deposition on Si, Ge, GaAs and GaN,” Mat. Res. Soc. Symp. Proc., 2004, vol. 786, 6 pages.Applicant
- Green et al., “The Effect of Surface Passivation on the Microwave Characteristics of Undoped AlGaN/GaN HEMT's,” IEEE Electron Device Letters, 2000, 21(6):268 270.Applicant
- Gu et al., “AlGaN/GaN MOS Transistors using Crystalline ZrO2 as Gate Dielectric,” Proceedings of SPIE, 2007, vol. 6473, 64730S-1-8.Applicant
- Higashiwaki et al. “AlGaN/GaN Heterostructure Field-Effect Transistors on 4H-SiC Substrates with Current-Gain Cutoff Frequency of 190 GHz,” Applied Physics Express, 2008, 021103-1-3.Applicant
- Hwang et al., “Effects of a Molecular Beam Epitaxy Grown AlN Passivation Layer on AlGaN/GaN Heterojunction Field Effect Transistors,” Solid-State Electronics, 2004, 48:363-366.Applicant
- Im et al., “Normally off GaN MOSFET Based on AlGaN/GaN Heterostructure with Extremely High 2DEG Density Grown on Silicon Substrate,” IEEE Electron Device Letters, 2010, 31(3):192-194.Applicant
- Karmalkar and Mishra, “Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using a Field Plate,” IEEE Transactions on Electron Devices, 2001, 48(8):1515-1521.Applicant
- Karmalkar and Mishra, “Very High Voltage AlGaN/GaN High Electron Mobility Transistors Using a Field Plate Deposited on a Stepped Insulator,” Solid-State Electronics, 2001, 45:1645-1652.Applicant
- Keller et al., “GaN—GaN Junctions with Ultrathin AlN Interlayers: Expanding Heterojunction Design,” Applied Physics Letters, 2002, 80(23):4387-4389.Applicant
- Keller et al., “Method for Heteroepitaxial Growth of High Quality N-Face GaN, InN and AlN and their Alloys by Metal Organic Chemical Vapor Deposition,” U.S. Appl. No. 60/866,035, filed Nov. 15, 2006, 31 pages.Applicant
- Khan et al., “AlGaN/GaN Metal Oxide Semiconductor Heterostructure Field Effect Transistor,” IEEE Electron Device Letters, 2000, 21(2):63-65.Applicant
- Kim, “Process Development and Device Characteristics of AlGaN/GaN HEMTs for High Frequency Applications,” PhD Thesis, University of Illinois at Urbana-Champaign, 2007, 120 pages.Applicant
- Kumar et al., “High Transconductance Enhancement-mode AlGaN/GaN HEMTs on SiC Substrate,” Electronics Letters, 2003, 39(24):1758-1760.Applicant
- Kuraguchi et al., “Normally-off GaN-MISFET with Well-controlled Threshold Voltage,” Phys. Stats. Sol., 2007, 204(6):2010-2013.Applicant
- Lanford et al., “Recessed-gate Enhancement-mode GaN HEMT with High Threshold Voltage,” Electronic Letters, 2005, 41(7):449-450.Applicant
- Lee et al., “Self-aligned Process for Emitter- and Base-regrowth GaN HBTs and BJTs,” Solid-State Electronics, 2001, 45:243-247.Applicant
- Mishra et al., “N-face High Electron Mobility Transistors with Low Buffer Leakage and Low Parasitic Resistance,” U.S. Appl. No. 60/908,914, filed Mar. 29, 2007, 21 pages.Applicant
- Mishra et al., “Polarization-induced Barriers for N-face Nitride-based Electronics,” U.S. Appl. No. 60/940,052, filed May 24, 2007, 29 pages.Applicant
- Mishra et al., “Growing N-polar III-nitride structures,” U.S. Appl. No. 60/972,467, filed Sep. 14, 2007, 7 pages.Applicant
- Mishra et al., “AlGaN/GaN HEMTs—An Overview of Device Operation and Applications,” Proceedings of the IEEE, 2002, 90(6):1022-1031.Applicant
- Nanjo et al., “Remarkable Breakdown Voltage Enhancement in AlGaN Channel High Electron Mobility Transistors,” Applied Physics Letters 92 (2008), 3 pages.Applicant
- Napierala et al., “Selective GaN Epitaxy on Si(111) Substrates Using Porous Aluminum Oxide Buffer Layers,” Journal of the Electrochemical Society, 2006. 153(2):G125-G127, 4 pages.Applicant
- Ota and Nozawa, “AlGaN/GaN Recessed MIS-gate HFET with High-threshold-voltage Normally-off Operation for Power Electronics Applications,” IEEE Electron Device Letters, 2008, 29(7):668-670.Applicant
- Palacios et al., “AlGaN/GaN HEMTs with an InGaN-based Back-barrier,” Device Research Conference Digest, 2005, DRC '05 63rd, pp. 181-182.Applicant
- Palacios et al., “AlGaN/GaN High Electron Mobility Transistors with InGaN Back-Barriers,” IEEE Electron Device Letters, 2006, 27(1):13-15.Applicant
- Palacios et al., “Fluorine Treatment to Shape the Electric Field in Electron Devices, Passivate Dislocations and Point Defects, and Enhance the Luminescence Efficiency of Optical Devices,” U.S. Appl. No. 60/736,628, filed Nov. 15, 2005, 21 pages.Applicant
- Palacios et al., “Nitride-based High Electron Mobility Transistors with a GaN Spacer,” Applied Physics Letters, 2006, 89:073508-1-3.Applicant
- Pei et al., “Effect of Dielectric Thickness on Power Performance of AlGaN/GaN HEMTs,” IEEE Electron Device Letters, 2009, 30(4):313-315.Applicant
- “Planar, Low Switching Loss, Gallium Nitride Devices for Power Conversion Applications,” SBIR N121-090 (Navy), 2012, 3 pages.Applicant
- Rajan et al., “Advanced Transistor Structures Based on N-face GaN,” 32M International Symposium on Compound Semiconductors (ISCS), Sep. 18-22, 2005, Europa-Park Rust, Germany, 2 pages.Applicant
- Saito et al., “Recessed-gate Structure Approach Toward Normally off High-voltage AlGaN/GaN HEMT for Power Electronics Applications,” IEEE Transactions on Electron Device, 2006, 53(2):356-362.Applicant
- Shelton et al., “Selective Area Growth and Characterization of AlGaN/GaN Heterojunction Bipolar Transistors by Metalorganic Chemical Vapor Deposition,” IEEE Transactions on Electron Devices, 2001, 48(3):490-494.Applicant
- Shen, “Advanced Polarization-based Design of AlGaN/GaN HEMTs,” Jun. 2004, PhD Thesis, University of California, Santa Barbara, 192 pages.Applicant
- Sugiura et al., “Enhancement-mode n-channel GaN MOSFETs Fabricated on p-GaN Using HfO2 as Gate Oxide,” Electronics Letters, 2007, vol. 43, No. 17, 2 pages.Applicant
- Suh et al., “High Breakdown Enhancement Mode GaN-based HEMTs with Integrated Slant Field Plate,” U.S. Appl. No. 60/822,886, filed Aug. 18, 2006, 16 pages.Applicant
- Suh et al. “High-Breakdown Enhancement-mode AlGaN/GaN HEMTs with Integrated Slant Field-Plate,” Electron Devices Meeting, 2006, IEDM '06 International, 3 pages.Applicant
- Suh et al., “III-Nitride Devices with Recessed Gates,” U.S. Appl. No. 60/972,481, filed Sep. 14, 2007, 18 pages.Applicant
- Tipirneni et al. “Silicon Dioxide-encapsulated High-Voltage AlGaN/GaN HFETs for Power-Switching Applications,” IEEE Electron Device Letters, 2007, 28(9):784-786.Applicant
- Vetury et al., “Direct Measurement of Gate Depletion in High Breakdown (405V) Al/GaN/GaN Heterostructure Field Effect Transistors,” IEDM 98, 1998, pp. 55-58.Applicant
- Wang et al., “Comparison of the Effect of Gate Dielectric Layer on 2DEG Carrier Concentration in Strained AlGaN/GaN Heterostructure,” Mater. Res. Soc. Symp. Proc., 2007, vol. 831, 6 pages.Applicant
- Wang et al., “Enhancement-mode Si3N4/AlGaN/GaN MISHFETs,” IEEE Electron Device Letters, 2006, 27(10):793-795.Applicant
- Wu, “AlGaN/GaN Microwave Power High-Mobility Transistors,” PhD Thesis, University of California, Santa Barbara, Jul. 1997, 134 pages.Applicant
- Wu et al., “A 97.8% Efficient GaN HEMT Boost Converter with 300-W Output Power at 1 MHz,” Electronic Device Letters, 2008, IEEE, 29(8):824-826.Applicant
- Yoshida, “AlGan/GaN Power FET,” Furukawa Review, 2002, 21:7-11.Applicant
- Zhang, “High Voltage GaN HEMTs with Low on-resistance for Switching Applications,” PhD Thesis, University of California, Santa Barbara, Sep. 2002, 166 pages.Applicant
- Zhanghong Content, Shanghai Institute of Metallurgy, Chinese Academy of Sciences, “Two-Dimensional Electron Gas and High Electron Mobility Transistor (HEMT),” Dec. 31, 1984, 17 pages.Applicant
- Authorized officer Agnès Wittmann-Regis, International Preliminary Report on Patentability in PCT/US2013/035837, mailed Oct. 23, 2014, 6 pages.Applicant
- Authorized officer Yukari Nakamura, International Preliminary Report on Patentability in PCT/US2013/050914, mailed Jan. 29, 2015, 8 pages.Applicant