US 7,369,435 B2Grant
Write once read only memory employing floating gates
Issue Date:2008-05-06
•21 Claims
•8 Drawing Sheets
Abstract
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate transistor has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The floating gate transistor can be programmed by trapping charge on the floating gate.
Metadata
Assignee
- Micron Technology, Inc.
Inventor
- Leonard Forbes
Application Information
Application Number:US 11/215,618
Filing Date:2005-08-30
Priority Date:2002-06-21
Art Unit:2824
Classifications
IPC:
G11C11/34
Patent Drawings (8 sheets)
Description
Cross Reference to Related Applications
[0001] The present application is a divisional of U.S. application Ser. No. 10/177,083, filed Jun. 21, 2002 now U.S. Pat. No. 7,193,893, which is herein incorporated by reference in its entirety.
[0002] This application is related to the following commonly assigned U.S. patent application: “Write Once Read Only Memory Employing Charge Trapping in Insulators,” Ser. No. 10/177,077, filed Jun. 21, 2002, now issued as U.S. Pat. No. 6,804,136, which is herein incorporated by reference.
Field of the Invention
[0003] The present invention relates generally to semiconductor integrated circuits and, more particularly, to write once read only memory employing floating gates.
Background of the Invention
[0004] Many electronic products need various amounts of memory to store information, e.g. data. One common type of high speed, low cost memory includes dynamic random access memory (DRAM) comprised of individual DRAM cells arranged in arrays. DRAM cells include an access transistor, e.g a metal oxide semiconducting field effect transistor (MOSFET), coupled to a capacitor cell. Another type of high speed, low cost memory includes floating gate memory cells. A conventional horizontal floating gate transistor structure includes a source region and a drain region separated by a channel region in a horizontal substrate. A floating gate is separated by a thin tunnel gate oxide. The structure is programmed by storing a charge on the floating gate. A control gate is separated from the floating gate by an intergate dielectric. A charge stored on the floating gate effects the conductivity of the cell when a read voltage potential is applied to the control gate. The state of cell can thus be determined by sensing a change in the device conductivity between the programmed and un-programmed states.
[0005] With successive generations of DRAM chips, an emphasis continues to be placed on increasing array density and maximizing chip real estate while minimizing the cost of manufacture. It is further desirable to increase array density with little or no modification of the DRAM optimized process flow.
[0006] A requirement exists for memory devices which need only be programmed once, as for instance to function as an electronic film in a camera. If the memory arrays have a very high density then they can store a large number of very high resolution images in a digital camera. If the memory is inexpensive then it can for instance replace the light sensitive films which are used to store images in conventional cameras.
[0007] Thus, there is a need for improved DRAM technology compatible write once read only memory. It is desirable that such write once read only memory be fabricated on a DRAM chip with little or no modification of the DRAM process flow. It is further desirable that such write once read only memory operate with lower programming voltages than that used by conventional DRAM cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.
References
- [0008] L. Forbes, W. P. Noble and E. H. Cloud, “MOSFET Technology for Programmable Address Decode and Correction,” U.S. Pat. No. 6,521,950;
- [0009] B. Eitan et al., “Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM device,” IEEE Electron Device Lett., Vol. 22, No. 11, pp. 556-558, (November 2001);
- [0010] B. Etian et al., “NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., Vol. 21, No. 11, pp. 543-545, (November 2000));
- [0011] S. Sze, Physics of Semiconductor Devices, Wiley, New York, 1981, pp. 504-506);
- [0012] L. Forbes and J. Geusic, “Memory Using Insulator Traps,” U.S. Pat. No. 6,140,181.
Summary of the Invention
[0013] The above mentioned problems for creating DRAM technology compatible write once read only memory cells as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. This disclosure teaches structures and methods using floating gate devices as write once read only memory in a DRAM integrated circuit. The structures and methods use the existing process sequence for MOSFET's in DRAM technology.
[0014] In particular, an illustrative embodiment of the present invention includes a write once read only memory cell. The write once read only memory cell includes a floating gate transistor. The floating gate transistor has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The floating gate transistor can be programmed by operation in a reverse direction trapping charge on the floating gate adjacent to the first source/drain region such that the programmed floating gate transistor operates at reduced drain source current when read in a forward direction.
[0015] These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
Brief Description of the Drawings
[0016] FIG. 1A is a block diagram of a metal oxide semiconductor field effect transistor (MOSFET) in a substrate according to the teachings of the prior art.
[0017] FIG. 1B illustrates the MOSFET of FIG. 1A operated in the forward direction showing some degree of device degradation due to electrons being trapped in the gate oxide near the drain region over gradual use.
[0018] FIG. 1C is a graph showing the square root of the current signal (Ids) taken at the drain region of the conventional MOSFET versus the voltage potential (VGS) established between the gate and the source region.
[0019] FIG. 2A is a diagram of a programmed MOSFET which can be used as a write once read only memory cell according to the teachings of the present invention.
[0020] FIG. 2B is a diagram suitable for explaining the method by which the MOSFET of the write once read only memory cell of the present invention can be programmed to achieve the embodiments of the present invention.
[0021] FIG. 2C is a graph plotting the current signal (Ids) detected at the drain region versus a voltage potential, or drain voltage, (VDS) set up between the drain region and the source region (Ids vs. VDS).
[0022] FIG. 3 illustrates a portion of a memory array according to the teachings of the present invention.
[0023] FIGS. 4A-4B illustrates the operation of the novel write once read only memory cell formed according to the teachings of the present invention.
[0024] FIG. 5 illustrates the operation of a conventional DRAM cell.
[0025] FIG. 6 illustrates a memory device according to the teachings of the present invention.
[0026] FIG. 7 is a block diagram of an electrical system, or processor-based system, utilizing write once read only memory constructed in accordance with the present invention.
Description of the Preferred Embodiments
[0027] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.
[0028] The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
[0029] FIG. 1A is useful in illustrating the conventional operation of a MOSFET such as can be used in a DRAM array. FIG. 1A illustrates the normal hot electron injection and degradation of devices operated in the forward direction. As is explained below, since the electrons are trapped near the drain they are not very effective in changing the device characteristics.
[0030] FIG. 1A is a block diagram of a metal oxide semiconductor field effect transistor (MOSFET) 101 in a substrate 100. The MOSFET 101 includes a source region 102, a drain region 104, a channel region 106 in the substrate 100 between the source region 102 and the drain region 104. A gate 108 is separated from the channel region 108 by a gate oxide 110. A sourceline 112 is coupled to the source region 102. A bitline 114 is coupled to the drain region 104. A wordline 116 is coupled to the gate 108.
[0031] In conventional operation, a drain to source voltage potential (Vds) is set up between the drain region 104 and the source region 102. A voltage potential is then applied to the gate 108 via a wordline 116. Once the voltage potential applied to the gate 108 surpasses the characteristic voltage threshold (Vt) of the MOSFET a channel 106 forms in the substrate 100 between the drain region 104 and the source region 102. Formation of the channel 106 permits conduction between the drain region 104 and the source region 102, and a current signal (Ids) can be detected at the drain region 104.
[0032] In operation of the conventional MOSFET of FIG. 1A , some degree of device degradation does gradually occur for MOSFETs operated in the forward direction by electrons 117 becoming trapped in the gate oxide 110 near the drain region 104. This effect is illustrated in FIG. 1B . However, since the electrons 117 are trapped near the drain region 104 they are not very effective in changing the MOSFET characteristics.
[0033] FIG. 1C illustrates this point. FIG. 1C is a graph showing the square root of the current signal (Ids) taken at the drain region versus the voltage potential (VGS) established between the gate 108 and the source region 102. The change in the slope of the plot of SQRT Ids versus VGS represents the change in the charge carrier mobility in the channel 106.
[0034] In FIG. 1C , ΔVT represents the minimal change in the MOSFET's threshold voltage resulting from electrons gradually being trapped in the gate oxide 110 near the drain region 104, under normal operation, due to device degradation. This results in a fixed trapped charge in the gate oxide 110 near the drain region 104. Slope 103 represents the charge carrier mobility in the channel 106 for FIG. 1A having no electrons trapped in the gate oxide 110. Slope 105 represents the charge mobility in the channel 106 for the conventional MOSFET of FIG. 1B having electrons 117 trapped in the gate oxide 110 near the drain region 104. As shown by a comparison of slope 103 and slope 105 in FIG. 1C , the electrons 117 trapped in the gate oxide 110 near the drain region 104 of the conventional MOSFET do not significantly change the charge mobility in the channel 106.
[0035] There are two components to the effects of stress and hot electron injection. One component includes a threshold voltage shift due to the trapped electrons and a second component includes mobility degradation due to additional scattering of carrier electrons caused by this trapped charge and additional surface states. When a conventional MOSFET degrades, or is “stressed,” over operation in the forward direction, electrons do gradually get injected and become trapped in the gate oxide near the drain. In this portion of the conventional MOSFET there is virtually no channel underneath the gate oxide. Thus the trapped charge modulates the threshold voltage and charge mobility only slightly.
[0036] The inventor, along with others, have previously described programmable memory devices and functions based on the reverse stressing of MOSFET's in a conventional CMOS process and technology in order to form programmable address decode and correction in U.S. Pat. No. 6,521,950 entitled “MOSFET Technology for Programmable Address Decode and Correction.” That disclosure, however, did not describe write once read only memory solutions, but rather address decode and correction issues. The inventors also describe write once read only memory cells employing charge trapping in gate insulators for conventional MOSFETs. The same is described in commonly assigned U.S. patent application, entitled “Write Once Read Only Memory Employing Charge Trapping in Insulators,” Ser. No. 10/177,077, filed Jun. 21, 2002, now issued as U.S. Pat. No. 6,804,136. The present application, however, describes write once read only memory cells formed from conventional flash memory device structures.
[0037] According to the teachings of the present invention, normal flash memory cells can be programmed by operation in the reverse direction and utilizing avalanche hot electron injection to trap electrons on the floating gate of the floating gate transistor. When the programmed floating gate transistor is subsequently operated in the forward direction the electrons trapped on the floating gate cause the channel to have a different threshold voltage. The novel programmed floating gate transistors of the present invention conduct significantly less current than conventional flash cells which have not been programmed. These electrons will remain trapped on the floating gate unless negative control gate voltages are applied. The electrons will not be removed from the floating gate when positive or zero control gate voltages are applied. Erasure can be accomplished by applying negative control gate voltages and/or increasing the temperature with negative control gate bias applied to cause the trapped electrons on the floating gate to be re-emitted back into the silicon channel of the MOSFET.
[0038] FIG. 2A is a diagram of a programmed floating gate transistor which can be used as a write once read only memory cell according to the teachings of the present invention. As shown in FIG. 2A the write once read only memory cell 201 includes a floating gate transistor in a substrate 200 which has a first source/drain region 202, a second source/drain region 204, and a channel region 206 between the first and second source/drain regions, 202 and 204. In one embodiment, the first source/drain region 202 includes a source region 202 for the floating gate transistor and the second source/drain region 204 includes a drain region 204 for the floating gate transistor. FIG. 2A further illustrates a floating gate 208 separated from the channel region 206 by a floating gate insulator 210. An array plate 212 is coupled to the first source/drain region 202 and a transmission line 214 is coupled to the second source/drain region 204. In one embodiment, the transmission line 214 includes a bit line 214. Further as shown in FIG. 2A , a control gate 216 is separated from the floating gate 208 by a gate dielectric 218.
[0039] As stated above, write once read only memory cell 201 is comprised of a programmed floating gate transistor. This programmed floating gate transistor has a charge 217 trapped on the floating gate 208. In one embodiment, the charge 217 trapped on the floating gate 208 includes a trapped electron charge 217.
[0040] FIG. 2B is a diagram suitable for explaining the method by which the floating gate of the write once read only memory cell 201 of the present invention can be programmed to achieve the embodiments of the present invention. As shown in FIG. 2B the method includes programming the floating gate transistor. Programming the floating gate transistor includes applying a first voltage potential V1 to a drain region 204 of the floating gate transistor and a second voltage potential V2 to the source region 202.
[0041] In one embodiment, applying a first voltage potential V1 to the drain region 204 of the floating gate transistor includes grounding the drain region 204 of the floating gate transistor as shown in FIG. 2B . In this embodiment, applying a second voltage potential V2 to the source region 202 includes biasing the array plate 212 to a voltage higher than VDD, as shown in FIG. 2B . A gate potential VGS is applied to the control gate 216 of the floating gate transistor. In one embodiment, the gate potential VGS includes a voltage potential which is less than the second voltage potential V2, but which is sufficient to establish conduction in the channel 206 of the floating gate transistor between the drain region 204 and the source region 202. As shown in FIG. 2B , applying the first, second and gate potentials (V1, V2, and VGS respectively) to the floating gate transistor creates a hot electron injection into the floating gate 208 of the floating gate transistor adjacent to the source region 202. In other words, applying the first, second and gate potentials (V1, V2, and VGS respectively) provides enough energy to the charge carriers, e.g. electrons, being conducted across the channel 206 that, once the charge carriers are near the source region 202, a number of the charge carriers get excited into the floating gate 208 adjacent to the source region 202. Here the charge carriers become trapped.
[0042] In an alternative embodiment, applying a first voltage potential V1 to the drain region 204 of the floating gate transistor includes biasing the drain region 204 of the floating gate transistor to a voltage higher than VDD. In this embodiment, applying a second voltage potential V2 to the source region 202 includes grounding the array plate 212. A gate potential VGS is applied to the control gate 216 of the floating gate transistor. In one embodiment, the gate potential VGS includes a voltage potential which is less than the first voltage potential V1, but which is sufficient to establish conduction in the channel 206 of the floating gate transistor between the drain region 204 and the source region 202. Applying the first, second and gate potentials (V1, V2, and VGS respectively) to the floating gate transistor creates a hot electron injection into the floating gate 208 of the floating gate transistor adjacent to the drain region 204. In other words, applying the first, second and gate potentials (V1, V2, and VGS respectively) provides enough energy to the charge carriers, e.g. electrons, being conducted across the channel 206 that, once the charge carriers are near the drain region 204, a number of the charge carriers get excited into the floating gate 208 adjacent to the drain region 204. Here the charge carriers become trapped as shown in FIG. 2A .
[0043] In one embodiment of the present invention, the method is continued by subsequently operating the floating gate transistor in the forward direction in its programmed state during a read operation. Accordingly, the read operation includes grounding the source region 202 and precharging the drain region a fractional voltage of VDD. If the device is addressed by a wordline coupled to the gate, then its conductivity will be determined by the presence or absence of stored charge in the floating gate. That is, a gate potential can be applied to the control gate 216 by a wordline 220 in an effort to form a conduction channel between the source and the drain regions as done with addressing and reading conventional DRAM cells. However, now in its programmed state, the conduction channel 206 of the floating gate transistor will have a higher voltage threshold.
[0044] FIG. 2C is a graph plotting a current signal (IDS) detected at the second source/drain region 204 versus a voltage potential, or drain voltage, (VDS) set up between the second source/drain region 204 and the first source/drain region 202 (IDS vs. VDS). In one embodiment, VDS represents the voltage potential set up between the drain region 204 and the source region 202. In FIG. 2C , the curve plotted as 205 represents the conduction behavior of a conventional floating gate transistor where the transistor is not programmed (is normal or not stressed) according to the teachings of the present invention. The curve 207 represents the conduction behavior of the programmed floating gate transistor (stressed), described above in connection with FIG. 2A , according to the teachings of the present invention. As shown in FIG. 2C , for a particular drain voltage, VDS, the current signal (IDS2) detected at the second source/drain region 204 for the programmed floating gate transistor (curve 207) is significantly lower than the current signal (IDS1) detected at the second source/drain region 204 for the conventional floating gate cell (curve 205) which is not programmed according to the teachings of the present invention. Again, this is attributed to the fact that the channel 206 in the programmed floating gate transistor of the present invention has a different voltage threshold.
[0045] Some of these effects have recently been described for use in a different device structure, called an NROM, for flash memories. This latter work in Israel and Germany is based on employing charge trapping in a silicon nitride layer in a non-conventional flash memory device structure. Charge trapping in silicon nitride gate insulators was the basic mechanism used in MNOS memory devices, charge trapping in aluminum oxide gates was the mechanism used in MIOS memory devices, and the present inventor, along with another, disclosed charge trapping at isolated point defects in gate insulators in U.S. Pat. No. 6,140,181 entitled “Memory Using Insulator Traps.” However, none of the above described references addressed forming write once read only memory cells in conventional flash memory cell device structures.
[0046] That is, in contrast to the above work, the present invention discloses programming a floating gate transistor to trap charge and reading the device to form a write once read only memory (WOROM) based on a modification of DRAM technology.
[0047] FIG. 3 illustrates a portion of a memory array 300 according to the teachings of the present invention. The memory in FIG. 3 , is shown illustrating a pair of write once read only floating gate memory cells 301-1 and 301-2 formed according to the teachings of the present invention. As one of ordinary skill in the art will understand upon reading this disclosure, any number of write once and read only floating gate memory cells can be organized in an array, but for ease of illustration only two are displayed in FIG. 3 . As shown in FIG. 3 , a first source/drain region, 302-1 and 302-2 respectively, is coupled to an array plate 304. A second source/drain region, 306-1 and 306-2 respectively, is coupled to a bitline, 308-1 and 308-2 respectively. Each of the bitlines, 308-1 and 308-2, couple to a sense amplifier, shown generally at 310. A wordline, 312-1 and 312-2 respectively, is couple to a control gate, 318-1 and 318-2 respectively, for each of the write once read only floating gate memory cells, 301-1 and 301-2. A floating gate, 320-1 and 320-2 respectively, is separated from a channel region, 322-1 and 322-2, in the write once read only floating gate memory cells, 301-1 and 301-2, beneath the control gate, 318-1 and 318-2. Finally, a write data/precharge circuit is shown at 324 for coupling a first or a second potential to bitline 308-1. The illustrated write data/precharge circuit 324 is connected to a write data/precharge control line 325. As one of ordinary skill in the art will understand upon reading this disclosure, the write data/precharge circuit 324 is adapted to couple either a ground to the bitline 308-1 during a write operation in the reverse direction, or alternatively to precharge the bitline 308-1 to fractional voltage of VDD during a read operation in the forward direction. As one of ordinary skill in the art will understand upon reading this disclosure, the array plate 304 can be biased to a voltage higher than VDD during a write operation in the reverse direction, or alternatively grounded during a read operation in the forward direction.
[0048] As shown in FIG. 3 , the array structure 300 has no capacitors. Instead, according to the teachings of the present invention, the first source/drain region or source region, 302-1 and 302-2, are coupled via a conductive plug directly to the array plate 304. In order to write, the array plate 304 is biased to voltage higher than VDD and the devices stressed in the reverse direction by grounding the data or bit line, 308-1 or 308-2. If the write once read only memory cell, 301-1 or 301-2, is selected by a word line address, 312-1 or 312-2, then the write once read only memory cell, 301-1 or 301-2, will conduct and be stressed with accompanying hot electron injection into the cells floating gate, 320-1 or 320-2, adjacent to the source region, 302-1 or 302-2. Alternatively, the array plate 304 can be grounded and the data or bit line, 308-1 or 308-2 driven to some voltage higher than VDD. Again, if the write once read only memory cell, 301-1 or 301-2, is selected by a word line address, 312-1 or 312-2, then the write once read only memory cell, 301-1 or 301-2, will conduct and be stressed with accompanying hot electron injection into the cells floating gate, 320-1 or 320-2, adjacent to the drain region, 306-1 or 306-2. During read, the write once read only floating gate memory cell, 301-1 or 301-2, is operated in the forward direction with the array plate 304 grounded and the bit line, 308-1 or 308-2, and respective second source/drain region or drain region, 306-1 and 306-2, of the cells precharged to some fractional voltage of VDD. If the device is addressed by the word line, 312-1 or 312-2, then its conductivity will be determined by the presence or absence of stored charge on the cells floating gate, 320-1 or 320-2, and so detected using the DRAM sense amplifier 310. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein. The array would thus be addressed and read in the conventional manner used in DRAM's, but programmed as write once read only memory cells in a novel fashion.
[0049] In operation the devices can be subjected to hot electron stress in the reverse direction by biasing the array plate 304, and read while grounding the array plate 304 to compare a stressed write once read only memory cell, e.g. cell 301-1, to an unstressed dummy device/cell, e.g. 301-2, as shown in FIG. 3 . The write and possible erase feature could be used during manufacture and test to initially program all cells or devices to have similar or matching conductivity before use in the field. The sense amplifier 310 can then detect small differences in cell or device characteristics due to stress induced changes in device characteristics during the write operation.
[0050] As one of ordinary skill in the art will understand upon reading this disclosure such arrays of write once read only memory cells are conveniently realized by a modification of DRAM technology. That is, the transfer devices in the DRAM arrays are replaced by flash memory type devices with floating gates. Conventional transistors for address decode and sense amplifiers can be fabricated after this step with normal thin gate insulators of silicon oxide. Because the devices in the array have a floating gate they can be erased by biasing the control or address gate with a large negative potential.
[0051] FIGS. 4A-B and 5 are useful in illustrating the use of charge storage in the gate insulator to modulate the conductivity of the write once read only memory cell according to the teachings of the present invention. That is, FIGS. 4A-4B illustrates the operation of the novel write once read only memory cell 401 formed according to the teachings of the present invention. And, FIG. 5 illustrates the operation of a conventional DRAM cell 501. As shown in FIG. 4A , the gate insulator 410 is made thicker than in a conventional DRAM cell. For example, an embodiment of the gate insulator 410 has a thickness 411 equal to or greater than 10 nm or 100 Å (10−6 cm). In the embodiment shown in FIG. 4A a write once read only memory cell has dimensions 413 of 0.1 μm (10−5 cm) by 0.1 μm. The capacitance, Ci, of the structure depends on the dielectric constant, εi, and the thickness of the insulating layers, t. In an embodiment, the dielectric constant is 0.3×10−12 F/cm and the thickness of the insulating layer is 10−6 cm such that Ci=εi/t, Farads/cm2 or 3×10−7 F/cm2. In one embodiment, a charge of 1012 electrons/cm2 is programmed into the floating gate of the write once read only floating gate memory cell. This produces a stored charge Δ Q=1012 electrons/cm2×1.6×10−19 Coulombs. In this embodiment, the resulting change in the threshold voltage (Δ Vt) of the write once read only floating gate memory cell will be approximately 0.5 Volts (Δ Vt=ΔQ/Ci or 1.6×10−7/3×10−7=½ Volt). For Δ Q=1012 electrons/cm3 in an area of 10−10 cm2, this embodiment of the present invention involves trapping a charge of approximately 100 electrons in the floating gate of the write once read only floating gate memory cell. In this embodiment, an original VT is approximately ½ Volt and the VT with charge trapping is approximately 1 Volt.
[0052] FIG. 4B aids to further illustrate the conduction behavior of the novel write once read only floating gate memory cell of the present invention. As one of ordinary skill in the art will understand upon reading this disclosure, if the write once read only floating gate memory cell is being driven with a control gate voltage of 1.0 Volt (V) and the nominal threshold voltage without the floating gate charged is ½ V, then if the floating gate is charged the floating gate transistor of the present invention will be off and not conduct. That is, by trapping a charge of approximately 100 electrons in the floating gate of the write once read only floating gate memory cell, having dimensions of 0.1 μm (10−5 cm) by 0.1 μm, will raise the threshold voltage of the write once read only floating gate memory cell to 1.0 Volt and a 1.0 Volt control gate potential will not be sufficient to turn the device on, e.g. Vt=1.0 V, I=0.
[0053] Conversely, if the nominal threshold voltage without the floating gate charged is ½ V, then I=μCox×(W/L)×((Vgs−Vt)2/2), or 12.5 μA, with μCox=μCi=100 μA/V2 and W/L=1. That is, the write once read only floating gate memory cell of the present invention, having the dimensions describe above will produce a current I=100 μA/V2×(¼)×(½)=12.5 μA. Thus, in the present invention an unwritten, or un-programmed write once read only floating gate memory cell can conduct a current of the order 12.5 μA, whereas if the floating gate is charged then the write once read only floating gate memory cell will not conduct. As one of ordinary skill in the art will understand upon reading this disclosure, the sense amplifiers used in DRAM arrays, and as describe above, can easily detect such differences in current on the bit lines.
[0054] By way of comparison, in a conventional DRAM cell 550 with a 30 femtoFarad (fF) storage capacitor 551 charged to 50 femto Coulombs (fC), if these are read over 5 nS then the average current on a bit line 552 is only 10 μA (I=50 fC/5 ns=10 μA). Thus, storing a 50 fC charge on the storage capacitor shown in FIG. 5 equates to storing 300,000 electrons (Q=50 fC/(1.6×10−19)=30×104=300,000 electrons).
[0055] According to the teachings of the present invention, the floating gate transistors in the array are utilized not just as passive on or off switches as transfer devices in DRAM arrays but rather as active devices providing gain. In the present invention, to program the floating gate transistor “off,” requires only a stored charge in the floating gate of about 100 electrons if the area is 0.1 μm by 0.1 μm. And, if the write once read only floating gate memory cell is unprogrammed, e.g. no stored charge trapped in the floating gate, and if the floating gate transistor is addressed over 10 nS a of current of 12.5 μA is provided. The integrated drain current then has a charge of 125 fC or 800,000 electrons. This is in comparison to the charge on a DRAM capacitor of 50 fC which is only about 300,000 electrons. Hence, the use of the floating gate transistors in the array as active devices with gain, rather than just switches, provides an amplification of the stored charge, in the floating gate, from 100 to 800,000 electrons over a read address period of 10 nS.
[0056] In FIG. 6 a memory device is illustrated according to the teachings of the present invention. The memory device 640 contains a memory array 642, row and column decoders 644, 648 and a sense amplifier circuit 646. The memory array 642 consists of a plurality of write once read only floating gate memory cells 600, formed according to the teachings of the present invention whose word lines 680 and bit lines 660 are commonly arranged into rows and columns, respectively. The bit lines 660 of the memory array 642 are connected to the sense amplifier circuit 646, while its word lines 680 are connected to the row decoder 644. Address and control signals are input on address/control lines 661 into the memory device 640 and connected to the column decoder 648, sense amplifier circuit 646 and row decoder 644 and are used to gain read and write access, among other things, to the memory array 642.
[0057] The column decoder 648 is connected to the sense amplifier circuit 646 via control and column select signals on column select lines 662. The sense amplifier circuit 646 receives input data destined for the memory array 642 and outputs data read from the memory array 642 over input/output (I/O) data lines 663. Data is read from the cells of the memory array 642 by activating a word line 680 (via the row decoder 644), which couples all of the memory cells corresponding to that word line to respective bit lines 660, which define the columns of the array. One or more bit lines 660 are also activated. When a particular word line 680 and bit lines 660 are activated, the sense amplifier circuit 646 connected to a bit line column detects and amplifies the conduction sensed through a given write once read only floating gate memory cell and transferred to its bit line 660 by measuring the potential difference between the activated bit line 660 and a reference line which may be an inactive bit line. Again, in the read operation the source region of a given cell is couple to a grounded array plate (not shown). The operation of Memory device sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
[0058] FIG. 7 is a block diagram of an electrical system, or processor-based system, 700 utilizing write once read only floating gate memory 712 constructed in accordance with the present invention. That is, the write once read only memory (WOROM) 712 utilizes the modified flash cell as explained and described in detail in connection with FIGS. 2-4 . The processor-based system 700 may be a computer system, a process control system or any other system employing a processor and associated memory. The system 700 includes a central processing unit (CPU) 702, e.g., a microprocessor, that communicates with the write once read only floating gate memory 712 and an I/O device 708 over a bus 720. It must be noted that the bus 720 may be a series of buses and bridges commonly used in a processor-based system, but for convenience purposes only, the bus 720 has been illustrated as a single bus. A second I/O device 710 is illustrated, but is not necessary to practice the invention. The processor-based system 700 can also includes read-only memory (ROM) 714 and may include peripheral devices such as a floppy disk drive 704 and a compact disk (CD) ROM drive 706 that also communicates with the CPU 702 over the bus 720 as is well known in the art.
[0059] It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device 700 has been simplified to help focus on the invention. At least one of the write once read only floating gate memory cell in WOROM 712 includes a programmed flash cell.
[0060] It will be understood that the embodiment shown in FIG. 7 illustrates an embodiment for electronic system circuitry in which the novel memory cells of the present invention are used. The illustration of system 700, as shown in FIG. 7 , is intended to provide a general understanding of one application for the structure and circuitry of the present invention, and is not intended to serve as a complete description of all the elements and features of an electronic system using the novel memory cell structures. Further, the invention is equally applicable to any size and type of memory device 700 using the novel memory cells of the present invention and is not intended to be limited to that described above. As one of ordinary skill in the art will understand, such an electronic system can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device.
[0061] Applications containing the novel memory cell of the present invention as described in this disclosure include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
Conclusion
[0062] Utilization of a modification of well established DRAM technology and arrays will serve to afford an inexpensive memory device which can be regarded as disposable if the information is later transferred to another medium, for instance CDROM's. The high density of DRAM array structures will afford the storage of a large volume of digital data or images at a very low cost per bit. There are many applications where the data need only be written once, the low cost of these memories will make it more efficient to just utilize a new memory array, and dispose of the old memory array, rather than trying to erase and reuse these arrays as is done with current flash memories.
[0063] It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims
What is claimed is:
1. A method of forming a memory cell, comprising:
forming a floating gate transistor in a modified dynamic random access memory fabrication process, wherein forming the floating gate transistor includes:
forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate;
forming a gate insulator above the channel region;
forming a floating gate above the gate insulator;
forming a gate dielectric on the floating gate;
forming a control gate on the gate dielectric;
forming an array plate;
forming a conductive plug coupling the first source/drain region to the array plate; and
forming a bitline coupled to the second source/drain region such that the memory cell can be programmed to have a trapped charge in the floating gate by biasing the array plate to a voltage higher than VDD, grounding the bitline, and selecting the control gate by a wordline address, and wherein a programmed floating gate transistor will operate at reduced drain source current in a forward direction.
2. The method of claim 1, wherein forming the gate insulator above the channel region includes forming a gate insulator having a thickness of at least 10 nanometers (nm).
3. A method of forming a memory cell, comprising:
forming a transistor, wherein forming the transistor includes:
forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate;
forming a gate insulator above the channel region;
forming a floating gate above the gate insulator;
forming a gate dielectric on the floating gate;
forming a control gate on the gate dielectric;
forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the transistor; and
forming reading circuitry to read the transistor in a forward direction.
4. The method of claim 3, wherein the memory cell is formed using substantially dynamic random access memory fabrication processes.
5. The method of claim 3, wherein forming programming circuitry includes forming circuitry to apply a first voltage potential greater than VDD to the first source/drain region and forming circuitry to apply a ground potential to the second source/drain region, and forming circuitry to apply a gate potential to the control gate.
6. The method of claim 3, wherein forming programming circuitry includes coupling an array plate to the first source/drain region.
7. The method of claim 3, wherein forming the gate insulator above the channel region includes forming a gate insulator having a thickness of approximately 10 nanometers (nm).
8. The method of claim 3, wherein forming the gate insulator above the channel region includes forming a silicon dioxide gate insulator.
9. A method of forming a memory array, comprising:
forming an array of transistors, wherein forming at least one transistor includes:
forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate;
forming a gate insulator above the channel region;
forming a floating gate above the gate insulator;
forming a gate dielectric on the floating gate;
forming a control gate on the gate dielectric;
forming a wordline coupled to control gates in the array of transistors;
forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the transistor; and
forming reading circuitry to read the transistor in a forward direction.
10. The method of claim 9, wherein forming programming circuitry includes coupling an array plate to the first source/drain regions of transistors in the array of transistors.
11. The method of claim 9, wherein forming the gate insulator above the channel region includes forming a gate insulator having a thickness of at least 10 nanometers (nm).
12. The method of claim 9, wherein forming the gate insulator above the channel region includes forming a silicon dioxide gate insulator.
13. The method of claim 9, wherein forming programming circuitry includes forming circuitry to apply a first voltage potential greater than VDD to the first source/drain region and forming circuitry to apply a ground potential to the second source/drain region, and forming circuitry to apply a gate potential to the control gate.
14. The method of claim 9, wherein the memory array is formed using substantially dynamic random access memory fabrication processes.
15. A method of forming an electronic system, comprising:
forming a memory array including a plurality of transistors, wherein forming at least one transistor includes:
forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate;
forming a gate insulator above the channel region;
forming a floating gate above the gate insulator;
forming a gate dielectric on the floating gate;
forming a control gate on the gate dielectric;
forming a wordline coupled to control gates in the array of transistors;
forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the transistor;
forming reading circuitry to read the transistor in a forward direction;
forming a bus coupled to the memory array; and
coupling the array of transistors to a processor.
16. The method of claim 15, wherein forming programming circuitry includes forming circuitry to apply a first voltage potential greater than VDD to the first source/drain region and forming circuitry to apply a ground potential to the second source/drain region, and forming circuitry to apply a gate potential to the control gate.
17. The method of claim 15, wherein forming reading circuitry includes forming circuitry to apply a ground potential to the first source/drain region, and forming circuitry to apply a fractional voltage of VDD to the second source/drain region during a reading operation.
18. The method of claim 15, wherein forming programming circuitry includes coupling an array plate to the first source/drain regions of transistors in the array of transistors.
19. The method of claim 15, wherein forming the gate insulator above the channel region includes forming a gate insulator having a thickness of at least 10 nanometers (nm).
20. The method of claim 15, wherein the memory array is formed using substantially dynamic random access memory fabrication processes.
21. The method of claim 15, wherein forming the gate insulator above the channel region includes forming a silicon dioxide gate insulator.
Patent Citations (230)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3381114(A) | 1968-04-01 | Nakanuma | Applicant |
| US3641516(A) | 1972-02-01 | Casrucci et al. | Applicant |
| US3665423(A) | 1972-05-01 | Nakamuma et al. | Applicant |
| US3877054(A) | 1975-04-01 | Boulin et al. | Applicant |
| US3964085(A) | 1976-06-01 | Kahng et al. | Applicant |
| US4152627(A) | 1979-05-01 | Priel et al. | Applicant |
| US4215156(A) | 1980-07-01 | Dalal et al. | Applicant |
| US4217601(A) | 1980-08-01 | DeKeersmaecker et al. | Applicant |
| US4333808(A) | 1982-06-01 | Bhattacharyya et al. | Applicant |
| US4399424(A) | 1983-08-01 | Rigby | Applicant |
| US4413022(A) | 1983-11-01 | Suntola et al. | Applicant |
| US4507673(A) | 1985-03-01 | Aoyama et al. | Applicant |
| US4590042(A) | 1986-05-01 | Drage | Applicant |
| US4647947(A) | 1987-03-01 | Takeoka et al. | Applicant |
| US4661833(A) | 1987-04-01 | Mizutani | Applicant |
| US4767641(A) | 1988-08-01 | Kieser et al. | Applicant |
| US4888733(A) | 1989-12-01 | Mobley | Applicant |
| US4920071(A) | 1990-04-01 | Thomas | Applicant |
| US4939559(A) | 1990-07-01 | DiMaria et al. | Applicant |
| US4993358(A) | 1991-02-01 | Mahawili | Applicant |
| US5006192(A) | 1991-04-01 | Deguchi | Applicant |
| US5016215(A) | 1991-05-01 | Tigelaar | Applicant |
| US5021999(A) | 1991-06-01 | Kohda et al. | Applicant |
| US5027171(A) | 1991-06-01 | Reedy et al. | Applicant |
| US5042011(A) | 1991-08-01 | Casper et al. | Applicant |
| US5080928(A) | 1992-01-01 | Klinedinst et al. | Applicant |
| US5111430(A) | 1992-05-01 | Morie | Applicant |
| US5198029(A) | 1993-03-01 | Dutta et al. | Applicant |
| US5253196(A) | 1993-10-01 | Shimabukuro | Applicant |
| US5274249(A) | 1993-12-01 | Xi et al. | Applicant |
| US5280205(A) | 1994-01-01 | Green et al. | Applicant |
| US5293560(A) | 1994-03-01 | Harari | Applicant |
| US5298447(A) | 1994-03-01 | Hong | Applicant |
| US5303182(A) | 1994-04-01 | Nakao et al. | Applicant |
| US5317535(A) | 1994-05-01 | Talreja et al. | Applicant |
| US5388069(A) | 1995-02-01 | Kokubo | Applicant |
| US5399516(A) | 1995-03-01 | Bergendahl et al. | Applicant |
| US5409859(A) | 1995-04-01 | Glass et al. | Applicant |
| US5410504(A) | 1995-04-01 | Ward | Applicant |
| US5424993(A) | 1995-06-01 | Lee et al. | Applicant |
| US5430670(A) | 1995-07-01 | Rosenthal | Applicant |
| US5434815(A) | 1995-07-01 | Smarandoiu et al. | Applicant |
| US5438544(A) | 1995-08-01 | Makino | Applicant |
| US5449941(A) | 1995-09-01 | Yamazaki et al. | Applicant |
| US5457649(A) | 1995-10-01 | Eichman et al. | Applicant |
| US5467306(A) | 1995-11-01 | Kaya et al. | Applicant |
| US5477485(A) | 1995-12-01 | Bergemont et al. | Applicant |
| US5485422(A) | 1996-01-01 | Bauer et al. | Applicant |
| US5493140(A) | 1996-02-01 | Iguchi | Applicant |
| US5508543(A) | 1996-04-01 | Hartstein et al. | Applicant |
| US5508544(A) | 1996-04-01 | Shah | Applicant |
| US5530581(A) | 1996-06-01 | Cogan | Applicant |
| US5530668(A) | 1996-06-01 | Chern et al. | Applicant |
| US5539279(A) | 1996-07-01 | Takeuchi et al. | Applicant |
| US5541871(A) | 1996-07-01 | Nishimura et al. | Applicant |
| US5541872(A) | 1996-07-01 | Lowrey et al. | Applicant |
| US5550770(A) | 1996-08-01 | Kuroda | Applicant |
| US5572459(A) | 1996-11-01 | Wilson et al. | Applicant |
| US5595606(A) | 1997-01-01 | Fujikawa et al. | Applicant |
| US5600587(A) | 1997-02-01 | Koike | Applicant |
| US5602777(A) | 1997-02-01 | Nawaki et al. | Applicant |
| US5627781(A) | 1997-05-01 | Hayashi et al. | Applicant |
| US5627785(A) | 1997-05-01 | Gilliam et al. | Applicant |
| US5670790(A) | 1997-09-01 | Katoh et al. | Applicant |
| US5677867(A) | 1997-10-01 | Hazani | Examiner |
| US5698022(A) | 1997-12-01 | Glassman et al. | Applicant |
| US5714766(A) | 1998-02-01 | Chen et al. | Applicant |
| US5735960(A) | 1998-04-01 | Sandhu et al. | Applicant |
| US5740104(A) | 1998-04-01 | Forbes | Applicant |
| US5754477(A) | 1998-05-01 | Forbes | Applicant |
| US5768192(A) | 1998-06-01 | Eitan | Applicant |
| US5795808(A) | 1998-08-01 | Park | Applicant |
| US5801105(A) | 1998-09-01 | Yano et al. | Applicant |
| US5801401(A) | 1998-09-01 | Forbes | Applicant |
| US5810923(A) | 1998-09-01 | Yano et al. | Applicant |
| US5822256(A) | 1998-10-01 | Bauer et al. | Applicant |
| US5828080(A) | 1998-10-01 | Yano et al. | Applicant |
| US5828605(A) | 1998-10-01 | Peng et al. | Applicant |
| US5840897(A) | 1998-11-01 | Kirlin et al. | Applicant |
| US5852306(A) | 1998-12-01 | Forbes | Applicant |
| US5856688(A) | 1999-01-01 | Lee et al. | Applicant |
| US5886368(A) | 1999-03-01 | Forbes et al. | Applicant |
| US5891773(A) | 1999-04-01 | Saitoh | Applicant |
| US5912488(A) | 1999-06-01 | Kim et al. | Applicant |
| US5916365(A) | 1999-06-01 | Sherman | Applicant |
| US5936274(A) | 1999-08-01 | Forbes et al. | Applicant |
| US5943262(A) | 1999-08-01 | Choi | Applicant |
| US5950925(A) | 1999-09-01 | Fukunaga et al. | Applicant |
| US5959896(A) | 1999-09-01 | Forbes | Applicant |
| US5973356(A) | 1999-10-01 | Noble et al. | Applicant |
| US5989958(A) | 1999-11-01 | Forbes | Applicant |
| US5991225(A) | 1999-11-01 | Forbes et al. | Applicant |
| US6005790(A) | 1999-12-01 | Chan et al. | Applicant |
| US6011725(A) | 2000-01-01 | Eitan | Applicant |
| US6013553(A) | 2000-01-01 | Wallace et al. | Applicant |
| US6020024(A) | 2000-02-01 | Maiti et al. | Applicant |
| US6027961(A) | 2000-02-01 | Maiti et al. | Applicant |
| US6031263(A) | 2000-02-01 | Forbes et al. | Applicant |
| US6034882(A) | 2000-03-01 | Johnson et al. | Applicant |
| US6049479(A) | 2000-04-01 | Thurgate et al. | Applicant |
| US6057271(A) | 2000-05-01 | Kenjiro et al. | Applicant |
| US6059885(A) | 2000-05-01 | Ohashi et al. | Applicant |
| US6072209(A) | 2000-06-01 | Noble et al. | Applicant |
| US6110529(A) | 2000-08-01 | Gardiner et al. | Applicant |
| US6115281(A) | 2000-09-01 | Aggarwal et al. | Applicant |
| US6122201(A) | 2000-09-01 | Lee et al. | Applicant |
| US6124729(A) | 2000-09-01 | Noble et al. | Applicant |
| US6125062(A) | 2000-09-01 | Ahn et al. | Applicant |
| US6140181(A) | 2000-10-01 | Forbes et al. | Applicant |
| US6141237(A) | 2000-10-01 | Eliason et al. | Applicant |
| US6141238(A) | 2000-10-01 | Forbes et al. | Applicant |
| US6141260(A) | 2000-10-01 | Ahn et al. | Applicant |
| US6143636(A) | 2000-11-01 | Forbes et al. | Applicant |
| US6150687(A) | 2000-11-01 | Noble et al. | Applicant |
| US6153468(A) | 2000-11-01 | Forbes et al. | Applicant |
| US6160739(A) | 2000-12-01 | Wong | Applicant |
| US6161500(A) | 2000-12-01 | Kopacz et al. | Applicant |
| US6166401(A) | 2000-12-01 | Forbes | Applicant |
| US6171900(B1) | 2001-01-01 | Sun | Applicant |
| US6185122(B1) | 2001-02-01 | Johnson et al. | Applicant |
| US6194228(B1) | 2001-02-01 | Fujiki et al. | Applicant |
| US6203613(B1) | 2001-03-01 | Gates et al. | Applicant |
| US6206972(B1) | 2001-03-01 | Dunham | Applicant |
| US6211035(B1) | 2001-04-01 | Moise et al. | Applicant |
| US6212103(B1) | 2001-04-01 | Ahrens et al. | Applicant |
| US6222768(B1) | 2001-04-01 | Hollmer et al. | Applicant |
| US6225168(B1) | 2001-05-01 | Gardner et al. | Applicant |
| US6232643(B1) | 2001-05-01 | Forbes et al. | Applicant |
| US6238976(B1) | 2001-05-01 | Noble et al. | Applicant |
| US6243300(B1) | 2001-06-01 | Sunkavalli | Applicant |
| US6246606(B1) | 2001-06-01 | Forbes et al. | Applicant |
| US6249020(B1) | 2001-06-01 | Forbes et al. | Applicant |
| US6252793(B1) | 2001-06-01 | Allen et al. | Applicant |
| US6269023(B1) | 2001-07-01 | Derhacobian et al. | Applicant |
| US6281144(B1) | 2001-08-01 | Cleary et al. | Applicant |
| US6294813(B1) | 2001-09-01 | Forbes et al. | Applicant |
| US6297539(B1) | 2001-10-01 | Ma et al. | Applicant |
| US6302964(B1) | 2001-10-01 | Umotoy et al. | Applicant |
| US6303481(B2) | 2001-10-01 | Park | Applicant |
| US6310376(B1) | 2001-10-01 | Ueda et al. | Applicant |
| US6313518(B1) | 2001-11-01 | Ahn et al. | Applicant |
| US6320784(B1) | 2001-11-01 | Muralidhar et al. | Applicant |
| US6320786(B1) | 2001-11-01 | Chang et al. | Applicant |
| US6337805(B1) | 2002-01-01 | Forbes et al. | Applicant |
| US6351411(B2) | 2002-02-01 | Forbes et al. | Applicant |
| US6353554(B1) | 2002-03-01 | Banks | Applicant |
| US6365470(B1) | 2002-04-01 | Maeda | Applicant |
| US6368941(B1) | 2002-04-01 | Chen et al. | Applicant |
| US6380579(B1) | 2002-04-01 | Nam et al. | Applicant |
| US6387712(B1) | 2002-05-01 | Yano et al. | Applicant |
| US6391769(B1) | 2002-05-01 | Lee et al. | Applicant |
| US6407435(B1) | 2002-06-01 | Ma et al. | Applicant |
| US6429063(B1) | 2002-08-01 | Eitan | Applicant |
| US6432779(B1) | 2002-08-01 | Hobbs et al. | Applicant |
| US6438031(B1) | 2002-08-01 | Fastow | Applicant |
| US6444039(B1) | 2002-09-01 | Nguyen | Applicant |
| US6444895(B1) | 2002-09-01 | Nikawa | Applicant |
| US6445023(B1) | 2002-09-01 | Vaartstra et al. | Applicant |
| US6445030(B1) | 2002-09-01 | Wu et al. | Applicant |
| US6449188(B1) | 2002-09-01 | Fastow | Applicant |
| US6456531(B1) | 2002-09-01 | Wang et al. | Applicant |
| US6456536(B1) | 2002-09-01 | Sobek et al. | Applicant |
| US6458701(B1) | 2002-10-01 | Chae et al. | Applicant |
| US6459618(B1) | 2002-10-01 | Wang | Applicant |
| US6465306(B1) | 2002-10-01 | Ramsbey et al. | Applicant |
| US6465334(B1) | 2002-10-01 | Buynoski et al. | Applicant |
| US6487121(B1) | 2002-11-01 | Thurgate et al. | Applicant |
| US6490204(B2) | 2002-12-01 | Bloom et al. | Applicant |
| US6490205(B1) | 2002-12-01 | Wang et al. | Applicant |
| US6495436(B2) | 2002-12-01 | Ahn et al. | Applicant |
| US6498362(B1) | 2002-12-01 | Forbes et al. | Applicant |
| US6504755(B1) | 2003-01-01 | Katayama et al. | Applicant |
| US6514828(B2) | 2003-02-01 | Ahn et al. | Applicant |
| US6521911(B2) | 2003-02-01 | Parsons et al. | Applicant |
| US6521950(B1) | 2003-02-01 | Shimabukuro et al. | Applicant |
| US6521958(B1) | 2003-02-01 | Forbes et al. | Applicant |
| US6534420(B2) | 2003-03-01 | Ahn et al. | Applicant |
| US6541816(B2) | 2003-04-01 | Ramsbey et al. | Applicant |
| US6545314(B2) | 2003-04-01 | Forbes et al. | Applicant |
| US6552387(B1) | 2003-04-01 | Eitan | Applicant |
| US6559014(B1) | 2003-05-01 | Jeon | Applicant |
| US6566699(B2) | 2003-05-01 | Eitan | Applicant |
| US6567303(B1) | 2003-05-01 | Hamilton et al. | Applicant |
| US6567312(B1) | 2003-05-01 | Torii et al. | Applicant |
| US6570787(B1) | 2003-05-01 | Wang et al. | Applicant |
| US6580118(B2) | 2003-06-01 | Ludwig et al. | Applicant |
| US6580124(B1) | 2003-06-01 | Cleeves et al. | Applicant |
| US6586785(B2) | 2003-07-01 | Flagan et al. | Applicant |
| US6618290(B1) | 2003-09-01 | Wang et al. | Applicant |
| US6630381(B1) | 2003-10-01 | Hazani | Examiner |
| US6642573(B1) | 2003-11-01 | Halliyal et al. | Applicant |
| US6674138(B1) | 2004-01-01 | Halliyal et al. | Applicant |
| US6714455(B2) | 2004-03-01 | Banks | Applicant |
| US6778441(B2) | 2004-08-01 | Forbes et al. | Applicant |
| US6867097(B1) | 2005-03-01 | Ramsbey et al. | Applicant |
| US6873539(B1) | 2005-03-01 | Fazan et al. | Applicant |
| US6996009(B2) | 2006-02-01 | Forbes | Applicant |
| US7045430(B2) | 2006-05-01 | Ahn et al. | Applicant |
| US2002/0003252(A1) | 2002-01-01 | Iyer | Applicant |
| US2002/0027264(A1) | 2002-03-01 | Forbes et al. | Applicant |
| US2002/0036939(A1) | 2002-03-01 | Tsai et al. | Applicant |
| US2002/0074565(A1) | 2002-06-01 | Flagan et al. | Applicant |
| US2002/0089023(A1) | 2002-07-01 | Yu et al. | Applicant |
| US2002/0109158(A1) | 2002-08-01 | Forbes et al. | Applicant |
| US2002/0115252(A1) | 2002-08-01 | Haukka et al. | Applicant |
| US2002/0155688(A1) | 2002-10-01 | Ahn et al. | Applicant |
| US2002/0155689(A1) | 2002-10-01 | Ahn et al. | Applicant |
| US2002/0192974(A1) | 2002-12-01 | Ahn et al. | Applicant |
| US2003/0017717(A1) | 2003-01-01 | Ahn et al. | Applicant |
| US2003/0032270(A1) | 2003-02-01 | Snyder et al. | Applicant |
| US2003/0235077(A1) | 2003-12-01 | Forbes | Applicant |
| US2003/0235081(A1) | 2003-12-01 | Forbes | Applicant |
| US2003/0235085(A1) | 2003-12-01 | Forbes | Applicant |
| US2004/0063276(A1) | 2004-04-01 | Yamamoto et al. | Applicant |
| US2005/0023574(A1) | 2005-02-01 | Forbes et al. | Applicant |
| US2005/0026375(A1) | 2005-02-01 | Forbes | Applicant |
| US2005/0036370(A1) | 2005-02-01 | Forbes | Applicant |
| US2005/0082599(A1) | 2005-04-01 | Forbes | Applicant |
| US2005/0085040(A1) | 2005-04-01 | Forbes | Applicant |
| US2006/0001080(A1) | 2006-01-01 | Forbes | Applicant |
| US2006/0008966(A1) | 2006-01-01 | Forbes et al. | Applicant |
| JP62-199019 | 1987-09-01 | Applicant | |
| JP3-222367 | 1991-10-01 | Applicant | |
| JP5090169 | 1993-04-01 | Applicant | |
| JP6-224431 | 1994-08-01 | Applicant | |
| JP6-302828 | 1994-10-01 | Applicant | |
| JP8-255878 | 1996-10-01 | Applicant | |
| JP2001-332546 | 2001-11-01 | Applicant | |
| WO-9907000(A2) | 1999-02-01 | Applicant | |
| WO-9917371(A1) | 1999-04-01 | Applicant |
Non-Patent Literature (200)
- Muller, R. S., et al., In: Device Electronics for Integrated Circuits, Second Edition, John Wiley & Sons, New York,(1986),p. 157.Applicant
- “International Technology for Semiconductor Roadmap”, http://public.itrs.net/Files/2001ITRS/Links/1999—SIA—Roadmap/, Semiconductor Industry Association,(1999).Applicant
- Aarik, Jaan , et al., “Phase transformations in hafnium dioxide thin films grown by atomic layer deposition at high temperatures”, Applied Surface Science, 173(1-2), (Mar. 2001),15-21.Applicant
- Aarik, Jaan , et al., “Texture development in nanocrystalline hafnium dioxide thin films grown by atomic layer deposition”, Journal of Crystal Growth, 220(1-2), (Nov. 15, 2000),105-113.Applicant
- Abbas, S. A., et al., “N-Channel Igfet Design Limitations Due to Hot Electron Trapping”, Technical Digest, International Electron Devices Meeting.. Washington, DC,(Dec. 1975),35-38.Applicant
- Adelmann, C , et al., “Atomic-layer epitaxy of GaN quantum wells and quantum dots on (0001) AIN”, Journal of Applied Physics, 91(8), (Apr. 15, 2002),5498-5500.Applicant
- Ahn, Seong-Deok , et al., “Surface Morphology Improvement of Metalorganic Chemical Vapor Deposition AI Films by Layered Deposition of AI and Ultathin TiN”, Japanese Journal of Applied Physics, Part 1 (Regular Papers, Short Notes & Review Papers), 39(6A), (Jun. 2000),3349-3354.Applicant
- Akasaki, I. , “Effects of AIN Buffer Layer on Crystallographic Structure and on Electrical and Optical Properties of GaN and Ga(1-x)AI(x)N [0 less than x (less than or equal to) 0.4] Films Grown on Sapphire Substrate by MOVPE”, Journal of Crystal Growth, 98, (1989),209-219.Applicant
- Asari, K , et al., “Multi-mode and multi-level technologies for FeRAM embedded reconfigurable hardware”, Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International, (Feb. 15-17, 1999),106-107.Applicant
- Benjamin, M. , “UV Photoemission Study of Heteroepitaxial AIGaN Films Grown on 6H-SiC”, Applied Surface Science, 104/105, (Sep. 1996),455-460.Applicant
- Bermudez, V. , “The Growth and Properties of AI and AIN Films on GaN(0001)-(1 × 1)”, Journal of Applied Physics, 79(1), (Jan. 1996),110-119.Applicant
- Bright, A A., et al., “Low-rate plasma oxidation of Si in a dilute oxygen/helium plasma for low-temperature gate quality Si/Sio2 interfaces”, Applied Physics Letters, 58(6), (Feb. 1991),619-621.Applicant
- Britton, J , et al., “Metal-nitride-oxide IC memory retains data for meter reader”, Electronics, 45(22), (Oct. 23, 1972),119-23.Applicant
- Bunshah, Rointan F., et al., “Deposition Technologies for Films and Coatings: Developments and Applications”, Park Ridge, N.J., U.S.A. : Noyes Publications, (1982),102-103.Applicant
- Carter, R J., “Electrical Characterization of High-k Materials Prepared by Atomic Layer CVD”, IWGI, (2001),94-99.Applicant
- Chae, Junghun , et al., “Atomic Layer Deposition of Nickel by the Reduction of Preformed Nickel Oxide”, Electrochemical & Solid-State Letters, 5(6), (Jun. 2002),C64-C66.Applicant
- Chaitsak, Suticai , et al., “Cu(InGa)Se/sub 2/ thin-film solar cells with high resistivity ZnO buffer layers deposited by atomic layer deposition”, Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 38(9A), (Sep. 1999),4989-4992.Applicant
- Chang, C. , “Novel Passivation Dielectrics-The Boron- or Phosphorus-Doped Hydrogenated Amorphous Silicon Carbide Films”, Journal of the Electrochemical Society, 132, (Feb. 1985),418-422.Applicant
- Fisch, D E., et al., “Analysis of thin film ferroelectric aging”, Proc. IEEE Int. Reliability Physics Symp., (1990),237-242.Applicant
- Forbes, L. , et al., “Field Induced Re-Emission of Electrons Trapped in SiO”, IEEE Transactions on Electron Devices, ED-26 (11), Briefs,(Nov. 1979),1816-1818.Applicant
- Hwang, N. , et al., “Tunneling and Thermal Emission of Electrons from a Distribution of Deep Traps in SiO”, IEEE Transactions on Electron Devices, 40(6), (Jun. 1993),1100-1103.Applicant
- Iddles, D M., et al., “Relationships between dopants, microstructure and the microwave dielectric properties of ZrO2-TiO2-SnO2 ceramics”, Journal of Materials Science, 27(23), (Dec. 1992),6303-6310.Applicant
- Kukli, K , et al., “Tailoring the dielectric properties of HfO2-Ta2O3 nanolaminates”, Appl. Phys. Lett., 68, (1996),3737-3739.Applicant
- Lee, A E., et al., “Epitaxially grown sputtered LaAI03 films”, Applied Physics Letters, 57(19), (Nov. 1990),2019-2021.Applicant
- Martins, R , “Transport Properties of Doped Silicon Oxycarbide Microcrystalline Films Produced by Spatial Separation Techniques”, Solar Energy Materials and Solar Cells, 41-42, (1996),493-517.Applicant
- Martins, R. , “Wide Band Gap Microcrystalline Silicon Thin Films”, Diffusion and Defect Data : Solid State Phenomena, 44-46, Part 1, Scitec Publications,(1995),299-346.Applicant
- Min, Jae-Sik , et al., “Atomic layer deposition of TiN films by alternate supply of tetrakis (ethylmethylamino)-titanium and ammonia”, Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 37(9A), (Sep. 1998),4999-5004.Applicant
- Min, J. , “Metal-organic atomic-layer deposition of titanium-silicon-nitride films”, Applied Physics Letters, 75(11), (1999),1521-1523.Applicant
- Moazzami, R , “Endurance properties of Ferroelectric PZT thin films”, Int. Electron Devices Mtg., San Francisco,(1990),417-20.Applicant
- Moazzami, R , “Ferroelectric PZT thin films for semiconductor memory”, Ph.D Thesis, University of California, Berkeley, (1991).Applicant
- Molnar, R. , “Growth of Gallium Nitride by Electron-Cyclotron Resonance Plasma-Assisted Molecular-Beam Epitaxy: The Role of Charged Species”, Journal of Applied Physics, 76(8), (Oct. 1994),4587-4595.Applicant
- Molodyk, A A., et al., “Volatile Surfactant-Assisted MOCVD: Application to LaAIO3 Thin Film Growth”, Chemical Vapor Deposition, 6(3), (Jun. 2000),133-138.Applicant
- Molsa, Heini , et al., “Growth of yttrium oxide thin films from beta -diketonate precursor”, Advanced Materials for Optics and Electronics, 4(6), (Nov.-Dec. 1994),389-400.Applicant
- Morishita, S , “Atomic-layer chemical-vapor-deposition of SiO/sub 2/ by cyclic exposures of CH/sub 3/OSi(NCO)/sub 3/ and H/sub 2/O/sub 2/”, Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 34(10), (Oct. 1995),5738-42.Applicant
- Moriwaki, M , “Improved metal gate process by simultaneous gate-oxide nitridation during W/WN/sub x/gate formation”, Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 39(4B), (Apr. 2000),2177-2180.Applicant
- Muller, D. A., et al., “The electronic structure at the atomic scale of ultrathin gate oxides”, Nature, 399, (Jun. 24, 1999),758-61.Applicant
- Nakagawara, Osamu , et al., “Electrical properties of (Zr, Sn)TiO4 dielectric thin film prepared by pulsed laser deposition”, Journal of Applied Physics, 80(1), (Jul. 1996),388-392.Applicant
- Nakajima, Anri , “NH/sub 3/-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability”, Applied Physics Letters, 80(7), (Feb. 2002),1252-1254.Applicant
- Nakajima, Anri , “Soft breakdown free atomic-layer-deposited silicon-nitride/SiO/sub 2/ stack gate dielectrics”, International Electron Devices Meeting. Technical Digest, (2001),6.5.1-4.Applicant
- Neumayer, D A., et al., “Materials characterization of ZrO/sub 2/-SiO/sub 2/ and HfO/sub 2/-SiO/sub 2/ binary oxides deposited by chemical solution deposition”, Journal of Applied Physics, 90(4), (Aug. 15, 2001), 1801-1808.Applicant
- Nieminen, Minna , “Formation and stability of lanthanum oxide thin films deposited from B-diketonate precursor”, Applied Surface Science, 174(2), (Apr. 16, 2001),155-165.Applicant
- Niilisk, A , “Atomic-scale optical monitoring of the initial growth of TiO2 thin films”, Proceedings of the SPIE—The International Society for Optical Engineering, 4318, (2001),72-77.Applicant
- Ohring, Milton , “The Materials Science of Thin Films”, Boston : Academic Press, (1992),118,121,125.Applicant
- Osten, H. J., et al., “High-k gate dielectrics with ultra-low leakage current based on praseodymium oxide”, International Electron Devices Meeting 2000. Technical Digest. IEDM, (2000),653-656.Applicant
- Pan, Tung M., et al., “High quality ultrathin CoTiO/sub 3/ high-k gate dielectrics”, Electrochemical and Solid-State Letters, 3(9), (Sep. 2000),433-434.Applicant
- Pan, Tung M., et al., “High-k cobalt-titanium oxide dielectrics formed by oxidation of sputtered Co/Ti or Ti/Co films”, Applied Physics Letters, 78(10), (Mar. 5, 2001),1439-1441.Applicant
- Pankove, J. , “Photoemission from GaN”, Applied Physics Letters, 25(1), (Jul. 1, 1974),53-55.Applicant
- Papadas, C. , “Modeling of the Intrinsic Retention Characteristics of FLOTOX EEPROM Cells Under Elevated Temperature Conditions”, IEEE Transaction on Electron Devices, 42, (Apr. 1995),678-682.Applicant
- Park, Byung-Eun , et al., “Electrical properties of LaAIO3/Si and Sr0.8Bi2.2Ta2O9/LaAIO3/Si structures”, Applied Physics Letters, 79(6), (Aug. 2001),806-808.Applicant
- Park, Jin-Seong , et al., “Plasma-Enhanced Atomic Layer Deposition of Tantalum Nitrides Using Hydrogen Radicals as a Reducing Agent”, Electrochemical & Solid-State Letters, 4(4), (Apr. 2001),C17-19.Applicant
- Perkins, Charles M., et al., “Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition”, Applied Physics Letters, 78(16), (Apr. 2001),2357-2359.Applicant
- Puurunen, R L., et al., “Growth of aluminum nitride on porous silica by atomic layer chemical vapour deposition”, Applied Surface Science, 165(2-3), (Sep. 12, 2000),193-202.Applicant
- Qi, Wen-Jie , et al., “MOSCAP and MOSFET characteristics using Zr02 gate dielectric deposited directly on Si”, Electron Devices Meeting, 1999. IEDM Technical Digest. International, (1999),145-148.Applicant
- Qi, Wen-Jie, et al., “Performance of MOSFETs with ultra thin ZrO/sub 2/ and Zr silicate gate dielectrics”, 2000 Symposium on VLSI Technology. Digest of Technical Papers, (2000),40-41.Applicant
- Ramakrishnan, E S., et al., “Dielectric properties of radio frequency magnetron sputter deposited zirconium titanate-based thin films”, Journal of the Electrochemical Society, 145(1), (Jan. 1998),358-362.Applicant
- Rayner Jr., G , et al., “The structure of plasma-deposited and annealed pseudo-binary ZrO2-SiO2 alloys”, Materials Research Society Symposium—Proceedings, 611, (2000),C131-C139.Applicant
- Renlund, G. M., “Silicon oxycarbide glasses: Part I. Preparation and chemistry”, J. Mater. Res., (Dec. 1991),pp. 2716-2722.Applicant
- Renlund, G. M., “Silicon oxycarbide glasses: Part II. Structure and properties”, J. Mater. Res., vol. 6, No. 12,(Dec. 1991),pp. 2723-2734.Applicant
- Ritala, Mikko , “Atomic Layer Epitaxy Growth of Titanium, Zirconium and Hafnium Dioxide Thin Films”, Annales Academiae Scientiarum Fennicae, (1994),24-25.Applicant
- Ritala, Mikko , “Zirconium dioxide thin films deposited by ALE using zirconium tetrachloride as precursor”, Applied Surface Science, 75, (Jan. 1994),333-340.Applicant
- Robertson, J. , “Band offsets of wide-band-gap oxides and implications for future electronic devices”, Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 18(3), (May-Jun. 2000),1785-1791.Applicant
- Rotondaro, A L., et al., “Advanced CMOS Transistors with a Novel HfSiON Gate Dielectric”, Symposium on VLSI Technology Digest of Technical Papers, (2002),148-149.Applicant
- Saito, Yuji , et al., “Advantage of Radical Oxidation for Improving Reliability of Ultra-Thin Gate Oxide”, 2000 Symposium on VLSI Technology Digest of Technical Papers, (2000),176-177.Applicant
- Saito, Yuji , et al., “High-Integrity Silicon Oxide Grown at Low-Temperature by Atomic Oxygen Generated in High-Density Krypton Plasma”, Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, (1999),152-153.Applicant
- Sanders, B W., et al., “Zinc Oxysulfide Thin Films Grown by Atomic Layer Deposition”, Chemistry of Materials, 4(5), (1992), 1005-1011.Applicant
- Shanware, A , et al., “Reliability evaluation of HfSiON gate dielectric film with 12.8 A SiO2 equivalent thickness”, International Electron Devices Meeting. Technical Digest, (2001),6.6.1-6.6.4.Applicant
- She, Min , et al., “Modeling and design study of nanocrystal memory devices”, IEEE Device Research Conference, (2001), 139-40.Applicant
- Shimada, H , et al., “Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer”, IEEE Transactions on Electron Devices, vol. 48, No. 8, (Aug. 200),1619-1626.Applicant
- Shin, Chang H., “Fabrication and Characterization of MFISFET Using AI2O3 Insulating Layer for Non-volatile Memory”, 12th International Symposium in Integrated Ferroelectrics, (Mar. 2000),9 pages.Applicant
- Shirota, R , et al., “A 2.3 mu m/sup 2/ memory cell structure for 16 Mb NAND EEPROMs”, International Electron Devices Meeting 1990. Technical Digest, San Francisco,(1990),103-106.Applicant
- Sneh, Ofer , et al., “Thin film atomic layer deposition equipment for semiconductor processing”, Thin Solid Films, 402(1-2), (Jan. 1, 2002),248-261.Applicant
- Solanki, Raj , et al., “Atomic Layer Deposition of Copper Seed Layers”, Electrochemical & Solid-State Letters, 3(10), (Oct. 2000),479-480.Applicant
- Song, Hyun-Jung , et al., “Atomic Layer Deposition of Ta2O5 Films Using Ta(OC2H5)5 and NH3”, Ultrathin SiO/sub 2/ and High-K Materials for ULSI Gate Dielectrics. Symposium, (1999),469-471.Applicant
- Suntola, T , “Atomic layer epitaxy”, Thin Solid Films, 216(1), (Aug. 28, 1992),84-89.Applicant
- Suntola, T. , “Atomic Layer Epitaxy”, Handbook of Crystal Growth, 3; Thin Films of Epitaxy, Part B: Growth Mechanics and Dynamics, Amsterdam,(1994),601-663.Applicant
- Sze, S M., “Physics of Semiconductor Devices”, New York : Wiley, (1981),504-506.Applicant
- Sze, S M., “Physics of Semiconductor Devices”, New York : Wiley, (1981),473.Applicant
- Sze, S M., “Physics of semiconductor devices”, New York: Wiley, (1981),504-506.Applicant
- Takemoto, J. H., et al., “Microstrip Resonators and Filters Using High-TC Superconducting Thin Films on LaAIO3”, IEEE Transaction on Magnetics, 27(2), (Mar. 1991),2549-2552.Applicant
- Tarre, A , et al., “Comparative study of low-temperature chloride atomic-layer chemical vapor deposition of TiO2 and SnO2”, Applied Surface Science, 175-176, (May 2001), 111-116.Applicant
- Van Dover, R B., “Amorphous lanthanide-doped TiOx dielectric films”, Applied Physics Letters, 74(20), (May 1999),3041-3043.Applicant
- Van Dover, Robert B., et al., “Deposition of Uniform Zr-Sn-Ti-O films by ON-Axis Reactive Sputtering”, IEEE Electron Device Letters, 19(9), (Sep. 1998),329-331.Applicant
- Van Dover, R. B., “Discovery of a useful thin-film dielectric using a composition-spread approach”, Nature, 392, (Mar. 12, 1998), 162-164.Applicant
- Viirola, H , “Controlled growth of antimony-doped tin dioxide thin films by atomic layer epitaxy”, Thin Solid Films, 251, (Nov. 1994),127-135.Applicant
- Viirola, H , et al., “Controlled growth of tin dioxide thin films by atomic layer epitaxy”, Thin Solid Films, 249(2), (Sep. 1994),144-149.Applicant
- Visokay, M R., “Application of HfSiON as a gate dielectric material”, Applied Physics Letters, 80(17), (Apr. 2002),3183-3185.Applicant
- Wei, L S., et al., “Trapping, emission and generation in MNOS memory devices”, Solid-State Electronics, 17(6), (Jun. 1974),591-8.Applicant
- White, M H., et al., “Characterization of thin-oxide MNOS memory transistors”, IEEE Transactions on Electron Devices, ED-19(12), (Dec. 1972),1280-1288.Applicant
- White, M H., “Direct tunneling in metal-nitride-oxide-silicon (MNOS) structures”, Programme of the 31st physical electronics conference, (1971),1.Applicant
- Wilk, G D., et al., “Hafnium and zirconium silicates for advanced gate dielectrics”, Journal of Applied Physics, 87(1), (Jan. 2000),484-492.Applicant
- Wilk, G. D., “High-K gate dielectrics: Current status and materials properties considerations”, Journal of Applied Physics, 89(10), (2001),5243-5275.Applicant
- Wolf, Stanley , et al., “Silicon Processing for the VLSI Era—vol. 1: Process Technology”, Second Edition, Lattice Press, Sunset Beach, California,(2000),443.Applicant
- Wood, S W., “Ferroelectric memory design”, M.A.Sc. thesis, University of Toronto, (1992).Applicant
- Yagishita, A , “Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current and uniform electrical characteristics”, International Electron Devices Meeting 2000. Technical Digest. IEDM, (Dec. 2000),663-666.Applicant
- Yoder, M , “Wide Bandgap Semiconductor Materials and Devices”, IEEE Transactions on Electron Devices, 43, (Oct. 1996),1633-1636.Applicant
- Zhang, H. , “Atomic Layer Deposition of High Dielectric Constant Nanolaminates”, Journal of The Electrochemical Society, 148(4), (Apr. 2001),F63-F66.Applicant
- Zhu, W J., et al., “Current transport in metal/hafnium oxide/silicon structure”, IEEE Electron Device Letters, 23, (2002),97-99.Applicant
- Zhu, W , et al., “HfO2 and HfAIO for CMOS: Thermal Stability and Current Transport”, IEEE International Electron Device Meeting 2001, (2001),463-466.Applicant
- Zucker, O , et al., “Application of Oxygen Plasma Processing to Silicon Direct Bonding”, Sensors and Actuators A, 36, (1993),227-231.Applicant
- “U.S. Appl. No. 10-177213 non-final office action mailed Apr. 23, 2004”, 12 pgs.Applicant
- “U.S. Appl. No. 10-177213 Notice of allowance mailed May 5, 2005”, 4 pgs.Applicant
- “U.S. Appl. No. 10-177213 Notice of allowance mailed Jul. 14, 2006”, 2 pgs.Applicant
- “U.S. Appl. No. 10-177213 Response filed Oct. 28, 2004 to final office action mailed Sep. 28, 2004”, 14 pgs.Applicant
- “U.S. Appl. No. 10-177213 Response filed Feb. 18, 2005 to non-final office action mailed Dec. 28, 2004”, 14 pgs.Applicant
- “U.S. Appl. No. 10-177213 Response filed May 5, 2006 to non-final office action mailed Feb. 8, 2006”, 12 pgs.Applicant
- “U.S. Appl. No. 10-177213 Response filed Jul. 27, 2004 to non-final office action mailed Apr. 23, 2004”, 6 pgs.Applicant
- “U.S. Appl. No. 10-177483 Notice of allowance mailed Oct. 5, 2004”, 5 pgs.Applicant
- “U.S. Appl. No. 10-177483 Notice of allowance mailed Dec. 31, 2003”, 4 pgs.Applicant
- “U.S. Appl. No. 10-177483 Notice of allowance mailed Jul. 12, 2005”, 4 pgs.Applicant
- “U.S. Appl. No. 10-190689 final office action mailed Feb. 27, 2007”, 9 pgs.Applicant
- “U.S. Appl. No. 10-190689 final office action mailed Feb. 9, 2005”, 8 pgs.Applicant
- “U.S. Appl. No. 10-190689 final office action mailed Apr. 6, 2006”, 7 pgs.Applicant
- “U.S. Appl. No. 10-190689 non-final office action mailed Oct. 6, 2005”, 7 pgs.Applicant
- “U.S. Appl. No. 10-190689 non-final office action mailed Jul. 8, 2003”, 6 pgs.Applicant
- “U.S. Appl. No. 10-190689 non-final office action mailed Aug. 23, 2006”, 7 pgs.Applicant
- “U.S. Appl. No. 10-190689 non-final office action mailed Aug. 25, 2004”, 5 pgs.Applicant
- “U.S. Appl. No. 10-190689 Notice of allowance mailed Dec. 30, 2003”, 4 pgs.Applicant
- “U.S. Appl. No. 10-190689 Response filed Jan. 6, 2006 to non-final office action mailed Oct. 6, 2005”, 18 pgs.Applicant
- “U.S. Appl. No. 10-190689 Response filed Oct. 20, 2003 to non-final office action mailed Jul. 8, 2003”, 42 pgs.Applicant
- “U.S. Appl. No. 10-190689 Response filed Nov. 10, 2004 to non-final office action mailed Aug. 25, 2006”, 18 pgs.Applicant
- “U.S. Appl. No. 10-190689 Response filed Nov. 22, 2006 to non-final office action mailed Aug. 23, 2006”, 18 pgs.Applicant
- “U.S. Appl. No. 10-190689 Response filed Apr. 11, 2005 to final office action mailed Feb. 9, 2005”, 20 pgs.Applicant
- “U.S. Appl. No. 10-190689 Response filed Apr. 11, 2005 to final office action mailed Feb. 9, 2005”, 20 pgs.Applicant
- “U.S. Appl. No. 10-190689 response filed Apr. 26, 2007 to final office action mailed Feb. 27, 2007”, 15 pgs.Applicant
- “U.S. Appl. No. 10-190689 Response filed May 6, 2004 to non-final office action mailed Mar. 30, 2004”, 18 pgs.Applicant
- “U.S. Appl. No. 10-190689 Response filed Jun. 6, 2006 to final office action mailed Apr. 6, 2006”, 18 pgs.Applicant
- “U.S. Appl. No. 10-190717 Amendment under 37 C.F.R. filed Jul. 26, 2004”, 24 pgs.Applicant
- “U.S. Appl. No. 10-190717 final office action mailed Apr. 19, 2005”, 12 pgs.Applicant
- “U.S. Appl. No. 10-190717 final office action mailed Apr. 26, 2004”, 11 pgs.Applicant
- “U.S. Appl. No. 10-190717 final office action mailed May 2, 2006”, 13 pgs.Applicant
- “U.S Appl. No. 10-190717 non-final office action mailed Oct. 7, 2004”, 11 pgs.Applicant
- “U.S. Appl. No. 10-190717 non-final office action mailed Nov. 1, 2005”, 13 pgs.Applicant
- “U.S. Appl. No. 10-190717 non-final office action mailed Jul. 20, 2006”, 14 pgs.Applicant
- “U.S. Appl. No. 10-190717 non-final office action mailed Sep. 25, 2003”, 14 pgs.Applicant
- “U.S. Appl. No. 10-190717 Notice of allowance mailed Dec. 13, 2006”, 5 pgs.Applicant
- “U.S. Appl. No. 10-190717 Response filed Jan. 26, 2004 to non-final office action mailed Sep. 25, 2003”, 26 pgs.Applicant
- “U.S. Appl. No. 10-190717 Response filed Jan. 7, 2005 to non-final office action mailed Oct. 7, 2004”, 23 pgs.Applicant
- “U.S. Appl. No. 10-190717 Response filed Nov. 20, 2006 to non-final office action mailed Jul. 20, 2006”, 14 pgs.Applicant
- “U.S. Appl. No. 10-190717 Response filed Feb. 1, 2006 to non-final office action mailed Nov. 1, 2005”, 24 pgs.Applicant
- “U.S. Appl. No. 10-190717 Response filed Jun. 30, 2006 to final office action mailed May 2, 2006”, 13 pgs.Applicant
- “U.S. Appl. No. 10-190717 Response filed Jul. 19, 2005 to final office action mailed Apr. 19, 2005”, 24 pgs.Applicant
- “U.S. Appl. No. 10-191336 final office action mailed Mar. 21, 2005”, 7 pgs.Applicant
- “U.S. Appl. No. 10-191336 final office action mailed May 23, 2006”, 7 pgs.Applicant
- “U.S. Appl. No. 10-191336 final office action mailed Jun. 8, 2005”, 6 pgs.Applicant
- “U.S. Appl. No. 10-191336 non-final office action mailed Nov. 2, 2005”, 9 pgs.Applicant
- “U.S. Appl. No. 10-191336 non-final office action mailed Mar. 3, 2004”, 8 pgs.Applicant
- “U.S. Appl. No. 10-191336 non-final office action mailed Aug. 20, 2003 PGS”, 10 pgs.Applicant
- “U.S. Appl. No. 10-191336 non-final office action mailed Aug. 20, 2004”, 7 pgs.Applicant
- “U.S. Appl. No. 10-191336 Notice of allowance mailed Nov. 14, 2006”, 2 pgs.Applicant
- “U.S. Appl. No. 10-191336 Response filed Nov. 10, 2004 to non-final office action mailed Aug. 20, 2004”, 19 pgs.Applicant
- “U.S. Appl. No. 10-191336 Response filed Nov. 20, 2003 to non-final office action mailed Aug. 20, 2003”, 41 pgs.Applicant
- “U.S. Appl. No. 10-191336 Response filed Feb. 2, 2006 to non-final office action mailed Nov. 2, 2005”, 19 pgs.Applicant
- “U.S. Appl. No. 10-191336 Response filed May 6, 2005 to final office action mailed Mar. 21, 2005”, 18 pgs.Applicant
- “U.S. Appl. No. 10-191336 Response filed Jun. 3, 2004 to non-final office action mailed Mar. 3, 2004”, 19 pgs.Applicant
- “U.S. Appl. No. 10-191336 Response filed Aug. 23, 2006 to final office action mailed May 23, 2006”, 10 pgs.Applicant
- “U.S. Appl. No. 10-191336 Response filed Aug. 8, 2005 to final office action mailed Jun. 8, 2005”, 21 pgs.Applicant
- “U.S. Appl. No. 10-739767 Notice of allowance mailed Oct. 14, 2004”, 6 pgs.Applicant
- “U.S. Appl. No. 10-739767 Notice of allowance mailed Dec. 1, 2005”, 6 pgs.Applicant
- “U.S. Appl. No. 10-739767 Notice of allowance mailed Feb. 18 2005”, 5 pgs.Applicant
- “U.S. Appl. No. 10-739767 Notice of allowance mailed May 30, 2006”, 6 pgs.Applicant
- “U.S. Appl. No. 10-930514 Notice of allowance mailed Oct. 4, 2005”, 1 pg.Applicant
- “U.S. Appl. No. 10-930514 Notice of allowance mailed Apr. 5, 2006”, 2 pgs.Applicant
- “U.S. Appl. No. 10-930514 Notice of allowance mailed Jun. 13, 2005”, 4 pgs.Applicant
- “U.S. Appl. No. 10-930514 Amendement under 37 C.F.R. filed Jan. 3, 2006”, 9 pgs.Applicant
- “U.S. Appl. No. 10-932955 non-final office action mailed Jan. 31, 2006”, 16 pgs.Applicant
- “U.S. Appl. No. 10-932955 Notice of allowance mailed May 4, 2005”, 4 pgs.Applicant
- “U.S. Appl. No. 10-932955 Notice of allowance mailed Jul. 31, 2006”, 4 pgs.Applicant
- “U.S. Appl. No. 10-932955 Response filed May 1, 2006 to non-final office action mailed Jan. 31, 2006”, 15 pgs.Applicant
- “U.S. Appl. No. 10-933050 final office action mailed Apr. 19, 2006”, 12 pgs.Applicant
- “U.S. Appl. No. 10-933050 final office action mailed Apr. 24, 2007”, 12 pgs.Applicant
- “U.S. Appl. No. 10-933050 non-final office action mailed Oct. 18, 2005”, 12 pgs.Applicant
- “U.S. Appl. No. 10-933050 non-final office action mailed Oct. 20, 2006”, 10 pgs.Applicant
- “U.S. Appl. No. 10-933050 Response filed Jan. 22, 2007 to non-final office action mailed Oct. 18, 2005”, 15 pgs.Applicant
- “U.S. Appl. No. 10-933050 Response filed Jan. 22, 2007 to non-final office action mailed Oct. 20, 2006”, 14 pgs.Applicant
- “U.S. Appl. No. 10-933050 Response filed Jun. 19, 2006 to final office action mailed Apr. 19, 2006”, 15 pgs.Applicant
- “U.S. Appl. No. 10-933050 Response filed Jun. 25, 2007 to final office action mailed Apr. 27, 2007”, 14 pgs.Applicant
- “U.S. Appl. No. 10/933,050, Non-Final Office Action mailed Sep. 11, 2007”, 13 pgs.Applicant
- “U.S. Appl. No. 11-005909 non-final office action mailed Sep. 12, 2006”, 5 pgs.Applicant
- “U.S. Appl. No. 11-005909 Notice of allowance mailed Jan. 16, 2007”, 2 pgs.Applicant
- “U.S. Appl. No. 11-005909 Response filed Dec. 12, 2006 to non-final office action mailed Sep. 12, 2006”, 9 pgs.Applicant
- “U.S. Appl. No. 11-006312 Notice of allowance mailed Mar. 8, 2006”, 2 pgs.Applicant
- “U.S. Appl. No. 11-006312 Notice of allowance mailed May 5, 2005”, 4 pgs.Applicant
- “U.S. Appl. No. 11-006312 Notice of allowance mailed Sep. 8, 2005 PGS4.pfd”, 4.Applicant
- “U.S. Appl. No. 11-215496 Notice of allowance mailed Jan. 25, 2006”, 6 pgs.Applicant
- “U.S. Appl. No. 11-215496 Notice of allowance mailed Jul. 6, 2006”, 2 pgs.Applicant
- “U.S. Appl. No. 11/005,909, Notice of Allowance mailed Sep. 7, 2007”, 6 pgs.Applicant
- “U.S. Appl. No. 11/217,771, Non-Final Office Action mailed Oct. 5, 2007”, 33 pgs.Applicant
- “U.S. Appl. No. 11/427,038, Restriction Requirement mailed Jul. 20, 2007”, 4 pgs.Applicant
- “U.S. Appl. No. 10-177077 Notice of allowance mailed Nov. 8, 2002”, 5 pgs.Applicant
- “U.S. Appl. No. 10-177077 Notice of allowance mailed Dec. 12, 2003”, 6 pgs.Applicant
- “U.S. Appl. No. 10-177077 Notice of allowance mailed Mar. 27, 2003”, 7 pgs.Applicant
- “U.S. Appl. No. 10-177077 Notice of allowance mailed Apr. 23, 2004”, 5 pgs.Applicant
- “U.S. Appl. No. 10-177083 Notice of allowance mailed Nov. 29, 2005 PGS4.pdf”, 4 pgs.Applicant
- “U.S. Appl. No. 10-177083 Notice of allowance mailed Dec. 16, 2003”, 3 pgs.Applicant
- “U.S. Appl. No. 10-177083 Notice of allowance mailed Apr. 20, 2004”, 4 pgs.Applicant
- “U.S. Appl. No. 10-177083 Notice of allowance mailed Apr. 4, 2006”, 2 pgs.Applicant
- “U.S. Appl. No. 10-177083 Notice of allowance mailed Aug. 12, 2005”, 5 pgs.Applicant
- “U.S. Appl. No. 10-177213 final office action mailed Sep. 28, 2004”, 16 pgs.Applicant
- “U.S. Appl. No. 10-177213 non-final office action mailed Dec. 28, 2004”, 12 pgs.Applicant
- “U.S. Appl. No. 10-177213 non-final office action mailed Feb. 8, 2006”, 6 pgs.Applicant