Semiconductor storage device capable of improving controllability of density and size of floating gate

[0002] The present invention relates to a semiconductor storage device that is electrically erasable and programmable and has non-volatility.

[0003] For achieving low power consumption and compacting of electronic equipment, there is needed a semiconductor storage device (EEPROM) that has a high degree of integration and a low power consumption and is electrically erasable and programmable. The semiconductor storage device having the non-volatility has a floating gate between its channel region and gate electrode, and this floating gate is operated as a carrier confining region, the device generally having the following problems.

[0004] (i) Since the number of injection and removal of electric charges in the floating gate are limited due to the problem of a reduction in reliability resulting from a hot carrier, there is a limitation in the number of times of write and erase operations.

[0005] (ii) A relatively thick insulating film is needed for maintaining the non-volatility. In order to inject an electron or a positive hole into the floating gate by the FOWLER-NORDHEIM tunnel effect through this thick insulating film, a high voltage of not lower than 10 V is required in the present situation. As a result, a hot carrier is generated, and this causes a deterioration of the insulating film by the influence of the formation of a trap and a reaction in the interface due to the hot carrier and alleviation of the hot carrier.

[0006] (iii) Since the write and erase operations are executed by a very small current flowing by charging and discharging of the floating gate, the time of charging and discharging is long (on the millisecond order).

[0007] Accordingly, a semiconductor storage device that resolves the above problems (i) through (iii) is proposed (Japanese Patent Laid-Open Publication No. HEI 7-302848). In this semiconductor storage device, as shown in FIG. 5, a source region 108 and a drain region 110 are formed at a specified interval on a semiconductor substrate 120, and a floating gate 104 is formed in a region opposite to a channel region 106 between the source and drain regions 108 and 110 via an insulating layer 112 on the semiconductor substrate 120. Then, the floating gate 104 is covered with an insulating layer 102, and a control gate 100 is formed on the insulating layer 102. As shown in FIG. 6, the floating gate 104 is provided in the form of a cluster or an island 122 constructed of a semiconductor material having a diameter of 1 nm to 20 nm. Then, the insulating layer 112 located between the channel region 106 and the floating gate 104 is made as thin as possible so as to allow an electron to directly pass through the layer 112 by the tunnel effect, and the energy level of the floating gate 104 is made lower than that of the channel region 106, thereby preventing the trapped electron from easily escaping.

[0008] The following two reference documents describe the fabricating methods of the above floating gate.

[0009] (1) A silicon nanocrystals based memory, Sandip Tiwari et al., Appl. Phys. Lett. 68 (10), p1377 (1996)

[0010] FIG. 7 shows a schematic diagram of a cross-section of a semiconductor storage device having a floating gate described in the above literature, where a tunnel insulating film 202 having a thickness of 1.1 nm to 1.8 nm is formed on a semiconductor substrate 201 on which a source region 206 and a drain region 207 are formed, and nano-crystals 203 having a diameter of 5 nm are formed at intervals of 5 nm on the tunnel insulating film 202 by a CVD (Chemical Vapor Deposition) system. The density of the nanocrystal 203 is 1×10¹²cm⁻². Further, a control gate insulating film 204 is formed on the nanocrystals 203, and SiO₂is deposited to a thickness of 7 nm on the control gate insulating film 204, thereby forming a control gate 205.

[0011] (2) Fast and Long Retention-time Nano-Crystal Memory, Hussein I. Hanafi et al., IEEE Trans. Electron Device, Vol. 43, p1553 (1996)

[0012] FIGS. 8A through 8C show a fabricating method of a semiconductor storage device having a floating gate described in the above literature, according to which a thermal oxide film 302 is formed to a thickness of 5 nm to 20 nm on a semiconductor substrate 301 (shown in FIG. 8A) and a high dose of ions of silicon Si or germanium Ge is implanted into the thermal oxide film 302 in a supersaturated state (shown in FIG. 8B). The ion implantation in this case is performed under, for example, the conditions of 5 keV and 5×10¹⁵cm⁻². Subsequently, a heat treatment is effected for 30 minutes at a temperature of 950° C. in an atmosphere of nitrogen N₂, thereby growing nano-crystals 303 of silicon Si or germanium Ge having a diameter of 5 nm in the thermal oxide film 302. Then, a source region 305 and a drain region 306 are formed at a regular interval on the semiconductor substrate 301, and a gate electrode 304 is formed on the thermal oxide film 302 oppositely to a region located between the source region 305 and the drain region 306 (shown in FIG. 8C).

[0013] As described in the above literatures (1) and (2), a shift voltage ΔVth of a threshold voltage Vth when one electron is stored in one nano-crystal is expressed by the following equation:

[0014] ΔVth=q(n_wel/ε_ox)(t_cnt1+(ε_OX/ε_si)t_well/2)  (equation 1)

[0015] where

[0016] q: electron charge,

[0017] n_well: nano-crystal density,

[0018] ε_ox: dielectric constant of oxide film,

[0019] t_cnt1: film thickness of control gate oxide film,

[0020] ε_si: dielectric constant of silicon, and

[0021] t_well: nano-crystal size.

[0022] As is apparent from the above equation 1, it can be understood that a variation in device characteristics (ΔVth) can be reduced by reducing a variation in nano-crystal density n_welland nano-crystal size t_well. The film thickness of the tunnel insulating film located between the nano-crystal and the channel is a determinant of the direct tunneling of an electron to the nano-crystal (the probability of tunneling is expressed by a function of the film thickness of the tunnel insulating film), and therefore, a variation in the film thickness of the tunnel insulating film influences the variation in write characteristics. As described above, the above nano-crystal density, nano-crystal size and film thickness of the tunnel insulating film located between the nano-crystal and the channel are the principal parameters to be controlled inherent in the memory.

[0023] The semiconductor storage device of the literature (1) utilizes the nano-crystals that happen to be present on the surface of the ground SiO2 film or the nano-crystals that grow in an island shape around random crystalline nuclei occurring in an early stage of CVD. Therefore, neither the nano-crystal density nor the nano-crystal size is controlled, and this leads to the problem that the characteristics vary. On the other hand, in regard to the film thickness of the tunnel insulating film located between the nano-crystals and the channel, because the semiconductor substrate is thermally oxidized in advance, it can be considered that the film thickness can be controlled by the prior art techniques.

[0024] In the semiconductor storage device of the literature (2), ions of silicon Si or germanium Ge are implanted into the thermal oxide film 302 and thereafter subjected to heat treatment for the growth of a nano-crystal in the thermal oxide film 302. However, the implanted ion concentration is distributed in the depthwise direction, for which the ion concentration in the thermal oxide film 302 cannot be uniformed. Therefore, the heat treatment is performed in the state in which the concentration distribution is varied, and therefore, the nano-crystal density in the depthwise direction inside the thermal oxide film 302 also has a distribution. Therefore, it is considered difficult to control the nano-crystal density, the nano-crystal size and the film thickness of the tunnel insulating film located between the nano-crystals and the channel. That is, in regard to the subjects of the nano-crystal density, the nano-crystal size and the film thickness of the tunnel insulating film located between the nano-crystals and the channel, it is difficult to improve the controllability and uniformity of them, and this leads to the problem that the characteristics are varied.

[0025] Furthermore, in order to implant ions into the very thin oxide film having the film thickness of 5 nm to 20 nm without making the ions reach the ground semiconductor substrate, it is required to achieve ion implantation with as low energy as possible, the energy being, for example, 5 keV with respect to the oxide film having a thickness of 20 nm. If the film thickness of the oxide film is further reduced, then the energy must be further reduced. With the performance of the ordinary ion implanter, it is difficult to control such a low-energy ion implantation, meaning that this is impractical as a fabricating method.

[0026] Accordingly, an object of the present invention is to provide a semiconductor storage device capable of improving controllability of density and size of a floating gate of crystal grains as well as the film thickness of an insulating film located between its region and a channel region and reducing the variation in characteristics such as a threshold voltage and a writing performance, the device also having a low consumption power and a non-volatility.

[0027] In order to achieve the aforementioned object, the present invention provides a semiconductor storage device comprising: a source region and a drain region formed of a semiconductor material; a channel region located between the source region and the drain region; a control gate region that is formed above the channel region and controls a channel current flowing through the channel region; and a first insulating film, a floating gate region and a second insulating film that are arranged in order from the control gate region side between the channel region and the gate region,

[0028] the floating gate region being comprised of a plurality of granular regions discretely linearly arranged substantially parallel to a surface of the channel region or a linear region continuously formed substantially parallel to the surface of the channel region.

[0029] According to the semiconductor storage device of the present invention, the floating gate region is constituted by the plurality of granular regions discretely linearly arranged substantially parallel to the surface of the channel region or the linear region continuously formed substantially parallel to the surface of the channel region, where the granular regions are one-dimensionally arranged or the linear region is one-dimensionally arranged. This arrangement reduces the degree of freedom of variation in comparison with the floating gate region arranged two-dimensionally or three-dimensionally, thereby theoretically improving the controllability of the size, number and position. The reason for the above will be described below.

[0030] First, for simplicity of explanation, here is now considered the case where x crystal grains are arranged in a limited square region. Assuming that there are N×N positions where the crystal grains are grown, a probability that the crystal grain will grow in each position is p and a probability that the crystal grain will not grow in the position is q, then a probability of the growth of x crystal grains is given by a binomial distribution (N>x, N and x are integers and q=1−p).

[0031] In the above case, the average gain number m to be arranged and dispersion σ²are expressed as:

[0032] average gain number m=N²pand dispersion σ²=N²pq=N²p(1−p).

[0033] When the crystal grains are grown in a specified row or column of this region (linear growth defined by the linear arrangement of crystal grains), an average gain number m′ and a dispersion σ′²become:

[0034] average gain number m′=Np′and dispersion σ′²=Np′q′=Np′(1−p′).

[0035] Assuming now that the average gain number m is m′, then

[0036] N²p=Np′

[0037] therefore,

[0038] p′=Np

[0039] σ′²=N²p(1−Np)

[0040] provided that (1−Np)>0. Then the consequence is:

[0041] (two-dimensional dispersion σ²)−(linear dispersion σ²)=N²p(1−p)−N²p(1−Np)=N²p²(N−1)>0

[0042] meaning that the two-dimensional dispersion has a greater variation (dispersion). In regard to the crystal grain size, if the average value of the crystal grain size of the two-dimensional arrangement and the crystal grain size of the linear arrangement are made equal to each other, then the variation of the two-dimensional arrangement similarly becomes greater.

[0043] Therefore, according to this semiconductor storage device, the controllability of the density and size of the floating gate region can be increased. Since no floating gate region is formed in the insulating film, the controllability of the film thickness of the second insulating film located between the floating gate region and the channel region can be improved, so that the variation in device characteristics can be remarkably reduced.

[0044] In one embodiment, the floating gate region is comprised of the plurality of granular regions and a size D of the granular regions in the floating gate satisfies the conditions:

[0045] q²/(4 πε_iD)>kT,

[0046] and

[0047] ε_i=(ε₁+ε₂)/2

[0048] where q is an electron charge, ε₁is a dielectric constant of the first insulating film, ε₂is a dielectric constant of the second insulating film, k is Boltzmann constant and T is a temperature.

[0049] According to the semiconductor storage device of the above embodiment, a self-capacitance C of one granular region in the floating gate region is expressed by 2 πε_iD, and an electrostatic energy when one electron is stored in one granular region becomes q²/(2C). In this case, to achieve an effect (coulomb blockade) for preventing an electron from entering into one granular region after one electron has been stored in the region for the suppression of the number of electrons to be stored in all the granular regions of the floating gate region to the required number, an increase in the electrostatic energy q²/(2C) when one electron is stored in one granular region is required to be greater than a thermal fluctuation energy kT. Therefore, by setting the size D of the granular region so as to satisfy the condition of q²/(4 πε_iD)>kT, the coulomb blockade can be utilized in each granular region of the floating gate region, so that the number of electrons to be stored can be controlled. This remarkably reduces a current to be used for writing when injecting an electron into the floating gate region, so that a low consumption power can be achieved.

[0050] In one embodiment, the floating gate region is made of one metal selected from the group consisting of tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium and iridium or a mixture or alloy of at least two metals selected from the group consisting of tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium and iridium.

[0051] According to the semiconductor storage device of the above embodiment, the granular regions or the linear region constituting the floating gate region is made of a metal material, and therefore, an electron can be confined in the floating gate region interposed between the first and second insulating films.

[0052] In one embodiment, the floating gate region is made of one semiconductor material selected from the group consisting of silicon, germanium, a mixture of silicon and germanium, a compound of the groups III and V or a compound of the groups II and VI.

[0053] According to the semiconductor storage device of the above embodiment, the granular regions or the linear region constituting the floating gate region is made of a semiconductor material, and therefore, an electron can be confined in the floating gate region interposed between the first and second insulating films.

[0054] In one embodiment, the floating gate region is the linear region, and the floating gate region is comprised of a polycrystal semiconductor.

[0055] According to the semiconductor storage device of the above embodiment, the linear region constituting the floating gate region is comprised of a polycrystal semiconductor, and therefore, an electron can be confined in the crystal grain in the linear region interposed between the first and second insulating films.

[0056] In one embodiment, a crystal grain size A in a lengthwise direction and a cross-sectional area S of the linear region of the floating gate region satisfy the conditions:

[0057] q²/(2C)>kT,

[0058] C=2 πε_iA/log [{(A/2+(A²/4+s²/4)^½)}/(S/2)]

[0059] and

[0060] ε_i=(ε₁+ε₂)/2

[0061] where q is the electron charge, ε₁is the dielectric constant of the first insulating film, ε₂is the dielectric constant of the second insulating film, k is Boltzmann constant and T is a temperature.

[0062] According to the semiconductor storage device of the above embodiment, the self-capacitance C of one crystal grain in the linear region of the floating gate region is expressed by:

[0063] C=2 πε_iA/log [{(A/2+(A²/4+s²/4)^½)}/(S/2)]

[0064] where the electrostatic energy when one electron is stored in one crystal grain becomes q²/(2C). In order to achieve the effect (coulomb blockade) for preventing an electron from entering into one crystal grain after one electron has been stored in the grain for the suppression of the number of electrons to be stored in the linear region of the floating gate region to the required number, an increase in the electrostatic energy q²/(2C) when one electron is stored in one crystal grain is required to be greater than the thermal fluctuation energy kT. Therefore, by setting the size A in the lengthwise direction and the cross-sectional area S of the crystal grain of the linear region of the floating gate region so as to satisfy the condition of q²/(2C)>kT, the coulomb blockade can be utilized in each crystal grain in the linear region of the floating gate region, so that the number of electrons to be stored can be controlled. This remarkably reduces a current to be used for writing when injecting an electron into the floating gate region, so that a low consumption power can be achieved.

[0065] In one embodiment, the number N of crystal grains in the linear region on the channel region and the size A of the crystal grain in the lengthwise direction of the linear region satisfy the conditions:

[0066] q(N/LWε_i)(t₁+(ε_i/ε₁)A/2)>kT/q

[0067] and

[0068] ε_i=(ε₁+ε₂)/2

[0069] where q is an electron charge, L is a length of the channel region, W is a width of the channel region, ε₁is a dielectric constant of the first insulating film, ε₂is a dielectric constant of the second insulating film and t₁is a film thickness of the first insulating film.

[0070] According to the semiconductor storage device of the above embodiment, in order to externally sense the shift voltage ΔVth representing a change in the threshold voltage Vth due to the electron stored in the floating gate region, the shift voltage ΔVth is required to be greater than the thermal fluctuation energy. Therefore, by setting the number N of the crystal grains in the floating gate region existing above the channel region so as to satisfy the condition:

[0071] ΔVth=q(N/LWε₁)(t_i+(ε_i/ε₁)A/2)>kT/q,

[0072] the shift voltage ΔVth of the threshold voltage Vth sufficient for the operation as a memory can be obtained.

[0073] The present invention also provides a semiconductor storage device comprised of a MOS transistor having a floating gate region located between a control gate region and a channel region,

[0074] the floating gate region being comprised of a plurality of nano-crystals linearly arranged substantially parallel to a surface of a channel region.

[0075] According to the semiconductor storage device of the above invention, the floating gate region is constituted by the plurality of nano-crystals linearly arranged substantially parallel to the surface of the channel region, where the nano-crystals are one-dimensionally arranged. This arrangement reduces the degree of freedom of variation in comparison with the floating gate region arranged two-dimensionally or three-dimensionally and improves the controllability of the size, number and position. Therefore, the present semiconductor storage device can improve the controllability of the density and size of the floating gate region, so that the variation in device characteristics can be remarkably reduced.

[0076] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

[0077] FIGS. 1A, 1B, 1C, 1D and 1E are views showing a fabricating method of a semiconductor storage device according to a first embodiment of the present invention;

[0078] FIGS. 2A, 2B, 2C, 2D and 2E are views showing a fabricating method of a semiconductor storage device according to a second embodiment of the present invention;

[0079] FIG. 3 is a sectional view of the semiconductor storage device of the first embodiment, wherein nano-crystals are formed on an SOI substrate;

[0080] FIG. 4 is a sectional view of the semiconductor storage device of the second embodiment, wherein nano-crystals are formed on an SOI substrate;

[0081] FIG. 5 is a sectional view of a prior art semiconductor storage device;

[0082] FIG. 6 is an enlarged view showing a floating gate of the above semiconductor storage device;

[0083] FIG. 7 is a schematic view of a cross-section of a prior art semiconductor storage device having nano-crystals on a tunnel insulating film; and

[0084] FIGS. 8A, 8B and 8C are views showing the processes of a fabricating method of a prior art semiconductor storage device having nano-crystals in its thermal oxide film.

[0085] The semiconductor storage device of the present invention will be described in detail below based on the embodiments thereof shown in the drawings.

[0086] FIGS. 1A through 1E are views showing a fabricating method of a semiconductor storage device according to a first embodiment of the present invention. In this first embodiment, a semiconductor storage device employing a granular floating gate will be described.

[0087] First, as shown in FIG. 1A, an element isolation insulating film 2 is formed on a monocrystal silicon substrate 1 by a general element isolating technique, forming an active region 3 having a width of 0.2 μm.

[0088] Next, as shown in FIG. 1B, the surface of the silicon substrate 1 is oxidized by RTO (Rapid Thermal Oxidation) under the following conditions, thereby forming a tunnel oxide film 4 that serves as a second insulating film having a thickness of 2 nm on the surface of the silicon substrate 1.

[0089] mixed gas of N₂O and O₂: N₂O/(N₂O+O₂)=65%

[0090] temperature: 1050° C. Then, a polycrystal silicon thin film 5 having a thickness of 10 nm is formed on the tunnel oxide film 4 by a CVD (Chemical Vapor Deposition) equipment.

[0091] Next, as shown in FIG. 1C, the polycrystal silicon thin film 5 is patterned by EB (Electron Beam) lithography and RIE (Reactive Ion Etching), thereby forming a thin line 5ahaving a width of 25 nm.

[0092] Next, as shown in FIG. 1D, the thin line 5amade of polycrystal silicon is oxidized in a water vapor atmosphere. If the oxidation is effected so that the film thickness of the oxide film becomes about 14 nm, the thin line 5acomes to have a form in which crystal grains 6athat serve as a granular region having a height of 3 nm and a size of about 11 nm are linearly arranged because the oxidation at the grain boundary in the water vapor atmosphere is twice as fast as a speed in dry oxygen. That is, the thin line 5ahas a form in which rectangular parallelepiped crystal grains having a height of 10 nm, a length of 15 nm and a width of 25 nm are continuously arranged in a line. Each crystal grain comes to have a length of 9 nm (=15−3×2) by being consumed in the lengthwise direction by 3 nm due to the oxidation from the grain boundary side, and comes to have a height of 3 nm (=10−7) and a width of 11 nm (=25−7×2) by being consumed by 7 nm due to the oxidation in the other directions.

[0093] Next, as shown in FIG. 1E, SiO₂is deposited to a thickness of 10 nm on the tunnel oxide film 4 and the crystal grains 6aby the CVD equipment, thereby forming a control gate insulating film 7 that serves as a first insulating film. Then, a polycrystal silicon region is formed on the control gate insulating film 7 and doped with phosphor at a high concentration for the reduction in resistance, and a gate electrode 8 is formed as a control gate region. The gate electrode 8 has a gate length of 0.2 μm.

[0094] Subsequently, source and drain regions 9 and 10 are formed on the active region 3 by the normal LSI (Large Scale Integrated Circuit) fabricating process, and an interlayer insulating film, a contact hole, interconnections and a passivation film (these are not shown) are successively formed. The gate electrode 8 controls a channel current flowing through the channel region 3alocated between the source and drain regions 9 and 10.

[0095] As a material for the floating gate 6, a material having a conductivity such as a metal may be employed, and it is acceptable to employ a metal of, for example, tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium and iridium or a mixture or alloy of these materials. In this case, the crystal grains 6athat serve as the granular regions constituting the floating gate 6 are made of metal, and therefore, an electron can be confined in the floating gate 6 interposed between the tunnel insulating film 4 and the control gate insulating film 7.

[0096] As another material for the floating gate 6, it is acceptable to employ a semiconductor material of germanium, a mixture of silicon and germanium, a compound of the groups III and V (a combination of Al, Ga or In belonging to the group III and P, As or Sb belonging to the group V), a compound of the groups II and VI (a combination of Zn, Cd or Hg belonging to the group II and O, S, Se or Te belonging to the group VI) or the like.

[0097] As described above, in the above semiconductor storage device, the controllability of the density and size of the crystal grains 6aof the floating gate 6 that serves as the carrier confining region can be improved. Since no floating gate is formed in the insulating film, the film thickness of the tunnel insulating film 4 between the crystal grains 6aand the channel region can easily be controlled, so that the variation in characteristics such as the threshold voltage and the writing performance can be reduced. There can be provided a semiconductor storage device capable of storing therein information at room temperature without necessitating cooling to the extremely low temperature. Furthermore, by employing this semiconductor storage device, an information storage device (memory) which has a reduced amount of elements and a small area, permits fast rewriting and has non-volatility can be realized.

[0098] By setting the size D of the granular region of the floating gate 6 so as to satisfy the conditions:

[0099] q²/(4 πε_iD)>kT,

[0100] and

[0101] ε_i=(ε₁+ε₂)/2

[0102] where

[0103] q: electron charge,

[0104] ε₁: dielectric constant of control gate insulating film 7 (first insulating film),

[0105] ε₂: dielectric constant of tunnel insulating film 4 (second insulating film),

[0106] k: Boltzmann constant and

[0107] T: temperature,

[0108] the coulomb blockade can be utilized in the crystal grains 6aof the floating gate 6, so that the number of electrons to be stored can be controlled. This can remarkably reduce the current to be used for writing to inject an electron into the floating gate 6, so that a low consumption power can be achieved.

[0109] The crystal grains 6athat serve as the granular region constituting the floating gate 6 are made of a semiconductor material, and therefore, electrons can be confined in the floating gate 6 interposed between the tunnel insulating film 4 and the control gate insulating film 7.

[0110] FIGS. 2A through 2E are views showing fabricating processes of a semiconductor storage device according to a second embodiment of the present invention. In this second embodiment, a semiconductor storage device uses a linear floating gate.

[0111] The above semiconductor storage device can be formed basically through the same processes as those of the first embodiment. However, in order to make the floating gate of a continuous thin line, polycrystal silicon is once processed into a thin line and thereafter oxidized in dry oxygen.

[0112] That is, as shown in FIG. 2A, an element isolation insulating film 12 is formed on a monocrystal silicon substrate 11 by the general element isolating technique, thereby forming an active region 3 having a width of 0.2 μm.

[0113] Next, as shown in FIG. 2B, the surface of the silicon substrate 11 is oxidized by RTO (Rapid Thermal Oxidation) under the following conditions, thereby forming a tunnel oxide film 14 that serves as a second insulating film having a thickness of 2 nm on the surface of the silicon substrate 11.

[0114] mixed gas of N₂O and O₂: N₂O/(N₂O+O₂)=65%

[0115] temperature: 1050° C.

[0116] Then, a polycrystal silicon thin film 15 having a thickness of 10 nm is formed on the tunnel oxide film 14 by a CVD equipment.

[0117] Next, as shown in FIG. 2C, the polycrystal silicon thin film 15 is patterned by EB (Electron Beam) lithography and RIE (Reactive Ion Etching), thereby forming a thin line 15ahaving a width of 25 nm.

[0118] Next, as shown in FIG. 2D, the thin line 15amade of polycrystal silicon is oxidized in dry oxygen. In the oxygen, the accelerated oxidation as observed at the grain boundary of the first embodiment is suppressed, and therefore, the thin line 15achanges into a floating gate 16 that is the linear region having a thickness of 3 nm and a width of 11 nm.

[0119] Next, as shown in FIG. 2E, SiO₂is deposited to a thickness of 10 nm on the tunnel oxide film 14 and the floating gate 16 by the CVD equipment, thereby forming a control gate insulating film 17 that serves as a first insulating film. Then, a polycrystal silicon region is formed on the control gate insulating film 17 and doped with phosphor at a high concentration for the reduction in resistance, and a gate electrode 18 is formed.

[0120] Subsequently, source and drain regions 19 and 20 are formed on the active region 13 by the normal LSI (Large Scale Integrated Circuit) fabricating process, and an interlayer insulating film, a contact hole, interconnections and a passivation film (these are not shown) are successively formed.

[0121] As a material for the above floating gate, a material having a conductivity such as a metal may be employed, and it is acceptable to employ a metal of, for example, tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium and iridium or a mixture or alloy of these materials. In this case, the crystal grains 16aconstituting the floating gate 16 are made of metal, and therefore, electrons can be confined in the floating gate 16 interposed between the tunnel insulating film 14 and the control gate insulating film 17.

[0122] As another material for the above floating gate, it is acceptable to employ a semiconductor material of germanium, a mixture of silicon and germanium, a compound of the groups III and V, a compound of the groups II and VI or the like.

[0123] In regard to the forming methods of the crystal grain 6athat serves as the floating gate 6 of the first embodiment and the linear region of the floating gate 16 of the second embodiment, the present invention is not limited to those of the first and second embodiments, and any appropriate fabricating method may be used depending on the material of the floating gate.

[0124] As described above, in the above semiconductor storage device, the controllability of the density and size of the crystal grains 16aof the floating gate 16 that serves as the carrier confining region can be improved. Since no floating gate is formed in the insulating film, the film thickness of the tunnel insulating film 14 between the crystal grains 16aand the channel region 13acan easily be controlled, so that the dispersion in characteristics such as the threshold voltage and the writing performance can be reduced. There can be provided a semiconductor storage device capable of storing therein information at room temperature without necessitating cooling to the extremely low temperature. Furthermore, by employing this semiconductor storage device, an information storage device (memory) which has a reduced amount of elements and a small area can be constructed, permits fast rewriting and has non-volatility can be realized.

[0125] Since the floating gate 16 is made of polycrystal semiconductor, electrons can be confined in the floating gate 16 interposed between the tunnel insulating film 14 and the control gate insulating film 17.

[0126] By setting the size A in the lengthwise direction and the cross-sectional area S of the crystal grain 16ain the linear region of the floating gate 16 so as to satisfy the conditions:

[0127] q²/(2C)>kT,

[0128] C=2 πε_iA/log [{(A/2+(A²/4+s²/4)^½)}/(S/2)]

[0129] and

[0130] ε_i=(ε₁+ε₂)/2

[0131] where

[0132] q: electron charge,

[0133] ε₁: dielectric constant of control gate insulating film 17 (first insulating film),

[0134] ε₂: dielectric constant of tunnel insulating film 14 (second insulating film),

[0135] k: Boltzmann constant and

[0136] T: temperature,

[0137] the coulomb blockade can be utilized in each crystal grain 16ain the linear region of the floating gate 16, so that the number of electrons to be stored can be controlled. This remarkably reduces the current to be used for writing to inject an electron into the floating gate 16, so that a low consumption power can be achieved.

[0138] By setting the number N of the crystal grains 16aof the floating gate 16 above the channel region and the size A of each crystal grain 16aso as to satisfy the conditions:

[0139] q(N/LWε_i)(t₁+(ε₁/ε₁)A/2)>kT/q

[0140] and

[0141] ε_i=(ε₁+ε₂)/2

[0142] where

[0143] q: electron charge,

[0144] L: length of channel region,

[0145] W: width of channel region, and

[0146] t₁: film thickness of tunnel insulating film 14,

[0147] the shift voltage ΔVth of the threshold voltage Vth sufficient for operation as a memory can be obtained.

[0148] Although the first and second embodiments employ the monocrystal silicon substrates 1 and 11, an SOI (Semiconductor on Insulator) substrate as provided by SIMOX (isolation by Implanted Oxygen) may be employed.

[0149] For example, as shown in FIG. 3, a tunnel insulating film 4 is formed on an SOI substrate constructed of a semiconductor substrate 31, a buried oxidation layer 32 and a semiconductor layer 33, and a floating gate 6 constructed of a plurality of granular regions is formed on the tunnel insulating film 4. Then, a control gate insulating film 7 is formed on the floating gate 6 and the tunnel insulating film 4, and a gate electrode 8 is formed in a region opposite to a channel region 3alocated between a source region 9 and a drain region 10 formed in the semiconductor layer 33 on the control gate insulating film 7.

[0150] As shown in FIG. 4, a tunnel insulating film 14 is formed on an SOI substrate constructed of a semiconductor substrate 41, a buried oxidation layer 42 and a semiconductor layer 43, and a linear floating gate 16 is formed on the tunnel insulating film 14. Then, a control gate insulating film 17 is formed on the floating gate 16 and the tunnel insulating film 14, and a gate electrode 18 is formed in a region opposite to a channel region 13alocated between a source region 19 and a drain region 20 formed in the semiconductor layer 43 on the control gate insulating film 17.

[0151] According to the semiconductor storage device of the present invention, a floating gate is constructed of linearly discretely arranged crystal grains or linearly continuously arranged crystal grains. Therefore, the controllability of the density (number) and size of the crystal grains of the floating gate can be improved without dispersion in comparison with a floating gate region arranged two-dimensionally or three-dimensionally. Furthermore, since no floating gate is formed in an insulating film, the film thickness of an insulating film located between the floating gate region and a channel region can easily be controlled, so that the variation in characteristics such as a threshold voltage and a writing performance can be reduced. There can be provided a semiconductor storage device capable of storing therein information at room temperature without necessitating cooling to an extremely low temperature. Furthermore, by employing this semiconductor storage device, an information storage device (memory) which has a reduced amount of elements and a small area, permits fast rewriting and has non-volatility can be provided.

[0152] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.