US 6,778,441 B2Grant
Integrated circuit memory device and method
Issue Date:2004-08-17
•81 Claims
•15 Drawing Sheets
Abstract
Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Metadata
Assignee
- Micron Technology, Inc.
Inventors
- Leonard Forbes
- Jerome M. Eldridge
- Kie Y. Ahn
Application Information
Application Number:US 09/945,498
Filing Date:2001-08-30
Priority Date:2001-08-30
Art Unit:7
Classifications
IPC:
G11C 1604H01L 29788H01L 21336
Field of Search:
25731525731625731736518526438257438259438262438268438270438264
Patent Drawings (15 sheets)
Description
Cross Reference to Related Application
[0002] This application is related to the following co-pending, commonly assigned U.S. patent applications: “DRAM Cells with Repressed Memory Metal Oxide Tunnel Insulators,” Ser. No. 09/945,395, “Programmable Array Logic or Memory Devices with Asymmetrical Tunnel Barriers,” , Ser. No. 09/943,134, “Flash Memory with Low Tunnel Barrier Interpoly Insulators,” Ser. No. 09/945,507, and “Field Programmable Logic Arrays with Metal Oxide and/or Low Tunnel Barrier Interpoly Insulators,” Ser. No. 09/945,512, “SRAM Cells with Repressed Floating Gate Memory, Metal Oxide Tunnel Interpoly Insulators,” Ser. No. 09/945,554, “Programmable Memory Address and Decode Devices with Low Tunnel Barrier Interpoly Insulators,” Ser. No. 09/945,500, which are filed on even date herewith and each of which disclosure is herein incorporated by reference.
Field of the Invention
[0003] The present invention relates generally to integrated circuits, and in particular to DEAPROM memory-with low tunnel barrier interpoly insulators which require refresh.
Background of the Invention
[0004] Flash memories have become widely accepted in a variety of applications ranging from personal computers, to digital cameras and wireless phones. Both INTEL and AMD have separately each produced about one billion integrated circuit chips in this technology.
[0005] The original EEPROM or EARPROM and flash memory devices described by Toshiba in 1984 used the interpoly dielectric insulator for erase. (See generally, F. Masuoka et al. “A new flash EEPROM cell using triple polysilicon technology,” IEEE Int. Electron Devices Meeting, San Francisco, pp. 464-67, 1984; F. Masuoka et al., “256 K flash EEPROM using triple polysilicon technology,” IEEE Solid-State Circuits Conf., Philadelphia, pp. 168-169, 1985). Various combinations of silicon oxide and silicon nitride were tried. (See generally, S. Mori et al., “reliable CVD inter-poly dialectics for advanced E&EEPROM,” Symp. On VLSI Technology, Kobe, Japan, pp. 16-17, 1985). However, the rough top surface of the polysilicon floating gate resulted in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems.
[0006] Widespread use of flash memories did not occur until the introduction of the ETOX cell by INTEL in 1988. (See generally, U.S. Pat. No. 4,780,424, “Process for fabricating electrically alterable floating gate memory devices,” Oct. 25, 1988; B. Dipert and L. Hebert, “Flash memory goes mainstream,” IEEE Spectrum, pp. 48-51, October, 1993; R. D. Pashley and S. K. Lai, “Flash memories, the best of two worlds,” IEEE Spectrum, pp. 30-33, December 1989). This extremely simple cell and device structure resulted in high densities, high yield in production and low cost. This enabled the widespread use and application of flash memories anywhere a non-volatile memory function is required. However, in order to enable a reasonable write speed the ETOX cell uses channel hot electron injection, the erase operation which can be slower is achieved by Fowler-Nordhiem tunneling from the floating gate to the source. The large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, result in slow write and erase speeds even at very high electric fields. The combination of very high electric fields and damage by hot electron collisions in the oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase.
[0007] Other approaches to resolve the above described problems include; the use of different floating gate materials, e.g. SiC, SiOC, GaN, and GaAIN, which exhibit a lower work function (see FIG. 1A), the use of structured surfaces which increase the localized electric fields (see FIG. 1B), and amorphous SiC gate insulators with larger electron affinity, χ, to increase the tunneling probability and reduce erase time (see FIG. 1C).
[0008] One example of the use of different floating gate (FIG. 1A) materials is provided in U.S. Pat. No. 5,801,401 by L. Forbes, entitled “FLASH MEMORY WITH MICROCRYSTALLINE SILICON CARBIDE AS THE FLOATING GATE STRUCTURE.” Another example is provided in U.S. Pat. No. 5,852,306 by L. Forbes, entitled “FLASH MEMORY WITH NANOCRYSTALLINE SILICON FILM AS THE FLOATING GATE.” Still further examples of this approach are provided in pending applications by L. Forbes and K. Ahn, entitled “DYNAMIC RANDOM ACCESS MEMORY OPERATION OF A FLASH MEMORY DEVICE WITH CHARGE STORAGE ON A LOW ELECTRON AFFINITY GaN OR GaAIN FLOATING GATE,” Ser. No. 08/908098, and “VARIABLE ELECTRON AFFINITY DIAMOND-LIKE COMPOUNDS FOR GATES IN SILICON CMOS MEMORIES AND IMAGING DEVICES,” Ser. No. 08/903452.
[0009] An example of the use of the structured surface approach (FIG. 1B) is provided in U.S. Pat. No. 5,981,350 by J. Geusic, L. Forbes, and K. Y. Ahn, entitled “DRAM CELLS WITH A STRUCTURE SURFACE USING A SELF STRUCTURED MASK.” Another example is provided in U.S. Pat. No. 6,025,627 by L. Forbes and J. Geusic, entitled “ATOMIC LAYER EXPITAXY GATE INSULATORS AND TEXTURED SURFACES FOR LOW VOLTAGE FLASH MEMORIES.”
[0010] Finally, an example of the use of amorphous SiC gate insulators (FIG. 1C) is provided in U.S. patent application Ser. No. 08/903453 by L. Forbes and K. Ahn, entitled “GATE INSULATOR FOR SILICON INTEGRATED CIRCUIT TECHNOLOGY BY THE CARBURIZATION OF SILICON.”
[0011] Additionally, graded composition insulators to increase the tunneling probability and reduce erase time have been described by the same inventors. (See, L. Forbes and J. M. Eldridge, “GRADED COMPOSITION GATE INSULATORS TO REDUCE TUNNELING BARRIERS IN FLASH MEMORY DEVICES,” application Ser. No. 09/945514.
[0012] The authors of the present invention have also previously described the concept of a programmable read only memory which requires refresh or is volatile as a consequence of leakage currents though gate dielectrics with a low tunnel barrier between a floating gate and the silicon substrate/well, transistor source, drain, and body regions. (See generally, L. Forbes, J. Geusic and K. Ahn, “DEAPROM (Dynamic Electrically Alterable Programmable Read Only Memory) UTILIZING INSULATING AND AMORPHOUS SILICON CARBIDE GATE INSULATOR,” application Ser. No. 08/902,843). An application relating to leakage currents through an ultrathin gate oxide has also been provided. (See generally, L. Forbes, E. H. Cloud, J. E. Geusic, P. A. Farrar, K. Y. Ahn, and A. R. Reinberg; and D. J. McElroy, and L. C. Tran, “DYNAMIC FLASH MEMORY CELLS WITH ULTRATHIN TUNNEL OXIDES,” U.S. Pat. No. 6,249,460).
[0013] However, all of these approaches relate to increasing tunneling between the floating gate and the substrate such as is employed in a conventional ETOX device and do not involve tunneling between the control gate and floating gate through an inter-poly dielectric.
[0014] Therefore, there is a need in the art to provide improved DEAPROM cells which increase memory densities while avoiding the large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, which result in slow write and erase speeds even at very high electric fields. There is also a need to avoid the combination of very high electric fields and damage by hot electron collisions in the which oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase. Further, when using an interpoly dielectric insulator erase approach, the above mentioned problems of having a rough top surface on the polysilicon floating gate which results in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems must be avoided.
Summary of the Invention
[0015] The above mentioned problems with DEAPROM memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for DEAPROM memories with metal oxide and/or low tunnel barrier interpoly insulators which require refresh. That is, the present invention describes the use of an ultra-thin metal oxide inter-poly dielectric insulators between the control gate and the floating gate to create a memory cell which has a high current gain, and is easy to program by tunneling but which requires refresh. The low barrier tunnel insulator between the floating gate and control gates makes erase of the cell easy but results in the requirement for refresh. These devices act like DRAM's and can be utilized as DRAM replacements. A coincident address is achieved by addressing both the control gate address lines (y-address) and source address lines (x-address).
[0016] In one embodiment of the present invention, the DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
[0017] These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
Brief Description of the Drawings
[0018] FIGS. 1A-1C illustrate a number of previous methods for reducing tunneling barriers in DEAPROM memory.
[0019] FIG. 2 illustrates one embodiment of a floating gate transistor, or DEAPROM memory cell, according to the teachings of the present invention.
[0020] FIG. 3 illustrates another embodiment of a floating gate transistor, or DEAPROM memory cell, according to the teachings of the present invention.
[0021] FIG. 4 is a perspective view illustrating an array of silicon pillars formed on a substrate as used in one embodiment according to the teachings of the present invention.
[0022] FIGS. 5A-5E are cross sectional views taken along cut line 5—5 from FIG. 4 illustrating a number of floating gate and control gate configurations which are included in the scope of the present invention.
[0023] FIGS. 6A-6D illustrate a number of address coincidence schemes can be used together with the present invention.
[0024] FIG. 7A is an energy band diagram illustrating the band structure at vacuum level with the low tunnel barrier interpoly insulator according to the teachings of the present invention.
[0025] FIG. 7B is an energy band diagram illustrating the band structure during an erase operation of electrons from the floating gate to the control gate across the low tunnel barrier interpoly insulator according to the teachings of the present invention.
[0026] FIG. 7C is a graph plotting tunneling currents versus the applied electric fields (reciprocal applied electric field shown) for an number of barrier heights.
[0027] FIG. 8 is an energy band diagram illustrating work function, tunnel barrier heights and electron affinities for a low tunnel barrier intergate insulator according to the teachings of the present invention.
[0028] FIG. 9 illustrates a block diagram of an embodiment of an electronic system according to the teachings of the present invention.
Description of the Preferred Embodiments
[0029] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. The embodiments are intended to describe aspects of the invention in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and changes may be made without departing from the scope of the present invention. In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art.
[0030] The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
[0031] The present invention describes the use of an ultra-thin metal oxide inter-poly dielectric insulators having a tunnel barrier of less than 1.5 eV between the control gate and the floating gate. As shown in FIG. 2, the ultra-thin metal oxide inter-poly dielectric insulators having a tunnel barrier of less than 1.5 eV are used to create a memory cell which has a high current gain, and is easy to program by tunneling but which requires refresh. The low barrier tunnel insulator between the floating gate and control gates makes erase of the cell easy but results in the requirement for refresh. One possible array structure is shown in FIG. 6A, described in more detail below. These devices of the present invention act like DRAM's and can be utilized as DRAM replacements. In brief, FIG. 6A illustrates that a coincident address is achieved by addressing both the control gate address lines (y-address) and source address lines (x-address).
[0032] Also, as described in more detail below, FIG. 7A shows the conventional silicon oxide gate insulator with a high barrier and then the low tunnel barrier interpoly or intergate insulator between the floating gate and the control gate, as according to the present invention. According to the teachings of the present invention, if the interpoly dielectric is thin enough, e.g. less than 20 Angstroms, or the barrier is low enough, e.g. less than 1.5 eV, to allow a very easy erase then there will be some finite leakage current when the device is addressed for read operations and/or is in a standby state. This will require refresh of the memory state. The tunneling current in erasing charge from the floating gate by tunneling to the control gate will then be as shown and described below in FIG. 7C given by an equation of the form:
[0033] J=B exp(−Eo/E)
[0034] where E is the electric field across the interpoly dielectric insulator 707 and Eo depends on the barrier height. Aluminum oxide has a current density of 1 A/cm2at a field of about E=1V/20Å=5×10+6V/cm. Silicon oxide transistor gate insulators have a current density of 1 A/cm2at a field of about E =2.3V/23 A=1×10+7V/cm. The lower electric field in the aluminum oxide interpoly insulator for the same current density reflects the lower tunneling barrier of less than 2.0 eV as opposed to the 3.2 eV tunneling barrier of silicon oxide.
[0035] FIG. 7C, discussed below, illustrates the dependence of the tunneling currents on electric field (reciprocal electric field) and barrier height. Low barriers will result in high current densities at low electric fields during write and erase, however, they will also conduct some small but significant current during the electric fields employed, for read and as a consequence the data must be refreshed. These memory devices work on a dynamic basis.
[0036] As stated above, the present invention describes the use of metal oxide interpoly dielectric insulators between the control gate and the floating gate. An example is shown in FIG. 2 for a planar structure, or horizontal DEAPROM memory cell. According to the teachings of the present invention. The use of metal oxide films for this purpose offer a number of advantages including:
[0037] (i) Flexibility in selecting a range of smooth metal film surfaces and compositions that can be oxidized to form tunnel barrier insulators.
[0038] (ii) Employing simple “low temperature oxidation” to produce oxide films of highly controlled thickness, composition, purity and uniformity.
[0039] (iii) Avoiding inadvertent inter-diffusion of the metal and silicon as well as silicide formation since the oxidation can be carried out at such low temperatures.
[0040] (iv) Using metal oxides that provide desirably lower tunnel barriers, relative to barriers currently used such as SiO2.
[0041] (v) Providing a wide range of higher dielectric constant oxide films with improved capacitance characteristics.
[0042] (vi) Providing a unique ability to precisely tailor tunnel oxide barrier properties for various device designs and applications.
[0043] (vii) Permitting the use of thicker tunnel barriers, if needed, to enhance device performance and its control along with yield and reliability.
[0044] (viii) Developing layered oxide tunnel barriers by oxidizing layered metal film compositions in order, for example, to enhance device yields and reliability more typical of single insulating layers.
[0045] (ix) Eliminating soft erase errors caused by the current technique of tunnel erase from floating gate to the source.
[0046] FIG. 2 illustrates one embodiment of a floating gate transistor, or DEAPROM memory cell 200, according to the teachings of the present invention. As shown in FIG. 2, the DEAPROM memory cell 200 includes a first source/drain region 201 and a second source/drain region 203 separated by a channel region 205 in a substrate 206. A floating gate 209 opposes the channel region 205 and is separated therefrom by a gate oxide 211. A control gate 213 opposes the floating gate 209. According to the teachings of the present invention, the control gate 213 is separated from the floating gate 209 by a low tunnel barrier intergate insulator 215 having a tunnel barrier height of less than 1.5 eV, and which requires refresh.
[0047] In one embodiment of the present invention, low tunnel barrier intergate insulator 215 includes a metal oxide insulator selected from the group consisting of nickle oxide (NiO) and aluminum oxide (Al2O3) and having a thickness of less than 20 Angstroms. In an alternative embodiment of the present invention, the low tunnel barrier intergate insulator 215 includes a transition metal oxide and the transition metal oxide is selected from the group consisting of Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, and Gd2O3having a tunnel barrier of less than 1.5 eV. In still another alternative embodiment of the present invention, the low tunnel barrier intergate insulator 215 includes a Perovskite oxide tunnel barrier selected from the group consisting of SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3having a tunnel barrier of less than 1.5 eV.
[0048] According to the teachings of the present invention, the floating gate 209 includes a polysilicon floating gate 209 having a metal layer 216 formed thereon in contact with the low tunnel barrier intergate insulator 215. Likewise, the control gate 213 includes a polysilicon control gate 213 having a metal layer 217 formed thereon in contact with the low tunnel barrier intergate insulator 215. In one embodiment, the metal layers 216 and 217, are formed of platinum (Pt). In an alternative embodiment, the metal layers 216 and 217, are formed of aluminum (Al).
[0049] FIG. 3 illustrates another embodiment of a floating gate transistor, or DEAPROM memory cell 300, according to the teachings of the present invention. As shown in the embodiment of FIG. 3, the DEAPROM memory cell 300 includes a vertical non volatile memory cell 300. In this embodiment, the DEAPROM memory cell 300 has a first source/drain region 301 formed on a substrate 306. A body region 307 including a channel region 305 is formed on the first source/drain region 301. A second source/drain region 303 is formed on the body region 307. A floating gate 309 opposes the channel region 305 and is separated therefrom by a gate oxide 311. A control gate 313 opposes the floating gate 309. According to the teachings of the present invention, the control gate 313 is separated from the floating gate 309 by a low tunnel barrier intergate insulator 315 having a tunnel barrier height of less than 1.5 eV, and which requires refresh.
[0050] In one embodiment of the present invention, low tunnel barrier intergate insulator 315 includes a metal oxide insulator selected from the group consisting of nickle oxide (NiO) and aluminum oxide (Al2O3) and having a thickness of less than 20 Angstroms. In an alternative embodiment of the present invention, the low tunnel barrier intergate insulator 315 includes a transition metal oxide and the transition metal oxide is selected from the group consisting of Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, and Gd2O3having a tunnel barrier of less than 1.5 eV. In still another alternative embodiment of the present invention, the low tunnel barrier intergate insulator 315 includes a Perovskite oxide tunnel barrier selected from the group consisting of SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3having a tunnel barrier of less than 1.5 eV.
[0051] According to the teachings of the present invention, the floating gate 309 includes a polysilicon floating gate 309 having a metal layer 316 formed thereon in contact with the low tunnel barrier intergate insulator 315. Likewise, the control gate 313 includes a polysilicon control gate 313 having a metal layer 317 formed thereon in contact with the low tunnel barrier intergate insulator 315. In one embodiment, the metal layers 316 and 317, are formed of platinum (Pt). In an alternative embodiment, the metal layers 316 and 317, are formed of aluminum (Al).
[0052] As shown in FIG. 3, the floating gate 309 includes a vertical floating gate 309 formed alongside of the body region 307. In the embodiment shown in FIG. 3, the control gate 313 includes a vertical control gate 313 formed alongside of the vertical floating gate 309.
[0053] As will be explained in more detail below, the floating gate 309 and control gate 313 orientation shown in FIG. 3 is just one embodiment for a vertical non volatile memory cell 300, according to the teachings of the present invention. In other embodiments, explained below, the floating gate includes a horizontally oriented floating gate formed alongside of the body region. In this alternative embodiment, the control gate includes a horizontally oriented control gate formed above the horizontally oriented floating gate.
[0054] FIG. 4 is a perspective view illustrating an array of silicon pillars 400-1, 400-2, 400-3, . . . , 400-N, formed on a substrate 406 as used in one embodiment according to the teachings of the present invention. As will be understood by one of ordinary skill in the art upon reading this disclosure, the substrates can be (i) conventional p-type bulk silicon or p-type epitaxial layers on p+ wafers, (ii) silicon on insulator formed by conventional SIMOX, wafer bonding and etch back or silicon on sapphire, or (iii) small islands of silicon on insulator.
[0055] As shown in FIG. 4, each pillar in the array of silicon pillars 400-1, 400-2, 400-3, . . . , 400-N, includes a first source/drain region 401 and a second source/drain region 403. The first and the second source/drain regions, 401 and 403, are separated by a body region 407 including channel regions 405. As shown in FIG. 4, a number of trenches 430 separate adjacent pillars in the array of silicon pillars 400-1, 400-2, 400-3, . . . , 400-N. Trenches 430 are referenced in connection with the discussion which follows in connection with FIGS. 5A-5E.
[0056] FIGS. 5A-5E are cross sectional views taken along cut line 5—5 from FIG. 4. As mentioned above in connection with FIG. 3, a number of floating gate and control gate configurations are included in the present invention. FIG. 5A illustrates one such embodiment of the present invention. FIG. 5A illustrates a first source/drain region 501 and second source/drain region 503 for a DEAPROM memory cell 500 formed according to the teachings of the present invention. As shown in FIG. 5, the first and second source/drain regions, 501 and 503, are contained in a pillar of semiconductor material, and separated by a body region 507 including channel regions 505. As shown in the embodiments of FIGS. 5A-5E, the first source/drain region 501 is integrally connected to a buried sourceline 525. As one or ordinary skill in the art will understand upon reading this disclosure the buried sourceline 525 is be formed of semiconductor material which has the same doping type as the first source/drain region 501. In one embodiment, the sourceline 525 is formed of semiconductor material of the same doping as the first source/drain region 501, but is more heavily doped than the first source/drain region 501.
[0057] As shown in the embodiment of FIG. 5A, a pair of floating gates 509-1 and 509-2 are formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.
[0058] In this embodiment, a single control gate 513 is shared by the pair of floating gates 509-1 and 509-2 on opposing sides of the trench 530. As one of ordinary skill in the art will understand upon reading this disclosure, the shared single control gate 513 can include an integrally formed control gate line. As shown in FIG. 5A, such an integrally formed control gate line 513 can be one of a plurality of control gate lines which are each independently formed in the trench, such as trench 530, below the top surface of t he pillars 500-1 and 500-2 and between the pair of floating gates 509-1 and 509-2. In one embodiment, according to the teachings of the present invention, each floating gate, e.g. 509-1 and 509-2, includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.
[0059] As shown in the embodiment of FIG. 5B, a pair of floating gates 509-1 and 509-2 are formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.
[0060] In the embodiment of FIG. 5B, a plurality of control gate lines are again formed in trenches, e.g. trench 530, below the top surface of the pillars, 500-1 and 500-2, and between the pair of floating gates 509-1 and 509-2. However, in this embodiment, each trench, e.g. 530, houses a pair of control gate lines, shown as 513-1 and 513-2. Each one of the pair of control gate lines 513-1 and 513-2 addresses the floating gates, 509-1 and 509-2 respectively, on opposing sides of the trench 530. In this embodiment, the pair of control gate lines, or control gates 513-1 and 513-2 are separated by an insulator layer.
[0061] As shown in the embodiment of FIG. 5C, a pair of floating gates 509-1 and 509-2 are again formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.
[0062] In the embodiment of FIG. 5C, the plurality of control gate lines are disposed vertically above the floating gates. That is, in one embodiment, the control gate lines are located above the pair of floating gates 509-1 and 509-2 and not fully beneath the top surface of the pillars 500-1 and 500-2. In the embodiment of FIG. 5C, each pair of floating gates, e.g. 509-1 and 509-2, in a given trench shares a single control gate line, or control gate 513.
[0063] As shown in the embodiment of FIG. 5D, a pair of floating gates 509-1 and 509-2 are formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.
[0064] In the embodiment of FIG. 5D, the plurality of control gate lines are disposed vertically above the floating gates. That is, in one embodiment, the control gate lines are located above the pair of floating gates 509-1 and 509-2 and not fully beneath the top surface of the pillars 500- land 500-2. However, in the embodiment of FIG. 5D, each one of the pair of floating gates, e.g. 509-1 and 509-2, is addressed by an independent one of the plurality of control lines or control gates, shown in FIG. 5D as 513-l and 513-2.
[0065] As shown in the embodiment of FIG. 5E, a single floating gate 509 is formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. According to the teachings of the present invention, the single floating gate 509 can be either a vertically oriented floating gate 509 or a horizontally oriented floating gate 509 formed by conventional processing techniques, or can be a horizontally oriented floating gate 509 formed by replacement gate techniques. In one embodiment of the present invention, the floating gate 509 has a vertical length facing the body region 505 of less than 100 nm. In another embodiment, the floating gate 509 has a vertical length facing the body region 505 of less than 50 nm. In one embodiment, as shown in FIG. 5E, the floating gate 509 is shared, respectively, with the body regions 507-1 and 507-2, including channel regions 505-1 and 505-2, in adjacent pillars 500-1 and 500-2 located on opposing sides of the trench 530. And, as shown in FIG. 5E, the control gate includes a single horizontally oriented control gate line, or control gate 513 formed above the horizontally oriented floating gate 509.
[0066] As one of ordinary skill in the art will understand upon reading this disclosure, in each of the embodiments described above in connection with FIGS. 5A-5E the floating gates 509 are separated from the control gate lines, or control gates 513 with a low tunnel barrier intergate insulator in accordance with the descriptions given above in connection with FIG. 3. That is, according to the teachings of the present invention, the low tunnel barrier intergate insulator has a thickness of less than 20 Angstroms and/or a low tunnel barrier of less than 1.5 eV. The modifications here are to use tunneling through the interpoly dielectric to realize DEAPROM memory devices which require refresh. The vertical devices include an extra flexibility in that the capacitors, e.g. gate oxide and intergate insulator, are easily fabricated with different areas. This readily allows the use of very high dielectric constant inter-poly dielectric insulators with lower tunneling barriers.
[0067] FIGS. 6A-6D illustrate that a number of address coincidence schemes can be used together with the present invention. FIG. 6A illustrates a NOR DEAPROM memory array 610 having a number of DEAPROM memory cells 600-1, 600-2, 600-3, using a coincidence address array scheme. For purposes of illustration, FIG. 6A shows a sourceline 625 coupled to a first source/drain region 601 in each of the number of DEAPROM memory cells 600-1, 600-2, 600-3. The sourceline is shown oriented in a first selected direction in the DEAPROM memory array 610. In FIG. 6A, a number of control gate lines 630 are shown oriented in a second selected direction in the DEAPROM memory array 610. As shown in FIG. 6A, the number of control gate lines 630 are coupled to, or integrally formed with the control gates 613 for the number of DEAPROM memory cells 600-1, 600-2, 600-3. As shown in FIG. 6A, the second selected direction is orthogonal to the first selected direction. Finally, FIG. 6A shows a number of bitlines 635 oriented in a third selected direction in the DEAPROM memory array 610. As shown in FIG. 6A, the number of bitlines are coupled to the second source/drain regions in the number of DEAPROM memory cells 600-1, 600-2, 600-3. In the embodiment shown in FIG. 6A the third selected direction is parallel to the second selected direction and the number of control gate lines 630 serve as address lines. Also, as shown in FIG. 6A, the DEAPROM memory array 610 includes a number of backgate or substrate/well bias address lines 640 coupled to the substrate.
[0068] Using FIG. 6A as a reference point, FIGS. 6B-6D illustrate of top view for three different coincidence address scheme layouts suitable for use with the present invention. First, FIG. 6B provides the top view layout of the coincidence address scheme described in connection with FIG. 6A. That is, FIG. 6B illustrates a number of sourcelines 625 oriented in a first selected direction, a number of control gate lines 630 oriented in a second selected direction, and a number of bitlines 635 oriented in a third selected direction for the DEAPROM memory array 600. As explained above in connection with FIG. 6A, in this embodiment, the second and third selected direction are parallel to one another and orthogonal to the first selected direction such that the number of control gate lines 630 serve as address lines.
[0069] FIG. 6C provides the top view layout of another coincidence address scheme according to the teachings of the present invention. This is, FIG. 6C illustrates a number of sourcelines 625 oriented in a first selected direction, a. number of control gate lines 630 oriented in a second selected direction, and a number of bitlines 635 oriented in a third selected direction for the DEAPROM memory array 600. In the embodiment of FIG. 6C, the first selected direction and the third selected direction are parallel to one another and orthogonal to the second selected direction. In this embodiment, the number of control gate lines 630 again serve as address lines.
[0070] FIG. 6D provides the top view layout of yet another coincidence address scheme according to the teachings of the present invention. This is, FIG. 6D illustrates a number of sourcelines 625 oriented in a first selected direction, a number of control gate lines 630 oriented in a second selected direction, and a number of bitlines 635 oriented in a third selected direction for the DEAPROM memory array 600. In the embodiment of FIG. 6D, the first selected direction and the second selected direction are parallel to one another and orthogonal to the third selected direction. In this embodiment, the number of bitlines 635 serve as address lines.
[0071] As will be apparent to one of ordinary skill in the art upon reading this disclosure, and as will be described in more detail below, write can still be achieved by hot electron injection and/or, according to the teachings of the present invention, tunneling from the control gate. According to the teachings of the present invention, block erase is accomplished by driving the control gates with a relatively large positive voltage and tunneling from the metal on top of the floating gate to the metal on the bottom of the control gate.
[0072] FIG. 7A is an energy band diagram illustrating the band structure at vacuum level with the low tunnel barrier interpoly insulator according to the teachings of the present invention. FIG. 7A is useful in illustrating the reduced tunnel barrier off of the floating gate to the control gate and for illustrating the respective capacitances of the structure according to the teachings of the present invention.
[0073] FIG. 7A shows the band structure of the silicon substrate, e.g. channel region 701, silicon dioxide gate insulator, e.g. gate oxide 703, polysilicon floating gate 705, the low tunnel barrier interpoly dielectric 707, between metal plates 709 and 711, and then the polysilicon control gate 713, according to the teachings of the present invention. FIG. 7A illustrates the conventional silicon oxide gate insulator 703 between the floating gate 705 and the channel region 701 with a high barrier, e.g. 3.2 eV. FIG. 7A further illustrates the low tunnel barrier interpoly insulator 707 between the floating gate 705 and the control gate 713. According to the teachings of the present invention, if the interpoly dielectric 707 is thin enough, e.g. less than 20 Angstroms, or the barrier is low enough, e.g. less than 1.5 eV, to allow a very easy erase then there will be some finite leakage current when the device is addressed for read operations and/or is in a standby state. Thus, according to the teachings of the present invention, this will require refresh of the memory state for the DEAPROM.
[0074] The design considerations involved are determined by the dielectric constant, thickness and tunneling barrier height of the interpoly dielectric insulator 707 relative to that of the silicon dioxide gate insulator, e.g. gate oxide 703. The tunneling probability through the interpoly dielectric 707 is an exponential function of both the barrier height and the electric field across this dielectric.
[0075] FIG. 7B is an energy band diagram illustrating the band structure during an erase operation of electrons from the floating gate 705 to the control gate 713 across the low tunnel barrier interpoly insulator 707 according to the teachings of the present invention. FIG. 7B is similarly useful in illustrating the reduced tunnel barrier off of the floating gate 705 to the control gate 713 and for illustrating the respective capacitances of the structure according to the teachings of the present invention.
[0076] As shown in FIG. 7B, the electric field is determined by the total voltage difference across the structure, the ratio of the capacitances (see FIG. 7A), and the thickness of the interpoly dielectric 707. The voltage across the interpoly dielectric 707 will be, ΔV2=V C1/(C1+C2), where V is the total applied voltage. The capacitances, C, of the structures depends on the dielectric constant, ∈r, the permittivity of free space, e0, and the thickness of the insulating layers, t, and area, A, such that C=∈r∈0A/t, Farads/cm2, where ∈rrepresents the low frequency dielectric constant. The electric field across the interpoly dielectric insulator 707, having capacitance, C2, will then be E2=ΔV2/t2, where t2 is the thickness of this layer.
[0077] The tunneling current in erasing charge from the floating gate 705 by tunneling to the control gate 713 will then be as shown in FIG. 7B given by an equation of the form:
[0078] J=B exp(−Eo/E)
[0079] where E is the electric field across the interpoly dielectric insulator 707 and Eo depends on the barrier height. Aluminum oxide has a current density of 1 A/cm2at a field of about E=1V/20 A=5×10+6V/cm. Silicon oxide transistor gate insulators have a current density of 1 A/cm2at a field of about E =2.3V/23 A=1×10+7V/cm.
[0080] The lower electric field in the aluminum oxide interpoly insulator 707 for the same current density reflects the lower tunneling barrier of less than 2.0 eV, shown in FIG. 7B, as opposed to the 3.2 eV tunneling barrier of silicon oxide 703, also illustrated in FIG. 7B. Low barriers, according to the teachings of the present invention, will result in high current densities at low electric fields during write and erase, however, they will also conduct some small but significant current during the electric fields employed for read and as a consequence the data must be refreshed. Thus, the DEAPROM devices of the present invention work on a dynamic basis.
[0081] FIG. 7C is a graph plotting tunneling currents versus the applied electric fields (reciprocal applied electric field shown) for a number of barrier heights. FIG. 7C illustrates the dependence of the tunneling currents on electric field (reciprocal applied electric field) and barrier height. The fraction of voltage across the interpoly or intergate insulator, ΔV2, can be increased by making the area of the intergate capacitor, C2, (e.g. intergate insulator 707) smaller than the area of the transistor gate capacitor, C1 (e.g. gate oxide 703). This would be required with high dielectric constant intergate dielectric insulators 707 and is easily realized with the vertical floating gate structures described above in connection with FIGS. 3, and 5A-5E.
[0082] FIG. 8 is an energy band diagram illustrating work function, tunnel barrier heights and electron affinities for a low tunnel barrier intergate insulator according to the teachings of the present invention.
[0083] Table A illustrates insulators of the order of 0.6 to 1.5 eV which are appropriate for use as the low tunnel barrier intergate insulator of the present invention. The values shown are for low tunnel barrier intergate insulators selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. Also, as described above, the floating gate will include a polysilicon floating gate having a metal layer: formed thereon in contact with the low tunnel barrier intergate insulator and the control gate will include a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. In one embodiment, the metal layers are formed of platinum (Pt). In an alternative embodiment, the metal layers are formed of aluminum (Al). Thus, Table A illustrates the tunneling barrier values for the low tunnel barrier intergate insulator formed between these respective metal layers.
| TABLE A | ||||||
|---|---|---|---|---|---|---|
| E | ε | ε | χ | Φ | Φ | |
[0084] Methods of Formation
[0085] Several examples are outlined below in order to illustrate how a diversity of such metal oxide tunnel barriers can be formed, according to the teachings of the present invention. Processing details and precise pathways taken which are not expressly set forth below will be obvious to one of ordinary skill in the art upon reading this disclosure. Firstly, although not included in the details below, it is important also to take into account the following processing factors in connection with the present invention:
[0086] (i) The poly-Si layer is to be formed with emphasis on obtaining a surface that is very smooth and morphologically stable at subsequent device processing temperatures which will exceed that used to grow Metal oxide.
[0087] (ii) The native SiOXoxide on the poly-Si surface must be removed (e.g., by sputter cleaning in an inert gas plasma in situ) just prior to depositing the metal film. The electrical characteristics of the resultant Poly-Si/Metal/Metal oxide/Metal/Poly-Si structure will be better defined and reproducible than that of a Poly-Si/Native SiOX/Metal/Metal oxide/Poly-Si structure.
[0088] (iii) The oxide growth rate and limiting thickness will increase with oxidation temperature and oxygen pressure. The oxidation kinetics of a metal may, in some cases, depend on the crystallographic orientations of the very small grains of metal which comprise the metal film. If such effects are significant, the metal deposition process can be modified in order to increase its preferred orientation and subsequent oxide thickness and tunneling uniformity. To this end, use can be made of the fact that metal films strongly prefer to grow during their depositions having their lowest free energy planes parallel to the film surface. This preference varies with the crystal structure of the metal. For example, fcc metals prefer to form {111} surface plans. Metal orientation effects, if present, would be larger when only a limited fraction of the metal will be oxidized and unimportant when all or most of the metal is oxidized.
[0089] (iv) Modifications in the structure shown in FIG. 2 may be introduced in order to compensate for certain properties in some metal/oxide/metal layers. Such changes are reasonable since a wide range of metals, alloys and oxides with quite different physical and chemical properties can be used to form these tunnel junctions.
[0090] Example I. Formation of Al2O3or NiO Tunnel Barriers
[0091] As stated above, the conventional large barrier insulating dielectrics are silicon oxide and silicon nitride. The realities are that silicon oxide is not an optimum choice for memory type devices, because the 3.2 eV tunnel barrier is too high resulting in premature failure of the insulators and limiting the number of operational cycles to be in the order of 105to 107.
[0092] According to one embodiment of the present invention, a low tunneling barrier interpoly insulator is used instead, such as Al2O3or NiO having a thickness of less than 20 Angstroms so that the tunneling barrier is less than 1.5 eV. A number of studies have dealt with electron tunneling in Al/Al2O3/Al structures where the oxide was grown by “low temperature oxidation ” in either molecular or plasma oxygen. Before sketching out a processing sequence for these tunnel barriers, note:
[0093] (i) Capacitance and tunnel measurements indicate that the Al2O3thickness increases with the log (oxidation time), similar to that found for PbO/Pb as well as a great many other oxide/metal systems.
[0094] (ii) Tunnel currents are asymmetrical in this system with somewhat larger currents flowing when electrons are injected from the Al/Al2O3interface developed during oxide growth. This asymmetry is due to a minor change in composition of the growing oxide: there is a small concentration of excess metal in the Al2O3, the concentration of which diminishes as the oxide is grown thicker. The excess Al+3ions produce a space charge that lowers the tunnel barrier at the inner interface. The oxide composition at the outer Al2O3/Al contact is much more stoichiometric and thus has a higher tunnel barrier. In situ ellipsometer measurements on the thermal oxidation of Al films deposited and oxidized in situ support this model. In spite of this minor complication, Al/Al2O3/Al tunnel barriers can be formed that will produce predictable and highly controllable tunnel currents that can be ejected from either electrode. The magnitude of the currents are still primarily dominated by Al2O3thickness which can be controlled via the oxidation parametrics.
[0095] With this background, we can proceed to outline one process path out of several that can be used to form Al2O3tunnel barriers. Here the aluminum is thermally oxidized although one could use other techniques such as plasma oxidation or rf sputtering in an oxygen plasma. For the sake of brevity, some details noted above will not be repeated.
[0096] (i) Sputter deposit aluminum on poly-Si at a temperature of ˜25 to 150 degrees C. Due to thermodynamic forces, the micro-crystallites of the f.c.c. aluminum will have a strong and desirable (111) preferred orientation.
[0097] (ii) Oxidize the aluminum in situ in molecular oxygen using temperatures, pressure and time to obtain the desired Al2O3thickness. The thickness increases with log (time) and can be controlled via time at a fixed oxygen pressure and temperature to within 0.10 Angstroms, when averaged over a large number of aluminum grains that are present under the counter-electrode. One can readily change the Al2O3thickness from ˜15 to 35 Å by using appropriate oxidation parametrics. The oxide will be amorphous and remain so until temperatures in excess of 400 degrees C are reached. The initiation of recrystallization and grain growth can be suppressed, if desired, via the addition of small amounts of glass forming elements (e.g., Si) without altering the growth kinetics or barrier heights significantly.
[0098] (iii) Re-evacuate the system and deposit a second layer of aluminum.
[0099] (iv) Deposit the Poly-Si control gate layer using conventional processes.
[0100] In an alternative embodiment, nickel (Ni) can be oxidized to form thin super-conducting tunnel diodes or tunneling magnetoresistive elements.
[0101] As mentioned above, these oxide insulators are used as low tunnel barriers, of the order 0.6 to 1.5 eV, as the inter-poly or inter-gate dielectric insulators. The characteristics of these oxide insulators are also summarized in FIG. 10. According to the teachings of the present invention, low barriers are utilized in dynamic memory elements which are easy to write and/or erase but as a consequence of the low barrier require refresh. To achieve the correct barrier height different contact metals as for instance aluminum (Al) and platinum (Pt) may be used as illustrated in FIGS. 2 and 3. That is according to the teachings of the present invention the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. Likewise, as described above the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. In one embodiment, the metal layers are formed of platinum (Pt). In an alternative embodiment, the metal layers are formed of aluminum (Al). FIG. 9 illustrates the tunneling barrier values for the Al2O3and NiO intergate insulator embodiments formed between these respective metal layers. In conjunction with these embodiments of the invention, the low tunnel barrier interpoly insulator is formed with a thickness of less than 20 Angstroms such that the tunnel barrier is less than 1.5 eV.
[0102] Example II. Formation of Single- and Multi-Layer Transition Metal Oxide Tunnel Barriers.
[0103] The band gap energies and barrier heights of some conventional gate insulators as silicon oxide, silicon nitride and aluminum oxide as well as tantalum oxide have been investigated and described in detail. Formation of single and double-layer dielectric layers of oxides of Ta2O5and similar transition metal oxides can be accomplished by thermal as well as plasma oxidation of films of these metals.
[0104] In some cases the characteristics of the resulting dielectric insulators are not yet well known or well defined. Part of this detail is recounted as follows.
[0105] For example, single layers of Ta2O5, TiO2, ZrO2, Nb2O5and similar transition metal oxides can be formed by “low temperature oxidation” of numerous Transition Metal (e.g., TM oxides) films in molecular and plasma oxygen and also by rf sputtering in an oxygen plasma. The thermal oxidation kinetics of these metals have been studied for decades. In essence, such metals oxidize via logarithmic kinetics to reach thicknesses of a few to several tens of angstroms in the range of 100 to 300 C. Excellent oxide barriers for Josephson tunnel devices can be formed by rf sputter etching these metals in an oxygen plasma. Such “low temperature oxidation” approaches differ considerably from MOCVD processes used to produce these TM oxides. MOCVD films require high temperature oxidation treatments to remove carbon impurities, improve oxide stoichiometry and produce recrystallization. Such high temperature treatments also cause unwanted interactions between the oxide and the underlying silicon and thus have necessitated the introduction of interfacial barrier layers.
[0106] An approach was developed utilizing “low temperature oxidation” to form duplex layers of TM oxides. Unlike MOCVD films, the oxides are very pure and stoichiometric as formed. They do require at least a brief high temperature (est. 700 to 800 degrees C. but may be lower) treatment to transform their microstructures from amorphous to crystalline and thus increase their dielectric constants to the desired values (>20 or so). Unlike MOCVD oxides, this treatment can be carried out in an inert gas atmosphere, thus lessening the possibility of inadvertently oxidizing the poly-Si floating gate. While this approach was directed at developing methods and procedures for producing high dielectric constant films for storage cells for DRAMs, the same teachings can be applied to producing thinner metal oxide tunnel films for DEAPROM memory devices described. The dielectric constants of these TM oxides are substantially greater (>25 to 30 or more) than those of PbO and Al2O3. Duplex layers of these high dielectric constant oxide films are easily fabricated with simple tools and also provide improvement in device yields and reliability. Each oxide layer will contain some level of defects but the probability that such defects will overlap is exceedingly small. Effects of such duplex layers were first reported by one of the present authors, J. M. Eldridge, and are well known to practitioners of the art. It is worth mentioning that highly reproducible TM oxide tunnel barriers can be grown by rf sputtering in an oxygen ambient. Control over oxide thickness and other properties in these studies were all the more remarkable in view of the fact that the oxides were typically grown on thick (e.g., 5,000 Å) metals such as Nb and Ta. In such metal-oxide systems, a range of layers and suboxides can also form, each having their own properties. In the present disclosure, control over the properties of the various TM oxides will be even better since we employ very limited thicknesses of metal (perhaps 10 to 100 Å or so) and thereby preclude the formation of significant quantities of unwanted, less controllable sub-oxide films. Thermodynamic forces will drive the oxide compositions to their most stable, fully oxidized state, e.g., Nb2O5, Ta2O5, etc. As noted above, it will still be necessary to crystallize these duplex oxide layers. Such treatments can be done by RTP and will be shorter than those used on MOCVD and sputter-deposited oxides since the stoichiometry and purity of the “low temperature oxides” need not be adjusted at high temperature.
[0107] Although perhaps obvious to those skilled in the art, one can sketch out a few useful fabrication guides:
[0108] (i) Thinner TM layers will be used in this invention relative to those used to form DRAMs. Unlike DRAMs where leakage must be eliminated, the duplex oxides used here must be thin enough to carry very controlled levels of current flow when subjected to reasonable applied fields and times.
[0109] (ii) The TM and their oxides are highly refractory and etchable (e.g., by RIE). Hence they are quite compatible with poly-Si control gate processes and other subsequent steps.
[0110] (iii) TM silicide formation will not occur during the oxidation step. It could take place at a significant rate at the temperatures used to deposit the poly-Si control gate. If so, several solutions can be applied including:
[0111] (i) Insert certain metals at the TM/poly-Si boundaries that will prevent inter-diffusion of the TM and the poly-Si.
[0112] (ii) Completely oxide the TMs. The electrical characteristics of the resulting poly-Si/TM oxide 1/TM oxide 2/poly-Si structure will be different in the absence of having TM at the oxide/metal interfaces.
[0113] Insulator and contact metal layer combinations, e.g. platinum (Pt) and aluminum (Al) with appropriate barrier heights, according to the teachings of the present invention, have been circled in FIG. 9. Also, as described above, the transition metal oxide interpoly insulators can be formed having a thickness of less than 20 Angstroms such that the tunnel barrier is less than 1.5 eV as required by the present invention.
[0114] Example III. Formation of Alternate Metal Compound Tunnel Barriers.
[0115] Although no applications may be immediately obvious, it is conceivable that one might want to form a stack of oxide films having quite different properties, for example, a stack comprised of a high dielectric constant (k) oxide/a low k oxide/a high k oxide. “Low temperature oxidation” can be used to form numerous variations of such structures. While most of this disclosure deals with the formation and use of stacks of oxide dielectrics, it is also possible to use “low temperature oxidation” to form other thin film dielectrics such as nitrides, oxynitrides, etc. that could provide additional functions such as being altered by monochromatic light, etc. These will not be discussed further here.
[0116] Example IV. Formation of Perovskite Oxide Tunnel Barriers.
[0117] Oxide tunnel barriers having a wide range of properties can also be grown via oxidation of alloy films of appropriate compositions. Thin film barriers of platinum, palladium and similar noble metals must be added to prevent inter-diffusion and degradation of the perovskite oxides with the poly-Si layers. Some processing remarks are stated below.
[0118] For example, results have been obtained which demonstrate that at least a limited range of high temperature, super-conducting oxide films can be made by thermally oxidizing Y-Ba-Cu alloy films. “Low temperature oxidation” and short thermal treatments in an inert ambient at 700 C. in order to form a range of perovskite oxide films from parent alloy films have also been employed. The dielectric constants of crystallized, perovskite oxides can be very large, with values in the 100 to 1000 or more range. The basic process is more complicated than that needed to oxidize layered films of transition metals. (See Example II.) The TM layers would typically be pure metals although they could be alloyed. The TMs are similar metallurgically as are their oxides. In contrast, the parent alloy films that can be converted to a perovskite oxide are typically comprised of metals having widely different chemical reactivities with oxygen and other common gasses. In the Y-Ba-Cu system referenced above, Y and Ba are among the most reactive of metals while the reactivity of Cu approaches (albeit distantly) those of other noble metals. If the alloy is to be completely oxidized, then thin film barriers such as Pd, Pt, etc. or their conductive oxides must be added between the Si and the parent metal film to serve as: electrical contact layers; diffusion barriers; and, oxidation stops. In such a case, the Schottky barrier heights of various TM oxides and perovskite oxides in contact with various metals will help in the design of the tunnel device. In the more likely event that the perovskite parent alloy film will be only partially converted to oxide and then covered with a second layer of the parent alloy (recall the structure of FIG. 2), then the barrier heights will represent that developed during oxide growth at the parent perovskite alloy/perovskite oxide interface. Obviously, such barrier heights cannot be predicted ab initio for such a wide class of materials but will have to be developed as the need arises. This information will have to be developed on a system-by-system basis.
[0119] System Level
[0120] FIG. 9 illustrates a block diagram of an embodiment of an electronic system 901 according to the teachings of the present invention. In the embodiment shown in FIG. 9, the system 901 includes a memory device 900 which has an array of memory cells 902, address decoder 904, row access circuitry 906, column access circuitry 908, control circuitry 910, and input/output circuit 912. Also, as shown in FIG. 10, the circuit 901 includes a processor 914, or memory controller for memory accessing. The memory device 900 receives control signals from the processor 914, such as WE*, RAS* and CAS* signals over wiring or metallization lines. The memory device 900 is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device 900 has been simplified to help focus on the invention. At least one of the memory cells 902 has a memory cell formed according to the embodiments of the present invention. That is, at least one memory cell includes a low tunnel barrier interpoly insulator according to the teachings of the present invention.
[0121] It will be understood that the embodiment shown in FIG. 9 illustrates an embodiment for electronic system circuitry in which the novel memory cells of the present invention are used. The illustration of system 901, as shown in FIG. 9, is intended to provide a general understanding of one application for the structure and circuitry of the present invention, and is not intended to serve as a complete description of all the elements and features of an electronic system using the novel memory cell structures. Further, the invention is equally applicable to any size and type of memory device 901 using the novel memory cells of the present invention and is not intended to be limited to that described above. As one of ordinary skill in the art will understand, such an electronic system can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device.
[0122] Applications containing the novel memory cell of the present invention as described in this disclosure include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
[0123] Method of Operation
[0124] Write can be achieved by tunneling from the control gate by driving the control gate negative and/or channel hot electron injection as in flash memory devices. Erase would be accomplished by driving the control gates with a relatively large positive voltage and tunneling from the metal on top of the floating gate to the metal on the bottom of the control gate. Read is accomplished by driving the control gate with a smaller positive voltage, if no electrons are stored on the floating gate the transistor will turn on. If electrons are stored on the floating gate the transistor will not turn on or only turn on at a lower conductivity state, this constitutes the memory function.
[0125] During a read operation the control gate is driven with the same positive polarity voltage that is used for erase. A low tunnel barrier between the floating gate and the control gate will make the erase operation easy but will also result in some finite leakage current at the lower positive control gate voltage during read. If as in DRAMs a retention time of one second is required then the leakage current at the read voltage must be small. If the gate oxide is 2 nm (20 Å) thick then the capacitance is about 1.6×10−6F/cm2and a 1 Volt difference will store a charge of 1.6×10−6Coulombs/cm2. A retention time of one second requires a leakage current of less than about 10−6Amps/cm2; as shown in FIG. 7C if the tunneling barrier is 1.25 eV and the electric field in the low barrier interpoly/intergate insulator is less than about 1.5×106V/cm then this will be achieved. On the other hand, if during erase the electric field in the interpoly/intergate insulator is over 2.5×106V/cm then the erase current will be over 1 Amp/cm2and erase will be easily achieved in less than a microsecond. The lower tunneling barrier, 1.25 eV, results in a much faster erase at much lower electric fields and than in conventional flash memory devices which require fields of 107V/cm to achieve the same erase current of 1 Amp/cm2with a silicon oxide tunnel barrier of 3.2 eV.
[0126] The high electric fields in conventional flash memory devices result in premature insulator failures and reliability failures since these electric fields are very close to the dielectric strength of the silicon oxide gate insulators. Here the tunnel barriers are very low in the order of 0.6 to 1.5 eV, while this makes the erase very easy on the other hand the finite leakage currents require that these memory devices be refreshed, in other words they emulate DRAMs.
Conclusions
[0127] Low barrier tunnel insulators are described between the floating gate and control gate in a flash memory type devices to form DEAPROM cells which require refresh. These low barrier insulators, 1.5−0.6 eV, are easily fabricated by the oxidation of a transition metal or a composite metal layer. The devices work on a dynamic basis and must be refreshed, in this respect they emulate DRAM's. While the amount of charge stored on the floating gate is small the transistor provides gain and charge multiplication resulting in a large output signal and ease of reading the stored data. If there is an adverse capacitance ratio due to a large difference of dielectric constants then the vertical gate structures described previously can be employed.
[0128] Write can be achieved by the normal channel hot electron injection and gate current through the silicon oxide to the floating gate. This is done by selecting a particular column by applying a high control gate voltage and applying relatively large drain voltage as is done with conventional ETOX memory devices. However, according to the teachings of the present invention, write can also be accomplished by applying a positive voltage to the substrate or well select line and a large negative voltage to the control gates, electrons will tunnel from the control gate to the floating gate. The low tunnel barrier will provide an easy write operation and the selection of the substrate or well bias will provide selectivity and address only one device.
[0129] According to the teachings of the present invention, erase is achieved by providing a negative voltage to the substrate or well address line and a large positive voltage to the control gate. This causes electrons to tunnel off of the floating gate on to the control gate. A whole row can be erased by addressing all the column lines along that row and a block can be erased by addressing multiple row back gate or substrate/well address lines.
[0130] Read is accomplished as in conventional ETOX memory devices. A column line is addressed by applying a positive control gate voltage and sensing the current along the data bit or drain row address line.
[0131] The above structures and fabrication methods have been described, by way of example, and not by way of limitation, with respect to DEAPROM memory with low tunnel barrier interpoly insulators.
[0132] It has been shown that the low tunnel barrier interpoly insulators of the present invention avoid the large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, which result in slow write and erase speeds even at very high electric fields. The present invention also avoids the combination of very high electric fields and damage by hot electron collisions in the which oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase. Further, the low tunnel barrier interploy dielectric insulator erase approach, of the present invention remedies the above mentioned problems of having a rough top surface on the polysilicon floating gate which results in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems.
Documents
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Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A DEAPROM memory array, comprising:
a number of DEAPROM memory cells, wherein each DEAPROM memory cell includes:
a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region and a second source/drain region separated by a channel region;
a floating gate opposing the channel region in the number of pillars and separated therefrom by a gate oxide.
a control gate opposing the floating gate; and
wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms;
a number of sourcelines coupled to the first source/drain regions along a first selected direction in the DEAPROM memory array;
a number of control gate lines coupled to the control gates along a second selected direction in the DEAPROM memory array;
a number of bitlines coupled to the second source/drain regions along a third selected direction in the DEAPROM memory array; and
wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.
2. The DEAPROM memory array of claim 1, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
3. The DEAPROM memory array of claim 1, wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
4. The DEAPROM memory array of claim 1, wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
5. The DEAPROM memory array of claim 1, wherein the second selected direction and the third selected direction are parallel to one another and orthogonal to the first selected direction, and wherein the number of control gate lines serve as address lines.
6. The DEAPROM memory array of claim 1, wherein the first selected direction and the third selected direction are parallel to one another and orthogonal to the second selected direction, and wherein the number of control gate lines serve as address lines.
7. The DEAPROM memory array of claim 1, wherein the first selected direction and the second selected direction are parallel to one another and orthogonal to the third selected direction, and wherein the number of bitlines serve as address lines.
8. An array of DEAPROM memory cells, comprising:
a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
a number of control gates opposing the floating gates;
a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates arc separated from the floating gates by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator has a tunnel barrier of less than 1.5 eV;
a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells ; and
wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.
9. The array of DEAPROM memory cells of claim 8, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
10. The array of DEAPROM memory cells of claim 8, wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
11. The array of DEAPROM memory cells of claim 8, wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
12. The array of DEAPROM memory calls of claim 8, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.
13. The array of DEAPROM memory cells of claim 8, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.
14. The array of DEAPROM memory cells of claim 8, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.
15. The array of DEAPROM memory cells of claim 8, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control gate lines.
16. The array of DEAPROM memory cells of claim 8, wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.
17. The array of DEAPROM memory cells of claim 16, wherein the plurality of control gate lines are disposed vertically above the floating gates.
18. An electronic system, comprising:
a processor; and
a memory device coupled to the processor, wherein the memory device includes an array of DEAPROM memory cells, comprising:
a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
a number of control gates opposing the floating gates;
a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells,
a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates fire separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms;
a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells; and
wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.
19. The electronic system of claim 18, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
20. The electronic system of claim 18, wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the low tunnel barrier includes a tunnel barrier of less than 1.5 eV.
21. The electronic system of claim 18, wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
22. The electronic system of claim 18, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.
23. The electronic system of claim 18, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.
24. The electronic system of claim 18, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.
25. The electronic system of claim 18, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.
26. The electronic system of claim 18, wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.
27. The electronic system of claim 26, wherein the plurality of control gate lines are disposed vertically above the floating gates.
28. A method for forming an array of DEAPROM memory cells, comprising:
forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
forming a number of control gates opposing the floating gates;
forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates lines are separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms;
forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells; and
wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.
29. The method of claim 28, wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
30. The method of claim 28, wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier inter gate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
31. The method of claim 28, wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein forming the low tunnel barrier intergate insulator includes forming a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV.
32. The method of claim 28, wherein forming the plurality of control gate lines includes forming each control gate line in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.
33. The method of claim 28, wherein forming the plurality of control gate lines includes forming a pair of control gate lines in each trench below the top surface of the pillar and between the pair of floating gales such that each control gate line addresses a floating gate on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.
34. The method of claim 28, wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates such that each pair of floating gates shares a single control gate line.
35. The method of claim 28, wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates, and forming the plurality of control lines such that each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.
36. The method of claim 28, wherein forming each floating gate includes forming a horizontally oriented floating gate in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposite sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.
37. The method of claim 36, wherein the forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates.
38. A memory array, comprising:
a number of memory cells, wherein each memory cell includes:
a first source/drain region and a second source/drain region separated by a channel region;
a floating gate opposing the channel region and separated therefrom by a gate oxide;
a control gate opposing the floating gate; and
wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms;
a number of sourcelines coupled to the first source/drain regions along a first selected direction in the memory array,
a number of control gate lines coupled to the control gates along a second selected direction in the memory array;
a number of bitlines coupled to the second source/drain regions along a third selected direction in the memory array; and
wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.
39. The memory array of claim 38, wherein the memory cells include electronically alterable programmable read-only memory.
40. An array of memory cells, comprising:
a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
a number of control gates opposing the floating gates;
a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator has a tunnel barrier of less than 1.5 eV;
a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and
wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.
41. The array of memory cells of claim 40, wherein the memory cells include electronically alterable programmable read-only memory.
42. A method for forming an array of memory cells, comprising:
forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
forming a number of control gates opposing the floating gates;
forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates lines arc separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms;
forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and
wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.
43. The array of memory cells of claim 42, wherein the memory cells include electronically alterable programmable read-only memory.
44. An electronic system, comprising:
a processor; and
a memory device coupled to the processor, wherein the memory device includes an array of memory cells, comprising:
a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
a number of control gates opposing the floating gates;
a number of buried source/lines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms;
a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of memory cells; and
wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.
45. The memory array of claim 38, wherein the low tunnel hairier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
46. The memory array of claim 38, wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
47. The memory array of claim 38, wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
48. The memory array of claim 38, wherein the second selected direction and the third selected direction are parallel to one another and orthogonal to the first selected direction, and wherein the number of control gate lines serve as address lines.
49. The memory ray of claim 38, wherein the first selected direction and the third selected direction are parallel to one another and orthogonal to the second selected direction, and wherein the number of control gate lines serve as address lines.
50. The memory ray of claim 38, wherein the first selected direction and the second selected direction are parallel to one another and orthogonal to the third selected direction, and wherein the number of bitlines serve as address lines.
51. The array of memory cells of claim 40, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
52. The array of memory cells of claim 40, wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
53. The array of memory cells of claim 40, wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
54. The array of memory cells of claim 40, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.
55. The array of memory cells of claim 40, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each french houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.
56. The array of memory cells of claim 40, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.
57. The array of memory cells of claim 40, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control gate lines.
58. The array of memory cells of claim 40, wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.
59. The may of memory cells of claim 58, wherein the plurality of control gate lines are disposed vertically above the floating gates.
60. The electronic system of claim 44, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
61. The electronic system of claim 44, wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the low tunnel harrier includes a tunnel barrier of less than 1.5 eV.
62. The electronic system of claim 44, wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
63. The electronic system of claim 44, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gales, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.
64. The electronic system of claim 44, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one On opposing sides of the french respectively, and wherein the pair of control gate lines are separated by an insulator layer.
65. The electronic system of claim 44, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.
66. The electronic system of claim 38, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.
67. The electronic system of claim 38, wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.
68. The electronic system of claim 67, wherein the plurality of control gate lines arc disposed vertically above the floating gates.
69. The method of claim 42, wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
70. The method of claim 42, wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).
71. The method of claim 42, wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein forming the low tunnel barrier intergate insulator includes forming a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV.
72. The method of claim 42, wherein forming the plurality of control gate lines includes forming each control gate line in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.
73. The method of claim 42, wherein forming the plurality of control gate lines includes forming a pair of control gate lines in each trench below the top surface of the pillar and between the pair of floating gates such that each control gate line addresses a floating gate on opposing sides of the trench respectively and wherein the pair of control gate lines are separated by an insulator layer.
74. The method of claim 42, wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates such that each pair of floating gates shares a single control gate line.
75. The method of claim 42, wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines arc disposed vertically above the floating gates, and forming the plurality of control lines such that each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.
76. The method of claim 42, wherein forming each floating gate includes forming a horizontally oriented floating gate in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposite sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.
77. The method of claim 42, wherein the forming the plurality of control gale lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates.
78. A method for forming an array of memory cells, comprising:
forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
forming a number of control gates opposing the floating gates;
forming a number of busied sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
forming a number of control gate lines formed integrally with the member of control gates along a second selected direction in the array of memory cells;
separating the number of control gates lines from the floating gates by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV;
forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and
wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.
79. The array of memory cells of claim 77, wherein the memory cells include electronically alterable programmable read-only memory.
80. A method for forming an electronic system, comprising:
providing a memory device including an array of memory cells formed by:
forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
forming a number of control gates opposing the floating gates;
forming a number of buried sourcelines disposed below the number of pillars arid coupled to the first source/drain regions along a first selected direction in the array of memory cells;
forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells
separating the number of control gates lines from the floating gatos by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms;
forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and
wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench; and
connecting the memory device to a processor.
81. The method of claim 80, wherein separating the number of control gates lines from the floating gates by a low tunnel barrier intergate insulator includes separating the number of control gates lines from the floating gates by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV.
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