US 6,049,496 AGrant
Circuit and Method for Low Voltage, Current Sense Amplifier
Issue Date:2000-04-11
•17 Claims
•14 Drawing Sheets
Abstract
An improved circuit and method for a low voltage, current sense amplifier is provided. Embodiments of the present invention capitalize on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of the transistors are biased to modify the threshold voltage of the transistor (V.sub.t). The conductive sidewall member configuration conserves surface space and achieves a higher density of surface structures per chip. The structures offer performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.
Metadata
Assignee
- Micron Technology, Inc.
Inventors
- Leonard Forbes
- Wendell P. Noble
Application Information
Application Number:US 0504432
Filing Date:1998-03-30
Priority Date:1998-03-30
Art Unit:288
Classifications
IPC:
G11C 700
Field of Search:
365257205;207;208369;370;378
Patent Drawings (14 sheets)
Description
Related Applications
This application is related to the following co-filed and commonly assigned applications, attorney docket no. 303.413US1, entitled "Circuit and Method for Low Voltage, Voltage Sense Amplifier," attorney docket no. 303.471US1, entitled "Circuit and Method for Gate-Body Structures in CMOS Technology," and attorney document no. 303.403US1 entitled "Structure and Method for Gated Lateral Bipolar Transistors" which are hereby incorporated by reference.
Field of the Invention
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to circuits, methods and structure for gated lateral bipolar transistors.
Background of the Invention
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits require the use of an ever increasing number of linked transistors. As the number of transistors required increases, the surface space on silicon chip/die dwindles. It is one objective then, to construct transistors which occupy less surface area on the silicon chip/die.
Metal-oxide semiconductor field effect transistors (MOS transistors) are prevalent in integrated circuit technology because they generally demand less power than their counterpart, bipolar transistors. Bipolar transistors, on the other hand, also possess certain advantages over MOS transistors, such as speed. Therefore, it is another objective and attempts have been made to combine the technological designs of bipolars and MOS transistors in an effort to maximize the benefits of both transistor types.
Various types of lateral transistors have been historically described and utilized in complementary metal-oxide semiconductor (CMOS) technology. Lateral bipolar transistors have received renewed interest with the advent of bipolar complementary metal-oxide semiconductor (BiCMOS) technologies. Recently the action of newer devices has been described in new terms and a more careful distinction made between the different types of transistor action possible. Both gate-body connected MOS transistors and gated lateral bipolar transistors have been described. The term gate-body connected transistors is used to describe vertical or other device structures where the body of the MOS transistor also serves as the base of a bipolar transistor but each device functions separately as a normal transistor and MOS transistor action is dominant. Applying the gate voltage to the body serves primarily to change the threshold voltage of the MOS transistor.
Other structures are possible where the gate and base are common and the bipolar transistor and MOS transistor are in parallel but the bipolar transistor current is dominant. In a gated lateral transistor, not only the structures but also the operation is merged and most current flows along a surface under the gate in either MOS or bipolar operation. In the case of a gated lateral bipolar transistor, at low gate voltages around threshold (V.sub.t), they can act as gate-body connected MOS transistors. At higher input voltages, V.sub.t or more, the bipolar action can dominate and they are more appropriately described as gated lateral bipolar transistors.
Much effort has been placed into the study of these merged transistor structures. Both vertical and lateral structures have been studied. These studies do not look to solutions for conserving precious die space in the fabrication of integrated circuits. Likewise, previous efforts have not been able to maximize low power operation and simultaneously maximize switching speeds. It is desirable then to invent new transistor structures and then to apply those improved structures in circuits and methods which can accommodate the faster switching speed and low power consumption. Any improved circuit configuration should desirably remain fully integrateable with prevalent integrated circuit design.
Summary of the Invention
The above mentioned problems with integrated circuit technology and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A circuit and method are described which accord these benefits.
In particular, an illustrative embodiment of the present invention includes a current sense amplifier. The current sense amplifier includes a pair of cross coupled inverters where each inverter is formed from a complementary pair of gated lateral bipolar transistors. The complementary pair includes both a first channel type transistor and a second channel type transistor. The gated lateral bipolar transistor includes a first layer of semiconductor material extending outwardly from a substrate. The first layer of semiconductor material has opposing sidewall surfaces and an upper surface. The gated lateral bipolar transistor has a second layer of semiconductor material formed on and extending outwardly from the upper surface of the first layer of semiconductor material. The second layer of semiconductor material similarly has opposing sidewall surfaces and an upper surface. The gated lateral bipolar transistor includes a emitter/source region and a collector/drain region formed on portions of the upper surface of the second layer. The gated lateral bipolar transistor includes a dielectric layer formed on a portion of the upper surface of the second layer of semiconductor material and on portions of the opposing sidewall surfaces of the first and second layers of semiconductor material. There is a gate formed on the dielectric layer. Conductive sidewall members are disposed adjacent to portions of the dielectric layer which are formed on the opposing sidewall surfaces of the first and second layers of semiconductor material. The conductive sidewall members couple to the gate, and to portions of the first layer of semiconductor material such that the transistors give metal-oxide semiconductor (MOS) type conduction and bipolar junction transistor (BJT) type conduction underneath the gate.
The current sense amplifier also includes a pair of bit lines coupled to the inputs of the first channel type transistor in each inverter. Further the current sense amplifier includes a pair of input/output lines where each one of the pair of input/output lines couples to an output of one of the cross-coupled inverters and to the gates of the other inverter.
In another embodiment, a current sense amplifier circuit is provided. The current sense amplifier circuit includes a pair of cross coupled inverters, wherein each inverter comprises a complementary pair of gated lateral bipolar transistors. The complementary pair comprises a first channel type transistor and a second channel type transistor. Each gated lateral bipolar transistor has a body region formed of single crystalline semiconductor material which extends outwardly from a substrate. The body region has an upper surface and opposing sidewalls. The body region additionally has a highly doped, retrograded bottom layer. A emitter/source region and a collector/drain region is formed within a portion of the upper surface of the body region. A gate is formed above the upper surface of the body region. Conductive sidewall members are disposed adjacent to the opposing sidewalls of the body region. A pair of bit lines couple to the inputs of the first channel type transistors in each inverter. A pair of input/output lines each individually couple to an output of one of the cross-coupled inverters and to the gates of the other inverter.
In another embodiment, a method of fabricating a current sense amplifier is provided. The method includes forming a pair of cross coupled inverters where each inverter comprises a pair of gated lateral bipolar transistors. Forming the gated lateral bipolar transistors includes forming a first layer of semiconductor material which extends outwardly from a substrate. The first layer of semiconductor material is formed to have opposing sidewall surfaces and an upper surface. The method further includes forming a second layer of semiconductor material on and extending outwardly from the upper surface of the first layer of semiconductor material. The second layer of semiconductor material is also formed having opposing sidewall surfaces and an upper surface. A emitter/source region and a collector/drain region are formed on a portion of the upper surface of the second layer. The method includes forming a dielectric layer on a portion of the upper surface of the second layer of semiconductor material and on portions of the opposing sidewall surfaces of the first and second layer of semiconductor material. A gate is formed on the dielectric layer. The method additionally includes forming conductive sidewall members disposed adjacent to portions of the dielectric layer and formed on the opposing sidewall surfaces of the first and second layer of semiconductor materials. The conductive sidewall members are formed to couple to the gate and to portions of the first layer of semiconductor material such that the transistors give metal-oxide semiconductor (MOS) type conduction and bipolar junction transistor (BJT) type conduction underneath the gate. A pair of bit lines are formed to couple to the inputs of the first channel type transistors in each inverter. A pair of input/output lines are forming such that each one individually couples to an output of one of the cross-coupled inverters and to the gates of the other inverter.
In another embodiment, an information handling system is provided. The information handling system includes a central processing unit, a random access memory, and a system bus for communicatively coupling the central processing unit and the random access memory. The information handling system further includes a current sense amplifier. The current sense amplifier includes the embodiment presented above.
Thus, an improved circuit and method are provided. The circuit includes transistors which combine BJT and MOS transistor conduction. This new circuit allows for low voltage level operation and enhanced switching action over conventional bipolar complementary metal-oxide semiconductor (BiCMOS) devices. The improved circuit employs gated lateral bipolar connected transistors in a format which is fully compatible with CMOS technology. Thus, the circuit does not require additional chip surface space, nor additional processing steps.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
Brief Description of the Drawings
FIG. 1A is a perspective view illustrating a current sense amplifier according to the teachings of the present invention.
FIG. 1B is a top view of the current sense amplifier shown in FIG. 1A.
FIG. 1C is a schematic diagram illustrating an embodiment of the current sense amplifier of FIG. 1A.
FIGS. 2A-2J illustrate an embodiment of a process of fabrication of a current sense amplifier.
FIG. 3 is a block diagram illustrating an information handling system according to an embodiment of the present invention.
Detailed Description
In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.
The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
The term "horizontal" as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as "on", "side" (as in "sidewall"), "higher", "lower", "over" and "under" are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.
Throughout this specification the designation "n+" refers to semiconductor material that is heavily doped n-type semiconductor material, e.g., monocrystalline silicon or polycrystalline silicon. Similarly, the designation "p+" refers to semiconductor material that is heavily doped p-type semiconductor material. The designations "n-" and "p-" refer to lightly doped n and p-type semiconductor materials, respectively.
FIG. 1A is a perspective view illustrating generally an embodiment of a portion of a current sense amplifier according to the teachings of the present invention. Specifically, current sense amplifier 50 is a six transistor device. Four of of the six transistors are formed using, for example, the technique described below with respect to FIGS. 2A through 2J. It is these four transistors which are the focus of the present invention. Each of these four transistors in current sense amplifier 50 is either an n-channel metal-oxide semiconductor (NMOS) or a p-channel metal-oxide semiconductor (PMOS) transistor. Two of the four transistors arc NMOS transistors, Q.sub.2 and Q.sub.4 respectively. The other two arm PMOS transistors, Q.sub.1 and Q.sub.3 respectively. Each NMOS and PMOS transistor includes a body region, 110 and 105 respectively, formed of single crystalline semiconductor material that extends outwardly from a substrate 100. The body regions 110 and 105 have an upper surface 112 and opposing sidewalls 111. In one embodiment, the NMOS body region 110 is formed from a p- silicon material and the PMOS body region 105 is formed from n- silicon material.
The substrate 100 is p- silicon material. In an exemplary embodiment, the NMOS and PMOS body regions, 110 and 105 respectively, are formed on an insulator layer 180 formed on the substrate 100. Both of the NMOS and PMOS transistors include emitter/source regions, 106 and 108 respectively, formed within the upper surface 112 of the body regions, 110 and 105 respectively. Likewise, each of the NMOS and PMOS transistors include a collector/drain region, 107 and 109 respectively, formed within the upper surface 112 of the body regions, 110 and 105 respectively.
A dielectric layer 120 is formed on the upper surface 112 and on portions of the opposing sidewalls 111 for both the NMOS and PMOS transistors. The NMOS transistors, Q.sub.2 and Q.sub.4, include a gate 130 on the dielectric layer 120. The PMOS transistors, Q.sub.1 and Q.sub.3, include a gate 131 formed on the dielectric layer 120. In one embodiment, gate 131 is formed of p+ silicon material and gate 130 is formed of n+ silicon material.
The NMOS transistors, Q.sub.2 and Q.sub.4, include conductive sidewall members 140. The PMOS transistors, Q.sub.1 and Q.sub.3, similarly include conductive sidewall members 145. In one embodiment, the conductive sidewall members 140 are formed of p+ silicon material and the conductive sidewall members 145 are formed of n+ silicon material. Conductive sidewall members, 140 and 145 respectively, are disposed adjacent to portions of the dielectric layer 120 formed on the opposing sidewall surfaces 111. In one embodiment, the conductive sidewall members, 140 and 145 respectively, couple to the gates, 130 and 131 respectively, of the NMOS and PMOS transistors. The conductive sidewall members, 140 and 145 respectively, further couple to a portion of the opposing sidewalls 111 of the NMOS and PMOS transistors such that the transistors give metal oxide semiconductor (MOS) type conduction and bipolar junction transistor (BJT) type conduction underneath the gates, 130 and 131 respectively. In one embodiment, the conductive sidewall members, 140 and 145 respectively, are formed of polysilicon.
Current sense amplifier 50 also includes cross-coupled inverters 104 and 103. Inverter 103 comprises the combination of transistor Q.sub.1 and Q.sub.2. The gates of transistors Q.sub.1 and Q.sub.2 are coupled together by gate contact 160. Gate contact 160 couples to gate 130 of transistor Q.sub.2 through a refractory metal 132. Gate contact 160 couples to gate 131 of transistor Q.sub.1 through a refractory metal 132. Similarly, inverter 104 includes transistors Q.sub.3 and Q.sub.4. The gates of transistors Q.sub.3 and Q.sub.4 are coupled together by gate contact 161. Gate contact 161 couples to gate 130 of transistor Q.sub.4 through a refractory metal 132. Likewise, gate contact 161 couples to gate 131 of transistor Q.sub.3 through a refractory metal 132. The collector/drain regions, 107 and 109 respectively, of inverter 103 are coupled together by a metal shunt 162. Likewise, the collector/drain regions, 107 and 109 respectively, of inverter 104 are coupled together by a shunt 163. Metal shunt 163 is cross-coupled to gate contact 160. Metal shunt 162 is cross-coupled to gate contact 161. A pair of bit lines (BL and BL*), 190 and 192 respectively, are coupled to the emitter/source regions 106 of transistors Q.sub.2 and Q.sub.4. The emitter/source regions 106 of transistors Q.sub.2 and Q.sub.4 are additionally coupled to ground through gated lateral NMOS transistors, shown in FIG. 1C, which act as load resistors on the bit lines, 190 and 192 respectively. The current sense amplifier 50 includes a pair of input/output lines, 150 and 152. One input/output line 150 is coupled to metal shunt 162 of inverter 103 and to gate contact 161 of inverter 104. The metal shunt 162 of inverter 103 serves as the output for inverter 103. Input/output line 152 couples to metal shunt 163 of inverter 104 and to gate contact 160 of inverter 105. The metal shunt 163 serves as the output for inverter 104.
FIG. 1B is a top view of the embodiment of FIG. 1. FIG. 1B illustrates the outputs and gates of inverters 104 and 103 cross-coupled together through input/output lines, 150 and 152 respectively.
FIG. 1C is a schematic diagram of the current sense amplifier shown in FIG. 1A with two load transistors, 195 and 196, included in the illustration. The operation of the embodiment of FIG. 1A is described in connection with the schematic diagram of FIG. 1C. When a conventional memory cell is read, the data contained in that cell is placed on the bit line associated with the cell. Each bit line includes a complementary bit line. In FIG. 1C, by way of illustration and not for limitation, the data cell bit line is illustrated by bit line (B/L) 190 and the complementary bit line is illustrated by bit line (B/L*) 192. In FIG. 1C, the cross coupled part of current sense amplifier 50 comprises four transistors, Q.sub.1, Q.sub.2, Q.sub.3 and Q.sub.4 respectively. Transistors Q.sub.2 and Q.sub.4 are NMOS transistors. Transistors Q.sub.1 and Q.sub.3 are PMOS transistors. During a read cycle, the input/output lines shown as 150 and 152 are precharged to some fractional voltage of V.sub.cc, hence, placing a positive voltage on lines 150 and 152. This positive voltage is passed to the gates of NMOS transistors, Q.sub.2 and Q.sub.4, turning them on. Activation of NMOS transistors ,Q.sub.2 and Q.sub.4, permits conduction between emitter/source regions 106 and collector/drain regions 107 in transistors Q.sub.2 and Q.sub.4. Conduction in transistors Q.sub.2 and Q.sub.4 couple bit lines B/L 190 and B/L* 192 with input/output lines, 150 and 152 respectively. Input/output line 150 is coupled to the gates of inverter 104 and input/output line 152 is coupled to the gates of inverter 103. If bit line B/L 190 carries a logic state "0", the cross-coupled structure will cause the gate of PMOS transistor Q.sub.3 to go low, turning on transistor Q.sub.3. Activating transistor Q.sub.3 permits conduction between emitter/source region 108 and collector/drain region 109 in PMOS transistor Q.sub.3. Conduction in transistor Q.sub.3 couples a high voltage level V.sub.cc to input/output line 152. The presence of a high voltage or enhanced voltage on input/output line 152 and the cross-coupled nature of the inverters affects the gate in PMOS transistor Q.sub.1, forcing PMOS transistor Q.sub.1 to remain off. Simultaneously, the ground voltage potential of load resistor 195 is coupled through n-channel transistor Q.sub.2 to input/output line 150, pulling input/output line 150 to ground. The cross coupled nature of the sense amplifier serves to further turn on transistor Q.sub.2, pulling line 150 even further to ground.
Alternatively, if bit line B/L 190 carried a logic state of "1", the cross-coupled nature of inverters 104 and 103 would force the gate of PMOS transistor Q.sub.3 to remain off. Meanwhile, the ground potential level associated with load transistor 196 would couple through activated NMOS transistor Q.sub.4 and the cross-coupled nature of inverters 104 and 103 would activate the gate in PMOS transistor Q.sub.1. The low voltage level at the gate of transistor Q.sub.1 would turn on transistor Q.sub.1, permitting conduction between emitter/source 108 and collector/drain 109 of PMOS transistor Q.sub.1. Conduction through PMOS transistor Q.sub.1 would couple a high voltage level V.sub.cc to input/output line 150, driving input/output line 150 higher, and simultaneously, driving input/output line 152 to ground through transistor Q.sub.4.
FIGS. 2A through 2J illustrate an embodiment of the various processing steps for fabricating a current sense amplifier formed from a complementary pair of gated lateral bipolar transistors. FIG. 2A begins with a lightly doped p- silicon substrate 200. A thin oxide pad layer is grown and then additional oxide is deposited on the substrate, such as by chemical vapor deposition (CVD), to form 0.2 micrometers (.mu.m). A photoresist is applied and selectively exposed to reveal p-channel metal oxide semiconductor (PMOS) device region 221. The oxide layer 220 is etched from the PMOS device regions 221, such as by reactive ion etching (RIE). Wells of n-type silicon material are formed in the substrate 200 to form the PMOS device regions 221. The n-wells 225 of n-type material can be formed by any suitable method, such as by ion implantation. The n-wells 225 are formed to a thickness of approximately 0.4 .mu.m. The photoresist is removed using conventional photoresist stripping techniques. The structure is now as it appears in FIG. 2A.
FIG. 2B illustrates the structure after the next sequence of processing steps. The oxide layer 220 is stripped, such as by RIE and a fresh gate oxide 250 is thermally grown on and across the upper surface 245 of the n-well 225 and the p-substrate 200. A p+ polysilicon gate material 260A is deposited across the surface of the oxide layer 250. The p+ layer 260A is formed to a thickness of approximately 0.2 .mu.m. The p+ layer 260A can be deposited through any suitable method, such as through chemical vapor deposition (CVD). A photoresist is applied and selectively exposed to provide a mask-defining an n-channel metal-oxide semiconductor (NMOS) device region 222. An n+ polysilicon gate material 260B is formed in the NMOS device region 222 through a process such as ion implantation of n-type impurity ions. In one embodiment, the n+ dopant is Arsenic (As). The structure is now as appears in FIG. 2B.
FIG. 2C illustrates the structure after the next sequence of processing steps. The photoresist is stripped, using conventional photoresist stripping techniques. A nitride pad 270 is formed on and across the surface of the n+ gate material 260B and the p+ gate material 260A. The nitride pad 270 is deposited by any suitable process, such as chemical vapor deposition (CVD). The nitride pad is deposited to a thickness of approximately 0.4 .mu.m. A photoresist is applied and selectively exposed to provide a mask which defines and covers the PMOS and NMOS device regions, 221 and 222 respectively. The nitride cap 270 in between device regions, 221 and 222, is removed. The nitride cap 270 is removed by any suitable etching technique, such as by RIE. The p+ gate material 260A in between device regions, 221 and 222, is removed. And, the gate oxide 250 in between device regions, 221 and 222, is removed. Each of these materials can be removed by etching using the RIE technique.
Still using the photoresist as a mask, the etching process is continued into the p- substrate 200 to a depth of approximately 0.2 .mu.m below the bottom of the n-well 225/substrate 200 interface. The etching is performed through any suitable process, such as by RIE. These etching steps leave trenches 242 between the device regions 221 and 222. The structure is now as shown in FIG. 2C. The photoresist is next stripped, using conventional photoresist stripping techniques.
FIG. 2D illustrates the structure after the next series of processing steps. An insulator layer 280 is formed beneath the device regions, 221 and 222 respectively so as to form a semiconductor on insulator (SOI) structure. The insulator layer 280 is formed using, for example, the techniques of U.S. application Ser. No. 08/745,708, entitled Silicon-On-Insulator Islands and Method for Their Formation (the '708 Application), or U.S. Pat. No. 5,691,230, entitled Technique for Producing Small Islands of Silicon on Insulator (the '230 Patent). The '708 application and the '230 Patent are incorporated by reference. The insulator layer 280 separates the p- single crystalline silicon structure 205 of the NMOS device region 222, and the n-well 225 single crystalline silicon structure of the PMOS device region 221 from the substrate 200.
Next, intrinsic polysilicon 290 is deposited by any suitable methods, such as by CVD, to fill the trenches 242. The trenches 242 are planarized stopping on the nitride pads 270. The intrinsic polysilicon 290 in trenches 242 can be planarized by any suitable process, such as by chemical mechanical polishing/planarization (CMP). The intrinsic polysilicon 290 is etched back to leave approximately 0.1-0.2 .mu.m on the bottom of the trenches 242. The etch can be performed using any suitable method such as reactive ion etching (RIE). Oxide 291 is deposited such as by CVD to fill trenches 242. The oxide 291 is etched back approximately 0.4 .mu.m to the level of the top of the gates 260. A nitride spacer 295 is deposited such as by CVD. The nitride spacer 295 is directionally etched to leave on the exposed vertical sidewalls of the nitride pad 270. The structure is now as shown in FIG. 2D.
FIG. 2E illustrates the structure following the next sequence of process steps. The oxide 291 and the intrinsic polysilicon 290 are directionally etched using the nitride spacer 295 overhang as a mask. An n+ polysilicon layer 294A is deposited by CVD. The n+ polysilicon 294A is etched, such as by reactive ion etching, to leave on the vertical sidewalls of the oxide spacer 291. The n+ polysilicon layer 294A serves as the conductive sidewall members for the PMOS device region 221. The structure is now as shown in FIG. 2E.
FIG. 2F illustrates the structure after the next sequence of process steps. Silicon dioxide 292 is deposited in the trenches 242 and then planarized using CMP. The silicon dioxide 292 may be deposited by any suitable method, such as by CVD. A photoresist is applied and selectively exposed to reveal only the NMOS device regions 222. The exposed n+ polysilicon 294A is selectively etched to remove from the sidewalls of the NMOS device regions 222. A p+ polysilicon layer 294B is then deposited by CVD to fill the slots left from removal of the n+ polysilicon 294A and is then removed from the top surface of the structures by any suitable method, such as RIE or CMP. The p+ polysilicon layer 294B serves as the conductive sidewall members for the NMOS device region 222. The structure is now as shown in FIG. 2F.
FIG. 2G illustrates the structure following the next sequence of process steps. A phosphoric acid is applied to remove the nitride cap 270 and the nitride spacer 295 from the active device regions, 221 and 222 respectively. Removal of the nitride cap 270 and the nitride spacer 295 exposes the p+ and n+ gate material, 260A and 260B respectively. A gate contact 296 is deposited, such as by CVD, over the p+ and n+ gate regions, 260A and 260B respectively. In one embodiment, the gate contact 296 is formed of tungsten (W). In another embodiment, the gate contact 296 is any other suitable refractory metal. The gate contact 296 is planarized, such as by CMP, such that the gate contact 296 is left only over the p+ and n+ gate regions, 260A and 260B respectively. The device is now as shown in FIG. 2G.
FIG. 2H is a cross-sectional view along cut line 2H--2H of FIG. 2G. FIG. 2H illustrates the structure after the following sequence of process steps. A photoresist is applied and selectively exposed to mask the gate regions 244. The gate contact 296 material and the n+ or p+ polysilicon gate materials 260B and 260A, which remain exposed are etched to the underlying gate oxide 250. The etching may be performed using RIE. The structure is now as is shown in FIG. 2H.
FIG. 2I is a top view of FIG. 2H. Using the same mask, the p+ or n+ polysilicon layers 294B and 294A, located between the device regions 221 and 222, are removed by etching. The etching can be performed using any suitable method, such as RIE.
FIG. 2J illustrates the structure following the next series of process steps. The photoresist is removed using conventional photoresist stripping techniques. An anneal is performed to out diffuse Boron (B) from the p- layer 205 and to out diffuse Arsenic (As) from the n-well 225. The anneal also serves to out diffuse the dopants from the p+ and n+ polysilicon layers, 294B and 294A respectively. Hence, the annealing serves to dope the adjoining sandwiched intrinsic polysilicon 290. Boron and Arsenic, respectively, will out diffuse into the intrinsic polysilicon 290 in approximately equal amounts. This process step effectively enhances the thickness of the p+ and n+ polysilicon conductive sidewall members, 294B and 294A respectively.
A photoresist is applied and exposed to cover the NMOS gated lateral bipolar transistor 51. Then, a p+ emitter/source region 298A and a collector/drain region 299A are ion implanted using self-aligning process techniques with the gate 260A. The photoresist is then stripped using conventional photoresist stripping techniques.
Another photoresist is applied and exposed, this time to cover the PMOS gated lateral bipolar transistor 52. Another ion implantation step is used to form an n+ emitter/source region 298B and a collector/drain region 299B in the NMOS gated lateral bipolar transistor 52. The photoresist is once again removed. The structure is now as shown in FIG. 2J.
The remaining contact holes and wiring required to form the current sense amplifier 50 are achieved through conventional metallization processing steps.
FIG. 3 is a block diagram illustrating an information handling system 300 according to an embodiment of the present invention. The information handling system includes a central processing unit (CPU) 304. The central processing unit 304 is coupled to a memory unit 330 by a system bus 310. By way of illustration and not by way of limitation, the memory unit 330 is a random access memory (RAM). The random access memory unit can be constructed to include the current sense amplifier structure embodiment presented above.
Conclusion
An improved circuit and method for a current sense amplifier arc provided. The present invention conserves die space and achieves enhanced transistor response. The stores offer performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiment and the other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims
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What is claimed is:
1. A current sense amplifier circuit, comprising: a pair of cross coupled inverters, wherein each inverter comprises a complementary pair of gated lateral bipolar transistors, the complementary pair comprising a first channel type transistor and a second channel type transistor, each gated lateral bipolar transistor comprising: a body region formed of single crystalline semiconductor material and extending outwardly from a substrate, the body region having an upper surface and opposing sidewalls; a emitter/source region formed within a portion of the upper surface of the body region; a collector/drain region formed within a portion of the upper surface of the body region; a gate formed above the upper surface of the body region; and conductive sidewall members disposed adjacent to the opposing sidewalls of the body region; a pair of bit lines coupled to the emitter/source regions of the first channel type transistor in each inverter; and a pair of input/output lines, each one within the pair of input/output lines coupled to the collector/drain regions of one of the cross-coupled inverters and to the gates of the other inverter.
2. The current sense amplifier circuit of claim 1, wherein the first channel type transistor comprises an n-channel metal-oxide semiconductor (NMOS) transistor, and wherein the second channel type transistor comprises a p-channel metal-oxide semiconductor (PMOS) transistor.
3. The current sense amplifier circuit of claim 1, further comprising a dielectric layer disposed between the upper surface of the body region and the gate, and the dielectric layer disposed between the opposing sidewalls of the body region and the conductive sidewall members.
4. The current sense amplifier circuit of claim 1, wherein the conductive sidewall members couple to the gate, and wherein the conductive sidewall members couple to a portion of the opposing sidewalls.
5. The current sense amplifier circuit of claim 1, further comprising an insulator layer formed between the body region and the substrate.
6. A method of fabricating a current sense amplifier, the method comprising: forming a pair of cross coupled inverters, wherein forming each inverter comprises forming a complementary pair of gated lateral bipolar transistors, the complementary pair comprising a first channel type transistor and a second channel type transistor, and wherein forming each gated lateral bipolar transistor comprises: forming a body region formed of single crystalline semiconductor material and extending outwardly from a substrate, the body region having an upper surface and opposing sidewalls; forming a emitter/source region within a portion of the upper surface of the body region; forming a collector/drain region within a portion of the upper surface of the body region; forming a gate above the upper surface of the body region; and forming conductive sidewall members disposed adjacent to the opposing sidewalls of the body region; forming a pair of bit lines to couple to the emitter/source regions of the first channel type transistor in each inverter; and forming a pair of input/output lines, and forming each one within the pair of input/output lines to couple to the collector/drain regions of one of the cross-coupled inverters and to the gates of the other inverter.
7. The method of fabricating a current sense amplifier of claim 6, wherein forming the body region of each transistor includes forming the body region on an insulator layer formed on the substrate.
8. The method of fabricating a current sense amplifier of claim 6, wherein forming the complementary pair of gated lateral bipolar connected transistors comprises forming an n-channel metal-oxide semiconductor (NMOS) transistor as the first channel type transistor, and forming a p-channel metal-oxide semiconductor (PMOS) transistor as the second channel type transistor.
9. The method of fabricating a current sense amplifier of claim 6, wherein the method further comprises forming a dielectric layer between the upper surface of the body region and the gate, and forming a dielectric layer between the opposing sidewalls of the body region and the conductive sidewall members.
10. The method of fabricating a current sense amplifier of claim 6, wherein forming the conductive sidewall members comprises coupling the conductive sidewall members to the gate, and coupling the conductive sidewall members to a portion of the opposing sidewalls.
11. The method of fabricating a current sense amplifier of claim 6, wherein forming the conductive sidewall members comprises polysilicon.
12. An information handling system comprising: a central processing unit; a random access memory; and a system bus for communicatively coupling the central processing unit and the random access memory, the random access memory (RAM) further including a current sense amplifier, the current sense amplifier further comprising: a pair of cross coupled inverters, wherein each inverter comprises a complementary pair of gated lateral bipolar transistors, the complementary pair comprising a first channel type transistor and a second channel type transistor, each gated lateral bipolar transistor comprising: a body region formed of single crystalline semiconductor material and extending outwardly from a substrate, the body region having an upper surface and opposing sidewalls; a emitter/source region formed within a portion of the upper surface of the body region; a collector/drain region formed within a portion of the upper surface of the body region; a gate formed above the upper surface of the body region; and conductive sidewall members disposed adjacent to the opposing sidewalls of the body region; a pair of bit lines coupled to the emitter/source regions of the first channel type transistor in each inverter; and a pair of input/output lines, each one within the pair of input/output lines coupled to the collector/drain regions of one of the cross-coupled inverters and to the gates of the other inverter.
13. The information handling system of claim 12, wherein the first channel type transistor comprises an n-channel metal-oxide semiconductor (NMOS) transistor, and wherein the second channel type transistor comprises a p-channel metal-oxide semiconductor (PMOS) transistor.
14. The information handling system of claim 12, wherein each gated lateral bipolar transistor further comprises a dielectric layer disposed between the upper surface of the body region and the gate, and a dielectric layer disposed between the opposing sidewalls of the body region and the conductive sidewall members.
15. The information handling system of claim 12, wherein the conductive sidewall members couple to the gate, and wherein the conductive sidewall members couple to a portion of the opposing sidewalls.
16. The information handling system of claim 12, each gated lateral bipolar transistor further comprising an insulator layer formed between the body region and the substrate.
17. The information handling system of claim 12, wherein the conductive sidewall members are polysilicon.
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