Isolated Sidewall Capacitor With Dual Dielectric

This invention is related to the following copending U.S. patent applications:

1) Ser. No. 08/577,178, filed Dec. 22, 1995, entitled "Isolated Sidewall Capacitor";

2) Ser. No. 08/577,168, filed Dec. 22, 1995, entitled "Isolated Sidewall Capacitor Having a Compound Plate Electrode";

3) Ser. 08/577,165, filed Dec. 22, 1995, entitled "Isolated Sidewall Capacitor with L-Shaped Dielectric";

all filed on the same day, assigned to the present assignee, and incorporated by reference in their entireties.

This invention is directed to capacitors and the manufacture of the same, and more particularly to a stacked capacitor employing a dual dielectric structure which is suitable for use with high dielectric constant materials.

In the manufacture of ultra large scale integration (ULSI) circuit devices, DRAM (dynamic random access memory) and FRAM (ferroelectric random access memory) chips have become increasingly dense. As density increases, feature size shrinks, and so too does memory cell size. The capacitors that are an integral part of memory cells must therefore take up a minimum of space (i.e. have a small "footprint") and still be capable of storing large amounts of electrical charge (i.e. a capacitance on the order of 30 fF).

Stacked capacitors are one type of capacitor structure that has achieved a small footprint. However, because capacitance is a function of dielectric area and the dielectric constant of the dielectric material, as the area decreases the dielectric constant must increase. Currently available high dielectric constant materials provide at best a capacitance/area of 100 fF/sq. micron, so the area must be on the order of 0.3 sq microns.

The use of high dielectric constant materials presents a problem when using traditional materials like silicon as an electrode. The silicon can react with the high dielectric constant material or oxidize during deposition of the high dielectric constant material to form an interface layer of silicon dioxide, which reduces the effective dielectric constant of the dielectric material.

Deposition temperature and leakage are other problems involved in high dielectric constant materials. Because they must be deposited at relatively high temperatures, the first-deposited electrode is formed from a high melting point conductive material which does not oxidize or react with the dielectric. In addition, the electrode material should have a large work function to increase the barrier. Platinum (Pt) and other similar material are suitable for use as electrodes in this situation. However, these electrode materials are typically difficult to pattern using conventional processes. For example, using reactive ion etching (RIE) to pattern Pt results in sloped sidewalls which, given a thick layer, can result in a significant reduction of available surface area on which to form the capacitor. Additionally, while high dielectric constant materials must be isolated from silicon, a good connection must be formed between the capacitor and the semiconductor circuit elements in the substrate.

Thus, there remains a need for a capacitor which can be produced using high dielectric constant materials yet avoids the problems associated with a reduction in the effectiveness of the finished structure.

It is therefore an object of the present invention to provide a capacitor which incorporates a high dielectric constant material which minimizes or avoids contact between silicon and the high dielectric constant material, especially during high dielectric constant material deposition.

It is a further object to provide a capacitor which incorporates a high dielectric constant material which minimizes patterning steps for the electrodes.

It is an additional object to provide a capacitor which incorporates a high dielectric constant material which allows a good connection between the capacitor and the semiconductor circuit elements in the substrate.

It is another object to provide a capacitor which incorporates a high dielectric constant material with an area of approximately 0.3 sq. microns.

It is yet another object to provide a capacitor which incorporates a high dielectric constant material which is suitable for large scale production.

In accordance with the above listed and other objects, a capacitor structure is provided with two capacitors. The first capacitor includes a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, a first opening formed in the first conductor and first non-conductor, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, filled by a second conductor. The second capacitor includes the second conductor, a first non-conductor disposed over the top portion of the second conductor, a third conductor disposed over the first non-conductor, and the third conductor electrically connected to the first conductor. A second non-conductor isolates the first conductor from the second conductor.

These and other features, aspects, and advantages will be more readily apparent and better understood from the following detailed description of the invention, in which:

FIG. 1 shows an isolated sidewall capacitor with a dual dielectric;

FIGS. 2(a) through 2(g) illustrate the steps to manufacture the dual dielectric capacitor.

FIG. 3 shows another embodiment of the isolated sidewall capacitor with a dual dielectric; and

FIG. 4 illustrates an alternate step for the step illustrated in FIG. 2(f), all in accordance with the present invention.

Referring now to the drawings and more particularly to FIG. 1, a dual dielectric capacitor structure is shown. A substrate (not shown) has a dielectric (non-conductive) layer 102 formed thereon, and a conductive plug 104 embedded in layer 102. Plug 104 provides contact to the desired circuit elements (also not shown) in the underlying substrate. An optional electrically conductive diffusion barrier 120 may be located on top of conductive plug 104. A conductive layer 106 is formed on top of dielectric 102, having an opening therein, which is filled by a high dielectric constant sidewall spacer 110. Sidewall spacer 110 defines another opening which is filled with electrode 112. Electrode 112 has a top portion 114 which extends at least out over sidewall spacer 110, and a high dielectric constant layer 116 is located on top portion 114. Another conductive layer 118 is located on layer 116, and layer 118 joins layer 106. A low dielectric constant material 108 with vertical portion 109 isolates conductive layers 106 and 118 from electrode 112.

FIGS. 2(a) through 2(g) illustrate one set of steps that may be used to manufacture the capacitor of FIG. 1. In FIG. 2(a), dielectric layer 102 has been formed and patterned by conventional means, for example by reactive ion etching (RIE). Dielectric layer 102 may be SiO.sub.2, SiN.sub.x, phosphosilicate glass, (PSG), borophosphosilicate glass (BPSG), a spin-on-glass, flowable oxide, or similar materials. Note also that more than one dielectric layer can be used in place of single layer 102 Conductive plug 104 has been formed by a conventional process such as chemical vapor deposition (CVD) followed by planarization by chemical mechanical polishing (CMP) for example. Plug 104 may be doped polysilicon, W, or any suitably conductive material. Note that the diameter of plug 104 is not critical, and may be significantly narrower or wider than as shown. After an etch-back process to recess plug 104 below the surface of dielectric 102, diffusion barrier 120 has been formed again by a conventional process such as sputtering, and may be Ta.sub.1-x Si.sub.x N.sub.y with 0<x<1 and y>0, TiN, or similar materials.

Conductive layer 200 and dielectric layer 202 are then formed by conventional means, for example sputter deposition for layer 200 and low temperature CVD, plasma CVD, or sputter deposition for layer 202. An optional adhesion layer (not shown) may be used between layer 200 and layer 202. Conductive layer 200 may be selected from the groups of materials known as noble metals (e.g. Au, Pt, Pd, Ir, Rh, etc.), alloys of noble metals with either noble or non-noble metals, metals whose oxides are conducting (e.g. Ru, Mo, etc.), electrically conducting oxides (e.g. RuO.sub.2, IrO.sub.2, Re.sub.2 O.sub.3, etc.), oxidation resistant electrically conducting silicides or nitrides (e.g. Ta.sub.1-x Si.sub.x N.sub.y, TiN, WN, etc.), or similar materials. Dielectric layer 202 may be of SiO.sub.2, SiN.sub.x, Al.sub.2 O.sub.3, flowable oxides, spin-on-glasses, BSG, BPSG, high dielectric constant materials such as BST, or similar materials.

In FIG. 2(b), conductive layer 200 and dielectric layer 202 are patterned conventionally (by reactive ion etching, for example) to form an opening 204 and top electrode 106. Diffusion barrier 120 can function as an etch stop during patterning of layers 200 and 202. Opening 204 may be approximately 0.2 to 0.5 microns in diameter.

Opening 204 is then cleaned using conventional means, for example RIE. In FIG. 2(c), a conformal layer of high dielectric constant material 206 is formed, for example by chemical vapor deposition (CVD), and in FIG. 2(d), material 206 is patterned to form sidewall spacer 110 by conventional means, for example by reactive ion etching (RIE), leaving opening 205. High dielectric constant material 206 may be selected from the groups of materials known as ferroelectrics, paraelectrics, perovskites, layered perovskites, relaxors, pyrochlores, or any material with a dielectric constant roughly greater than or equal to 20. Examples of such materials are Ta.sub.2 O.sub.5, (Ta.sub.2 O.sub.5).sub.x (TiO.sub.2).sub.1-x with 0<x<1, PbMg.sub.x Nb.sub.1-x O.sub.3+y with 0<x<0.5, 0<y<1 (PMN), (Ba,Sr)TiO.sub.3 (BST or BSTO), SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT), BaTiO.sub.3, SrTiO.sub.3, PbZr.sub.1-x Ti.sub.x O.sub.3 (PZT), PbZrO.sub.3, Pb.sub.1-x La.sub.x TiO.sub.3 (PLT), and Pb.sub.1-x La.sub.x (Zr.sub.y Ti.sub.1-y).sub.1-x/4 O.sub.3 (PLZT).

In FIG. 2(e), another conductive layer has been formed and patterned by conventional means (by RIE or ion beam sputtering, for example) to form electrode 112. The bottom of electrode 112 fills opening 205 and a top portion 114 of electrode 112 extends at least out over the top of sidewall spacer dielectric 110. Top portion 114 may also extend out over layer 202 as well. Electrode 112 may be selected from the same group of materials as conductive layer 106. In FIG. 2(f), a second layer of high dielectric constant material is deposited and patterned in a conventional manner to form dielectric layer 116. For process simplicity, electrode 112 and layer 116 may be deposited sequentially and then patterned simultaneously. Layer 116 may be formed from the same class of materials as sidewall spacer dielectric 110.

In FIG. 2(g), a dielectric layer of the same or different material as layer 202 is formed over the structure from FIG. 2(f) and patterned by conventional means (for example a self-aligned reactive ion etching process) to leave a dielectric sidewall spacer 108 with a vertical portion 109 and expose the top surface of electrode 112.

Finally, a third electrode 118 is formed over the structure from FIG. 2(g) which is electrically connected to and forms a common electrode with conductive layer 106, resulting in the structure shown in FIG. 1. Electrode 118 may be formed from the same types of materials as electrodes 112 and 106, plus metals whose oxides are non-conducting (e.g. Ti, Al, TiN, W, etc). or a combination material such as a TiN liner with an overcoat of doped polysilicon or W, but is not required to be the same material. Dielectric sidewall spacer 108 with vertical portion 109 prevents shorting between top portion 114 of electrode 112 and electrode 118.

After completion, the capacitor structure may be annealed. During annealing, diffusion barrier 120 acts either as a barrier to oxygen diffusion or a barrier to plug material diffusion or both.

The resulting structure contains two capacitors connected in parallel; the first a sidewall capacitor formed by electrodes 106 and 112 with sidewall spacer dielectric 110, and the second a planar capacitor formed by electrode 112 and 118 with dielectric 116. The sidewall capacitor provides about 60-70% of the necessary capacitance, and the planar capacitor increases the capacitance by 30-40%. Both capacitors have their edges protected with a thick dielectric 108 and thus problems with high fields at the corners and edges of the electrodes are eliminated.

Sample values for the stacked capacitor structure are as follows:

Using these measurements, the aspect ratio of gap 204 is 1:1, which is a reasonable value to be uniformly coated by a chemical vapor deposition (CVD) process.

FIG. 3 shows another embodiment of the dual dielectric capacitor. FIG. 3 is similar to FIG. 1 except that dielectric 300 extends down to surround the perimeter of top portion 114 of electrode 112, and has a horizontal portion 301. Dielectric 302 has no vertical portion as compared to dielectric because dielectric 300 isolates top portion 114 of electrode from electrodes 118 and 106.

FIG. 4 shows an alternate step to that shown in FIG. 2(f) that may be used to manufacture the capacitor of FIG. 3. In FIG. 4, a conformal layer of high dielectric material is deposited and patterned in a conventional manner to form dielectric layer 300 and expose the top surface of electrode 106. Layer 300 may be formed from the same class of materials as sidewall spacer dielectric 110. Processing continues as above with formation of third electrode 118. In comparison to the structure of FIG. 1, the structure of FIG. 3 has the disadvantage of requiring an additional lithographic alignment step to pattern dielectric 300. However, the structure of FIG. 3 does not require the application and patterning of additional dielectric 109.

In summary, a capacitor has been provided which incorporates a high dielectric constant material which minimizes or avoids contact between silicon and the high dielectric constant material, especially during high dielectric constant material deposition. Furthermore, patterning steps for the electrodes have been minimized, and a good connection is provided between the capacitor and the semiconductor circuit elements in the substrate. The resulting structure has an area of approximately 0.3 sq. microns, and is suitable for large scale production.

While the invention has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Thus, the invention is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the invention and the appended claims.