MIS Transistor Structure for Increasing Conductance Between Source and Drain Regions

The present invention generally relates to field effect transistors and more particularly to a metal-insulator-semiconductor (MIS) transistor having increased conductance between the source and drain regions.

Typical MOS transistors uses a semiconductor substrate in which a source region and a drain region are defined in the semiconductor substrate at opposite sides of a channel region also defined in the substrate. A gate insulator is provided on the channel region and a gate electrode is provided on the gate insulator and thus above the channel region. When a number of such MOS transistors are assembled on a common semiconductor substrate, as in the case of a large scale integrated circuit (LSI), there appears a leakage path between the MOS transistors formed in the substrate. Such a leakage path deteriorates the operation of the MOS transistors and hence the operation of the integrated circuit.

In a conventional LSI, the MOS transistors are isolated from each other by providing a field insulator region between the transistors. Such an insulator region is formed by oxidization of surface of the substrate. However, the field insulator region for isolating the MOS transistor occupies a large area on the substrate and presents the problem that the number of the MOS transistors which can be assembled on the LSI is reduced.

On the other hand, there is another type of MOS transistor having a so-called semiconductor-on-insulator (SOI) structure in which the transistor is formed on an insulator. Referring to FIG. 1 showing a typical example of such a MOS transistor having the SOI structure, the transistor comprises a silicon single crystal film 1 provided in the form of an island on an insulator layer 2 formed on a substrate 3. Because of this reason, the silicon single crystal film 1 will be referred to as a silicon island 1. The silicon island 1 is divided into a source region 1a and a drain region 1b with a channel region therebetween which is covered by a gate insulator 4. Further, a gate electrode 5 is provided so as to cover the gate insulator 4. The gate electrode 5 extends from the silicon island 1 and forms a gate contact area 5' on the insulator layer 2 for contact with a wiring electrode. In such an SOI structure, each MOS transistor is provided on the insulator layer 2 and the problem of isolation of plural transistors is eliminated.

FIG. 2 shows a cross section of the silicon island 1 taken along a line 3--3', of FIG. 1. Referring to FIG. 2, a channel 4a for passing carriers through the silicon island 1 from the source region 1a to the drain region 1b (see FIG. 1) is formed immediately below the gate insulator 4. It should be noted that the gate width which is defined as the width of the silicon island 1 measured perpendicularly to the gate length of the MOS transistor, is represented by W.sub.O and the height of the gate defined as the height of the silicon island 1, is represented by W.sub.H.

In such a conventional MOS transistor having the SOI structure, there is a problem in that the total current which can flow between the source region and the drain region is limited by the cross sectional area of the channel 4a. As the channel 4a is formed immediately below the gate insulator 4 in the form of thin layer, the overall cross sectional area of the channel 4a is approximated by the total gate width WG which is represented by using the gate width W.sub.O and the gate height W.sub.H, as WG=W.sub.O +2W.sub.H. In order to increase the current or the conductance between the source and of the gate width W.sub.O or the size of the gate height W.sub.H. However, such an increase results in an increase in the size of the MOS transistor which is undesirable from the view point of assembling the MOS transistors in an LSI form.

FIG. 3 shows another prior art MOS transistor proposed to solve the aforementioned problem. In FIG. 3, parts corresponding to those parts in the preceding drawings are given identical reference numerals and the description thereof will be omitted.

Referring to FIG. 3 showing the cross section of this another prior art MOS transistor device, there is provided another gate electrode 6 directly on the insulator layer 2 which in turn is formed on the substrate 3 similarly to the previous case. The gate electrode 6 is buried under an insulator layer 7 and a silicon island 10 is provided on the insulator layer 7. The silicon island 10 is covered by the gate insulator 4 except for its bottom surface, which is in contact with the insulator layer 7 and a pair of doped regions 10a and 10b, which are formed in the silicon island 10 as the source and drain regions. These source and drain regions 10a and 10b are connected to wiring electrodes through respective contact holes (not shown) provided in the gate insulator 4. Similarly to the device of FIG. 1, the gate electrode 5 is provided on the gate insulator 4. Further, the silicon island 10 is buried under an insulator layer 8 together with the gate insulator 4 and the gate electrode 5.

In this prior art transistor, there is formed a channel 4b along the bottom of the silicon island 10 in correspondence to the gate electrode 6 and another channel 4c along the top of the silicon island 10 in correspondence to the gate electrode 5. As the channels are formed along the top and bottom of the silicon island 1, the overall cross sectional area of the channel is nearly doubled and the conductance of the MOS transistor is increased correspondingly.

However, even with such a structure, it is easily understood that there is a practical limitation in the increase in the conductance of the transistor because of the resulting excessive increase in the size of the transistor. Further, such a transistor has a problem in that the structure becomes complex and needs many steps in manufacturing.

Accordingly, it is a general object of the present invention to provide a novel and useful MIS transistor wherein the aforementioned problems are eliminated.

Another object of the present invention is to provide a MIS transistor wherein the conductance between a source region and a drain region is substantially increased, but with a simultaneous decrease in the size of the MIS transistor.

Another object of the present invention is to provide a MIS transistor comprising an isolated silicon body defined with a source region, a drain region and a channel region, wherein the isolated silicon body has a width (W.sub.O), measured perpendicularly to a direction connecting the source region and which is the drain region, set to be substantially smaller than twice the maximum extension (W.sub.MAX) of the depletion region in the channel region (W.sub.O <2W.sub.MAX). According to the present invention, the threshold voltage of the MIS transistor is decreased substantially and the carrier concentration level in the channel formed in the channel region when the MIS transistor is in the turned on state is substantially increased. As a result, the conductance of the transistor between the source and drain regions when the transistor is in the turned on state is substantially increased while at the same time the size of the MIS transistor is reduced.

Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with attached drawings.

FIG. 1 is a perspective view showing a prior art MOS transistor having a typical SOI structure;

FIG. 2 is a cross sectional view of the transistor of FIG. 1 taken in a plane along a line 3--3' in the drawing;

FIG. 3 is a cross sectional view showing another prior art MOS transistor having the SOI structure;

FIG. 4 is a perspective view showing a first embodiment of the MIS transistor according to the present invention;

FIG. 5 is a cross sectional view showing an essential part of the MIS transistor of FIG. 4;

FIG. 6(A) shows the formation of the inversion layer in the MIS transistor of FIG. 4;

FIG. 6(B) shows the formation of the inversion layer in the prior art MIS transistor;

FIG. 7 is a graph showing the change in transistor gain factor in relation to various different total gate widths, for the MIS transistor having the structure shown in FIG. 4;

FIGS. 8(A) and (B) are cross sectional views respectively taken in planes along the lines 8(A)--8(A') and 8(B)--8(B') in FIG. 4;

FIG. 9 shows a second embodiment of the MIS transistor of the present invention;

FIG. 10 shows a third embodiment of the MIS transistor of the present invention; and

FIG. 11 is a plan, bottom surface view of the MIS transistor of FIG. 10.

FIG. 4 shows a first embodiment of the MIS transistor of the present invention. In the description.. hereinafter, the description will be given for a MOS transistor which uses an oxide film for the gate insulator. However, the present invention is by no means limited to the MOS transistor but is applicable in general as well to the MIS transistor using a non-oxide insulating material for the gate insulator.

Referring to the drawing, the transistor is a p-channel type MOS transistor and comprises an isolated silicon body 11 provided on a silicon oxide insulator layer 12 which in turn is provided on a silicon substrate 13. The silicon body 11 comprises a source region 11a doped to the p.sup.+ -type, a drain region 11b also doped to the p.sup.+ -type and a channel region 11c (not shown in FIG. 4, see FIG. 5) doped to the n-type and is located between the source region 11a and the drain region 11b. In the example illustrated, the carrier concentration level in the channel region 11c is set to about 3.times.10.sup.15 cm.sup.-3. Further, a source contact region 11a' and a drain contact region 11b' are connected respectively to the source region 11a and the drain region 11b for contact with wiring electrodes (not shown). For this purpose, each of the source contact region 11a' and the drain contact region 11b' has an enlarged area forming, affording a connection pad.

FIG. 5 shows the channel region 11c of the silicon body 11 in cross section taken in a plane along the line 5--5' in FIG. 4. Referring to FIG. 5, the channel region 11c is covered with a gate insulator 14 having a thickness of about 100 .ANG.. It should be noted that the channel region 11c has a height W.sub.H and a width W.sub.O, in which the width W.sub.O is measured perpendicularly to the gate length GL of the MOS transistor as defined in FIG. 4. In the illustrated example, the width W.sub.O is set to about 0.1 -0.2 .mu.m, and the height W.sub.H is set to about 0.4-0.5 .mu.m. Further, the level of the impurity concentration in the channel region 11c is set to about 3.times.10.sup.15 cm.sup.31 3. As will be described later, the width W.sub.O is set smaller than twice the maximum extension, W.sub.MAX, of the depletion region formed in the channel region 11c. Further, a polysilicon gate electrode 15 covers the gate insulator 14. As can be seen in FIG. 4, the gate electrode 15 extends on the insulator 12 generally perpendicularly to a direction of the silicon body 11 extending along a line connecting the source region 11a and the drain region 11b. At an end of the gate electrode 15, there is formed a connection pad 15' for connection to a wiring electrode (not shown).

Next, the operation of the MOS transistor of the present invention will be described with reference to FIG. 6(A) in comparison with the prior art structure shown in FIG. 6(B). In FIG. 6(A), parts constructed identically to corresponding parts in the preceding drawings are given identical reference numerals and the description thereof will be omitted. Further, for the sake of comparison, parts in FIG. 6(B) corresponding to parts in FIG. 6(A) are given identical reference numerals.

First, formation of the strong inversion state in the prior art device will be described with reference to FIG. 6(B). In this prior art device, the channel region 11c is made to have a gate width W.sub.O ' which is substantially larger than the gate width W.sub.O of the MOS transistor of FIG. 5. Further, it will be assumed that the rest of the device has a construction identical to the device of FIG. 5. Referring to FIG. 6(B), there is formed a depletion region 11c' in the channel region 11c in response to application of a negative voltage on the gate electrode 15. This depletion region 11c' extends further (inwardly) with increasing levels of the voltage on the gate electrode 15, and when the voltage on the gate electrode 15 has reached a threshold voltage Vth of the MOS transistor, the depletion region 11c' reaches a maximum distance W.sub.MAX which is determined as a function of the impurity concentration level in the channel region 11c as follows:

where K.sub.S is the dielectric constant of silicon, .epsilon..sub.o is the vacuum permittivity, q is a constant equal to 1.60.times.10.sup.-19 coulomb, .phi..sub.F is a Fermi potential measured from a midpoint in the forbidden band, and N.sub.D is the concentration of the donors in the channel region 11c. It should be noted that the parameter .phi..sub.F is determined by N.sub.D. Thus, the maximum extent of the depletion region 11c' is determined once the impurity concentration of the channel region is determined. The following Table I lists some examples of W.sub.MAX as a function of N.sub.D.

When the extent of the depletion region reaches the value W.sub.MAX there appear holes forming a channel 11d in the channel region 11c along a boundary to the gate insulator 14. With further increase in the gate voltage beyond the threshold voltage Vth, the concentration of holes is increased and the conductance between the source and the drain regions is increased.

It should be noted that in the prior art device of FIG. 6(B), the width W.sub.O ' of the channel region 11c exceeds 2W.sub.MAX and thus there remains a neutral zone 11e at the center of the region 11c. In such a prior art structure, there is no way to increase the conductance of the MOS transistor in the fully turned ON state except for increasing the size of the channel region such as the width W.sub.O ' or the height W.sub.H which, however, is contradictory to the requirement of reducing the size of the device.

Next, the operation of the MOS transistor of the present invention will be described with reference to FIG. 6(A). As already described, the essential feature of the present invention is to reduce the width W.sub.O of the channel region 11c to a valve substantially smaller than, i.e., W.sub.O <2W.sub.MAX. In other words, the channel region 11c of the silicon body 11 is fully depleted. In the illustrative example of FIG. 6(A), corresponding to the structure of FIG. 5, the gate width W.sub.O is set to 0.1-0.2 .mu.m which is much smaller than 2W.sub.MAX which in turn is about 1.03 .mu.m (2.times.5300 .ANG.) when a dose of 3.times.10.sup.15 cm.sup.-3 is used for the n-type channel region 11c.

In such a structure, the carriers 11d forming the conductive channel in the channel 14a region 11c appear when a voltage much smaller than the threshold voltage V.sub.th of the MOS transistor is applied to the gate electrode 15 because of the smaller depletion charge in the depletion region 11c' confined within the channel region 11c. It should be noted that the channel region 11c in the device of the invention (FIG. 6A) has a width W.sub.O which is much smaller than the maximum extent of the depletion region W.sub.MAX in a conventional device (FIG. 6B). With further increases in the voltage at the gate electrode 15, the concentration of the carriers 11d in the channel 11c increases because of the sharp rise of the surface potential in the depletion region 11c' confined within the channel region 11c. Such a sharp rise of the surface potential is achieved due to the fact that there arises no increase in the depletion charge with increased levels of the gate voltage in the device of the invention, in view of the fully depleted channel region 11c (FIG. 6A). Thus, the present invention achieves the increase in the conductance of the MOS transistor between the source region 11a and the drain region 11b by reducing the gate width W.sub.O of the transistor (FIG. 6A).

FIG. 7 shows the result of measurement of the transistor gain factor .beta. for the MOS transistor of FIG. 5 with various different total gate widths WG. Here, the total gate width WG is defined as WG W.sub.O +2W.sub.H, as already described. The measurement is made for the structure of FIG. 5 having a gate length GL of 10 .mu.m while applying a voltage of -1 volt between the drain region and the source region. As can be seen in the drawing, the parameter BETA (.beta.) decreases linearly in logarithmic scale with the decreasing total gate width GW until the total gate width WG reaches about 2 .mu.m. Once the total gate width WG is decreased below about 2 .mu.m, the gain factor .mu. starts deviating from the linear trend in an upward direction indicating that the conductance between the source and the channel region increases with decreasing values of the total gate width WG.

Thus, the MOS transistor of the present invention increases the conductance by decreasing the gate width W.sub.O to less than two times the maximum extension of the depletion layer in the channel region (W.sub.O <2W.sub.MAX). At the same time, it is desirable to maintain a substantial value of the height W.sub.H in order to maintain an increased level of conductance. Preferably, the height W.sub.H is set relatively to the width W.sub.O so as to satisfy the relation:

By choosing the gate width W.sub.O and the gate height W.sub.H as such, one can achieve a substantial value for the total gate length WG even when the gate width W.sub.O is decreased.

Next, manufacturing of the MOS transistor of FIG. 4 will be described briefly, with further reference to FIGS. 8(A) and 8(B). First, the silicon substrate 13 is oxidized by heating under an atmosphere containing oxygen and the insulator layer 12 having the thickness of about 1.0 .mu.m is formed. Next, a polysilicon layer is deposited on the insulator layer 12 in a thickness of about 0.5 .mu.m. This polysilicon layer is then doped to the n-type and melted by laser irradiation. After cooling, the molten polysilicon is recrystallized into a single crystal film of n-type. Then, this single crystal film of silicon has deposited thereon a photoresist and a pattern of the silicon body 11 is drawn on the photoresist by exposure to electron beam. After the selective removal of the photoresist according to the exposed pattern, the single crystal film of silicon is subjected to anisotropic etching using a mixture of bromine (Br.sub.2) and helium (He). After the etching, the remaining photoresist is removed and the silicon body thus formed is subjected to oxidization using a hydrochloric solution. As a result, the gate layer insulator 14 and patterned having a thickness of about 100 .ANG. is formed. After the gate insulator 14 is formed, a polysilicon layer is deposited on the gate insulator 14 and thereby the gate electrode 15 is formed. Further, ion implantation is performed for forming the source region 11a as well as the source contact region 11a' and the drain region 11b as well as the drain contact region 11b', such as by implanting boron fluoride (BF.sub.2) with a dose of 2.times.10.sup.15 cm.sup.-2 under an acceleration voltage of 40 keV. After the ion implantation, a phosphosilicate glass (PSG) protection layer 16 is provided so as to cover the whole structure of FIG. 4 and wiring electrodes 17 are made to contact with the source contact region 11a', the drain contact region 11b' and the gate contact region 15' as shown in the cross sectional view of FIGS. 8(A) and (B) respectively showing the cross section taken along an X--X' line and a Y--Y' line of FIG. 4.

Although the present invention is described for the p-channel type MOS transistor in the description heretofore, the present invention is by no means limited to the p-channel type MOS transistor but may be applicable to the n-channel type MOS transistor as well.

FIG. 9 shows a second embodiment of the MOS transistor of the present invention. In FIG. 9, parts constructed identically to corresponding parts in the preceding drawings are given identical reference numerals and the description thereof will be omitted.

In this embodiment, a silicon body 21 is provided on the insulator layer 12 formed on the silicon substrate 13. The silicon body 21 comprises a contact region 21a, three source regions 21b, 21c and 21d branched from the contact region 21a, three channel parts 21e, 21f and 21g respectively connected to the source regions 21b, 21c and 21d, three drain regions 21h, 21i and 21j respectively connected to the channel regions 21e, 21f and 21g, and another contact region 21k connected to the drain regions 21h, 21i and 21j. The source regions and the drain regions may be doped to the p.sup.+ -type similarly to the case of the first embodiment, and in this case, the channel regions 21e-21g are doped to the n-type. Further, each of the channel regions 21e-21g are covered with gate insulators 21l, 21m and 21 n. Further, a gate electrode 25 is provided on the silicon body 21 so as to make contact with the gate insulators 21l-21n. In this embodiment, the total gate width WG can be increased as a result of the use of the three branched channel regions and the conductance of the MOS transistor is further improved. It should be noted of course that the width W.sub.O for each of the channel regions 21e-21g is set substantially smaller than 2W.sub.MAX, similarly to the case of the first embodiment. As a result, the total gate width WG is in this case represented as WG=6W.sub.H +3W.sub.O. Further, the number of branches of the source regions, channel regions and the drain regions is not limited to three but may be any desirable number.

It should be noted that the transistors in FIG. 4 and FIG. 9 may be formed directly on a semiconductor body.

FIG. 10 shows a third embodiment of the MOS transistor of the present invention. In this embodiment, a pit 30 is formed in a silicon substrate 32 except for a part corresponding to a silicon plate 31. In other words, the silicon plate 31 extends upwardly from the bottom of the pit 30. At both ends of the silicon plate 31, a source region 31a and a drain region 31b are formed in continuation with the substrate 32 at the bottom of the pit 30. In other words, the part 31c of the silicon plate 31 between the source region 31a and the drain region 31b acts as the channel region. The silicon plate 31 including the source region 31a and the drain region 31b is isolated from the rest of the substrate 32 by a channel cut layer (not shown in FIG. 10, see FIG. 11) at the bottom of the pit 30 which surrounds the silicon plate 31 and the source and drain regions 31a and 31b. Such a channel cut layer may be formed by a vertical ion implantation of phosphorus for example with a dose of about 3.times.10.sup.13 cm.sup.-2. After the formation of the channel cut layer, the entire surface of the silicon plate 31 is oxidized to form a gate insulator film 34. Further, a gate electrode 35 of polysilicon is deposited on the gate insulator film 34. This gate electrode 35 extends along the surface of the substrate 32 defining the bottom wall of the pit 30 and upwardly on the vertical side wall of the pit 30, and thereafter along the upper surface of the substrate 32, with an insulating layer 35' intervening between the gate electrode 35 and the of the pit 30 as well as the upper surface of the substrate 32. Thereafter, the source region 31a and the drain region 31b are doped by an oblique ion implantation using the gate electrode 35 as the mask for the silicon plate 31. According to this embodiment, one can construct the MOS transistor on the silicon substrate directly.

FIG. 11 shows a plan view of the MOS transistor of FIG. 10 in the state before the gate insulator 34 and the gate electrode 35 are formed, in which the channel cut layer is shown by a dotted region.

In the description heretofore, it was assumed that the semiconductor substrate is silicon. However, the present invention is not limited as such but silicon carbide may also be used for the semiconductor substrate. Further, as already described, the present invention is not limited to the p-channel type MIS transistor but may be applicable also to the n-channel type transistor. In this case, the channel region is doped to the p-type, the source region is doped to the n-type and the drain region is doped to the n-type.

Further, the present invention is not limited to these embodiments but numerous variations and modifications may be made without departing from the scope of the invention.