Insulated-Gate Vertical Field-Effect Transistor With High Current Drive and Minimum Overlap Capacitance

This invention relates generally to field-effect transistors ("FETs"), and more particularly to those FETs having a channel region that is generally vertical with respect to the horizontal plane of the silicon wafer.

As the performance and complexity of integrated circuits, and in particular memory circuits, increases, the area of an individual transistor on the integrated circuit must decrease in order to maintain die size and to control manufacturing costs. In the past, vertical FETs were introduced either in a trench or a V-groove to align the channel region of the FET vertically. Therefore, the area of the FET could be reduced because the channel did not use valuable horizontal area leading to a larger die area. A problem with many of the vertical designs is that performance is sacrificed as the area is decreased. Parasitic capacitance from the gate of the FET to the source ("overlap capacitance"), drain, or substrate can increase in the vertical FET, which results in a lower maximum operating frequency. In addition, in many vertical designs, the drain contact is made at the bottom of the FET through the substrate or by directly metallizing the bottom surface of the die, and thus the drain and source contacts cannot both be made at the surface of the transistor.

Accordingly, a need remains for a vertical FET having an area smaller than a horizontal FET having a comparable channel region, while having minimum gate parasitic capacitance and the option of surface gate, source, and drain contacts.

It is, therefore, an object of the invention to provide a vertical FET having a small horizontal area suitable for high density integration on a silicon die.

Another object of the invention is to provide a vertical FET having low parasitic gate capacitance in order to maintain a high maximum operating frequency.

A further object of the invention is to provide a vertical FET having a high current drive capability.

An advantage of the invention is that the vertical FET requires no additional masking steps beyond those normally required for the fabrication of an integrated random access memory.

Another advantage of the invention is that the source, drain, and gate contacts of the vertical FET may all be contacted from the top surface of the die, if desired.

Another advantage of the invention is that the gate region within each trench sidewall contains no discontinuous features that decrease breakdown voltage.

According to the present invention, an insulatedgate vertical FET has a channel region and gate structure that is formed along the sidewall of trench in a P-type semiconductor substrate. The drain and source regions of the FET are formed in the mesa and the base portions of the trench. All contacts to the gate, drain, and source regions can be made from the top surface of the semiconductor substrate. One or more sidewalls of the trench are oxidized with a thin gate oxide dielectric layer followed by a thin polysilicon deposited film to form an insulated gate layer. A reactive ion etch step removes the insulated gate layer from the mesa and the base portions of the trench. An enhanced N-type implant creates the drain and source regions in the mesa and the base portions of the trench. The trench is partially filled with a spacer oxide layer to reduce gate-to-source overlap capacitance. A conformal conductive polysilicon layer is deposited over the insulated gate layer. A portion of the conductive polysilicon layer is extended above the surface of the trench onto the mesa to form a gate contact. A field oxide covers the entire surface of the FET, which is opened in the mesa to form gate and drain contacts, and in the base to form the source contact.

The foregoing and other objects, features and advantages of the invention are more readily apparent from the following detailed description of a preferred embodiment of the invention, which proceeds with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

FIGS. 1-1A, 2-3, 4-4A, 5, 6-6A, 7, 8 and 8A are plan and sectional views of a semiconductor substrate at various stages of processing in accordance with the invention that ultimately form an insulated-gate vertical FET.

The sectional view of a completed insulated-gate vertical FET 10 is shown in the sectional view of FIG. 8. A semiconductor substrate 12 forms the starting material for the FET. The substrate material can be P-type or N-type silicon formed in a wafer, epitaxial layer, or well. The top surface of the substrate defines a reference surface for defining subsequent vertical structures. A trench in the substrate 12 forms the channel region and the gate structure of the vertical FET 10. The trench defines a surface including first and second mesa portions 14A and 14B at the level of the reference surface of the substrate 12, one or more sidewalls 16, and a base 18 recessed from the reference surface. An insulated gate layer 20 is formed on the sidewalls 16 of the trench, which includes a gate dielectric layer 22 and a gate conductive layer 24.

A first enhanced N-type layer 26 implanted in the first portion of the mesa l4A forms the first current node of the transistor, typically the drain. However, since the drain and source are interchangeable in an FET, the N-type layer 26 can also serve as the source. A second enhanced N-type layer 28 is implanted in the base 18 of the trench to form the second current node of the transistor, typically the source. Again, given the interchangeability of the current nodes, the second enhanced N-type layer 28 can also serve as the drain.

A spacer dielectric layer 30 partially fills the base 18 of the trench and a conductive layer 32 is deposited along the sidewalls 16 of the trench over the insulated gate layer 20 extending from the spacer dielectric layer 30 to the reference surface of the substrate 12. The conductive layer 32 forms part of a gate contact and is spaced apart from the enhanced N-type layer 28 by the spacer dielectric layer 30 to decrease the parasitic overlap capacitance between the gate and source of the FET.

The conductive layer 32 and the spacer dielectric layer 30 are opened to expose the second enhanced N-type layer 28. A field dielectric layer 34 covers the entire surface of the FET 10, and is opened in three places to form drain, source, and gate contacts. The field dielectric layer 34 is opened above the first enhanced N-type layer 26 to form a drain contact 36, which is covered with an interconnect line 42; above the second enhanced N-type layer 28 to form a source contact 38, which is covered with an interconnect line 44; and above the conductive layer 32 in the second portion 14B of the mesa to form a gate contact 40, which is covered with an interconnect line 46.

The structure and method for making the FET 10, and the nature of the individual layers including dimensions and suitable materials is described in greater detail below.

Referring now to FIG. 1, there is shown a sectional view of a partially processed silicon substrate 12 having a patterned photoresist layer 11 over an optional thin grown oxide layer 15. The substrate can be either P-type or N-type material depending upon whether an N-channel or a P-channel FET is desired. FIG. 1A is a corresponding plan view showing the contours of the photoresist opening, which will determine the nature of the trench. In the case of a rectangular pattern, a trench having four sidewalls and a rectangular base is formed. Other patterns, including a circular pattern resulting in one continuous sidewall and polygonal patterns resulting in multiple sidewalls are possible within the constraints of the photolithographic equipment that is used.

In FIG. 2, the trench is formed with a reactive ion etch, revealing first and second mesa portions 14A and 14B, sidewalls 16, and a base portion 18. The sidewalls 16 of the trench form the body of the FET 10 that includes the channel region. The FET 10 can thus be formed in one or more of the sidewalls 16. The etchant species for removing the silicon substrate and creating the trench can be CF.sub.4, or any other conventional etchant species. The depth of the trench defines the length of the channel of the FET 10. Therefore, the channel is ideally etched to a depth equal to the desired length of the channel region, up to a maximum length of about 8000 to 10000 Angstroms. The width, and consequently the width to length ("W/L") ratio of the FET 10, is determined by the dimensions of the photoresist pattern.

In FIG. 3, the insulated gate layer 20 is revealed in greater detail. The insulated gate layer 20 is comprised of a gate dielectric layer 22 such as oxide, and a gate conductive layer 24 such as polysilicon. The gate oxide layer is grown along the entire surface of the trench to a depth of about 200 to 250 Angstroms, but this depth can be made thinner or thicker as required by the application. The thin gate polysilicon layer 24 is deposited onto the surface of the oxide layer 22 to a thickness of about 500 to 1000 Angstroms. Again, the thickness can be easily adjusted as required by the application. The gate polysilicon layer 24 is highly conformal with oxide layer 22. The gate polysilicon layer 24 forms the active gate contact of the FET 10, which inverts the substrate silicon 12 in the sidewalls 16 of the trench. Therefore, it is desirable that the gate polysilicon layer 24 be doped with an appropriate dopant such as phosphorous to form a conductive layer capable of inverting the entire channel region. A suitable sheet resistance for the gate polysilicon layer 24 after the doping step is completed is about 50 ohms per square.

In FIG. 4, the insulated gate layer 24 is removed in a first portion l4A of the mesa, and first and second enhanced N-type ("N+") layers 26 and 28 are implanted into the first portion l4A of the mesa and into the base of the trench 18 to form the active drain and source of the FET 10. The gate polysilicon layer 24 is removed with a reactive ion etch. The gate polysilicon layer remains on the sidewalls 16 since the reactive ion etch acts primarily in the vertical directional and the gate polysilicon layer 24 is conformal to the sidewalls 16. After the gate polysilicon layer 24 is removed with the reactive ion etch, the gate oxide layer 22 is removed from the first portion 14A of the mesa and the base 18 by an oxide etch. After the insulated gate layer 20 is removed, first and second enhanced N-type layers 26 and 28 are implanted into the first portion of the mesa 14A and the base 18. A suitable implant dosage is 9.times.10.sup.15 ions per cm.sup.2 at 30 KeV. The P-N junction between the enhanced N-type layers and the P-type body of the FET 10 using this implant dosage occurs at a depth of approximately 2000 to 4000 Angstroms.

The corresponding plan view is shown in FIG. 4A, revealing the first enhanced N-type layer 26 in the first portion of the mesa l4A, the gate dielectric layer 22 and the gate conductive layer 24 along the sidewalls of the trench and in the second portion of the mesa 14B, and the second enhanced N-type layer 28 in the base of the trench.

The base 18 of the trench is partially filled with a spacer oxide layer 30 in FIG. 5. The spacer oxide layer 30 minimizes the parasitic overlap capacitance between the gate and the source of the FET 10. The spacer oxide layer 30 is a thick conformal layer that is deposited over the surface of the FET 10, which completely fills in the trench. A mechanical planerization removes most of the spacer oxide layer 30 from the mesa portions of the trench, while leaving the spacer oxide layer 30 in the trench. A subsequent oxide etch removes any remaining oxide from the mesa portions of the trench, and etches back the spacer oxide layer 30 in the trench to partially fill the trench to a thickness of about 2000 to 3000 Angstroms. However, the thickness of the spacer oxide layer 30 can be adjusted depending upon the reduction in the parasitic overlap capacitance that is desired.

In FIG. 6 a conductive layer 32 is added that contacts the insulated gate layer 20 in order to provide a surface contact for the gate of the FET 10. The conductive layer 32 is a conformal polysilicon layer that is deposited over the entire surface. Once the conductive layer 32 has been deposited, it is masked and etched away in the first portion l4A of the mesa and at the base 18 of the trench. The conductive layer remains on the sidewalls 16 of the trench and in the second portion 14B of the mesa. A suitable thickness for the conductive layer is about 2000 Angstroms. The polysilicon is doped with an appropriate dopant such as phosphorous to render it conductive. A suitable sheet resistance upon completion of the doping step is about 25 to 35 ohms per square.

The corresponding plan view is shown in FIG. 6A, revealing the first enhanced N-type layer 26 in the first portion of the mesa l4A, the gate dielectric layer 22, the gate conductive layer 24, and the conductive layer 32 along the sidewalls of the trench and in the second portion of the mesa 14B, and the spacer dielectric layer 30 in the base of the trench.

In FIG. 7, a center portion of the spacer dielectric layer 30 is etched away using a conventional oxide etch to reveal the second enhanced N-type layer 28. The opening in the spacer dielectric layer 30 subsequently serves as a top surface source contact. A thick, conformal field dielectric layer 34 such as oxide is subsequently deposited over the entire surface of the FET 10. As discussed above, the field dielectric is etched in three places to form a drain contact 36, a source contact 38, and a gate contact 40. Each contact is respectively covered with a separate interconnect line 42, 44, and 46 for interconnecting the FET 10 with other circuit components. The interconnect lines can be polysilicon, doped polysilicon, or metal such as gold or aluminum.

The corresponding plan view is shown in FIG. 8A in outline form only. The outline of the gate dielectric layer 22, the gate conductive layer 24, and the conductive layer 32 along the sidewalls of the trench and in the second portion of the mesa 14B is shown. The location of the drain contact 36, source contact 38, and gate contact 40, as well as the drain interconnect line 42, the source interconnect line 44, and the gate interconnect line is also shown.

Therefore, it has been shown that an insulated-gate vertical FET has a small horizontal area suitable for high density integration on a silicon die, since the gate and channel area are disposed along and within one or more sidewalls of the trench. The active gate region is continuous along the trench sidewall and is protected from further processing steps. The active gate region within each trench sidewall 16 is continuous from the mesa to the base and contains no sharp corners, edges, steps or other such discontinuous features that decrease breakdown voltage. Low parasitic gate-to-source overlap capacitance is reduced by the spacer dielectric layer 30 in order to maintain a high maximum operating frequency. Note in FIG. 8 that only the thin gate conductive layer 24 remains in close proximity to the second enhanced N-type layer 28, establishing a minimum overlap capacitance. Furthermore, the vertical FET has a high current drive capability at a given W/L ratio since the parasitic capacitance is low. It has also been shown that the vertical FET 10 requires no additional masking steps beyond those normally required for the fabrication of an integrated random access memory. For example, the N+ implant used to form the source and drain regions is typically creates the storage node of the capacitor for a memory cell.

It has also been shown that the source, drain, and gate contacts of the vertical FET 10 may all be contacted from the top surface of the die, if desired. It is appreciated, however, by those skilled in the art that the exact configuration and layout of the FET 10 can be changed in many ways. For example, the drain and gate contacts need not be placed in a row as shown in FIGS. 8 and 8A, but can be orthogonally arranged if required by layout considerations. Also, the source region of the FET 10 need not be contacted from the surface, but can be contacted through additional N-type layers in contact with N-type layer 28, or by directly metallizing the bottom surface of the die by any conventional means taught in the prior art. The source region of the FET 10 may also be coupled to a capacitor in a DRAM array configuration, while still maintaining the minimized gate-to-source overlap capacitance of the present invention.

The vertical FET 10 of the present invention is suitable for use in many applications, such as in a DRAM array, in an inverter, a buffer or driver circuit, or a stand-alone power FET. If minimum area is required, it is desirable that the gate of the vertical FET 10 be constructed in only one of the sidewalls of a rectangular trench. If maximum drive current is required for a power FET, it is desirable that the gate of the vertical FET 10 be constructed in all four sidewalls of a rectangular trench.

Having described and illustrated the principles of the invention in a preferred embodiment thereof, it is apparent that the invention can be modified in arrangement and detail without departing from those principles. For example, the polarity of the N-type and P-type layers discussed herein can be reversed, depending upon whether a P-channel or N-channel device is selected. As another example, the materials selected for the various layers and their attendant specifications can all be changed to suit the requirements of the application. Therefore, we claim all modifications and variations of the invention falling within the spirit and scope of the following claims.