US 6,003,144 AGrant
Error Detection and Correction
Issue Date:1999-12-14
•48 Claims
•24 Drawing Sheets
Abstract
A computer system having a CPU, a disk array system accessible by the CPU, and a disk array controller that includes error detection and connection logic. The disk array controller includes a processor and a memory system connected to signal lines carrying data bits, address bits, and check bits. An error detection and correction device is connected to detect and correct N-bit errors in the data bits using the check bits, N being greater than two. An error in the address bits is detected using the same check bits. The data bits are organized as multiple bytes, and the error detection and correction device is connected to detect and correct up to eight-bit errors in each byte and to detect a single-bit error or a two-adjacent-bit error in the address bits.
Metadata
Assignee
- Compaq Computer Corporation
Inventors
- Sompong P. Olarig
- Michael F. Angelo
Application Information
Application Number:US 8600295
Filing Date:1997-06-30
Priority Date:1997-06-30
Art Unit:275
Classifications
IPC:
G06F 1100
Field of Search:
395321183.18;185.05;185.06;185.0737.2;37.6;37.7;39.1;40.13;37.11;37.12;44;45
Patent Drawings (24 sheets)
Description
Background
The invention relates to error detection and correction.
Error correction codes (ECCs) have been developed that both detect and correct certain types of errors. One class of ECC algorithm includes the "Hamming code," which is capable of detecting multibit errors and correcting single-bit errors. Another well known ECC algorithm is the "Reed-Solomon code," which is able to correct two-bit errors per word.
In D.C. Bossen, "B-Adjacent Error Correction," IBM J. Res. Develop., pp. 402-408 (July 1970), Reed-Solomon and Hamming type codes are described which are capable of correcting not only single-bit errors but also single clusters of multiple adjacent-bit errors.
Some disk array controllers made by Compaq Computer Corporation, such as those sold with the SMART2 disk array controllers, use an ECC algorithm (referred to as the SMART2 ECC algorithm) that protects 64 bits of data with 16 check bits. The SMART2 ECC code can detect and correct errors in 8 adjacent data bits within a single byte. The SMART2 ECC code was implemented to protect data written into and read from write cache buffers in the disk array controller.
Summary
The invention may have one or more of the following advantages. Without adding check bits, detection of address errors and detection and correction of the full range of errors in a data byte (from a single-bit error to an eight-bit error in a byte) can be achieved using the same set of check bits. In addition, the error detection and correction code can be extended to detect and correct 16-bit errors in a word, 32-bit errors in a double word, and so forth.
In general, the invention features a computer system having a CPU, a disk array system accessible by the CPU, and a disk array controller connected to the disk array system. The disk array controller includes a processor and a memory system coupled to the processor. The memory system is connected to signal lines carrying data bits, address bits, and check bits. An error detection and correction device is connected to detect and correct multiple errors in the data bits using the check bits, and to detect an error in the address bits using the same check bits. The data bits are organized as multiple bytes. The error detection and correction device is connected to detect and correct up to eight-bit errors in each byte, and the error detection and correction device is connected to detect a single-bit error or a two-adjacent-bit error in the address bits.
Implementations of the invention may include one or more of the following features. The memory system is connected to signal lines carrying 64 or fewer data bits and 16 check bits.
In general, in another aspect, the invention features a computer system having a memory system connected to signal lines carrying data bits, address bits, and check bits. An error detection and correction device is connected to detect and correct N-bit errors in the data bits using the check bits, and to detect an error in the address bits using the same check bits, N being greater than two.
Implementations of the invention may include one or more of the following features. The data bits are organized as bytes, and the error detection and correction device is connected to detect and correct up to eight-bit errors in each byte. The error detection and correction device is connected to detect a single-bit error or a two-adjacent-bit error in the address bits. The memory system is connected to signal lines carrying 64 or fewer data bits and 16 check bits. The memory system is connected to signal lines carrying 32 or fewer address bits. The error detection and correction device generates a syndrome table that includes entries mapped to correctable or uncorrectable errors, and a detected address error is mapped to an uncorrectable error entry. The computer system also includes a disk controller, and the memory system is located in the disk controller. A disk system is connected to the disk controller, the memory system being used as a cache for data transferred to the disk system. The memory system includes a main memory of the computer system. The error detection and correction device includes a decoder connected to receive the check bits, address bits, and data bits to generate an indication that a memory address or data error has occurred. A correction circuit is connected to correct the data bits if a correctable memory data error is present. The error detection and correction device further includes a partial address check bit generator to generate partial address check bits based on the memory address bits. The decoder is connected to further receive the partial address check bits to determine if a memory address or data error has occurred.
In general, in another aspect, the invention features a computer system having a processor and a memory system coupled to the processor. The memory system is connected to signal lines carrying 64 or fewer data bits, 32 or fewer address bits, and 16 check bits. An error detection and correction device is connected to detect and correct up to eight-bit errors in the data bits using the check bits, and to detect a single-bit error or a two-adjacent-bit error in the address bits using the same check bits. The error detection and correction device generates a syndrome table that includes entries mapped to correctable or uncorrectable errors, and a detected address error is mapped to an uncorrectable error entry. A mass storage device is accessible by the processor.
In general, in another aspect, the invention features a method of detecting and correcting errors in a memory system, the memory system storing data bits, address bits, and check bits. The data bits, address bits, and check bits are received. An error in the address bits is detected using the check bits. N-bit errors in the data bits are detected and corrected using the same check bits, N being greater than two.
In general, in another aspect, the invention features a disk controller having a memory system connected to signal lines carrying data bits, address bits, and check bits. An error detection and correction device is connected to detect and correct N-bit errors in the data bits using the check bits, and to detect an error in the address bits using the same check bits, N being greater than two.
Brief Description of the Drawings
FIG. 1 is a block diagram of the computer system.
FIG. 2 is a block diagram of a disk array controller.
FIG. 3 is a block diagram of the data path and logic (including error detection and correction logic) in a memory controller.
FIG. 4 is a block diagram of the error detection and correction logic.
FIG. 5 is an address parity check matrix.
FIG. 6 is a data parity check matrix.
FIGS. 7A-7N are a syndrome table.
FIGS. 8 and 9 are block diagrams of memory devices connected to multiple error detection and correction units.
FIG. 10 is a block diagram of a disk array controller connected to network systems.
FIG. 11 is a block diagram of a main memory system in a computer.
Description
Referring to FIG. 1, a computer system includes a disk array controller 110 connected to a disk array system 112. The disk array controller 110 is connected to a Peripheral Component Interconnect (PCI) bus 106 for communication with other components of the computer system.
The disk array controller 110 has a memory (which can be made of synchronous dynamic random access memories or SDRAMs) to store data. To protect data stored in the memory, the disk array controller includes error detection and correction (EDC) logic. The EDC logic can correct any combination of eight-bit wide errors in any particular byte. The data width of the memory is 64 bits or 8 bytes. Using 16 check bits, the EDC logic in the disk array controller can protect all 8 bytes of the memory data. In addition, using the same 16 check bits, the EDC logic can detect single and two-adjacent bit errors (two physically adjacent bits) in a 32-bit address used to access the memory. All detected address bit errors are indicated as uncorrectable errors.
A processor board 101 is also connected to the PCI bus 106 and includes a central processing unit (CPU) 100 connected to a CPU-PCI bridge 102, which controls communication between the PCI bus 106 and the CPU 100. The CPU-PCI bridge 102 also includes a memory controller for controlling main memory 104.
The PCI bus 106 is further connected to a video controller 108 connected to a video display 114. The computer system also includes an expansion bus, which can be an Extended Industry Standard Architecture (EISA) bus 128. Communication between the PCI bus 106 and the EISA bus 128 is controlled by a PCI-EISA bridge 116. The EISA bus 128 is connected to EISA slots 126 to receive expansion cards. The EISA bus 128 is also connected to an I/O controller 118, which provides interfaces to a keyboard 120, a serial port 122, and a parallel port 124.
Referring to FIG. 2, the disk array controller 110 includes a local PCI bus 184 on which are located SCSI controllers 186 that control reads and writes to the disk array system 112. Each SCSI controller 186 is connected to an array of disk drives. The disk array controller 110 can implement a Redundant Array of Inexpensive Disks (RAID) algorithm (e.g., RAID 1, RAID 4, or RAID 5) to protect data transferred between the disk array controller 110 and the disk array system 112.
A local processor card 182 is also located on the local PCI bus 184 and controls data transfers to the SCSI controllers 186. All data transfers between the disk array system 112 and the other components of the computer system are routed between the local PCI bus 184 and host PCI bus 106 through a PCI interface controller 192 that includes a PCI-PCI bridge 188 and a memory controller 190.
The write and read data to and from the disk array system are temporarily stored (or cached) in a memory 180, which can be implemented with synchronous dynamic random access memories (SDRAMs). Alternatively, regular DRAMs can also be used. SDRAMs, which can operate at, for example, 66 MHZ or 99 MHZ provide relatively fast data transfer speeds (e.g., 528 MBytes/sec at 66 MHZ and 832 MBytes/sec at 99 MHZ). The size of the memory 180 can be varied, with a possible memory size being two gigabytes.
By using the memory 180 to store write or read data being transferred to or from the disk array system 112, disk access speeds are improved as the components on the host PCI bus 106 do not need to wait for the relatively slow disk array system 112 to complete the write or read operation.
For example, for a disk write operation in which data is transferred from the host PCI bus 106 to the disk array, the write can be performed directly to the SDRAMs 180. Upon completion of the write, the PCI-PCI bridge 188 asserts a transaction complete indication. The write data in the memory 180 is later transferred (under control of the local processor card 182) to the disk array system 112 to complete the disk write operation. In this manner, the host PCI bus 106 is not tied up waiting for the disk array controller 110 to complete a write to the disk array system 112.
In addition to caching write or read data, the memory 180 can also store other types of data structures (such as data structures for use by the local processor card 182 or SCSI controllers 186).
To ensure the integrity of data read from the SDRAMs 180, the memory controller 190 (in the PCI interface controller 192) includes an EDC logic unit 189 which can detect and correct errors in the memory data bits MD[63:0] using 16 check bits CB[15:0]. The data bits MD[63:0] and check bits CB[15:0] form an 80-bit memory data bus. The EDC logic unit 189 can also detect single or two-adjacent bit errors in the 32-bit memory address (received from either the host PCI bus 106 or local PCI bus 184) used to read data from the memory 180.
Referring to FIG. 3, components of the EDC logic unit 189 in the memory controller 190 of the disk array controller 110 are shown. During a read cycle from the memory 180, data on the memory bus 177 are loaded into a latch 200 from the memory bus 177. The read data, which include check bits CB[15:0] and data bits MD[63:0] from the memory 180, are provided to an error detection and correction (EDC) circuit 202. Partial address check bits PCHK[15:0], generated by a partial address check bit generator 201 in response to the 32-bit address ADDR[31:0] on the internal address and data bus 179 (originally the PCI address from either the host or local PCI bus 106 or 184) provided to address the memory 180, are also received by the EDC circuit 202. Based on the retrieved check bits CB[15:0], partial address check bits PCHK[15:0], and the memory data MD[63:0], the EDC circuit 202 determines if an error has occurred in the memory data or address.
If the error is correctable, the erroneous bit or bits are flipped by the EDC circuit 202. If the error is uncorrectable, the EDC circuit 202 asserts a non-correctable status error signal to an interrupt controller 203. Data MUXDATA[63:0] from the EDC circuit 202 are provided to a latch 204, whose output is connected to buffers 206 for driving the read data onto the internal address and data bus 179 from the memory controller 190 to the PCI-PCI bridge 188.
During a write cycle to the memory 180 (from either PCI bus 106 or 184), write data (routed through the PCI-PCI bridge 188) are loaded from the internal address and data bus 179 into a 64-bit latch 208 whose output is connected to one input of a multiplexer 204. The other input of the multiplexer 204 is connected to receive the corrected memory data bits from the EDC circuit 202. The multiplexer 204 selects bytes from either the latch 208 or the EDC circuit 202 for output to a check-bit generator (CBG) 210, as well as to the input of a 64-bit buffer 212. The multiplexer 204 is used to route appropriate bytes to the memory bus 177 during a read-merge-write cycle, as described below. The buffer 212 drives the selected data signals onto the memory bus 177.
The check-bit generator 210 generates check bits from the 64-bit write data according to parity check matrices similar to the parity check matrices shown in FIGS. 5 and 6. The only difference is that during check bit generation by the generator 210, the check bits CB[15:0] are not used. Thus, each of the check bits is an exclusive OR of the data bits MD[63:0] that are associated with the value "1" and the corresponding partial address check bit PCHK. For example, the generated check bit CB[0] is the exclusive OR of data bits MD 1, 5-7, 10, 14, 15, 19, 23, 28, 37, 46, 55, and 56, and partial check bit PCHK[0]. Similarly, the generated check bit CB[1] is the exclusive OR of the data bits MD 2, 6, 7, 11, 15, 20, 29, 38, 47, 48, and 57, and the partial address check bit PCHK[1]. The other check bits CB[15:2] are generated in similar fashion.
The generated check bits CB[15:0] are provided to the input of a 16-bit buffer 214, which drives the states of the check bits CB[15:0] onto the memory bus 177 for storage in the memory 180 along with the write data MD[63:0].
If the write cycle is to fewer than all 8 data bytes of the memory bus 177, then a read-merge-write cycle is performed by the memory controller 190. In a read-merge-write cycle, the data stored in the memory 180 is first retrieved and provided to the input of the multiplexer 204 by the EDC circuit 202. The retrieved data corresponding to the bytes not written are then merged with the write data bytes from the latch 208 by the multiplexer 204 and presented as the write data at the output of the multiplexer 204. Thus, for example, if only bytes 0-3 and 6-7 are to be written to the memory 180 (with bytes 4 and 5 remaining unchanged in the write operation), then the read-merge-write operation would retrieve bytes 4 and 5 from the memory 180, merge them with the write bytes 0-3 and 6-7, and present the merged data at the output of the multiplexer 204.
Referring to FIG. 4, the EDC circuit 202 (FIG. 2) includes a syndrome bit generator 360 that receives partial address check bits PCHK[15:0], memory data check bits CB[15:0], and memory data bits MD[63:0]. The partial address check bits PCHK[15:0] are generated by an address check bit generator 302 from memory address signals ADDR[31:3] received from the PCI bus 106 or 184 (and latched by a latch 301) according to the address parity check matrix shown in FIG. 5. The output of the address check bit generator 302 is provided to inputs of 16 AND gates 303, which also receive the enable bit ENABLE.sub.-- ECC. The output of the AND gates 303 produce PCHK[15:0] by asserting configuration signals ENABLE.sub.-- ECC and ENABLE.sub.-- AECC. The signal ENABLE.sub.-- AECC when deasserted separately disables address error detection and correction. Thus, if desired, data EDC can be enabled (by asserting ENABLE.sub.-- ECC) while address EDC can be disabled (by deasserting ENABLE.sub.-- AECC).
The syndrome bit generator 360 generates syndrome bits CHKBIT[15:0] according to the data parity check matrix shown in FIG. 6. The syndrome bit signals CHKBIT[15:0] are provided to a fix bit generator 304, which generates fix bits FIXBIT[63:0] according to the syndrome table shown in FIGS. 7A-7N. For a correctable data bit error, the corresponding one of the fix bits FIXBIT[63:0] is set high. A set of 64 exclusive OR gates 306 receiving the fix bits FIXBIT[63:0] at one set of inputs and data bits MD[63:0] at a second set of inputs then flips the erroneous data bit by performing a bit-wise exclusive OR operation of the fix bits and memory data bits. For a no-error or uncorrectable error condition, the fix bits FIXBIT[63:0] are all "0"s.
The corrected data bits from the exclusive OR gates 306, as well as the syndrome bits CHKBIT[15:0], are provided to the "1" input of a multiplexer 308. The "0" input of the multiplexer 308 receives memory check bits CB[15:0] and memory data bits MD [63:0]. The multiplexer 308 selects between the corrected and uncorrected version of the memory data and check bits for output as MUXDATA[79:0], depending on whether a configuration signal ENABLE.sub.-- ECC (output of an internal configuration register, not shown) is set high, which occurs when error detection and correction is enabled. If the signal ENABLE.sub.-- ECC is high, then the corrected data bits from the exclusive OR gates 306 are output by the multiplexer 308.
The fix bit generator 304 also provides a signal CRERR (to indicate a correctable error has occurred) and a signal NCERR (to indicate a non-correctable error has occurred). The signal NCERR is gated with the signal ENABLE.sub.-- ECC by an AND gate 310, which outputs a signal C.sub.-- NCERR. The signal CRERR is gated with the signal ENABLE.sub.-- ECC by an AND gate 312, which outputs a signal C.sub.-- CRERR.
Once an error occurs, the interrupt controller 203 (FIG. 3) responds to assertion of either the C.sub.-- NCERR or C.sub.-- CRERR signals by generating an interrupt to the main CPU 100 of the computer system.
If the signal C.sub.-- CRERR is asserted, the interrupt controller 203 asserts an interrupt request (IRQ) signal to the CPU 100 to indicate that a correctable error has occurred. When the interrupt is acknowledged, a software interrupt routine determines the proper procedure for informing the operator of the error, such as creating a log file listing all such correctable errors. If a non-correctable error occurs, the interrupt controller 203 initiates a non-maskable interrupt (NMI) to indicate to the CPU 100 that the data retrieved from the memory 180 is unreliable. The NMI software routine determines the proper courses of action following a non-correctable error, which include notifying the operator of such non-correctable error and/or notifying the application software of the error so that the erroneous read cycle can be retried. Alternatively, the memory controller 190 can retry or terminate its cycle (on the host or local PCI bus 106 or 184 via PCI-PCI bridge 188) without returning the corrupted data to the requester.
When either the C.sub.-- NCERR or C.sub.-- CRERR signal is asserted, the syndrome bits are stored in a diagnostic register 205 (FIG. 3). The register 205 includes other diagnostic bits, including a bit which indicates whether the error occurred during a read cycle or read-merge-write cycle. Further, the memory address associated with the error condition is also stored in another diagnostic register (not shown). The bit stored in the diagnostic registers are accessible by the CPU 100 under control of the interrupt handler routine.
Referring to FIG. 5, the memory address parity check matrix shows how the partial address check bits PCHK[15:0] are generated from memory address bits ADDR[31:3]. A partial address check bit PCHK[Y] (Y=0-15) is generated by performing an exclusive OR operation of the address bits associated with the value "1". Thus, for example, the partial address check bit PCHK[0] is generated by performing an exclusive OR operation of address bits ADDR 3, 5-9, 18, 20, 25, and 28. Partial address check bit PCHK[1] is generated by performing an exclusive OR operation of address bits ADDR 3, 4, 9, 11, 15, 17, 18, and 26. The other partial address check bits are generated in similar fashion.
Referring to FIG. 6, the memory data parity check matrix shows how the syndrome bits CHKBIT[15:0] are generated. A syndrome bit CHKBIT[Y] (Y=0-15) is generated by performing an exclusive OR operation of all memory data bits MD[63:0] associated with a value "1", the corresponding check bit CB[Y], and the corresponding partial address check bit PCHK[Y].
Thus, for example, the syndrome bit CHKBIT[0] is generated by performing an exclusive OR operation of memory data bits MD 1, 5-7, 10, 14, 15, 19, 23, 28, 37, 46, 55, and 56, the check bit CB[0], and the corresponding partial address check bit PCHK[0]. Similarly, the syndrome bit CHKBIT[1] is generated by performing an exclusive OR operation of data bits MD 2, 6, 7, 11, 15, 20, 29, 38, 47, 48, and 56, check bit CB[1], and the corresponding partial address check bit PCHK[1]. The other syndrome bits CHKBIT[15:2] are generated in like fashion.
Referring to FIGS. 7A-7N, the syndrome bits CHKBIT[15:0] map into a syndrome table. The 16 syndrome bits can represent 65,536 possible positions in the syndrome table. For simplicity and brevity, only the positions in the syndrome table that map to a correctable error are shown; the uncorrectable positions in the syndrome table are omitted.
Each of the syndrome table positions contains 2 entries: the first entry is the hexadecimal value of the syndrome bits CHKBIT[15:0] represented as four hexadecimal numbers; and the second entry indicates the error position associated with the memory or check bit data.
The syndrome table is further divided into eight subsections, with each subsection corresponding to a type of error condition (that is, single-bit error, two-bit error, etc.). Each subsection is further divided into 10 columns, with each column representing a byte of the 10-byte memory data bus 177. The 10 possible memory data bytes include 8 bytes of memory data and 2 bytes of check bits.
The first subsection displays the syndrome code and position for a single-bit error (FIG. 7A). For example, the syndrome code CHKBIT[15:0] having a hexadecimal value of 8013 indicates an error in byte 0 at data position 7 (D07); a syndrome code having a hexadecimal value of 8087 indicates a single-bit error in byte 1 at data position D15; a syndrome code having a hexadecimal value of 80CD indicates a single-bit error in byte 2 at position D23; etc. An error in the check bytes (byte 8 and byte 9) is also detectable. For example, a syndrome code having a hexadecimal value of 0001 indicates a single-bit error at position CB0 (check bit 0); a syndrome code having a hexadecimal value of 0100 indicates a single-bit error at check bit position CB8; etc.
The second subsection of the syndrome table (as shown in FIG. 7B) illustrates the syndrome code and positions for two-bit errors occurring within the same byte. Thus, for example, a syndrome code having a hexadecimal value of C094 indicates a two-bit error in byte 0 at memory data positions 6 and 7 (D0607); a syndrome code having a hexadecimal value of C04A indicates a two-bit error in byte 1 at positions D14 and D15; etc. Similarly, for the check bits, a syndrome code having a hexadecimal value of 0003 indicates a two-bit error in byte 8 at check bits CB0 and CB1; a syndrome code having a hexadecimal value of 0300 indicates a two-bit error in byte 9 at check bits CB8 and CB9; etc.
As shown in FIGS. 7C-7E, the third subsection of the syndrome table shows the syndrome code and positions for three-bit errors within the same byte. Thus, for example, a syndrome code having a hexadecimal value of E059 indicates a three-bit error in byte 0 at memory data bits 5, 6, and 7 (D050607); a syndrome code having a hexadecimal value of 0007 indicates a three-bit error in the check bits in byte 8 at positions CB0, CB1, and CB2; etc.
The next subsection of the syndrome table (FIG. 7F-7H) shows the syndrome code and positions for four-bit errors within the same byte. Thus, for example, the syndrome code having a hexadecimal value of F0B1 indicates a four-bit error in byte 0 at memory data bits 4, 5, 6, and 7 (D04050607); a hexadecimal value of 000F indicates a four-bit error in byte 8 at positions CB0, 1, 2, and 3.
The remaining subsections (FIGS. 7I-7L) of the syndrome table show the syndrome code and positions for five-bit errors within the same byte (FIGS. 7I-7K), six-bit errors within the same byte (FIG. 7L-7M), seven-bit errors within the same byte (FIG. 7N), and eight-bit errors within the same byte (FIG. 7N).
One advantage offered by the EDC logic is that the same number of check bits can be used to detect for address errors while also maintaining the ability to detect and correct multiple-bit errors in the data and check bits (up to 8 erroneous bits per byte). Any error in the address bits is indicated as an uncorrectable error. A further advantage offered by the EDC logic is that it can detect and correct a full range of memory data errors: from a single-bit error to a complete error of a byte (that is, all eight-bits of the byte are erroneous). When an error occurs, the CPU or system software can be notified of the error.
In addition, by reorganizing the memory data path, the EDC code described above can be used to detect and correct up to 16-bit errors in a word (16 bits of memory data), 32-bit errors in a double word (32 bits of memory data), and so forth. Applications where these are particularly advantageous include memory systems in which x16 and x32 DRAM devices are used. FIG. 8 is an exemplary memory system in which x16 DRAM devices are used, and FIG. 9 is an exemplary memory system in which x32 memory devices are used.
Referring to FIG. 8, a memory 402 includes ten x16 DRAM devices 404A-J connected to 160 data bits, of which 128 bits are memory data bits and 32 are memory check bits. The memory system 402 is connected to two EDC units 406A and 406B, which can be implemented in separate ASICs, as separate logical units in one ASIC, or as part of a memory controller. Each EDC unit implements the EDC code described in connection with FIGS. 5-7, and the two EDC units 406A and 406B in combination provide protection for 16 bits of data in any particular word.
To allow detection and correction of up to 16 bits of data in a given word using the ECC code of FIGS. 5-7, the memory 402 can be thought of as being divided into two halves, with half the data bits and check bits (64 data bits and 16 check bits) being provided to the EDC unit 406A, and the other half of the data bits and check bits connected to the EDC unit 406B.
When implemented with discrete x16 DRAM devices 404A-J, each x16 DRAM device is effectively divided in two halves, with a first byte going to the first EDC unit 406A, and the second byte going to the second EDC unit 406B. Thus, the first EDC unit 406A detects and corrects errors in the first byte of each of the DRAM devices 404A-J, and the second EDC unit 406B detects and corrects errors in the second byte of each of the DRAM devices 404A-J. The EDC unit 406A receives 16 of the check bits, and the EDC unit 406B receives the other 16 check bits.
Thus, the EDC unit 406A can detect and correct up to 8-bit errors in each of the 8 bytes of data it receives from the memory system 402, while simultaneously, the EDC unit 406B can detect and correct up to 8-bit errors in each of the other 8 bytes of data it receives from the memory 402. Effectively, this provides the capability to detect and correct up to 16 bits of data in any given word from the memory 402.
One advantage offered by the system shown in FIG. 8 is that the memory 402 can withstand a complete failure of one of the x16 DRAM devices 404 without loss of data or system failure. A further advantage is that the ability to detect and correct 16 bits of data in a given word can be accomplished using just 32 check bits to protect 128 total data bits.
In addition, the EDC units can also detect a single-bit or two-adjacent-bit errors in the address used to access the memory 402. The address bits ADDR[3:0] are ignored in the address parity check matrix.
Referring to FIG. 9, four EDC units 506A-D are used to detect and correct up to 32 bits of error in any given 32-bit wide (or double word) data. In the example of FIG. 9, a memory 502 (which is implemented with two x32 DRAM devices) is connected to 256 bits of data and 64 check bits. In this organization, each x32 DRAM device 504 is divided into four bytes, with each byte connected to a corresponding one of the EDC units 506A-D. Thus, the EDC unit 506A detects and corrects up to 8-bit errors in the first byte of data of each of the DRAM devices 504A-J, the second EDC unit 506B detects and corrects up to 8-bit errors in the second byte of each of the DRAM devices, and the EDC units 506C and 506D detect and correct up to 8-bit errors in the third and fourth bytes, respectively, of the DRAM devices.
Effectively, the EDC units 506A-D, each receiving 16 of the 64 total check bits, in combination can detect and correct up to 32 adjacent bits of data within a given double word while at the same time detecting for an address error. The address bits ADDR[4:0] are ignored in the address parity check matrix.
Other embodiments are within the scope of the following claims. For example, although the EDC logic has been described in a disk array controller, the same logic can be applied to any other computer memory subsystem. For example, the EDC logic can be implemented to protect data stored in main memory, video memory, cache memory, etc. In addition, although the EDC logic has been explained in conjunction with a PCI system, the same logic can be implemented with other types of buses, such as the Industry Standard Architecture (ISA) bus, the MCA bus, etc.
Further, as an alternative, the EDC logic can be modified to detect a single address pin failure on a memory device. To reduce the number of pins, DRAMs and SDRAMs receive multiplexed address signals; that is, the address is separated into a row address portion and column address portion received on the same set of pins at different times. For example, the memory controller 190 can generate row address signals RADDR[13:0] when a row address strobe (RAS.sub.--) is active and column address signals CADDR[13:0] when a column address strobe (CAS.sub.--) is active for receipt by the memory devices in the main memory 104. Thus, if a memory device has a defective input address pin, two address bits would be erroneous--one bit in the row address and one bit in the column address. If memory address pin o of a memory device is defective, for example, the row address bit RADDR[0] and column address bit CADDR[0] received in the memory device would both be erroneous.
To detect for the single address pin failure, the address parity check matrix of FIG. 5 is modified such that each row address bit and column address bit received by a DRAM or SDRAM device on the same pin is next to each other. Thus, for example, address signals corresponding to RADDR[0] and CADDR[0] would be placed in address positions 4 and 5 in the address parity check matrix; address signals corresponding to RADDR[1] and CADDR[1] would be placed in address positions 6 and 7; and so forth.
FIGS. 10 and 11 illustrate other exemplary memory systems in which the EDC logic can be used.
Referring to FIG. 10, a disk array controller for connection to multiple network systems is shown. The disk array controller includes PCI interface controllers 602 and 610 connected between a local PCI bus 618 and a second PCI bus 620. The second PCI bus 620 is connected to network interface controllers 606 and 608, which can be Fibre Channel controllers, which are in turn connected to Fibre Channel networks. In this configuration, the disk array controller is connected to receive disk requests from multiple networks.
Each of the PCI interface controllers 602 and 610 is associated with its own local memory 604 and 612, respectively. A local processor section 616 is also connected to the PCI bus 618. EDC logic (as described above) is implemented in each of the PCI interface controllers 610 and 604 to protect data retrieved from local memories 612 and 604, respectively.
Referring to FIG. 11, the EDC logic can also be implemented in a main memory 630 of a computer system. The main memory 630 includes individual chips, which can be DRAM or SDRAM devices. The memory chips are connected to a memory data bus, which are then provided to one or more data ASICs 632 (in which the EDC logic is implemented). The data ASICs 632 are in turn connected to the host bus 634, on which a CPU 636 is located. A CPU-PCI bridge 638 is connected between the host bus 634 and a PCI bus 640. A memory controller inside the CPU-PCI bridge 636 provides control and address signals to the main memory 630. As explained above, a single date ASIC or multiple data ASICs can be used, depending on the number of data bits to be protected as well as the type of ASIC being used. For example, in one configuration, the memory 630 is 80 bits wide (64 data bits and 16 check bits) and includes ten x8 memory devices. The x8 memory devices are connected to a single data ASIC that includes EDC logic to detect and correct 8-bit errors in any given byte. In another configuration, the memory 630 is 160 bits wide and contains ten x16 memory devices. The x16 memory devices can be connected to two data ASICs to enable detection and correction of up to 16-bit errors in any given word in a similar way as the organization shown in FIG. 8. In a third configuration, the memory 630 can be 320 bits wide, contain ten x32 memory devices, and connected to four data ASICs similar to the organization shown in FIG. 9. This EDC feature can be extended to other memory organizations.
Claims
What is claimed is:
1. A computer system, comprising: a CPU; a disk array system accessible by the CPU; and a disk array controller connected to the disk array system, the disk array controller including: a processor; a memory system coupled to the processor, the memory system connected to signal lines carrying data bits, address bits, and check bits; and an error detection and correction device connected to detect and correct multiple errors in the data bits using the check bits, and to detect an error in the address bits using the same check bits, the data bits being organized as multiple bytes, wherein the error detection and correction device is connected to detect and correct up to eight-bit errors in each byte, wherein the error detection and correction device is connected to detect a single-bit error or a two-adjacent-bit error in the address bits, and wherein the error detection and correction device can be configured to disable detecting an error in the address bits while enabling detecting and correcting the data bits.
2. The computer system of claim 1, wherein the memory system is connected to signal lines carrying 64 or fewer data bits and 16 check bits.
3. A computer system, comprising: a memory system connected to signal lines carrying data bits, address bits, and at least 16 check bits; and an error detection and correction device connected to detect and correct N-bit errors in the data bits using the check bits, and to detect an error in the address bits using the same check bits, N being greater than two, wherein the error detection and correction device can be configured to disable detecting an error in the address bits while enabling detecting and correcting the data bits.
4. The computer system of claim 3, wherein the data bits are organized as bytes, and the error detection and correction device is connected to detect and correct up to eight-bit errors in each byte.
5. The computer system of claim 3, wherein the error detection and correction device is connected to detect a single-bit error or a two-adjacent-bit error in the address bits.
6. The computer system of claim 3, wherein the memory system is connected to signal lines carrying 64 or fewer data bits and 16 check bits.
7. The computer system of claim 3, wherein the memory system is connected to signal lines carrying 32 or fewer address bits.
8. The computer system of claim 3, wherein the error detection and correction device generates a syndrome table that includes entries mapped to correctable or uncorrectable errors, and a detected address error is mapped to an uncorrectable error entry.
9. The computer system of claim 3, further comprising: a disk controller, the memory system being located in the disk controller.
10. The computer system of claim 9, further comprising: a disk system connected to the disk controller, wherein the memory system is used as a cache for data transferred to the disk system.
11. The computer system of claim 3, wherein the memory system includes a main memory of the computer system.
12. The computer system of claim 3, wherein the error detection and correction device includes: a decoder connected to receive the check bits, address bits, and data bits to generate an indication that a memory address or data error has occurred; and a correction circuit connected to correct the data bits if a correctable memory data error is present.
13. The computer system of claim 12, wherein the error detection and correction device further includes a partial address check bit generator to generate partial address check bits based on the memory address bits, and wherein the decoder is connected to further receive the partial address check bits to determine if a memory address or data error has occurred.
14. The computer system of claim 13, wherein the memory system is connected to single lines carrying 32 or fewer address bits, and wherein the partial address check bit generator generates 16 partial address check bits PCHK[15:0] according to the following address parity check matrix: <----------------- Address Bits -------------------> 11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901 ______________________________________ PCHK [F] xxx0 0000 0000 0000 0000 0000 0000 0000 PCHK [E] xxx0 0000 0000 0000 0000 0000 0000 0000 PCHK [D] xxx0 0000 0000 0000 0000 0000 0000 0000 PCHK [C] xxx0 0000 0000 0000 0000 0000 0000 0000 PCHK [B] xxx0 0000 0000 0000 0000 0000 0000 0000 PCHK [A] xxx0 0010 0011 1000 0011 1110 0000 1110 PCHK [9] xxx0 1100 1100 0110 1100 0001 1011 0001 PCHK [8] xxx0 0101 0101 0101 0101 0101 0101 0101 PCHK [7] xxx0 0000 0000 1100 0000 0010 1000 0010 PCHK [6] xxx0 0000 0000 1000 0000 0000 0000 0001 PCHK [5] xxx0 0010 1010 0000 0000 0011 0010 0100 PCHK [4] xxx0 1000 0110 0010 1000 0100 0001 0000 PCHK [3] xxx0 0000 0000 0000 1000 1000 0100 0010 PCHK [2] xxx0 0001 0000 0011 0001 0000 1000 1000 PCHK [1] xxx1 1000 0101 0001 0110 0000 0010 0000 PCHK [0] xxx1 0111 1100 0000 0010 1000 0100 1000 ______________________________________
15. The computer system of claim 14, wherein the memory system is connected to signal lines carrying 64 or fewer data bits and 16 check bits, wherein the decoder generates 16 syndrome bits, and wherein the 16 syndrome bits are generated according to the following data parity check matrix: <-----------------------------Data Bits -----------------------------> SYNDROME BIT[Y] 11 1111 1111 2222 2222 2233 3333 3333 4444 4444 0123 4567 8901 2345 6789 0123 4567 8901 2345 6789 0123 4567 __________________________________________________________________________ F 0000 0001 0000 0001 0000 0001 0000 0001 0000 0001 0000 0001 E 0000 0010 0000 0010 0000 0010 0000 0010 0000 0010 0000 0010 D 0000 0100 0000 0100 0000 0100 0000 0100 0000 0100 0000 0100 C 0000 1000 0000 1000 0000 1000 0000 1000 0000 1000 0000 1000 B 0001 0000 0001 0000 0001 0000 0001 0000 0001 0000 0001 0000 A 0010 0000 0010 0000 0010 0000 0010 0000 0010 0000 0010 0000 9 0100 0000 0100 0000 0100 0000 0100 0000 0100 0000 0100 0000 8 1000 0000 1000 0000 1000 0000 1000 0000 1000 0000 1000 0000 7 1000 1110 0100 0111 0010 0011 0001 0001 0000 1000 0000 0100 6 0001 1100 1000 1110 0100 0111 0010 0011 0001 0001 0000 0100 5 0011 1000 0001 1100 1000 1110 0100 0111 0010 0011 0001 0001 4 0111 0001 0011 1000 0001 1100 1000 1110 0100 0111 0010 0011 3 0110 1100 0011 0110 0001 1011 0000 1101 1000 0110 0100 0011 2 0101 0110 0010 1011 0001 0101 0000 1010 0000 0101 1000 0010 1 0010 0011 0001 0001 0000 1000 0000 0100 0000 0010 0000 0001 0 0100 0111 0010 0011 0001 0001 0000 1000 0000 0100 0000 0010 Btye 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 __________________________________________________________________________ <----- Data Bits -----> <------- Check Bits -------> 4455 5555 5555 6666 CCCC CCCC CCCC CCCC 8901 2345 6789 0123 0123 4567 89AB CDEF __________________________________________________________________________ F 0000 0001 0000 0001 0000 0000 0000 0001 PCHK [F] E 0000 0010 0000 0010 0000 0000 0000 0010 PCHK [E] D 0000 0100 0000 0100 0000 0000 0000 0100 PCHK [D] C 0000 1000 0000 1000 0000 0000 0000 1000 PCHK [C] B 0001 0000 0001 0000 0000 0000 0001 0000 PCHK [B] A 0010 0000 0010 0000 0000 0000 0010 0000 PCHK [A] 9 0100 0000 0100 0000 0000 0000 0100 0000 PCHK [9] 8 1000 0000 1000 0000 0000 0000 1000 0000 PCHK [8] 7 0000 0010 0000 0001 0000 0001 0000 0000 PCHK [7] 6 0000 0100 0000 0010 0000 0010 0000 0000 PCHK [6] 5 0000 1000 0000 0100 0000 0100 0000 0000 PCHK [5] 4 0001 0001 0000 1000 0000 1000 0000 0000 PCHK [4] 3 0010 0001 0001 0000 0001 0000 0000 0000 PCHK [3] 2 0100 0001 0010 0000 0010 0000 0000 0000 PCHK [2] 1 1000 0000 0100 0000 0100 0000 0000 0000 PCHK [1] 0 0000 0001 1000 0000 1000 0000 0000 0000 PCHK [0] Byte 6 Byte 7 Byte 8 Byte 9 __________________________________________________________________________
16. The computer system of claim 15, wherein the error detection and correction device performs the error detection and correction according to the following syndrome table, an entry in the syndrome table being selected by a hexadecimal value of the syndrome bits: Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Byte 8 Byte 9 __________________________________________________________________________ Syndrome code (Hex) and position for a single bit 8013 8087 80CD 80E8 8074 803A 801D 1010 0001 0100 D07 D15 D23 D31 D39 D47 D55 D63 CB 0 CB 8 4087 40CD 40E8 4074 403A 401D 4080 2020 0002 0200 D06 D14 D22 D30 D38 D46 D54 D62 CB 1 CB 9 20CD 20E8 2074 203A 201D 2080 2040 4040 0004 0400 D05 D13 D21 D29 D37 D45 D53 D61 CB 2 CB A 10E8 1074 103A 101D 1080 1040 1020 8080 0008 0B00 D04 D12 D20 D28 D36 D44 DS2 D60 CB 3 CB B 0874 083A 081D 0880 0840 0820 0810 0808 0010 1000 D03 D11 D19 D27 D35 D43 D51 D59 CB 4 CB C 043A 041D 0480 0440 0420 0410 0408 0404 0020 2000 D02 D10 D18 D26 D34 D42 D50 D58 CB 5 CB D 021D 0280 0240 0220 0210 0208 0204 0202 0040 4000 D01 D09 D17 D25 D33 D41 D49 D57 CB 6 CB E 0180 0140 0120 0110 0108 0104 0102 0101 00B0 8000 D00 D08 D16 D24 D32 D40 D4B D56 CB 7 CB F Syndrome code (Hex) and position for double-bit within the same byte C094 C04A C025 C09C C04E C027 C09D 3030 0003 0300 D0607 D1415 D2223 D3031 D3839 D4647 D5455 D6263 CB 01 CB 89 A0DE A06F A0B9 A0D2 A069 A0BA A05D 5050 0005 0500 D0507 D1315 D2123 D2931 D3739 D4547 D5355 D6163 CB 02 CB 8A 90FB 90F3 9QF7 90F5 90F4 907A 903D 9090 0009 0900 D0407 D1215 D2023 D2831 D3639 D4447 D5255 D6063 CB 03 CB 8B 8867 B8BD 88D0 8868 8834 881A 880D 1818 0011 1100 D0307 D1115 D1923 D2731 D3539 D4347 D5155 D5963 CB 04 CB 8C 8429 849A 844D 84A8 84B4 842A 8415 1414 0021 2100 D0207 D1015 D1823 D2631 D3439 b4247 D5055 D5863 CB 05 CB 8D 820E 8207 828D 82C8; 8264 8232 8219 1212 0041 4100 D0107 D0915 D1723 D2531 D3339 D4147 D4955 D5763 CB 06 CB 8E 8193 81C7 81ED 81F8 817C 813E 811F 1111 0081 8100 D0007 D0815 D1623 D2431 D3239 D4047 D4855 D5663 CB 07 CB 8F 604A 6025 609C 604E 6027 609D 60C0 6060 0006 0600 D0506 D1314 D2122 D2930 D3738 D4546 D5354 D6162 CB 12 CB 9A 506F 50B9 50D2 5069 50BA 505D 50A0 A0A0 000A 0A00 D0406 D121A D2022 D2830 D3638 D4446 D5254 D6062 CB 13 CB 9B 48F3 48F7 48F5 48F4 487A 483D 4890 2828 0012 1200 D0306 D1114 D1922 D2730 D3538 D4346 D5154 D5962 CB 14 CB 9C 44BD 44D0 4468 4434 441A 440D 4488 2424 0022 2200 D0206 D1014 D1822 D2630 D3438 D4246 D5054 D5862 CB 15 CB 9D 429A 424D 42A8 4254 422A 4215 4284 2222 0042 4200 D0106 D0914 D1722 D2530 D3338 D4146 D4954 D5762 CB 16 CB 9E 4107 418D 41C8 4164 4132 4119 4182 2121 0082 8200 D0006 D0814 D1622 D2430 D3238 D4046 D4854 D5662 CB 17 CB 9F 3025 309C 304E 3027 309D 30C0 3060 C0C0 000C 0C00 D0405 D1213 D2021 D2829 D3637 D4445 D5253 D6061 CB 23 CB AB 28B9 28D2 2869 28BA 285D 28A0 2850 4848 0014 1400 D0305 D1113 D1921 D2729 D3537 D4345 D5153 D5961 CB 24 CB AC 24F7 24F5 24F4 247A 243D 2490 2448 4444 0024 2400 D0205 D1013 D1821 D2629 D3437 D4245 D5053 D5861 CB 25 CB AD 22D0 2268 2234 221A 220D 2288 2244 4242 0044 4400 D0105 D0913 D1721 D2529 D3337 D4145 D4953 D5761 CB 26 CB AE 214D 21A8 2154 212A 2115 2184 2142 4141 0084 8400 D0005 D0813 D1621 D2429 D3237 D4045 D4853 D5661 CB 27 CB AF 189C 184E 1827 189D 18C0 1860 1830 8888 0018 1B00 D0304 D1112 D1920 D2728 D3536 D4344 D5152 D5960 CB 34 CB BC 14D2 1469 14BA 145D 14A0 1450 1428 8484 0028 2800 D0204 D1012 D1820 D2628 D3436 D4244 D5052 D5860 CB 35 CB BD 12F5 12F4 127A 123D 1290 1248 1224 8282 0048 4800 D0104 D0912 D1720 D2528 D3336 D4144 D4952 D5760 CB 36 CB BE 1168 1134 111A 110D 1188 1144 1122 8181 0088 8800 D0004 D0812 D1620 D2428 D3236 D4044 D4852 D5660 CB 37 CB BF 0C4E 0C27 0C9D 0CC0 0C60 0C30 0C18 0C0C 0030 3000 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 45 CB CD 0A69 0ABA 0A5D 0AA0 0A50 0A28 0A14 0A0A 0050 5000 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 46 CB CE 09F4 097A 093D 0990 0948 0924 0912 0909 0090 9000 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB 47 CB CF 0627 069D 06C0 0660 0630 0618 060C 0606 0060 60 00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 56 CB DE 05BA 055D 05A0 0550 0528 0514 050A 0505 00A0 A000 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 57 CB DF 039D 03C0 0360 0330 0318 030C 0306 0303 00C0 C000 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 67 CB EF Syndrome code and position for any combination of 3 bits within the same byte E059 E0A2 E051 E0A6 E053 E0A7 E0DD 7070 0007 0700 D0506 D1314 D2122 D29.30 D3738 D4546 D5354 D6162 CB 012 CB 89A 07 15 23 31 39 47 55 63 D01C D03E D01F D081 D0CE D067 D0BD B0B0 C00B CB00 D0406 D1214 D2022 D2830 D3638 D4446 D5254 D6062 CB 013 CB 89B 07 15 23 31 39 47 55 63 C8E0 C870 C838 C81C C80E C807 CB8D 3838 0013 1300 D0306 D1114 D1922 D2730 D3538 D4346 D5154 D5962 CB 014 CB 89C 07 15 23 31 39 47 55 63 C4AE C457 C4A5 C4DC C46E C437 C495 3434 0023 2300 D0206 D1014 D1822 D2630 D3438 D4246 D5054 D5862 CB 015 CB 89D 07 15 23 31 39 47 55 63 C289 C2CA C265 C2BC C25E C22F C299 3232 0043 4300 D0106 D0914 D1722 D2530 D3338 D4146 D4954 D5762 CB 016 CB 89E 07 15 23 31 39 47 55 63 C114 C10A C105 C18C C146 C123 C19F 3131 0083 8300 D0006 D0814 D1622 D2430 D3238 D4046 D4854 D5662 CB 017 CB 89F 07 15 23 31 39 47 55 63 B036 B01B B083 B0CF B0E9 B0FA B07D D0D0 000D 0D00 D0405 D1213 D2021 D2829 D3637 D4445 D5253 D6061 CB 023 CB 8AB 07 15 23 31 39 47 55 63 ABAA AB55 A8A4 AB52 AB29 A89A AB4D 5858 0015 1500 D0305 D1113 D1921 D2729 D3537 D4345 D5153 D5961 CB 024 CB 8AC 07 15 23 31 39 47 55 63 A4E4 A472 A439 A492 A449 A4AA A455 5454 0025 2500 D0205 D1013 D1821 D2629 D3437 D4245 D5053 D5861 CB 025 CB 8AD 07 15 23 31 39 47 55 63 A2C3 A2EF A2F9 A2F2 A279 A2B2 A259 5252 0045 4500 D0105 D0913 D1721 D2529 D3337 D4145 D4953 D5761 CB 026 CB 8AE 07 15 23 31 39 47 55 63 A15E A12F A199 A1C2 A161 A1BE A15F 5151 0085 8500 D0005 b0813 D1621 D2429 D3237 D4045 D4853 D5661 CB 027 CB 8AF 07 15 23 31 39 47 55 63 988F 98C9 98EA 9875 98B4 985A 982D 9898 0019 1900 D0304 D1112 D1920 D2728 D3536 D4344 D5152 D5960 CB 034 CB 8BC 07 15 23 31 39 47 55 63 94C1 94EE 9477 94B5 94D4 946A 9435 9494 C029 29C0 D0204 D1012 D1820 D2628 D3436 D4244 D5052 D5860 CB 035 CB 8BD 07 15 23 31 39 47 55 63 92E6 9273 92B7 92D5 92E4 9272 9239 9292 0049 4900 D0104 D0912 D1720 D2528 D3336 D4144 D4952 D5760 CB 036 CB 8BE 07 15 23 31 39 47 55 63 917B 913 91D7 91E5 91FC 917E 913F 9191 0089 5900 D0004 D0812 D1G20 D2428 D3236 D4044 D4B52 D5GG0 CB 037 CB 8BF 07 15 23 31 39 47 55 63 BC5D 8CA0 8C50 8C28 8C14 8C0A 8C05 1C1C 0031 3100 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 045 CB BCD 07 15 23 31 39 47 55 63 BA7A BA3D A90 8A48 8A24 8A12 8A09 1A1A 0051 5100 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 046 CB 8CE 07 15 23 31 39 47 55 63 89E7 89FD 89F0 8978 893C 891E 890F 1919 0091 9100 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB 047 CB 8CF 07 15 23 31 39 47 55 63 8634 861A 860D 8 88 8644 8622 8611 1E16 0061 6100 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 056 CB 8DE 07 15 23 31 39 47 55 63 85A9 65DA 856D 85BB 855C 852E 8517 1515 00A1 A100 D0002 D0510 D1G1B D2426 D3234 D4042 D4550 D5658 CB 057 CB 8DF 07 15 23 31 39 47 55 836E 8347 B3AD 83D8 836C 833 831B 1313 00C1 C100 D0001 D0609 D1617 D2425 D3233 D4041 D4849 D5657 CB 067 CB 8EF 07 15 23 31 39 47 55 63 70A2 7051 70A6 7053 70A7 70DD 70E0 E0E0 000E 0E00 D0405 D1213 D2021 D2829 D3637 D4445 D5253 D6061 CB 123 CB 9AB 06 14 22 30 38 46 54 62 683E 681F 6881 68CE 6867 68BD 68D0 6868 0016 1600 D0305 D1113 D1921 D2729 D3537 D4345 D5153 D5961 CB 124 CB 9AC 06 14 22 30 38 46 54 62 6470 6438 641C 640E 6407 648D 64C8 6464 0026 2600 D0205 D1013 D1821 D2629 D3437 D4245 D5053 D5BE1 CB 125 CB 9AD 06 14 22 30 38 46 54 62 6257 62A5 E2DC 626E 6237 6295 62C4 6262 0046 4600 D0105 D0913 D1721 D2529 D3337 D4145 D4953 D5761 CB 12E CB 9AE 06 14 22 30 38 46 54 62 61CA 6165 61BC 615E 612F 6199 61C2 6161 0086 8600 D0005 D0813 D1621 D2429 D3237 D4045 D4853 D5GG1 CB 127 CB 9AF 06 14 22 30 38 46 54 62 581B 5B83 58CF 58E9 58FA 587D 58B0 A8A8 001A 1A00 D0304 D1112 D1920 D2728 D3536 D4344 D5152 D5960 CB 134 CB 9BC 06 14 22 30 38 46 54 62 5455 54A4 5452 5429 549A 544D 54AB A4A4 002A 2A00 D0204 D1012 D1820 D2628 D3436 D4244 D5052 D5860 CB 135 CB 9BD 0G 14 22 30 38 46 54 62 5272 5239 5292 5249 52AA 5255 52A4 A2A2 004A 4A00 D0104 D0912 D1720 D2528 D3336 D4144 D4952 D5760 CB 136 CB 9BE 06 14 22 30 38 46 54 62 51EF 51F9 51F2 5179 51B2 5159 51A2 A1A1 008A 8A00 D0004 D0812 D1620 D2428 D3236 D4044 D4852 D5660 CB 137 CB 9BF 06 14 22 20 38 46 54 62 4CC9 4CEA 4C75 4CB4 4C5A 4C2D 4C98 2C2C 0032 3200 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 145 CB 9CD 06 14 22 30 38 46 54 62 4AEE 4A77 4AB5 4AD4 4A6A 4A35 4A94 2A2A 0052 5200 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 146 CB 9CE 06 14 22 30 38 46 54 62 4973 49B7 49D5 49E4 4972 4939 4992 2929 0092 9200 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB 147 CB 9CF 06 14 22 30 38 46 54 62 46A0 4650 4628 4614 460A 4605 468C 2626 0062 6200 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 156 CB 9DE 06 14 22 30 38 46 54 62 453D 4590 4548 4524 4512 4509 458A 2525 00A2 A200 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 157 CB 9DF 06 14 22 30 38 46 54 62 431A 430D 4388 4344 4322 4311 4386 2323 00C2 C200 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 167 CB 9EF 06 14 22 30 38 46 54 62 3851 38A6 3853 38A7 38DD 38E0 3870 C8C8 001C 1C00 D0304 D1112 D1920 D2728 D3536 D4344 D5152 D5960 CB 234 CB ABC 05 13 21 29 37 45 53 61 341F 3481 34CE 3467 34BD 34D0 3468 C4C4 002C 2C00 D0204 D1012 D1820 D2628 D3436 D4244 D5052 D5860 CB 235 CB ABD 05 13 21 29 37 45 53 61 3238 321C 320E 3207 328D 32C8 3264 C2C2 004C 4C00 D0104 D0912 D1720 D2528 D3336 D4144 D4952 D5760 CB 236 CB ABE 05 13 21 29 37 45 53 61 31A5 31DC 316E 3137 3195 31C4 3162 C1C1 008C 8C00 D000 D0812 D1620 D2428 D3236 D4044 D4852 D5660 CB 237 CB ABF 405 13 21 29 37 45 53 61 2C83 2CCF 2CE9 2CFA 2C7D 2CB0 2C58 4C4C 0034 3400 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 245 CB ACD 05 13 21 29 37 45 53 61 2AA4 2A52 2A29 2A9A 2A4D 2AA8 2A54 4A4A 0054 5400 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 246 CB ACE 05 13 21 29 37 45 53 61 2939 2992 2949 29AA 2955 29A4 2952 4949 0094 9400 D0003 D0811 D1619 D2427 D3235 D404 D4851 D5659 CB 247 CB ACF 05 13 21 29 37 45 53 61 26EA 2675 26B4 265A 262D 2698 264C 4646 0064 6400 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 256 CB ADE 05 13 21 29 37 45 53 61 2577 25B5 25D4 256A 2535 2594 254A 4545 00A4 A400 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 257 CB ADF 05 13 21 29 37 45 53 61 2350 2328 2314 230A 2305 238C 2346 4343 00C4 C400 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 267 CB AEF 05 13 21 29 37 45 53 61 1CA6 1C53 1CA7 1CDD 1CE0 1C70 1C38 8C8C 0038 3800 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 345 CB BCD 04 12 20 28 36 44 52 60 1A81 1ACE 1A67 1ABD 1AD0 1A68 1A34 8ABA 0058 5800 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 346 CB BCE 04 12 20 28 36 44 52 60 191C 190E 1907 198D 19C8 1964 1932 8989 0098 9800 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB 347 CB BCF 04 12 20 28 36 44 52 6C 16CF 16E9 16FA 167D 16B0 1658 162C 8686 0068 6800 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 356 CB BDE 04 12 20 28 36 44 52 60 1552 1529 159A 154D 15AB 1554 152A 8585 00A8 AB00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 357 CB BDF 04 12 20 28 36 44 52 60 1375 13B4 135A 132D 1398 134C 1326 8383 00C8 C800 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 367 CB BEF 04 12 20 28 36 44 52 60 0E53 0EA7 0EDD 0EE0 0E70 0E38 0E1C 0E0E 0070 7000 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 456 CB CDE 03 11 19 27 35 43 51 59 0DCE 0D67 0DBD CDDC 0D68 0D34 0D1A 0DCD 00B0 B000 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 457 CB CDF 03 11 19 27 35 43 51 59 0BE9 0BFA 0B7D 0BB0 0B58 0B2C 0B16 0B0B 0CD0 DC00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 467 CB CEF 03 11 19 27 35 43 51 59 07A7 07DD 07E0 0770 0738 071C 070E 0707 00E0 E000 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 567 CB DEF 02 10 18 26 34 42 50 58 Syndrome code and position for any combination of 4 bits within the same byte F0B1 F0D6 F06B F0BB F0D3 F0E7 F0FD F0F0 000F 0F00 D0405 D1213 D2021 D2829 D3637 D4445 D5253 D6061 CB 0123 CB 89AB 0607 1415 2223 3031 3839 4647 5455 6263 E82D E898 E84C E826 E813 E887 E8CD 7878 0017 1700 D0305 D1113 D1921 D2729 D3537 D4345 D5153 D5961 CB 0124 CB 89AC 0607 1415 2223 3031 3839 4647 5455 6263 E463 E4BF E4D1 E4E6 E473 E4B7 E4D5 7474 C027 2700 D0205 D1013 D1821 D2629 D3437 D4245 D5053 D5861 CB 0125 CB 89AD 0607 1415 2223 3031 3839 4647 5455 6263 E244 E222 E211 E286 E243 E2AF E2D9 7272 0047 4700 D0105 D0913 D1721 D2529 D3337 D4145 D4953 D5761 CB C126 CB 89AE 0607 1415 2223 3031 3839 4647 5455 6263 E1D9 E1E2 E171 E1B6 E15B E1A3 E1DF 7171 0087 8700 D0005 D0813 D1621 D2429 D3237 D4045 D4853 D5661 CB 0127 CB 89AF 0607 1415 2223 3031 3839 4647 5455 6263 D808 D804 D802 D801 D88E D847 D8AD B8B8 001B 1B00 DC3C4 D1112 D1920 D2728 D3536 D4344 D5152 D5960 CB 0134 CB B9BC 0607 1415 2223 3031 3839 4647 5455 6263 D446 D423 D49F D4C1 D4EE D477 D4B5 B4B4 002B 2B00 D0204 D1C12 D182C D2628 D3436 D4244 D5052 D5860 CB 0135 CB 89BD 0607 1415 2223 3031 3839 4647 5455 6263 D261 D2BE D25F D2A1 D2DE D26F D2B9 B2B2 004B 4B00 D0104 DC912 D1720 D2528 D3336 D4144 D4952 D5760 CB 0136 CB 89BE 0607 1415 2223 3C31 3839 4647 5455 6263 D1FC D17E D13F D191 D1C6 D163 D1BF B1B1 008B 8B00 D00C4 DC812 D1620 D2428 D3236 D4C44 D4852 D5660 CB C137 CB 89BF 0607 1415 2223 3031 3839 4647 5455 6263 CCDA CC6D CCB8 CC5C CC2E CC17 CC85 3C3C 0033 3300 D02C3 D1C11 D1819 D2627 D3435 D4243 D5C51 D5859 CB 0145 CB 89CD 0607 1415 2223 3031 3839 4647 5455 6263 CAFD CAF0 CA78 CA3C CA1E CA0F CA89 3A3A 0053 5300 D0103 D0911 D17192 D2527 D3335 D4143 D4951 D5759 CB 0146 CB 89CE 0607 1415 223 3031 3839 4647 5455 6263 C960 C930 C918 C900 C906 C903 C98F 3939 0093 9300 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB 0147 CB 89CF 0607 1415 2223 3031 3839 4647 5455 6263 C6B3 C6D7 C6E5 C6FC C67E C63F C691 3636 0063 6300 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 0156 CB 89DE 0607 1415 2223 3031 3839 4647 5455 6263 C52E C517 C585 C500 C566 C533 C597 3535 00A3 A300 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 0157 CB 89DF 0607 1415 2223 3031 3839 4647 5455 6263 C309 C38A C345 C3AC C356 C32B C39B 3333 00C3 C300 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB C167 CB 89EF 0607 1415 2223 3031 3839 4647 5455 6263 B842 B821 B89E B84F B8A9 B8DA B86D D8D8 001D 1D00 DC304 D1112 D1920 D2728 D3536 D4344 D5152 D5960 CB C234 CB 8ABC 0507 1315 2123 2931 3739 4547 5355 6163 B40C B406 B403 B48F B4C9 B4EA B475 D4D4 002D 2D00 D0204 D1012 D1820 D2628 D3436 D4244 D5C52 D5860 CB C235 CB 8ABD 0507 1315 2123 2931 3739 4547 5355 6163 B22B B29B B2C3 B2EF B2F9 B2F2 B279 D2D2 004D 4D00 D0104 D0912 D1720 D252B D3336 D4144 D4952 D5760 CB C236 CB BABE 0507 1315 2123 2931 3739 4547 5355 6163 B1B6 B15B B1A3 B1DF B1E1 B1FE B17F D1D1 008D 8D00 D0004 D0812 D1620 D2428 D3236 D4044 D4852 D5660 CB C237 CB 8ABF 0507 1315 2123 2931 3739 4547 5355 6163 AC90 AC48 AC24 AC12 AC09 AC8A AC45 5C5C 0035 3500 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 0245 CB 8ACD 0507 1315 2123 2931 3739 4547 5355 6163 AAB7 AAD5 AAE4 AA72 AA39 AA92 AA49 5A5A 0055 5500 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 0246 CB 8ACE 0507 1315 2123 2931 3739 4547 5355 6163 A92A A915 A984 A942 A921 A99E A94F 5959 0095 9500 D0003 D0B11 D1619 D2427 D3235 D4043 D4851 D5659 CB 0247 CB 8ACF 0507 1315 2123 2931 3739 4547 5355 6163 A6F9 A6F2 A679 A6B2 A659 A6A2 AG51 5656 0065 6500 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 0256 CB 8ADE 0507 1315 2123 2931 3739 4547 5355 1G3 A564 A532 A519 A582 A541 A5AE A557 5555 00A5 A500 D0002 D0810 D1616 D2426 D3234 D4042 D4850 D5658 CB 0257 CB 8ADF 0507 1315 2123 2931 3739 4547 5355 1G3 A343 A3AF A3D9 A3E2 A371 A3B6 A35B 5353 00C5 C500 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 0267 CB 8AEF 0507 1315 2123 2931 3739 4547 5355 6163 9CB5 9CD4 9C6A 9C35 9C94 9C4A 9C25 9C9C 0039 3900 D0203 D1011 D1619 D2627 D3435 D4243 D5051 D5B59 CB 0345 CB 8BCD 0407 1215 2023 2831 3639 4447 5255 6063 9A92 9A49 9AAA 9A55 9AA4 9A52 9A29 9A9A 0059 5900 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 0346 CB 8BCE 0407 1215 2023 2831 3639 4447 5255 6063 990F 9989 99CA 9965 99B0 995E 992F 9999 0099 9900 D0003 D0511 D1619 D2427 D3235 D4C43 D4851 D5659 CB 0347 CB 8BCF 0407 1215 2023 2831 3639 4447 5255 6063 9GDC 966E 9637 9695 96C4 9662 9631 9696 0069 6900 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 0356 CB BBDE 0407 1215 2023 2831 3639 4447 5255 6063 9541 95A 9557 95A5 95DC 956E 9537 9595 00A9 A900 D0002 D0B10 D161B D2426 D3234 D4042 D4850 D5656 CB 0357 CB 8BDF 0407 1215 2023 2831 3639 4447 5255 6063 9366 9333 9397 93C5 93EC 9376 933B 9393 00C9 C900 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 0367 CB 8BEF 0407 1215 2023 2B31 3639 4447 5255 6063 8E40 8E20 BE10 8E08 8E04 8E02 6E01 1E1E 0071 7100 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 045 CB BCDE 0307 1115 1923 2731 3539 4347 5155 5693 8DDD 8DE0 8D70 8D38 6D10 6D0E 8D07 1D1D 00B1 B100 D0002 D0810 D1618 D2426 D3234 D4042 D4850 DBG58 CB 0457 CB BCDF 0307 1115 1923 2731 3539 4347 5155 5963 8BFA 8B7D BBB0 8B58 8B20 6B16 BB0B 1B1B 00D1 D100 D0001 D0B09 D1617 D2425 D3233 D4041 D4849 D5657 CB 0467 CB 8CEF 0307 1115 1923 2731 3539 4347 5155 5963 87B4 875A 872D 8798 8740 B726 8713 1717 00E1 E100 D0001 D0B09 D1617 D2425 D3233 D4041 D4849 D5E57 CB 0567 CB 8DEF 0207 1015 1823 2631 3439 4247 5055 5863 78D6 786B 78BB 78D3 78E7 78FD 78F0 E8E8 001E 1E00 D0304 D1112 D1920 D2728 D3536 D4344 D5152 D5960 CB 1234 CB 9AB0 0506 1314 2122 2930 3738 4546 5354 6162 7498 7440 7426 7413 7487 74CD 74E8 E4E4 002E 2E00 D0204 D1012 D1820 D2628 D3436 D4244 D5052 D5860 CB 1235 CB 9ABD 0506 1314 2122 2930 3738 4546 5354 6162 72BF 72D1 72E6 7273 72B7 72D5 72E4 E2E2 004E 4E00 D0104 D0912 D1720 D2528 D3336 D4144 D4952 D5760 CB 1236 CB 9ABE 0506 1314 2122 2930 3738 4546 5354 6162 7122 7111 7186 7143 71AF 71D9 71E2 E1E1 008E 8E00 D0004 D0812 D1620 D2428 D3236 D4044 D4852 D5660 CB 1237 CB 9ABF 0506 1314 2122 2930 3738 4546 5354 6162 6C04 6C02 6C01 6C8E 6C47 6CAD 6CD8 6C6C 0036 3600 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 245 CB 9ACD 0506 1314 2122 2930 3738 4546 5354 6162 6A23 6A9F 6AC1 6AEE 6A77 6AB5 6AD4 6A6A 0056 5600 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 1246 CB 9ACE 0506 1314 2122 2930 3738 4546 5354 6162 69BE 695F 69A1 69DE 696F 69B9 69D2 6969 0096 9600 D0003 D0811 D1619 D2427 D3235 D404 D4851 D5659 CB 1247 CB 9ACF 0506 1314 2122 2930 3738 3546 5354 6162 666D 66B8 6650 662E 6617 6685 66CC 6666 0066 6600 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 1256 CB 9ADE 0506 1314 2122 2930 3738 4546 5354 6162 65F0 6578 653C 651E 650F 6589 65CA 6565 00A6 A600 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 1257 CB 9ADF 0506 1314 2122 2930 3738 4546 5354 6162 63D7 63E5 63F0 637E 633F 6391 63C6 6363 00C6 C600 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 1267 CB 9AEF 0506 1314 2122 2930 3738 4546 5354 6162 5C21 5C9E 5C4F 5CA9 5CDA 5C6D 5CB8 ACAC 003A 3A00 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 1345 CB 9BCD 0406 1214 2022 2830 3638 4446 5254 6062 5A06 EA03 5ABF 5AC9 5AEA 5A75 5AB4 AAAA 005A 5A00 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 1346 CB 9BCE 0406 1214 2022 2830 3638 4446 5254 6062 599B 59C3 59EF 59F9 59F2 5979 59B2 A9A9 009A 9A00 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB 1347 CB 9BCF 0406 1214 2022 2830 3638 4446 5254 6062 5648 5624 5612 5609 56EA 5645 56A0 A6A6 006A 6A00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 1356 CB 9BDE 0406 1214 2022 2830 3638 4446 5254 6062 55D5 55E4 5572 5539 5592 5549 55AA A5A5 00AA AA00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 1357 CB 9BDF 0406 1214 2022 2830 3638 4446 5254 6062 53F2 5379 53B2 5359 53A2 5351 53A6 A3A3 000A CA00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 1367 CB 9BEF 0406 1214 2022 2830 3638 4446 5254 6062 4ED4 4E6A 4E35 4E94 4E4A 4E25 4E90 2E2E 0072 7200 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 1456 CB 9CDE 0306 1114 1922 2730 3538 4346 5154 5962 4D49 4DAA 4D55 4DA4 4D52 4D29 4D9A 2D2D 00B2 B200 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 1457 CB 9CDF 0306 1114 1922 2730 3538 4346 5154 5962 4B6E 4B37 4B95 4BC4 4B62 4B31 4B96 2B2B 00D2 D200 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 1467 CB 9CE 0306 1114 1922 2730 3538 4346 5154 5962 4720 4710 4708 A704 4702 4701 478E 2727 00E2 E200 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 1567 CB 9DEF 0206 1014 1822 2630 3438 4246 5054 5862 3C6B 3CBB 3CD3 3CE7 3CFD 3CF0 3C78 CCCC 003C 3C00 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5B59 CB 2345 CB ABCD 0405 1213 2021 2629 3637 4445 5253 6061 3A4C 3A26 3A13 3A87 3ACD 3AE8 3A74 CACA 005C 5C00 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 2346 CB ABCE 0405 1213 2021 2829 3637 4445 5253 6061 39D1 39E6 3973 39B7 39D5 39E4 3972 C9C9 009C 9C00 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5G59 CB 2347 CB ABCF 0405 1213 2021 2829 3637 4445 5253 6061 3602 3601 368E 3647 36AD 36D8 3660 C6C6 006C 6C00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D575 CB 2356 CB ABDE 0405 1213 2021 2829 3637 4445 5253 6061 359F 35C1 35EE 3577 35B5 35D4 356A C5C5 00AC AC00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 2357 CB ABDF 0405 1213 2021 2829 3637 4445 5253 6061 33B8 3350 332E 3317 3385 3300 3366 C3C3 00CC CC00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5G57 CB 2367 CB ABEF 0405 1213 2021 2B29 3637 4445 5253 6061 2E9E 2E4F 2EA9 2EDA 2E6D 2EBB 2E50 4E4E 0074 7400 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5756 CB 2456 CB ACDE 0305 1113 1921 2729 3537 4345 5153 5961 2D03 2D8F 2DC9 2DEA 2D75 2DB4 2D5A 4D4D 00B4 B400 D0002 D0810 D1618 D2426 D2234 D4042 D4850 D5658 CB 2457 CB ACDF 0305 1113 1921 2729 3537 4345 5153 5961 2B24 2B12 2B09 2B5A 2B45 2BA0 2B56 4B4B 00D4 D400 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 2467 CB ACEF 0305 1113 1921 2729 3537 4345 5153 5961 276A 2735 2794 274A 2725 2790 274E 4747 00E4 E400 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 2567 CB ADEF 0205 1013 1821 2629 3437 4245 5053 5861 1EBB 1ED3 1EE7 1EFD 1EF0 1E78 1E3C 8E8E 0078 7600 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 3456 CB BCDE 0304 1112 1920 2726 3536 4344 5152 5960 1D26 1D13 1D67 1DCD 1DE8 1D74 1D3A BD8D 00B8 B800 D0002 D0610 D1618 D2426 D3234 D4042 D4850 D565B CB 3457 CB BCDF 0304 1112 1920 2728 3536 4344 5152 5960 1B01 1BBE 1B47 1BAD 1BD8 1BG0 1B36 BB8B 00D8 D800 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 3467 CB BCEF 0304 1112 1920 2728 3536 4344 5152 5960 174F 17A9 17DA 176D 17BB 1750 172E 8787 00E8 E800 D0001 D0609 D1617 D2425 D3233 D4041 D4849 D5657 CB 3567 CB BDEF 0204 1012 1820 2628 3436 A244 5052 5860 0FD3 CFE7 0FFD 0FF0 0F78 0F30 0F1E 0F0F 00F0 F000 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 4567 CB CDEF 0203 1011 1819 2627 3435 4243 5051 5859 Syndrome code and position for any combination of 5 bits within the same byte F8C5 F8CE F876 F83B F893 F8C7 F8ED F8F8 001F 1F00 D03C4 D1112 D1920 D2728 D3536 D4344 D5152 D5960 CB 01234 CB 89ABC 050607 131415 212223 293031 373839 454647 535455 616263 F48B F4CB F4EB F4FB F4F3 F4F7 F4F5 F4F4 002F 2F00 D0204 D1C12 D1820 D2628 D3436 D4244 D5052 D5860 CB 01235 CB 89ABD 050607 131415 212223 293031 373839 454647 535455 616263 F2AC F256 F22B F29B F2C3 F2EF F2F9 F2F2 004F 4F00 D0104 D0912 D1720 D2528 D3336 D4144 D4952 D5760 CB 01236 CB 89ABE 050607 131415 212223 293031 373839 454647 535455 616263 F131 F196 F14B F1AB F1DB F1E3 F1FF F1F1 008F 8F00 D0004 D0812 D1620 D2428 D3236 D4044 D4852 D5660 CB 01237 CB 89ABF 050607 131415 212223 293031 373839 454647 535455 616263 EC17 EC85 E000 EC66 EC33 EC97 E005 7C7C 0037 3700 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 01245 CB 89ACD 050607 131415 212223 293031 373839 454647 535455 616263 EA30 EA18 EA00 EA06 EA03 EA8F EAC9 7A7A 0057 5700 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 01246 CB 89ACE 050607 131415 212223 293031 373839 454647 535455 616263 E9AD E9D8 E960 E936 E91B E983 E9CF 7979 0097 9700 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB 01247 CB 89ACF 050607 131415 212223 293031 373839 454647 535455 616263 E67E E63F E691 E6C6 E663 E6BF E6D1 7676 0067 6700 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 01256 CB 89ADE 050667 131415 212223 293031 373839 454647 535455 616263 E5E3 E5FF E5F1 E5F6 E57B E5B3 E5D7 7575 00A7 A700 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 01257 CB 89ABF 050607 131415 212223 293031 373839 454647 535455 616263 E3C4 E362 E331 E396 E34B E3AB E3DB 7373 00C7 C700 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 01267 CB 89AEF 050607 131415 212223 293031 373839 454647 535455 616263 DC32 DC19 DC82 DC41 DCAE DC57 DCA5 BCBC 003B 3B00 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 01345 CB 89BCD 040607 121415 202223 283031 363839 444647 525455 606263 DA15 DA84 DA42 DA21 DA9E DA4F DAA9 BABA 005B 5B00 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 01346 CB 89BCE 040607 121415 202223 283031 363839 444647 525455 606263 D988 D944 D922 D911 D986 D943 D9AF B9B9 009B 9B00 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB 01347 CB 89BCF 040607 121415 202223 283031 363839 444647 525455 606263 D65B D6A3 D6DF D6E1 D6FE D67F D6B1 B6B6 006B 6B00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 01356 CB 89BDE 040607 121415 202223 283031 363839 444647 525455 606263 D5C6 D563 D5BF D5D1 D5E6 D573 D5B7 B5B5 00AB AB00 D0002 DC810 D1618 D2426 D3234 D4042 D4850 D5658 CB C1357 CB 89BDF 040607 121415 202223 283031 363839 444647 525455 606263 D3E1 D3FE D37F D3B1 D3D6 D36B D3BB B3B3 00CB CB00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB C1367 CB 89BEF 040607 121415 202223 283031 363839 444647 525455 606263 CEC7 CEED CEF8 CE70 CE3E CE1F CE81 3E3E 0073 7300 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB C1456 CB 89CDE 030607 111415 192223 273031 353839 434647 515455 596263 CD5A CD2D CD98 CD40 CD26 CD13 CD87 3D3D 00B3 B300 D0002 D0810 D1618 D2426 D3234 D4C42 D4850 D5658 CB 01457 CB 89CDF 030607 111415 192223 273031 353839 434647 515455 596263 CB7D CBB0 CB58 CB20 CB16 CBCB CB8B 3B3B 00D3 D300 D0001 D0809 D1617 D2425 D3233 D4C41 D4849 D5657 CB 01467 CB 89CEF 030607 111415 192223 273031 35383 434647 515455 596263 C733 C797 C7C5 C7E0 C776 C73B C793 3737 00E3 E300 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 01567 CB 89DEF 020607 101415 182223 263031 343839 424647 505455 586263 BC78 BC3C BC1E BC0F BC89 BCCA BC65 DCDC 003D 3D00 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB C2345 CB 8ABCD 040507 121315 202123 282931 363739 444547 525355 606163 BA5F BAA1 BADE BA6F BAB9 BAD2 BA69 DADA 005D 5D00 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 02346 CB 8ABCE 040507 121315 202123 282931 363739 444547 525355 606163 B9C2 B961 B9BE B95F B9A1 B9DE B96F D9D9 009D 9D00 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB C2347 CB BABCF 040507 121315 202123 282931 363739 444547 525355 606163 B611 B686 B643 B6AF B6D9 B6E2 B671 D6D6 006D 6D00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB C2356 CB 8ABDE 040507 121315 202123 282931 363739 444547 525355 606163 B58C B546 B523 B59F B5C1 B5EE B577 D5D5 00AD AD00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 02357 CB 8ABDF 040507 121315 202123 282931 363739 444547 525355 606163 B3AB B3DB B3E3 B3FF B3F1 B3F6 B37B D3D3 00CD CD00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB C2367 CB 8ABEF 040507 121315 202123 282931 444547 525355 606163 AE8D AEC8 AE64 AE32 AE19 AE82 AE41 5E5E 0075 7500 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB C2456 CB 8ACDE 030507 111315 192123 272931 353739 434547 515355 596163 AD10 ADC8 ADC4 ADC2 AD01 AD8E AD47 5D5D 00B5 B500 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB C2457 CB 8ACDF 030507 111315 192123 272931 353739 434547 515355 596163 AB37 AB95 ABC4 AB62 AB31 AB96 AB4B 5B5B 00D5 D500 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB C2467 CB 8ACEF 030507 111315 192123 272931 353739 434547 515355 596163 A779 A7B2 A759 A7A2 A751 A7A6 A753 5757 00E5 E500 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB C2567 CB 8ADEF 020507 101315 182123 262931 343739 424547 5C5355 586163 9EA8 9E54 9E2A 9E15 9E84 9E42 9E21 9E9E 0079 7900 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 03456 CB 8BCDE 030407 111215 192023 272831 353639 434447 515255 596063 9D35 9D94 9D4A 9D25 9D9C 9D4E 9D27 9D9D 00B9 B900 D0002 D0B10 D1618 D2426 D3234 D4042 D4850 D5658 CB 03457 CB 8BCDF 030407 111215 192023 272831 353639 434447 515255 596063 9B12 9B09 9B8A 9B45 9BAC 9B56 9B2B 9B9B 00D9 D900 D0001 D0809 D1617 D2425 D3233 D4C41 D4849 D5657 CB C3467 CB 8BCEF 030407 111215 192023 272631 353639 434447 515255 596063 975C 972E 9717 9785 97CC 9766 9733 9797 00E9 E900 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB C3567 CB 8BDEF 020407 101215 182023 262631 343639 424447 505255 586063 8FC0 8F60 8F30 8F18 8F0C 8FC6 8F03 1F1F 00F1 F100 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB C4567 CB 8CDEF 020307 101115 181923 262731 343539 424347 505155 585963 7CEC 7C76 7C3B 7C93 7CC7 7CED 7CF8 ECEC 003E 3E00 D0203 D1011 D1819 D2627 D3435 D4243 D5051 D5859 CB 12345 CB 9ABCD 040506 121314 202122 282930 363738 444546 525354 606162 7ACB 7AEB 7AFB 7AF3 7AF7 7AF5 7AF4 EAEA 005E 5E00 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB 12346 CB 9ABCE 040506 121314 202122 282930 363738 444546 525354 606162 7956 792B 799B 79C3 79EF 79F9 79F2 E9E9 009E 9E00 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB 12347 CB 9ABCF 040506 121314 202122 282930 363738 444546 525354 606162 7685 76CC 7666 7633 7697 76C5 76EC E6E6 006E 6E00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 12356 CB 9ABDE 040506 121314 202122 282930 363738 444546 525354 606162 7518 750C 7506 7503 758F 75C9 75EA E5E5 00AE AE00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 12357 CB 9ABDF 040506 121314 202122 282930 363738 444546 525354 606162 733F 7391 73C6 7363 73BF 73D1 73E6 E3E3 00CE CE00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 12367 CB 9ABEF 040506 121314 202122 282930 363738 444546 525354 606162 6E19 6E82 6E41 6EAE 6E57 6EA5 6EDC 6E6E 0076 7600 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 12456 CB 9ACDE 030506 111314 192122 272930 353738 434546 515354 596162 6D84 6D42 6D21 6D9E 6D4F 6DA9 6DDA 6D6D 00B6 B600 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 12457 CB 9ACDF 030506 111314 192122 272930 353738 434546 515354 596162 6BA3 6BDF 6BE1 6BFE 6B7F 6BB1 6BD6 6B6B 00D6 D600 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 12467 CB 9ACEF 030506 111314 192122 272930 353738 434546 515354 596162 67ED 67F6 677C 673E 671F 6761 67CE 6767 00E6 E600 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 12567 CB 9ADEF 020506 101314 182122 262930 343738 424546 505354 586162 5E3C 5E1E 5ECF 5E89 5ECA 5EE5 5EBC AEAE 007A 7A00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 13456 CB 9BCDE 030406 111214 192022 272830 353638 434446 515254 596062 5DA1 5DDE 5D6F 5DB9 5DD2 5D69 5DBA ADAD 00BA BA00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 13457 CB 9BCDF 030406 111214 192022 272830 353638 434446 515254 596062 5B86 5B43 5BAF 5BD9 5BE2 5B71 5BB6 ABAB 00DA DA00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 13467 CB 9BCEF 030406 111214 192022 272830 353638 434446 515254 596062 57C8 5764 5732 5719 5782 5741 57AE A7A7 00EA EA00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 13567 CB 9BDEF 020406 101214 182022 262830 343638 424446 505254 586062 4F54 4F2A 4F15 4F84 4F42 4F21 4F9E 2F2F 00F2 F200 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 14567 CB 9CDEF 020306 101114 181922 262730 343538 424346 505154 585962 3E76 3E3B 3E93 3EC7 3EED 3EF8 3E7C CECE 007C 7C00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 23456 CB ABCDE 030405 111213 192021 272829 353637 434445 515253 596061 3DEB 3DFB 3DF3 3DF7 3DF5 3DF4 3D7A CDCD 00BC BC00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D565B CB 23457 CB ABCDF 030405 111213 192021 272829 353637 434445 515253 596061 3BCC 3B66 3B33 3B97 3BC5 3BEC 3B76 CBCB 00DC DC00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 23467 CB ABCEF 030405 111213 192021 272829 353637 434445 515253 596061 3782 3741 37AE 3757 37A5 37DC 376E C7C7 00EC EC00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 23567 CB ABDEF 020405 101213 182021 262829 343637 424445 505253 586061 2F1E 2FCF 2F89 2FCA 2F65 2FB0 2F5E 4F4F 00F4 F400 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 24567 CB ACDEF 020305 101113 181921 262729 343537 424345 505153 585961 1F3B 1F93 1FC7 1FED 1FF8 1F7C 1F3E 8F8F 00F8 F800 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 34567 CB BCDEF 020304 101112 181920 262728 343536 424344 505152 585960 Syndrome code and position for any combination of 6 bits within the same byte FCFF FCF1 FCF6 FC7B FCB3 FCD7 FCE5 FCFC 003F 3F00 D0203 D1011 D1819 D2627 D34353 D4243 D5051 D5859 CB C12345 CB 89ABCD 0405 1213 2021 2829 637 4445 5253 6061 0607 1415 2223 3031 3839 4647 5455 6263 FAD8 FA6C FA36 FA1B FA83 FACF FAE9 FAFA 005F 5F00 D0103 D0911 D1719 D2527 D3335 D4143 D4951 D5759 CB C12346 CB 89ABCE 0405 1213 2021 2829 3637 4445 5253 6061 0607 1415 2223 3031 3839 4647 5455 6263 F945 F9AC F956 F92B F99B F9C3 F9EF F9F9 009F 9F00 D0003 D0811 D1619 D2427 D3235 D4043 D4851 D5659 CB C12347 CB 89ABCF 0405 1213 2021 2829 3637 4445 5253 6061 0607 1415 2223 3031 3839 4647 5455 6263 F696 F64B F6AB F6DB F6E3 F6FF F6F1 F6F6 006F 6F00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB C12356 CB 89ABDE 0405 1213 2021 2829 3637 4445 5253 6061 0607 1415 2223 3031 3839 4647 5455 6263 F50B F58B F5CB F5EB F5FB F5F3 F5F7 F5F5 00AF AF00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 012357 CB 89ABDF 0405 1213 2021 2829 3637 4445 5253 6061 0607 1415 2223 3031 3839 4647 5455 6263 F32C F316 F30B F38B F3CB F3EB F3FB F3F3 00CF CF00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 012367 CB 89ABEF 0405 1213 2021 2829 3637 4445 5253 6061 0607 1415 2223 3031 3839 4647 5455 6263 EE0A EE05 EE8C EE46 EE23 EE9F EEC1 7E7E 0077 7700 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 012456 CB 89ACDE 03050 1113 1921 2729 3537 4345 5153 5961 0607 1415 2223 3031 3839 4647 5455 6263 ED97 EDC5 EDE0 ED76 ED3B ED93 EDC7 7D7D 00B7 B700 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 012457 CB 89ACDF 0305 1113 1921 2729 3537 4345 5153 5961 0607 1415 2223 3031 3839 4647 5455 6263 EBB0 EB58 EB2C EB16 EB0B EB8B EBCB 7B7B 00D7 D700 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 012467 CB 89ACEF 0305 1113 1921 2729 3537 4345 5153 5961 0607 1415 2223 3031 3839 4647 5455 6263 E7FE E77F E7B1 E7D6 E76B E7BB E7D3 7777 00E7 E700 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 012567 CB 89ADEF 0205 1013 1821 2629 3437 4245 5053 5861 0607 1415 2223 3031 3839 4647 5455 6263 DE2F DE99 DEC2 DE61 DEBE DE5F DEA1 BEBE 007B 7B00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 013456 CB 89BCDE 0304 1112 1920 2728 3536 4344 5152 5960 0607 1415 2223 3031 3839 4647 5455 6263 DDB2 DD59 DDA2 DD51 DDA6 DD53 DDA7 BDBD 00BB BB00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 013457 CB 89BCDF 0304 1112 1920 2728 3536 4344 5152 5960 0607 1415 2223 3031 3839 4647 5455 6263 DB95 DBC4 DB62 DB31 DB96 DB4B DBAB BBBB 00DB DB00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 013467 CB 89BCEF 0304 1112 1920 2728 3536 4344 5152 5960 0607 1415 2223 3031 3839 4647 5455 6263 D7DB D7E3 D7FF D7F1 D7F6 D77B D7B3 B7B7 00EB EB00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 013567 CB 89BDEF 0204 1012 1820 2628 3436 4244 5052 5860 0607 1415 2223 3031 3839 4647 5455 6263 CF47 CFAD CFD8 CF6C CF36 CF1B CF83 3F3F 00F3 F300 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5651 CB 014567 CB 89CDEF 0203 1011 1819 2627 3435 4243 5051 5859 0607 1415 2223 3031 3839 4647 5455 6263 BE65 BEB0 BE5E BE2F BE99 BEC2 BE61 DEDE 007D 7D00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 023456 CB 8ABCDE 0304 1112 1920 2728 3536 4344 5152 5960 0507 1315 2123 2931 3739 4547 5355 6163 Syndrome code and position for any combination of 7 adjacent bits within the same byte FEE2 FE71 FEB6 FE5B FEA3 FEDF FEE1 FEFE 007F 7F00 D0102 D0910 D1716 D2526 D3334 D4142 D4950 D5756 CB 0123456 CBB9ABCDE 030405 111213 192021 272829 353637 434445 515253 596061 0607 1415 2223 3031 3639 4647 5455 6263 FD7F FDB1 FDD6 FD6B FDBB FDD3 FDE7 FDFD 00BF DF00 D0002 D0610 D1616 D2426 D3234 D4042 D4850 D5657 CB 0123457 CB B9ABCDF 030405 111213 192021 272629 353637 434445 515253 585960 0607 1415 2223 3031 3839 4647 5455 616263 FB58 FB2C FB16 FB0B FB6B FBCB FBEB FBFB 00DF DF00 D0001 D0609 D1617 D2425 D3233 D4041 D4649 D5658 CB 0123467 CB B9ABCEF 030405 111213 192021 272629 353637 434445 515253 596061 0607 1415 2223 3031 3639 4647 5455 6263 F716 F70B F7BB F7CB F7EB F7FB F7F3 F7F7 00EF EF00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 0123567 CB B9ABDEF 0204 101213 162021 262629 343637 424445 505253 5B6061 050607 1415 2223 3031 3639 4647 5455 6263 EFBA EF45 EFAC EF56 EF2B EF9B EFC3 7F7F 00F7 F700 D0001 D0B09 D1617 D2425 D3233 D4041 D4B49 D5657 CB 0124567 CB B9ACDEF 020305 101113 181921 262729 343537 424345 505153 565961 0607 1415 2223 3031 3839 4647 5455 6263 DFAF DFD9 DFE2 DF71 DFB6 DF5B DFA3 BFBF 00FB FB00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 0134567 CB 89BCDEF 020304 101112 181920 262728 343536 424344 505152 555960 0607 1415 2223 3031 3639 4647 5455 6263 BFE5 BFF0 BF7E BF3F BF91 BFC6 BF63 DFDF 00FD FD00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 0234567 CB 8ABCDEF 020304 101112 161920 262726 343536 424344 505152 565960 0507 1315 2123 2931 3739 4547 5355 6163 7F71 7FB6 7F5B 7FA3 7FDF 7FE1 7FFE EFEF 00FE FE00 D0001 D0609 D1617 D2425 D3233 D4041 D4849 D5657 CB 1234567 CB 9ABCDEF 020304 101112 181920 262728 343536 424344 505152 585960 0506 1314 2122 2930 3738 4546 5354 6162 Syndrome code and position for 8 adj bit FF00 CB 89ABCDEF FF31 D0809101112131415 FF4B D2425262728293031 FF62 D0001020304050607 FF96 D1617181920212223 BDF8 BD7C BD3E BD1F BD81 BDCE BD67 DDDD 00BD BD00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 023457 CB 8ABCbF 0304 1112 1920 2728 3536 4344 5152 5960 0507 1315 2123 2931 3739 4547 5355 6163 BBDF BBE1 BBFE BB7F BBB1 BBD6 BB6B DBDB 00DD DD00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 023467 CB 8ABCEF 0304 1112 1920 2728 3536 4344 5152 5960 0507 1315 2123 2931 3739 4547 5355 6163 B791 B7C6 B763 B7BF B7D1 B7E6 B773 D7D7 00ED ED00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 023567 CB 8ABDEF 0204 1012 1820 2628 3436 4244 5052 5860 0507 1315 2123 2931 3739 4547 5355 6163 AF0D AF88 AF44 AF22 AF11 AF86 AF43 5F5F 00F5 F500 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 024567 CB 8ACDEF 0203 1011 1819 2627 3435 4243 5051 5859 0507 1315 2123 2931 3739 4547 5355 6163 9F28 9F14 9F0A 9F05 9F80 9F46 9F23 9F9F 00F9 F900 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 034567 CB 8BCDEF 0203 1011 1819 2627 3435 4243 5051 5859 0407 1215 2023 2831 3639 4447 5255 6063 7EF1 7EF6 7E7B 7EB3 7ED7 7EE5 7EFC EEEE 007E 7E00 D0102 D0910 D1718 D2526 D3334 D4142 D4950 D5758 CB 123456 CB 9ABCDE 0304 1112 1920 2728 3536 4344 5152 5960 0506 1314 2122 2930 3738 4546 5354 6162 7D6C 7D36 7D1B 7D83 7DCF 7DE9 7DFA EDED 00BE BE00 D0002 D0810 D1618 D2426 D3234 D4042 D4850 D5658 CB 123457 CB 9ABCDF 0304 1112 1920 2728 3536 4344 5152 5960 0506 1314 2122 2930 3738 4546 5354 6162 7B4B 7BAB 7BDB 7BE3 7BFF 7BF1 7BF6 EBEB 00DE DE00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 123467 CB 9ABCEF 0304 1112 1920 2728 3536 4344 5152 5960 0506 1314 2122 2930 3738 4546 5354 6162 7705 7780 7746 7723 779F 77C1 77EE E7E7 00EE EE00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 123567 CB 9ABDEF 0204 1012 1820 2628 3436 4244 5052 5860 0506 1314 2122 2930 3738 4546 5354 6162 6F99 6FC2 6F61 6FBE 6F5F 6FA1 6FDE 6F6F 00F6 F600 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 124567 CB 9ACDEF 0203 1011 1819 2627 3435 4243 5051 5859 0506 1314 2122 2930 3738 4546 5354 6162 5FBC 5F5E 5F2F 5F99 5FC2 5F61 5FBE AFAF 00FA FA00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 134567 CB 9BCDEF 0203 1011 1819 2627 3435 4243 5051 5859 0406 1214 2022 2830 3638 4446 5254 6062 3FF6 3F7B 3FB3 3FD7 3FE5 3FF0 3F7E CFCF 00FC FC00 D0001 D0809 D1617 D2425 D3233 D4041 D4849 D5657 CB 234567 CB ABCDEF 0203 1011 1819 2627 3435 4243 5051 5859 0405 1213 2021 2829 3637 4445 5253 6061 __________________________________________________________________________
17. The computer system of claim 3, wherein the memory system includes a memory device having address pins to receive the address bits, and wherein the error detection and correction device can detect failure of the address pin.
18. The computer system of claim 17, wherein the memory device receives the address bits in a multiplexed manner.
19. The computer system of claim 18, wherein the memory device receives the address bits as a row address and a column address at different times.
20. A computer system, comprising: a processor; a memory system coupled to the processor, the memory system connected to signal lines carrying 64 or fewer data bits and 16 check bits; an error detection and correction device connected to detect and correct up to eight-bit errors in the data bits using the check bits, and to detect a single-bit error or two-adjacent-bit error in the address bits using the same check bits, wherein the error detection and correction device generates a syndrome table that includes entries mapped to correctable or uncorrectable errors, and a detected address error is mapped to an uncorrectable error entry, and wherein the error detection and correction device can be configured to disable detecting an error in the address bits while enabling detecting and correcting the data bits.
21. A method of detecting and correcting errors in a memory system having address bits, the memory system storing data bits and at least 16 check bits, the method comprising: configuring address bit error detection; receiving the data bits, address bits, and check bits; detecting an error in the address bits using the check bits if the address bit error detection is enabled; and detecting and correcting N-bit errors in the data bits using the same check bits, N being greater than two.
22. The method of claim 21, wherein the data bits are organized as bytes, and the data error detecting and correcting step can detect and correct up to eight-bit errors in each byte.
23. The method of claim 21, wherein the address error detecting step can detect a single-bit error or a two-adjacent-bit error in the address bits.
24. The method of claim 21, wherein the memory system stores 64 or fewer data bits and 16 check bits.
25. The method of claim 21, wherein the memory system stores 32 or fewer address bits.
26. The method of claim 21, wherein the address error detecting step and data error detecting and correcting step generate a syndrome table that includes a plurality of entries mapped to correctable or uncorrectable errors, and wherein a detected address error is mapped to an uncorrectable error entry.
27. The method of claim 21, wherein the address error detecting step includes generating partial address check bits based on the memory address bits, and receiving the partial address check bits to determine if a memory address or data error has occurred.
28. A disk controller, comprising: a memory system connected to signal lines carrying data bits, address bits, and at least 16 check bits; and an error detection and correction device connected to detect and correct N-bit errors in the data bits using the check bits, and to detect an error in the address bits using the same check bits, N being greater than two, wherein the error detection and correction device can be configured to disable detecting an error in the address bits while enabling detecting and correcting the data bits.
29. The disk controller of claim 28, wherein the data bits are organized as bytes, and the error detection and correction device is connected to detect and correct up to eight-bit errors in each byte.
30. The disk controller of claim 28, wherein the error detection and correction device is connected to detect a single-bit error or a two-adjacent-bit error in the address bits.
31. The disk controller of claim 28, wherein the memory system is connected to signal lines carrying 64 or fewer data bits and 16 check bits.
32. The disk controller of claim 28, wherein the memory system is connected to signal lines carrying 32 or fewer address bits.
33. The disk controller of claim 28, wherein the memory system is used as a cache for data transferred to a disk system connected to the disk controller.
34. The disk controller of claim 28, wherein the memory system includes a memory device having address pins to receive the address bits, and wherein the error detection and correction device can detect failure of the address pin.
35. The disk controller of claim 34, wherein the memory device receives the address bits in a multiplexed manner.
36. The disk controller of claim 35, wherein the memory device receives the address bits as a row address and a column address at different times.
37. A computer system, comprising: a memory connected to signal lines carrying address bits, 128 or fewer data bits and 32 check bits; and an error detection and correction device connected to detcct and correct up to 16-bit errors in the data bits using the check bits, wherein the error detection and correction device is further connected to detect an address error using the same check bits, and wherein the error detection and correction device can be configured to disable detecting an error in the address bits while enabling detecting and correcting the data bits.
38. The computer system of claim 37, the data bits being organized as words, the error detection and correction device capable of detecting and correcting up to 16-bit errors in any particular word.
39. A computer system, comprising: a memory connected to signal lines carrying address data bits and 64 check bits; and an error detection and correction device connected to detect and correct up to N-bit errors in the data bits, N being greater than or equal to 32, wherein the error detection and correction device is further connected to detect an address error using the same check bits, and wherein the error detection and correction device can be configured to disable detecting an error in the address bits while enabling detecting and correcting the data bits.
40. The computer system of claim 39, wherein the memory is connected to 256 or fewer data bits.
41. The computer system of claim 39, wherein the data bits are organized as double words, and wherein the error and detection device is capable of detecting and correcting up to 32-bit errors in any particular double word.
42. A computer system, comprising: a memory connected to signal lines carrying address bits, M data bits and N check bits, the ratio of M to N being four, N being greater than or equal to 32; and an error detection and correction device connected to detect and correct up to N/2-bit errors in the M data bits using the check bits, wherein the error detection and correction device is further connected to detect an error in the address bits, and wherein the error detection and correction device can be configured to disable detecting an error in the address bits while enabling detecting and correctino the data bits.
43. The computer system of claim 42, wherein M is 128 and N is 32.
44. The computer system of claim 42, wherein M is 256 and N is 64.
45. A method of detecting and correcting errors in a memory having address bits, the memory storing M data bits and N check bits, the method comprising: configuring address bit error detection; receiving the address bits, M data bits and N check bits, the ratio of M to N being four, and N being greater than or equal to 32; detecting an error in the address bits using the check bits if the address bit error detection is enabled; and detecting and correcting up to N/2-bit errors in the data bits using the check bits.
46. The method of claim 45, wherein M is 128 and N is 32.
47. The method of claim 45, wherein M is 256 and N is 64.
48. A method of detecting and correcting errors in a memory having address bits, the memory storing data bits and check bits, the method comprising: configuring address bit error detection; receiving the data bits and address bits; detecting an error in the address bits using the check bits if the address bit error detection is enabled; and detecting and correcting up to 32-bit errors in the data bits using the check bits.
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