US 5,691,996 AGrant
Memory Implemented Error Detection and Correction Code With Address Parity Bits
Issue Date:1997-11-25
•2 Claims
•7 Drawing Sheets
Abstract
A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.
Metadata
Assignee
- International Business Machines Corporation
Inventors
- Chin-Long Chen
- Mu-Yue Hsiao
- Walter Heinrich Lipponer
- William Wu Shen
Application Information
Application Number:US 5704464
Filing Date:1995-12-11
Priority Date:1995-12-11
Art Unit:236
Classifications
IPC:
G11C 2900
Field of Search:
37139549.1;49.2;51.1;40.4;50.1185.06
Patent Drawings (7 sheets)
Description
Background of the Invention
The present invention is generally directed to error correction, decoding and e coding systems found in digital devices. The present invention incorporates by reference the invention disclosed in U.S. Ser. No. 08/538,691 filed Oct. 3, 1995, entitled "error detection and correction code for four-bit-per-chip memory system directed to multi-bit-per chip computer memory systems in which error correction and detection apparatus are provided to acheive correction of all single symbol errors and the detection of all single symbol errors occurring with a single bit error in a second symbol. More particularly, the present invention is directed to a memory assignment scheme, which assigns error correction code words to selected array modules, and incorporates parity address bits in this assignment scheme in order to provide an error correction and detection method and apparatus capable of detecting a variety of errors, including the detection of data fetched from an erroneous address.
In a computer system having b bits of memory available per chip, the failure of each chip can cause one to b erroneous bits in the output data depending upon the failure mode and the data originally stored. A b bit symbol error pattern is used to indicate one of all of the possible 2.sup.b -1 error patterns in the b bits for each computer chip. Normal error correction and detection systems employed in such situations would involve the use of a single error correction (SEC) and double error detection (DED) code. The SEC-DED code, however, is neither effective in correcting symbol errors generated from single chip failures, nor is effective in detecting symbol errors generated from double chip failures. On the other hand, a single symbol error correction and double symbol error detection code, a so-called SSC-DSD code, would provide an effective error correction and detection means to acheive high reliability in a b bit per chip memory. However, SSC-DSD codes require more check bits and more memory chips than are actually necessary for the problem. In particular, for a 64-bit data bus, the required SSC-DSD code would require four redundant memory chips for every 16 data chips to implement a (78,66) SSC-DSD code. Such codes would be 78 bits in length with 64 information bits and 14 check bits. Thus a memory system implementing this code would require 20 chips based upon the above memory organization.
Recognizing the stringent requirements of the SSC-DSD memory system, the present inventors devised a new coding scheme as described in detail in U.S. patent application Ser. No. 08/538,691 in which the number of redundant chips are decreased from 4 to 3 chips for a (76,64) code for each set of 16 chips. This code is then used to correct all single symbol errors and detect all single symbol errors plus a single bit error in a second symbol. In certain instances, however, although the data in storage is error free, an error condition can occur if data is fetched from the wrong address in memory. However, the invention introduced in U.S. Ser. No. 08/538,691 never addressed the issue of detection of data fetched from an erroneous address.
The present invention utilizes the coding scheme suggested in U.S. Ser. No. 08/538,691, but improves upon the code by generating address parity bits from system address bits and later including these in the generation of ECC word. Accordingly, a more efficient and more reliable improved computer memory system is provided through the use of the present invention. All of these are desirable results.
This application is related in subject matter to two other disclosures, Ser. Nos. 08/570,447 and 08/570,448 both filed on the same day as this application.
Summary of the Invention
In accordance with a preferred embodiment of the present invention, digital signal error detection is performed through the use of an apparatus and method for generating a plurality of address parity bits in a computer system from a string of received incoming system address bits. First the system address bits are divided into n groups. These n groups are then used in the generation of address parity bits with at least one address parity bit generated from each of said n groups.
In another embodiment of the present invention, the system address bits are divided into two groups. The first group having only high bits with a value of "1", and the second group having only low bits with a value or "0". The bits contained in each group is then subsequently combined to generate at least one high address parity bit, and a second low address parity bit.
Brief Description of the Drawings
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with further objects and advantages thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings in which:
FIG. 1 is an overall block diagram illustrating a memory system in which a memory word is stored on k separate chips each providing b bits to a computer memory system register;
FIG. 2 is a functional block diagram illustrating the 15 possible error patterns for the case in which there are four bits per chip;
FIGS. 3A and 3B are functional block diagrams illustrating the limits of error detectability for the circuits of the present invention;
FIG. 4 is a general ECC (Error Correction Code) flow diagram, illustrating various staging registers and line buffers involved in the store and fetch operations for the present invention;
FIG. 5 is an illustration of the processing of bits during a data store operation;
FIG. 6 is a further illustration of the operation of a data store command according to the concepts presented by the present invention;
FIG. 7 is an illustration of the processing of bits during a data fetch operation;
FIG. 8 is a further illustration of the operation of a data fetch command according to the concepts presented by the present invention;
FIG. 9 illustrates the arrangement of data in memory modules on the SIMM array(s).
Detailed Description of the Invention
The invention described below is particularly shown with respect to a particular example, namely the construction of a (76,64) code for a four-bit per chip computer memory system. However, the ideas presented herein are extensible to the general b bit per chip situation. In particular, it is noted that the number of rows of b by b submatrices in the parity check matrix is determined by the error correction capabilities that are desired. In the particular instance of the codes constructed in accordance with the present invention, three rows of by b submatrices are sufficient to provide the desired correction and detection capabilities. Likewise in general, codes constructed in accordance with the present invention will have k symbols. Each symbol will be represented by b bits. Since three of the symbols are employed for redundancy, there are thus k-3 information symbols and 3 symbols which comprise check bits.
With respect to the present invention for a (76,64) code, the parity check matrix for this code including an embodiment utilizing two address parity bits is given below:
Data Store Operation
During a store operation, in accordance with the embodiment represented by the parity check matrix shown in Table I, each of the 12 ECC check bits is generated. The 12 ECC check bits are generated in two stages. During the first stage, a partial ECC check bit is generated by exclusive OR circuits which take a subset of 64 data bits as indicated by the 1's in each row of the parity check matrix in Table I. For example, the first partial check bit is generated by exclusive-ORing data found at positions: 1, 5, 9, 13, 17, 21, 25, 29, 33, 36, 37, 38, 40, 41, 42, 43, 44, 47, 48, 49, 50, 53, 54, 57, 58, 59, 62 and 63.
These address parity bits are generated from selective combination of data from system address bits as discussed later in detail. During the second stage the partial check bits are combined with the address parity bits and data bits to generate the final 12 ECC check bits.
The set of 64 data bits together with the 12 check bits form an ECC word. Therefore, it seems that in the embodiment presented in Table I, when the two address parity bits are included, the ECC word is really a (78,66) code word. However, since the parity address bits have been used in the generation of the final 12 ECC check bits, it is unnecessary for them to be stored as part of the ECC word. Therefore, the code is still a (76,64) code since only 76 bits per code word are stored into the memory array or a SIMM (Single-Inline-Memory-Module) as shown in FIG. 9. The address parity bits are regenerated again during the fetch operation from incoming system address bits.
The ECC word is divided into 19 groups of 4 bit symbols. In storing data, the ECC word is stored in 19 differnt chips. That is each symbol is stored on a different chip. This situation is illustrated in FIG. 1 wherein memory system 10 is shown to be organized using m chips with b bits being delivered from each chip at a time. Thus, the ECC word in register 25 is mb bits long. For the example illustrated herein, m=19 and b=4.
When an array chip, say chip i, fails the data stored in that chip may or may not be in error depending on the data stored. If the data is in error, the number of errors may be one or more than one. FIG. 2 illustrates all of the possible error patterns 2.sup.b -1=15 for a failed chip i. FIGS. 3A and 3B illustrate the limits of error detectability in the present invention. FIG. 3A particularly shows the situation in which chip i produces from one to four errors while only a single error occurs in chip J. Reference numeral 20 in FIGS. 1 through 3 refer to the individual memory chips. FIG. 3B illustrates the situation in which chip i produces from one to four errors while only a single error occurs in address parity.
At the outset of a store operation data bits are stored in a plurality of storage buffers. In the example illustrated in Table II, given below, the 64 data bits are first stored in two storage buffers named STBUF.sub.- H.sub.- D(0 . . . 31) and STBUF.sub.- L.sub.- D(0 . . . 31), respectively. There are 32 bits of data in each storage buffer and these bits are renamed as SEC.sub.- O.sub.- H(0 . . . 31) and SEC.sub.- O.sub.- L(0 . . . 31) when wired into the memory modules, namely the modules of a SIMM.
The address parity bits are located in address buffers indicated as STORE.sub.- ADDRP.sub.- D(0 . . . 1) in Table II above. The address parity bits are generated from selective combination of data from system address bits as shown in the example provided below in Table III.
STORE.sub.- ADDRP.sub.- D(0) is generated from the parity of system address bits 1, 2, 5-14, 26, 27 and 30. Similarly, STORE.sub.- ADDRP.sub.- D(1) is the parity of system address bits 0, 3, 4, 5-25, and 31. As illustrated in table III, the mapping of system address bits to memory module depends on the size of the modules.
The final ECC check bits are then generated by combining the contents of the STORE.sub.- ADDRP with the data stored in the storage buffers STBUF and the data obtained from the partial check bits generated from the Exclusive-Or circuitry. In short, during the first stage, the partial check bits SY0(0 . . . 11)are generated from the high word data word STBUF.sub.- H.sub.- D(0 . . . 31) and SY1(0 . . . 11) are generated from the low data word STBUF.sub.- L.sub.- D(0 . . . 31). Then SY0 and SY1 and address parity bits are combined to produce the final check bits. The final 12 ECC check bits are stored in SEC.sub.- O.sub.- C(0 . . . 11) buffer. The following equation illustrates in detail the generation of the 12 ECC check bits and their final storage in the SEC.sub.- O.sub.- C(0 . . . 11) buffer.
The notation OPA(X.vertline..vertline.Y.vertline..vertline.Z) is used to describe a logic function that implements the odd parity of bits X,Y and Z. The generation of check bits is divided in two stages as mentioned earlier.
FIG. 4 is an illustration of the general ECC flow diagram. Logic steps 1 through 4, 100 through 400, are the various staging registers and line buffers used in the data store and data fetch operations. Logic steps 1 and 2, 100 and 200, involve different operations that finally allow the generation of ECC store operation 220 into the computer memory DRAM array 500. This information is later fetched from the DRAM array 500 to regenerate and decode the bits during the fetch operation, 300 through 400.
During the store operation, the ECC check bits 57 are generated from the 64 data bits 50 and the system address bits 52 as shown FIG. 5. The entire ECC word 58 is then stored into a memory array 500 to be used later during a fetch operation. FIG. 6 shows the storage of data in storage arrays 61, 62 and 63 before the generation of check bits 66,67 and 68.
Table I above is an embodiment of the present invention utilizing two address parity bits. Other embodiments are conceivable, however, in accordance to the concepts of the present invention where the number of address parity bits, can either be reduced to one or increased to more than two. Table IV given below provides another embodiment of the present invention where eight address parity bits are generated and used.
Data Fetch Operation
During a Fetch operation, the reverse of the store process implemented during the store operation is used as shown in FIGS. 7 and 8. Data 70, 72 and 55, including the ECC word, is first fetched from memory 500, as shown in FIG. 7. FIG. 9 illustrates the circuits used during an ECC fetch operation. Data fetched from the DRAM array chips are named MDRMUX.sub.- H(0 . . . 31) 92 for modules 1 to 8, MDRMUX.sub.- L(0 . . . 31) 94 for modules 9 to 16 and MDRMUX.sub.- C(0 . . . 11) 96 for modules 17 to 19.
When data is fetched from storage, a set of partial syndrome bits SYH(0 . . . 11) and SYL(0 . . . 11) is generated from the fetched data word from the DRAM array chips or the MDRMUX as illustrated in detail by the following equation:
The same circuits that are used in generating the partial check bits during the store operations are utilized again to regenerate the partial syndrome bits. So for example, partial syndrome bit i is the Exclusive-OR of the fetched data word at positions specified by 1's in the ith row of the parity check matrix. That is to say that the partial syndrome bits are generated by supplying specified signals to a set of exclusive.sub.- OR gates.
The syndrome bits SY(0 . . . 11) are then generated from the combination of the fetched data from check bits MDRMUX.sub.- C(0 . . . 11) and the address parity bits from Fetch.sub.- ADDRP(0 . . . m) generated from the incoming system address bits.
The partial syndrome bits SY(0 . . . 11) 72 are then decoded 74 to identify any possible errors as illustrated in FIG. 7. Module error indicators are then generated according to the formula given below during the decoding process to detect and indicate errors.
FIG. 8 illustrates a set of module errors indicators MOD.sub.- 00, MOD.sub.- 01, . . . MOD.sub.- 18 74. Any error will cause the setting of one of the MOD's. For example an error in module 0 will cause MOD.sub.- 00 to be set to 1. During the decoding operations, bit error indicators are also generated from circuit lines which are later used to invert the fetched data bits to correct certain errors. Invert lines 81 INV.sub.- H(0 . . . 31) 84, INV.sub.- L(0 . . . 31), and INV.sub.- C(0 . . . 11) are used in conjunction with bit errors so that when a bit error indicator is on, the corresponding data bit is corrected by inversion of the data. Bit error indicators 82 are generated from the following equations.
In this manner, the status of the module error and the syndromes are to enable a plurality of invert lines and generate other signals pertaining to types of errors 78 including a UE (Uncorrectable error) signal 79 or a CE (Correctable Error) signal 77.
FIG. 9 illustrates the arrangement of data in the memory modules on the SIMMs. There are 19 memory modules in a SIMM; a number of SIMMs can therefore be configured in this way into the memory. As illustrated, the data bits and check bits are divided into 4 bit symbols to store in 19 memory modules. SEC.sub.- O.sub.- H(0 . . . 31) are stored in modules 1 to 8, SEC.sub.- 0.sub.- L(0 . . . 31) are stored in modules 9 to 16, and SEC.sub.- 0.sub.- C(0 . . . 11) are stored in modules 17 to 19. The mapping of system address bits to memory modules depends on the module size as shown in Table IV and FIG. 9.
While the invention has been described in detail herein in accordance with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.
Claims
We claim:
1. A method of generating at least two address parity bits in a computer system from a string of received incoming system address bits, said incoming address bits comprising a vector with a multiplicity of lines each having segments b bits in length, said method comprising the steps of: dividing said vector lines into two groups as to provide at least two bits of address parity, wherein said first group having only high bits with a value of "1", and said second group having only low bits with a value of "0"; generating at least one address parity bit from each of said two groups by combining all bits of said first group to generate at least one high address parity bit, and combining all bits of said second group to generate at least one low address parity bit; said vector and said address parity having the following values: =======================DATA======================= 1 2 3 4 5 6 7 8 ==== ==== ==== ==== ==== ==== ==== ==== ______________________________________ 1000 1000 1000 1000 1000 1000 1000 1000 0100 0100 0100 0100 0100 0100 0100 0100 0010 0010 0010 0010 0010 0010 0010 0010 0001 0001 0001 0001 0001 0001 0001 0001 0110 1000 0010 1011 1010 1101 0101 1110 1101 0100 0001 0110 0101 1011 1111 1001 1011 0010 1010 1101 1000 0110 0100 1001 0110 0001 0101 1011 0100 1101 1100 0111 1000 1110 0111 1010 1001 0010 0110 0001 0100 1001 1110 0101 0111 0001 1101 0011 0010 1001 1110 1000 0111 1010 1011 0101 0001 0111 1001 0100 1110 0101 0110 1111 ====================================================== ______________________________________ =======================DATA======================= 9 10 11 12 13 14 15 16 ==== ==== ==== ==== ==== ==== ==== ==== ______________________________________ 1001 1101 1111 0011 1100 1100 1110 0110 0111 1011 1010 0010 1000 1000 1001 1101 0111 0110 1100 1111 0011 0011 1001 1011 1110 1101 1000 1010 0010 0010 0111 0110 1000 0001 1000 0111 1000 1110 1000 0100 0100 0011 0100 1110 0100 1001 0100 1100 0010 0101 0010 1110 0010 1001 0010 0001 0001 1111 0001 1001 0001 0111 0001 0011 0101 1000 1011 1000 0110 1000 0100 1000 1111 0100 0110 0100 1101 0100 1100 0100 0100 0010 1101 0010 1011 0010 0001 0010 1100 0001 1011 0001 0110 0001 0011 0001 ====================================================== ______________________________________ ==== ECC ==== ======= ADDRESS SYMBOL PARITY ID BITS 17 18 19 (CHIP) 20 ==== ==== ==== ID ==== ______________________________________ 1000 0000 0000 -- 01 0100 0000 0000 -- 11 0010 0000 0000 -- 10 0001 0000 0000 -- 11 0000 1000 0000 -- 10 0000 0100 0000 -- 01 0000 0010 0000 -- 00 0000 0001 0000 -- 00 0000 0000 1000 -- 00 0000 0000 0100 -- 00 0000 0000 0010 -- 01 0000 0000 0001 -- 10 ====================================================== ______________________________________
2. A method of generating at least two address parity bits in a computer system from a string of received incoming system address bits, said incoming address bits comprising a vector with a multiplicity of lines each having segments b bits in length, said method comprising the steps of: dividing said vector lines into eight groups so as to provide at least two bits of address parity, wherein said first group having only high bits with a value of "1", and said second group having only low bits with a value of "0"; generating at least one address parity bit from each of said two groups by combining all bits of said first group to generate at least one high address parity bit, and combining all bits of said second group to generate at least one low address parity bit; said vector and said address parity comprising: =======================DATA======================= 1 2 3 4 5 6 7 8 ==== ==== ==== ==== ==== ==== ==== ==== ______________________________________ 1000 1000 1000 1000 1000 1000 1000 1000 0100 0100 0100 0100 0100 0100 0100 0100 0010 0010 0010 0010 0010 0010 0010 0010 0001 0001 0001 0001 0001 0001 0001 0001 0110 1000 0010 1011 1010 1101 0101 1110 1101 0100 0001 0110 0101 1011 1111 1001 1011 0010 1010 1101 1000 0110 0100 1001 0110 0001 0101 1011 0100 1101 1100 0111 1000 1110 0111 1010 1001 0010 0110 0001 0100 1001 1110 0101 0111 0001 1101 0011 0010 1001 1110 1000 0111 1010 1011 0101 0001 0111 1001 0100 1110 0101 0110 1111 ====================================================== ______________________________________ =======================DATA======================= 9 10 11 12 13 14 15 16 ==== ==== ==== ==== ==== ==== ==== ==== ______________________________________ 1001 1101 1111 0011 1100 1100 1110 0110 0111 1011 1010 0010 1000 1000 1001 1101 0111 0110 1100 1111 0011 0011 1001 1011 1110 1101 1000 1010 0010 0010 0111 0110 1000 0001 1000 0111 1000 1110 1000 0100 0100 0011 0100 1110 0100 1001 0100 1100 0010 0101 0010 1110 0010 1001 0010 0001 0001 1111 0001 1001 0001 0111 0001 0011 0101 1000 1011 1000 0110 1000 0100 1000 1111 0100 0110 0100 1101 0100 1100 0100 0100 0010 1101 0010 1011 0010 0001 0010 1100 0001 1011 0001 0110 0001 0011 0001 ====================================================== ______________________________________ ==== ECC ==== ======= ADDRESS SYMBOL PARITY ID BITS 17 18 19 (CHIP) 20 21 ==== ==== ==== ID ==== ==== ______________________________________ 1000 0000 0000 -- 0111 1101 0100 0000 0000 -- 1111 0010 0010 0000 0000 -- 1011 0111 0001 0000 0000 -- 1100 1101 0000 1000 0000 -- 1000 0011 0000 0100 0000 -- 0110 0111 0000 0010 0000 -- 0001 0010 0000 0001 0000 -- 0000 1110 0000 0000 1000 -- 0000 1100 0000 0000 0100 -- 0001 1010 0000 0000 0010 -- 0110 1000 0000 0000 0001 -- 1011 1001 ====================================================== ______________________________________
Patent Citations (6)
Non-Patent Literature (1)
- Norbert Schumacher, Memory Controller Design in VLSI and Computer Peripheals, 1-38-1-42 1989.