Memory System and Method

This invention relates generally to memory systems and more particularly to error detection and correction (EDAC) used in memory systems.

As is known in the art, in many applications a memory board is arranged as shown in FIG. 1. Thus, such memory board includes a plurality of memory banks 10.sub.1 -10.sub.n. Each one of the memory banks 10.sub.1 -10.sub.n has a plurality of random access memories (RAMs), here for example, dynamic RAMs (DRAMs) 12.sub.0 -12.sub.m. Each bit of a data word on a corresponding one of lines D.sub.0 -D.sub.m is coupled to the data bit terminal, D, of a corresponding one of the DRAMs 12.sub.1 -12.sub.n in each one of the memory banks 10.sub.1 -10.sub.n. Thus, for example, data bit D.sub.0 of the data word is coupled to the data bit terminal, D, of the DRAMs 12.sub.0 in each of the memory banks 10.sub.1 -10.sub.n. Each data word includes, in addition to data, a plurality of bits for error detection and correction. For example, a Solomon-Reed code. Thus, for example, if the data portion of the data word includes 64 bits (i.e., 8 bytes), an additional byte (i.e.,8 bits) is included in the data word for error correction and detection. Thus, in this example m=71 and there are 72 DRAMs 12.sub.0 -12.sub.71 in each one of the memory banks 10.sub.1 -10.sub.n.

Each DRAM is addressable by an r bit address, A.sub.0 -A.sub.(r-1). Consider, for example the case where r=12. Thus, a 12 bit row address and a 12 bit column address are fed sequentially to the address terminals, A, of the DRAMs. More particularly, when the 12 bit row address is fed to the DRAM, a control signal is also fed to a column address select line (CAS) of the DRAM. Likewise, when the 12 bit row address is fed to the DRAM, a control signal is fed to the row address select line (RAS) for the DRAM. The read/write mode of the DRAMs is selected by a control signal on write line (WR). Thus, here each DRAM has 16 megabits of addressable locations and, therefore, each memory bank is able to store 16 megs of 9 byte digital words; 8 bytes of data and a byte for error detection and correction.

It is noted that the address signals are fed to the memory board by a logic network, not shown. In order to provide adequate power to address large numbers of DRAMs, drivers 14 are included. Typically, each driver 14 is adapted to drive about 18-36 DRAMS. Thus, assuming here that each driver 14 is used to drive 36 DRAMs, there are 2 drivers 14 for each one of the memory banks 10.sub.1 -10.sub.n.

Finally, as mentioned above, the EDAC may be performed on the data by checking the data read from the memory using a Solomon-Reed code, for example. However, a failure in one of the drivers 14 results in the 36 bits of data being written to an incorrect memory location. While parity checking of the address may be used to detect the presence of an error in the address, an EDAC will not be able to readily correct 36 bits of data which have become stored in the incorrect address location.

In accordance with the present invention, a memory system is provided having a plurality of memory banks. Each one of the memory banks has a plurality of addressable memory units. A driver is coupled to a set of address terminals of a corresponding one of the memory units in each one of the memory banks. Each bit of data is fed to, or from, a data terminal of a corresponding one of the memory units in each one of the memory banks. An error detection and correction (EDAC) unit is fed by the data passing to, or from, the memory system.

With such an arrangement, a failure of any one of the drivers results in an error in only one bit of the data stored in the incorrectly addressed location, and such single bit error is readily correctable by the EDAC unit upon its retrieval from the memory system.

For a more complete understanding of the invention, reference is now made to the following description taken together in conjunction with the accompanying drawing, in which:

FIG. 1 is a block diagram of a memory system according to the prior art which has been discussed above; and

FIG. 2 is a block diagram of a memory system according to the invention.

Referring now to FIG. 2, a memory system 20 is shown having a plurality of, here p, memory banks 22.sub.1-22.sub.p. Each one of the memory banks 22.sub.1 -22.sub.p includes a plurality of, here m+1, memory units, here DRAMs 24.sub.0 -24.sub.m. Each one of the DRAMs 24.sub.0 -24.sub.m has a set of address terminals, A, a data terminal, D, a column address select (CAS), a row address select (RAS) and a write enable (WR).

The memory 20 includes a plurality of, here m+1, drivers 26.sub.0 1-26.sub.m. Each one of the drivers 26.sub.0 -26.sub.m is coupled to the set of address terminals, A, of a corresponding one of the DRAMs 240-24.sub.m in each one of the memory banks 22.sub.1 -22.sub.p. Thus, for example, driver 26.sub.1 is coupled to DRAMs 24.sub.1 in each of the memory banks 22.sub.1 -22.sub.p. Likewise, for example, driver 26.sub.m is coupled to DRAMs 24.sub.m in each of the memory banks 22.sub.1 -22.sub.p.

Each one of the DRAMs 24.sub.0 -24.sub.m in each of the memory banks 22.sub.1 -22.sub.p include a data terminal, D. The data terminal, D, of one of the DRAMs 24.sub.0 -24.sub.m, in each one of the memory banks 22.sub.1 -22.sub.p is coupled to a corresponding one bit line of an m+1 bit line data bus, DB. Thus, here the data bus DB has m+1 bit lines D.sub.m -D.sub.0, as shown. Therefore, the data terminal, D, of DRAMs 24.sub.1, for example, in each one of the memory banks 22.sub.1 -22.sub.p is coupled to bit line D.sub.1 of the data bus DB. Likewise, the data terminal, D, of DRAMs 24.sub.m, for example, in each one of the memory banks 22.sub.1 -22.sub.p is coupled to bit line D.sub.m of the data bus DB.

An r bit address signal, A.sub.0 -A.sub.r-1, from an address/control logic 27, is fed to drivers 26.sub.0 -26.sub.m via an r+2 bit address bus 28, as shown. Each one of the drivers 26.sub.0 -26.sub.m is coupled to the set of address terminals A of a corresponding one of the DRAMs 24.sub.0 -24.sub.n, respectively, in each of the memory banks 22.sub.1 -22.sub.p, as shown. Thus example, the r bit output of driver 26.sub.1 is coupled to the r bit set of address terminals, A, of DRAMs 24.sub.1 in each of the memory banks 22.sub.1 -22.sub.p, as shown. Likewise, the r bit output of driver 26.sub.m is coupled to the r bit set of address terminal, A, of DRAMs 24.sub.m in each of the memory banks 22.sub.1 -22.sub.p, as shown.

Also, address/control logic 27 produces a row memory access signal on line RAS and a write enable signal on line WR for each one of the drivers 26.sub.0 -26.sub.m, as shown. Each one of the drivers 26.sub.0 -26.sub.m is coupled to the RAS and WR terminals of a corresponding one of the DRAMs 24.sub.0 -24.sub.n, respectively, in each one of the memory banks 22.sub.1 -22.sub.p, as shown. Thus, for example, the RAS line output of driver 26.sub.0 is coupled to the RAS terminals of DRAMs 24.sub.0 in each of the memory banks 22.sub.1 -22.sub.p, as shown, and the WR line output of driver 26.sub.0 is coupled to the WR terminals of DRAMs 24.sub.0 in each of the memory banks 22.sub.1 -22.sub.p, as shown.

A column memory access signal is produced by the address/control 27 on one of a plurality of, here p, lines CAS.sub.1 -CAS.sub.p, for each produced column address. More particularly, each one of the lines CAS.sub.1 -CAS.sub.p is coupled to a corresponding one of the memory banks 22.sub.1 -22.sub.p, respectively, as shown. Thus, if an m+1 bit digital word is to be written into, or read from, the DRAMs 24.sub.0 -24.sub.m in memory bank 22.sub.2, for example, when the r column bits of the address are produced by the drivers 26.sub.0 -26.sub.m, a column memory access signal is fed to line CAS.sub.2. Likewise, if an m+1 bit digital word is to be written into, or read from, the DRAMs 24.sub.0 -24.sub.m in memory bank 22.sub.p, for example, when the r column bits of the address are produced by the drivers 26.sub.0 -26.sub.m, a column memory access signal is fed to line CAS.sub.p.

An error detection and correction (EDAC) unit 30 is included. The error detection and correction unit 30, is of any conventional design, such as a Solomon-Reed code EDAC. Further, the EDAC unit 30 need not be on the same board as the memory banks but rather may be mounted on a controller board, not shown, and coupled to the memory board through a backplane, not shown. In any event, the data bus DB (i.e, bit lines D.sub.0 -D.sub.m) is coupled to EDAC 36, as shown. Therefore, a portion of the digital word on the data bus DB included data and the remaining portion included error detection and correction bits for the Solomon-Reed error detection and correction code. For example, if m=71, there will be 72 DRAMs 24.sub.0 -24.sub.71, and data bus DB will have 64 data bit lines D.sub.0 -D.sub.63 and eight error detection bit lines D.sub.64 -D.sub.71. With such arrangement, a failure of any one of the drivers 26.sub.0 -26.sub.71 results in an error in only one bit of the 72 bit data stored in a location incorrectly addressed because of the failed driver. This single bit of error in the data is corrected by the EDAC unit 30 upon its retrieval from the memory system 20.

Other embodiments are within the spirit and scope of the appended claims.