Serial Address Generator for Burst Memory

1. Field of the Invention

This disclosure relates to random access memory and specifically to a serial address generator for a burst-type random access memory.

2. Description of the Prior Art

Video RAM (random access memory), synchronous RAM and burst RAM each require a sequence of internally generated addresses for faster cycling and prevention of the external address bus lines from fast switching to suppress switching noise in the system. Typically the start address of a particular address burst is provided from an external source (a host computer or a processor) and as subsequent clock signals arrive at the address generator, the following addresses in the burst are generated continuously in sequence for the duration of the burst. The prior art presets the address sequencer (typically a counter) to the externally provided start address (A.sub.n) in response to a PRESET signal. The address sequencer output is updated with each .phi..sub.clock rising edge, and the outputs of the address generator are sequentially A.sub.n, A.sub.n+1, A.sub.n+2, etc.

Such a prior art address generator is shown in FIG. 1A including address sequencer 12 outputting the sequence of addresses to an output buffer 14. The three input signals to the address sequencer 12 are the input address signal (the start address A.sub.n), the .phi..sub.clock signal, and the PRESET signal. Additionally, a sequence control signal controls whether the address sequencer 12 counts up or down. In most applications, upcounting is used, and this function is built in, rather than being a control function. The associated timing diagram is shown in FIG. 2A.

Typically the address sequencer 12 (counter) includes a master side and a slave side, each initially set to the start address A.sub.n. It is to be understood that the device of FIG. 1A is a parallel device, where the start address A.sub.n is a multi-bit address provided by a plurality of lines, i.e. an address bus. The address out signal is also provided on a multi-line bus.

As seen in FIG. 2A, the first address out A.sub.n is output to buffer 14 when the Preset signal is applied, and kept until leading edge of .phi..sub.clock arrives. The second address out A.sub.n+1 is output to buffer 14 at the trailing edge of .phi..sub.clock and the following addresses are updated at every trailing edge of the .phi..sub.clock signal.

The address generator of FIG. 1A functions adequately; however it is slower than desired. Faster operation is desirable to improve system performance such as needed in a typical burst DRAM (dynamic random access memory) chip. The FIG. 1A address generator delivers the first address late, due to the propagation delay through the counters inside the address sequencer. This means a shorter start address duration time.

To improve the start address delivery, in a second prior art address generator the start address is provided from the Address Input directly, instead of going through the counters. (See FIG. 1B, and corresponding timing diagram FIG. 2B).

Rather than providing the start address A.sub.n to the address sequencer as in FIG. 1A, the address sequencer 12 of FIG. 1B is bypassed before and during the preset period by means of external address enable switch 24 and internal address enable switch 26, and the start address is provided directly to the output buffer via external address enable switch 24. This (start) address A.sub.n is therefore available almost immediately as the address out at buffer 14, without processing by the address sequencer 12.

However, further performance improvement (i.e., higher speed) is desirable in terms of address output.

In the above described prior art, the second address A.sub.n+1 is delivered by the address sequencer to the output buffer at the time of the trailing edge of the first .phi..sub.clock cycle. In accordance with the invention, instead the second address A.sub.n+1 is delivered to the output buffer at the leading edge of the .phi..sub.clock signal. Thus one half of a clock cycle is gained for each address burst.

After provision to the output buffer of the first address A.sub.n (which is externally supplied as in FIG. 1B) the external address line is disconnected from the output buffer by an external address enable switch, and an internal address enable switch which connects the address sequencer to the output buffer is closed, allowing the address sequencer to provide the subsequent internally generated address A.sub.n+1 to the output buffer, also as in FIG. 1B. Then, during the time that the start address A.sub.n is being provided to the output buffer, the address sequencer operates to calculate the subsequent address A.sub.n+1. The output addresses of each burst are thereby, each provided to the output buffer approximately 1/2 of a clock cycle earlier than in the prior art of FIG. 1B.

The externally provided address and the address out both begin with the same address A.sub.n which is the initial address in the burst, while using the preset signal to advance the counting of the sequence by one count.

Therefore, the address sequencer is preset to address A.sub.n+1 (the second address in the burst) following the externally provided start address A.sub.n. When the first clock signal arrives at the address sequencer, the address sequencer output is sampled by enabling the internal address enable (second) switch and disabling the external address enable (first) switch. The address sequencer output is updated with each rising edge of the clock signal .phi..sub.clock. Thereby the address sequencer generates each address one clock cycle ahead of the time that address would have been generated in the prior art, and the address output is supplied to the output buffer 1/2 clock cycle ahead of the prior art (FIG. 2B) timing. As in the prior art, the address sequencer includes a master/slave counter. However, in accordance with the invention and in order to set the address sequencer initially to the second address A.sub.n+1, the master side of the counter is initially set to value A.sub.n, and the slave side of the counter is initially set to value A.sub.n+1. This provides the desired incremental timing advantage over the prior art.

The present invention is applicable specifically to burst DRAM (dynamic RAM) operating in page mode, and is also applicable to other types of burst memory using sequential type addressing.

In accordance with the invention, operation of the address generator is the same as in the prior art except during the preset cycle. Thus the performance advantage is gained during the preset portion of the address burst. Since the addresses are output one-half cycle ahead of that provided in the prior art, this improves the operational performance of the system in which the burst memory is installed.

FIGS. 1A, 1B show prior art address generators.

FIGS. 2A, 2B show timing diagrams for the prior art address generators of respectively FIGS. 1A, 1B.

FIG. 3 shows an address generator in accordance with the present invention.

FIG. 4 shows a timing diagram for the address generator of FIG. 3.

FIG. 5 shows a schematic of the internal address enable switch, external address enable switch, and output buffer in accordance with the present invention.

FIG. 6 shows a counter in accordance with the present invention.

FIG. 7 shows detail of one cell of the counter of FIG. 6.

FIGS. 8, 9, and 10 show circuitry for generation of the timing signals for the address generator in accordance with the present invention.

FIGS. 11(a) and 11(b) show a timing diagram for an address generator in accordance with the present invention.

FIG. 3 shows in a block diagram serial address generator 18 in accordance with the invention. Address generator 18 includes address sequencer 20, output buffer 22, external address enable switch 24 (as in FIG. 1B) actuated by an external address enable control signal 28, and internal address enable switch 26 (as in FIG. 1B) actuated by an internal address enable control signal 30. Thus the serial address generator of FIG. 3 appears in the block diagram to be similar to the serial address generator of FIG. 1B; the distinction is in the internal structure and operation of address sequencer 20, which differs significantly from address sequencer 12 of FIGS. 1A and 1B.

Sequence control signal 32 (as in the prior art) determines whether address sequencer 20 is an up or down counter. Input signals on lines 34, 36 and 38 are conventional (as in the prior art). The output address ("address out") is provided on line 40. This circuit, like that of FIGS. 1A and 1B, is a parallel device providing a multi-bit address. Hence address line 34, the output from the address sequencer on line 42, and the address out line 40 each represent multi-line busses with as many lines as there are address bits in the particular application.

FIG. 4 illustrates timing for the address generator of FIG. 3, and specifically the timing for external address switch 24 and internal address switch 26 as controlled respectively by their control signals 28, 30 of FIG. 3. Initially, external address enable switch 24 is closed (the external address enable control signal 28 is high) thus providing the externally provided address on line 34 directly to buffer 22. After the initial address A.sub.n (which is externally provided) is provided to buffer 22, the signal .phi..sub.clock goes low, and the external address enable control signal 28 goes low, then the internal address enable signal 30 goes high, closing switch 26. At this time the address sequencer 20 has generated the second address A.sub.n+1.

As seen in the timing diagram of FIG. 4, generation of the second address A.sub.n+1 overlaps with provision of the start address A.sub.n. Thus within the first two .phi..sub.clock cycles, all of start address A.sub.n and second address A.sub.n+1 are output to buffer 22, in contrast to the prior art of FIG. 2B in which only 11/2 addresses are outputted within the first two occurrences of clock cycles .phi..sub.clock. This half-clock cycle advantage is the chief benefit of the present invention. Thus the generation of addresses ("Address sequencer out" in FIG. 4) is one clock cycle ahead of that in the prior art, and there is also a half clock timing advantage in the output addresses ("Address out") in contrast to the prior art of FIG. 2B.

In one embodiment the serial address generator of FIG. 3 is for use in a burst RAM operating in page mode, with the externally provided address being the first (start) address for each page. Therefore for example a RAM chip having 512 words per page requires nine bit addresses, i.e., 2.sup.9 =512. Thus, the address sequencer is a nine-bit counter. The serial address generator in accordance with the invention is also be suitable for other (non-page mode) types of serially generated addresses, with the addition of conventional stop circuitry to terminate a burst of predetermined length.

It is to be appreciated that the serial address generator of FIG. 3 is used in place of conventional serial address generator of FIGS. 1A, 1B as a portion typically of a RAM chip. The address out signal provided on line 40 is conventionally connected to an address decoder which selects the desired memory cell or cells to be written to or read from. (The remainder of the RAM chip is not illustrated herein as being conventional.)

FIGS. 5 through 10 show a detailed schematic of one embodiment of the present invention, corresponding to that shown in the block diagram of FIG. 3 except that the sequence control is not shown, due to only upcounting being available. In FIGS. 5 through 10 the small numbers adjacent each logic gate indicate the width (in micrometers) of each transistor gate of the logic gate. Thus, "P" indicates the width of a P channel transistor gate and "N" indicates the width of an N channel transistor gate. The gate length is equal for all transistors except where a two number notation is used i.e., "48/2" means the transistor gate width is 48 micrometers and the transistor gate length is 2 micrometers. The standard (default) transistor gate length is 1.2 micrometers, for this embodiment.

Table 1 shows the signal designations in the block diagram FIG. 3 and the corresponding signal designations in schematic FIGS. 5 to 10, and in the corresponding timing diagram of FIGS. 11(a), 11(b). In Table 1 there is no schematic equivalent to the sequence control signal in FIG. 3, since as explained above the circuit shown in the schematic of FIGS. 5 to 10 uses "up counting" only and does not have a down counting mode option.

Table 2 shows the externally provided input signals/lines for the circuit of FIGS. 5 to 10.

Table 3 shows the output signals for the circuit of FIGS. 5 to 10.

Table 4 shows the internal signals for the circuit of FIGS. 5 to 10.

FIG. 5 corresponds most closely to the block diagram of FIG. 3; however FIG. 5 is for a single address bit and hence shows only one of nine such identical circuits as would be used in FIG. 3. These nine circuits are connected in parallel to provide a nine bit address output signal in this particular exemplary embodiment of the invention.

With reference to FIG. 5, input signal An corresponds to the external Address A.sub.n on line 34 in FIG. 3. Signal AH (address hold) functions as the external address latching and disable. This is the external address enable signal, controlling switch 50 in FIG. 5 which corresponds to switch 24 in FIG. 3.

Similarly, the internal address supplied on line 42 of FIG. 3 is designated signal BN in FIG. 5, and is provided as an input to switch 52 corresponding to switch 26 in FIG. 3. Switch 52 is controlled by the internal address enable signal which in FIG. 5 is designated BAEN-. (The inverse of signal BAEN.) It is to be understood that the signal BN is provided from the counter portion of the address generator, described below.

Buffer 22 of FIG. 3 corresponds to the buffer circuitry 56 of FIG. 5. The outputs of the buffer circuitry of FIG. 5 are designated as a "left" and "right" Y (column address) and the inverses thereof (Y.sub.m-L, Y.sub.mL, Y.sub.m-R and Y.sub.mR). (Note there are two decoders, one for the left memory block and the other for the right memory block.) The output of buffer 56 corresponds to one bit of the address out signal of FIG. 3.

The left and right (L, R) signals of FIG. 5 control the buffer 56 outputs, to provide address signals to left or right decoders respectively. Also provided is column address power up signal YS, which disables the input address pass when the chip is in the precharge state. The internal start address output by the circuit of FIG. 5 (designated BA.sub.n) is an input to the associated counter cell, as described below.

FIG. 6 shows the counter (corresponding to the address sequencer 20 of FIG. 3) providing a nine-bit count. The counter has nine identical cells 60-1, 60-2, . . . , 60-9 connected as shown. Each cell has as a first input the internal start address BA.sub.n. The second cell input is the carry signal designated BC.sub.n-1 from the prior cell. Each cell also receives a first timing signal PRESET, and a second timing signal .phi..sub.clock. The output of each counter cell is an output address bit BN (which is the address out) which then goes to buffer 56 of FIG. 5, and a second output BC.sub.n which is the carry value to the subsequent cell.

It is to be understood that the counter of FIG. 6 occurs only once in the address sequencer 20 and services all nine address buffer circuits, of which only one is shown in FIG. 5.

FIG. 7 shows details of one of the cells of FIG. 6. Signal BC.sub.n-1 is the carry input signal, while signal BA.sub.n is the external address signal. The timing signals are .phi..sub.clock and PRESET (and their inverses). The cell output is the "real" address BN and a carry value BC.sub.n to the next cell. The cell of FIG. 7 includes conventionally a left-hand side which is the "slave" side 70 and a right hand side which is the "master" side 72 (indicated by the broken line). Thus, there are two latches 70a, 72a one for each side of the counter cell, with one latch at any one time updating its value while the second latch is holding the previously calculated data and transmitting it as output.

FIGS. 8, 9 and 10 show circuitry for generating the timing signals for the serial address generator. The two externally provided timing signals are RAS and CAS-PAD. These in turn generate as shown the internal timing signals. The sequence is that the input clock signal CAS-PAD generates timing signal CAS1.sub.b which in turn generates signal BAEN- which in turn generates signal .phi..sub.clock. The .phi..sub.clock signal of FIG. 3 is shown in the timing diagram of FIGS. 11(a), 11(b).

FIG. 8 shows the circuitry which provides the timing signal CAS1.sub.b which is a timing signal for the above-described counter circuitry. Note that signal CAS1.sub.b is in part determined by the signal BM (burst mode) and by the signal WE1 which in this case is the burst write input signal.

FIGS. 11a and 11b show the timing for the signals of FIGS. 5 to 10. The start address (designated A.sub.n in FIG. 3) is designated Y.sub.N in the timing diagram of FIGS. 11a and 11b. The output signal of the counter is designated Y.sub.N+1, Y.sub.N+2, . . . in the timing diagram. It can be seen that when the clock signal AS goes high, and after a particular period, the PRESET signal goes high. In turn, the PRESET signal going low is determined by the signal CAS-PAD going low.

The overall clock speed of the chip in terms of address generation is determined by the signal CAS-PAD; in one embodiment this signal has a 15 nanosecond period, providing a 66 MHz operating speed.

It is to be understood that in a typical operation of the serial address generator, the associated memory array is considered to be an array of memory cells arranged in rows and columns. Each "page" is one row, with the first address on the page being that of the first memory cell in the column. Signal BE/OE, (burst enable output enable) at the rising edge of AS determines whether one is to be in burst mode or in normal page mode. Signal BE/OE is determined by the host computer. The output of buffer 56 of the circuit of FIG. 5 is connected typically to a column predecoder for determining the particular column of a memory array to be addressed. A predecoder buffers the address signals prior to provision thereof to the decoder itself. The predecoder in this case saves power and increases operating speed, by serving as a buffer for the decoder proper.

The above description is illustrative and not limiting; further modifications will be apparent to one skilled in the art and are intended to be covered by the appended claims.