US 10,063,138 B1Grant
Bridgeless power factor correction circuits
Issue Date:2018-08-28
•20 Claims
•12 Drawing Sheets
Abstract
A power factor correction circuit comprises a pair of III-N based switches coupled to a first reference ground, and an inductive component connected in series with a current sensing resistor. A first side of the current sensing resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the current sensing resistor is coupled to a control circuit. The control circuit is also coupled to the second reference ground and is configured to measure current flowing through the inductive component during operation of the power factor correction circuit.
Metadata
Assignee
- Transphorm Inc.
Inventors
- Liang Zhou
- Yifeng Wu
Application Information
Application Number:US 15/428,726
Filing Date:2017-02-09
Priority Date:2014-07-17
Art Unit:2838
Classifications
IPC:
H02M1/42
Field of Search:
H02M 1/081H02M 1/088H02M 1/4208H02M 3/33507H02M 3/33523H02M 3/33592H02M 7/06H02M 7/127H02M 7/1555H02M 7/1623Y02B 70/1475
Patent Drawings (12 sheets)
Description
Cross-Reference to Related Applications
[0001] This is a continuation of U.S. application Ser. No. 14/802,333, filed on Jul. 17, 2015, which claims priority to U.S. Provisional Application No. 62/025,666, filed on Jul. 17, 2014. The disclosure of the prior application is considered part of and is incorporated by reference in the disclosure of this application.
Technical Field
[0002] This invention relates to power conversion circuits such as power factor correction circuits.
Background
[0003] Power factor correction (PFC) circuits have been widely adopted for performing AC-DC power conversion. Conventional PFC converters comprise a full-wave diode bridge rectifier connected to a boost circuit. Along the power delivery path (i.e., the path of current flow) from the AC power supply to the DC power supply, the current passes through two diodes while flowing through the bridge rectifier at the input stage and through another in the boost stage. Power loss associated with the diode voltage drop and current flowing through the diode is incurred for each of these three diodes, which sets a hard limit on the overall system efficiency.
Summary
[0004] In a first aspect, an electronic circuit comprises a first III-N based switch and a second III-N based switch, where a source of the first III-N based switch is coupled to a first reference ground and a drain of the second III-N based switch is coupled to a DC high voltage node. The electronic circuit also includes an inductive component connected in series with a resistor and coupled to a node between the first and second III-N based switches. A first side of the resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the resistor is coupled to a control circuit, wherein the control circuit is also coupled to the second reference ground.
[0005] In a second aspect, a method of sensing current in a power factor correction circuit includes a power factor correction circuit comprising a first III-N based switch and a second III-N based switch, wherein a source of the first III-N based switch is coupled to a first reference ground and a drain of the second III-N based switch is coupled to a DC high voltage node. The power factor correction circuit also includes an inductive component connected in series with a resistor and coupled to a node between the first and second III-N based switches. A first side of the resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the resistor is coupled to a control circuit, the control circuit including an amplifier which is also coupled to the second reference ground and has a bandwidth that is greater than a switching frequency of each of the first and second III-N based switches. The method comprises amplifying a voltage across the resistor and having the control circuit measure the voltage across the resistor.
[0006] In a third aspect, an electronic circuit comprises a first III-N based switch and a second III-N based switch, where a source of the first III-N based switch is coupled to a first reference ground and a drain of the second III-N based switch is coupled to a DC high voltage node. The electronic circuit also includes a third III-N based switch and a fourth III-N based switch, where a source of the third III-N based switch is coupled to the first reference ground and a drain of the fourth III-N based switch is coupled to the DC high voltage node. The electronic circuit further includes a first inductive component connected in series with a first resistor and coupled to a node between the first and second III-N based switches, and a second inductive component connected in series with a second resistor and coupled to a node between the third and fourth III-N based switches. A first side of the first resistor and a first side of the second resistor are each coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the first resistor and a second side of the second resistor are each coupled to a control circuit, wherein the control circuit is also coupled to the second reference ground.
[0007] Implementations of the devices and methods described herein may include one or more of the following features. The electronic circuit may be a power factor correction circuit. The control circuit can be configured to measure current flowing through the inductive component during operation of the electronic circuit. The control circuit can also be configured to measure voltage at the second side of the resistor relative to the second reference ground. The circuit may further include a printed circuit board with a first metal layer between a second metal layer and a third metal layer, wherein a trench is formed in the first metal layer, the trench separating the first metal layer into first and second portions which are electrically isolated from one another. The first portion of the first metal layer may serve as a ground plane for the first reference ground, and the second portion of the first metal layer may serve as a ground plane for the second reference ground.
[0008] The electronic circuit may be a power factor correction circuit. The control circuit can be configured to measure current flowing through the inductive component during operation of the electronic circuit. The control circuit can also be configured to measure voltage at the second side of the resistor relative to the second reference ground. The circuit may further include a printed circuit board with a first metal layer between a second metal layer and a third metal layer, wherein a trench is formed in the first metal layer, the trench separating the first metal layer into first and second portions which are electrically isolated from one another. The first portion of the first metal layer may serve as a ground plane for the first reference ground, and the second portion of the first metal layer may serve as a ground plane for the second reference ground.
[0009] The resistance of the resistor may be less than 50 milli-ohms. Furthermore, the first and second III-N based switches can each be configured to be switched at a frequency of at least 50 kHz. The control circuit may also include an amplifier powered by a voltage supply which is coupled to the second reference ground. The amplifier may have a bandwidth that is greater than a switching frequency of each of the first and second III-N based switches.
[0010] As used herein, two or more contacts or other items such as conductive channels or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, e.g., is about the same, at all times under any bias conditions.
[0011] As used herein, “blocking a voltage” refers to the ability of a transistor, device, or component to prevent significant current, such as current that is greater than 0.001 times the operating current during regular conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, while a transistor, device, or component is blocking a voltage that is applied across it, the total current passing through the transistor, device, or component will not be greater than 0.001 times the operating current during regular conduction. Devices with off-state currents which are larger than this value exhibit high loss and low efficiency, and are typically not suitable for many applications.
[0012] As used herein, a “high-voltage device”, e.g., a high-voltage switching transistor, is an electronic device which is optimized for high-voltage switching applications. That is, when the transistor is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, or about 1200V or higher, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, e.g., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block all voltages between 0V and at least Vmax, where Vmax is the maximum voltage that can be supplied by the circuit or power supply, and Vmax can for example be 300V, 600V, 1200V, or other suitable blocking voltage required by the application.
[0013] As used herein, a “III-Nitride” or “III-N device” is a device based on III-N materials. The III-N device can be designed to operate as an enhancement-mode (E-mode) transistor device, such that the threshold voltage of the device (i.e., the minimum voltage that must be applied to the gate relative to the source in order to turn the device on) is positive. Alternatively, the III-N device can be a depletion-mode (D-mode) device, having a negative threshold voltage. The III-N device can be a high-voltage device suitable for high voltage applications. In such a high-voltage device, when the device is biased off (e.g., the voltage on the gate relative to the source is less than the device threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high-voltage in the application in which the device is used, which for example may be 100V, 300V, 600V, 1200V, 1700V, or higher. When the high voltage device is biased on (e.g., the voltage on the gate relative to the source is greater than the device threshold voltage), it is able to conduct substantial current with a low on-voltage. The maximum allowable on-voltage is the maximum voltage that can be sustained in the application in which the device is used.
[0014] Bridgeless power factor correction circuits are described herein. In particular implementations, methods and configurations for sensing the boost inductor current are described. The details of one or more disclosed implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims.
Description of Drawings
[0015] FIGS. 1A and 1B are circuit schematics of Totem Pole bridgeless power factor correction (PFC) circuits.
[0016] FIGS. 2A-2D illustrate the fundamental operating principles of the PFC circuit of FIG. 1B .
[0017] FIGS. 3-4 are circuit schematics of bridgeless PFC circuits which are configured to allow for sensing of the inductor current.
[0018] FIG. 5 is a cross-sectional view of a III-N transistor.
[0019] FIGS. 6A and 6B illustrate a plan view (top view) and circuit schematic, respectively, of a hybrid electronic device.
[0020] FIG. 7 is an exploded view of an example PCB board that a PFC circuit can be mounted on.
[0021] FIGS. 8-10 are circuit schematics of bridgeless PFC circuits which are configured to allow for sensing of the inductor current.
[0022] Like reference symbols in the various drawings indicate like elements.
Detailed Description
[0023] FIGS. 1A and 1B illustrate circuit schematics of Totem Pole bridgeless power factor correction (PFC) circuits. In the PFC circuit of FIG. 1A , the AC input voltage supply 102 (Vac) is at one end electrically connected to a node 126 (VD) between diodes 132 (D1) and 134 (D2) and at an opposite end electrically connected to or electrically coupled to the first end of an inductive component 142 (L), e.g., an input inductor or boost inductor. The opposite end of the inductive component 142 is electrically connected to or electrically coupled to a node 128 (VS) between active switches 136 (S1) and 138 (S2). The anode of diode 134 and the source of switch 138 are electrically connected to or electrically coupled to a low side node 122 of the circuit. The cathode of diode 132 and the drain of switch 136 are electrically connected to or electrically coupled to a high side node 124 of the circuit. The output capacitor 144 (C) which is charged by the circuit also has a first end connected to the high side node 124 and an opposite end connected to the low side node 122. The circuit of FIG. 1A utilizes diodes 132 and 134 for line frequency rectification. The circuit of FIG. 1B is the same as that of FIG. 1A , except that diodes 132 and 134 are replaced by switches 133 (SD1) and 135 (SD2) so that line frequency synchronous rectification can be performed, thereby decreasing losses and improving circuit efficiency.
[0024] FIGS. 2A-2B illustrate the fundamental operating principles of the PFC circuit of FIG. 1B during the positive AC line half-cycle, while current flows from the AC voltage supply 102 into the inductive component 142. During the positive AC line half-cycle, current 210 flows from low side node 122 up through switch 135, and then through the AC voltage supply 102 and the inductive component 142. During this cycle, switch 133 is biased OFF, and switch 135 may be biased ON or OFF, although it is preferable for switch 135 to be biased ON in order to reduce conduction losses through the switch. Switch 138 is actively switched in order to control whether the current flows back down to node 122 (as in FIG. 2A ) or up to node 124 and charges the capacitor 144 (as in FIG. 2B ). As illustrated in FIG. 2A , when switch 136 is biased OFF (i.e., the gate of switch 136 is biased relative to the source of switch 136 at a voltage that is less than the threshold voltage of switch 136) and switch 138 is biased ON (i.e., the gate of switch 138 is biased relative to the source of switch 138 at a voltage that is larger than the threshold voltage of switch 138), the current 210 flows downward through switch 138, and switch 136 blocks a voltage which is about equal to the voltage difference between nodes 124 and 122. Referring to FIG. 2B , when switch 138 is switched OFF, the current flows upwards through switch 136, and switch 138 blocks a voltage which is about equal to the voltage difference between nodes 124 and 122. After switch 138 has been switched OFF and while current flows through switch 136, switch 136 may be switched ON in order to reduce conduction losses through switch 136.
[0025] FIGS. 2C-2D illustrate the fundamental operating principles of the PFC circuit of FIG. 1B during the negative AC line half-cycle, while current 210 flows from the inductive component 142 into the AC voltage supply 102. During the negative AC line half-cycle, current 210 flows through the inductive component 142 into the AC voltage supply 102, and then upwards through switch 133. During this cycle, switch 135 is biased OFF, and switch 133 may be biased ON or OFF, although it is preferable for switch 133 to be biased ON in order to reduce conduction losses through the switch. Switch 136 is actively switched in order to control whether the current flowing into the inductive component 142 flows upwards from node 122 through switch 138 (as in FIG. 2D ) and charges the capacitor 144, or downwards from node 124 through switch 136 (as in FIG. 2C ). As illustrated in FIG. 2C , when switch 138 is biased OFF and switch 136 is biased ON, the current 210 flows downward through switch 136, and switch 138 blocks a voltage which is about equal to the voltage difference between nodes 124 and 122. Referring to FIG. 2D , when switch 136 is switched OFF, the current 210 flows upwards through switch 138, and switch 136 blocks a voltage which is about equal to the voltage difference between nodes 124 and 122. After switch 136 has been switched OFF and while current 210 flows through switch 138, switch 138 may be switched ON in order to reduce conduction losses through switch 136.
[0026] Referring to the PFC circuit of FIGS. 1B and 2A-2D , node 122 functions as the reference ground for the DC output voltage of the PFC circuit (i.e., the voltage across the capacitor 144), and node 124 functions as the DC high voltage node. The voltage between nodes 124 and 122 is then utilized as a DC output voltage to power the load 146 (RL). In some implementations, node 122 is connected to an earth ground, while in other implementations it is left floating and functions as a floating reference ground.
[0027] The voltage signals applied to the gates of switches 136 and 138 are provided by a first DC voltage supply. In the case of switch 136, the voltage from the first DC voltage supply applied to the gate of switch 138, is referenced to the reference ground (node 122).
[0028] In order for the PFC circuit of FIGS. 1B and 2A-2D to operate properly, the switches 136 and 138 control the input current to be in phase with the AC input voltage. To achieve this operation, it may be necessary to sense the input current 210.
[0029] Referring now to FIG. 3 , a first method of sensing the inductor current includes connecting a high bandwidth isolated current sensor 304, such as a Hall sensor, in series with the inductive component 142 (e.g., between the AC voltage supply 102 and the inductor 142). However, Hall sensors tend to be very expensive and have a limited bandwidth, and so a more cost-efficient and agile solution may be desirable. The sensor 304 could alternatively be a current transformer (CT). However, due to the 50/60 Hz line current, the magnetic core of the CT will be very large and expensive, and could still have saturation problems if there is an imbalance in the AC line current.
[0030] FIG. 4 illustrates a second configuration for sensing the inductor current. In the configuration of FIG. 4 , a resistor 404 is placed in series with the inductive component 142 and the AC voltage supply 102 (e.g., between the AC voltage supply 102 and the inductor 142), and the voltage across the resistor 404 is amplified and sensed by a control circuit 430. However, due to the positioning of the resistor 404 in the circuit, sensing the absolute voltage at the node between the resistor 404 and inductive component 142 (relative to reference ground 122) does not result in a meaningful measurement for determining the inductor current. Instead, a second reference ground 422 (also referred to as a control ground) which is electrically isolated from the reference ground 122 is provided on an opposite side of the resistor 404 from the control circuit 430. An amplifier (not shown) within the control circuit 430 is powered by a voltage supply 432 (Vcc) which is coupled (or referenced) to the second reference ground 422 (via node 422′, which is electrically connected to node 422), and the voltage supply 434 (Vg) which supplies control signals to the gate of switch 138 is coupled (or referenced) to the first reference ground 122 (via node 122′, which is electrically connected to node 122).
[0031] In order to achieve high performance and high circuit efficiency, switches 136 and 138 can be provided as devices that have low reverse recovery charge Qrr and are capable of being switched at high frequencies. For example, switches 136 and 138 can be capable of being switched at frequencies of at least 50 kHz, at least 80 kHz, or at least 100 kHz without sustaining substantial switching losses. Traditional high power switching devices which are capable of blocking high voltages, such as IGBT's and power MOSFETs, which are typically silicon-based devices, experience switching losses at these frequencies that are greater than can be tolerated. These devices also inherently include parasitic diodes anti-parallel to their channels. On the other hand, III-Nitride or III-N field effect transistors, such as the III-N HEMT shown in FIG. 5 , are capable of blocking the required high voltages while inherently being capable of higher switching speeds than a traditional IGBT or power MOS device. High voltage III-N devices, for example III-N HEMTs, have lower reverse recovery charge in their semiconductor portions, as well as lower junction capacitances as compared to traditional IGBTs or power MOSFETs. They have been demonstrated to be capable of switching at frequencies which are in some cases at least as high as 1 MHz (1000 kHz), but typically greater than 80 kHz, greater than 100 kHz, greater than 300 kHz, or greater than 500 kHz, depending on the specific design.
[0032] In some implementations switches 136 and 138 are III-N devices, such as the III-N high electron mobility transistor (HEMT) illustrated in FIG. 5 . A typical III-Nitride HEMT, which is illustrated in FIG. 5 , includes a substrate 500 (e.g., a silicon substrate), a III-N buffer layer 502 formed of a III-N semiconductor material such as AlN or AlGaN, a III-N channel layer 506 formed of a III-N semiconductor material such as GaN, a III-N barrier layer 508 formed of a III-N semiconductor material (e.g., AlGaN or AlN) having a larger bandgap than that of the III-N channel layer 506, and a two-dimensional electron gas (2DEG) channel 516 formed in the III-N channel layer 506 adjacent to the III-N barrier layer 508, the 2DEG channel 516 serving as the conductive channel of the transistor. The III-N HEMT further includes source and drain contacts 510 and 512, respectively, which contact the 2DEG channel 516. A gate electrode 514, which is deposited between the source and drain contacts 510 and 512, is used to modulate the conductivity of the channel in the region directly below the gate electrode 514. Optionally, a gate insulator 520 is included between the gate electrode 514 and the underlying III-N semiconductor materials.
[0033] In some implementations, the III-N HEMT of FIG. 5 is an enhancement-mode device, having a threshold voltage greater than 0V. That is, in order to turn the device ON, a sufficiently positive voltage (e.g., greater than the device threshold voltage) must be applied to the gate 514 relative to the source 510. When 0V is applied to the gate 514 relative to the source, the device is in the OFF state.
[0034] Other devices which can inherently be switched at high frequencies could alternatively be used for switches 136 and 138. For example, a hybrid device 607, shown in FIGS. 6A and 6B , could be used for switches 136 and 138. Although the switches 136 and 138 could be depletion-mode (D-mode) devices, it is often preferable that switches 136 and 138 be enhancement-mode or E-mode devices. That is, the switch is in the OFF state when the control terminal is held at the same voltage as the low-side terminal, and is turned ON by switching the voltage at the control terminal to a sufficiently high positive voltage relative to the low-side terminal. Since single high-voltage enhancement-mode transistors can be difficult to fabricate reliably, one alternative to a single high-voltage E-mode transistor is to combine a high-voltage depletion-mode transistor 608 with a low-voltage E-mode transistor 609 in the configuration of FIGS. 6A and 6B to form a hybrid device 607. Hybrid device 607 can be operated in the same way as a single high-voltage E-mode transistor, and in many cases achieves the same or similar output characteristics as a single high-voltage E-mode transistor. FIG. 6A shows a plan view schematic diagram of hybrid device 607, and FIG. 6B shows a circuit schematic of hybrid device 607. Hybrid device 607 includes a high-voltage D-mode transistor 608 and a low-voltage E-mode transistor 609. In the configuration illustrated in FIGS. 6A and 6B , E-mode transistor 609 is a vertical transistor, having its drain electrode 613 on the opposite side of the device from its source electrode 611 and gate electrode 612, and D-mode transistor 608 is a lateral transistor, having its source electrode 614, gate electrode 615, and drain electrode 616 all on the same side of the device. However, other configurations for each of transistors 608 and 609 are possible as well.
[0035] The source electrode 611 of the low-voltage E-mode transistor 609 and the gate electrode 615 of the high-voltage D-mode transistor 608 are both electrically connected together, for example with wire bonds 669, and together form the source 621 of the hybrid device 607. The gate electrode 612 of the low-voltage E-mode transistor 609 forms the gate 622 of the hybrid device 607. The drain electrode 616 of the high-voltage D-mode transistor 608 forms the drain 623 of the hybrid device 607. The source electrode 614 of the high-voltage D-mode transistor 608 is electrically connected to the drain electrode 613 of the low-voltage E-mode transistor 609. As seen in FIG. 6A , drain electrode 613, which is on the opposite side of the E-mode transistor 609 from the source and drain electrodes 611 and 612, respectively, can be electrically connected to source electrode 614 by mounting the low-voltage E-mode transistor 609 directly on top of the source electrode 614 with the drain electrode 613 directly contacting the source electrode 614, for example by using a conductive solder or resin. As such, the footprint (and therefore the cross-sectional area) of the low-voltage E-mode transistor 609 can be smaller than that of the high-voltage D-mode transistor 608, and in particular the footprint of the low-voltage E-mode transistor 609 can be smaller than that of the source electrode 614 of high-voltage D-mode transistor 608.
[0036] As used herein, a “hybrid enhancement-mode electronic device or component”, or simply a “hybrid device or component”, is an electronic device or component formed of a depletion-mode transistor and an enhancement-mode transistor, where the depletion-mode transistor is capable of a higher operating and/or breakdown voltage as compared to the enhancement-mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement-mode transistor with a breakdown and/or operating voltage about as high as that of the depletion-mode transistor. That is, a hybrid enhancement-mode device or component includes at least 3 nodes having the following properties. When the first node (source node) and second node (gate node) are held at the same voltage, the hybrid enhancement-mode device or component can block a positive high voltage (i.e., a voltage larger than the maximum voltage that the enhancement-mode transistor is capable of blocking) applied to the third node (drain node) relative to the source node. When the gate node is held at a sufficiently positive voltage (i.e., greater than the threshold voltage of the enhancement-mode transistor) relative to the source node, current passes from the source node to the drain node or from the drain node to the source node when a sufficiently positive voltage is applied to the drain node relative to the source node. When the enhancement-mode transistor is a low-voltage device and the depletion-mode transistor is a high-voltage device, the hybrid component can operate similarly to a single high-voltage enhancement-mode transistor. The depletion-mode transistor can have a breakdown and/or maximum operating voltage that is at least two times, at least three times, at least five times, at least ten times, or at least twenty times that of the enhancement-mode transistor.
[0037] As used herein, a “high-voltage device”, such as a high-voltage transistor, is an electronic device which is optimized for high-voltage switching applications. That is, when the transistor is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, about 1200V or higher, or about 1700V or higher, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, i.e., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, or other suitable blocking voltage required by the application. In other words, a high-voltage device can block any voltage between 0V and at least Vmax, where Vmax is the maximum voltage that could be supplied by the circuit or power supply. In some implementations, a high-voltage device can block any voltage between 0V and at least 2*Vmax. As used herein, a “low-voltage device”, such as a low-voltage transistor, is an electronic device which is capable of blocking low voltages, such as between 0V and Vlow (where Vlow is less than Vmax), but is not capable of blocking voltages higher than Vlow. In some implementations, Vlow is equal to about |Vth|, greater than |Vth|, about 2*|Vth|, about 3*|Vth|, or between about |Vth| and 3*|Vth|, where |Vth| is the absolute value of the threshold voltage of a high-voltage transistor, such as a high-voltage-depletion mode transistor, contained within the hybrid component in which a low-voltage transistor is used. In other implementations, Vlow is about 10V, about 20V, about 30V, about 40V, or between about 5V and 50V, such as between about 10V and 40V. In yet other implementations, Vlow is less than about 0.5*Vmax, less than about 0.3*Vmax, less than about 0.1*Vmax, less than about 0.05*Vmax, or less than about 0.02*Vmax.
[0038] In the hybrid device 607 of FIGS. 6A and 6B , while the high-voltage D-mode transistor 608 typically lacks a parasitic diode anti-parallel to the channel, the low-voltage E-mode transistor 609 may include an intrinsic parasitic anti-parallel diode. Or, an external diode can be connected anti-parallel to the channel. In the case where transistor 609 includes an intrinsic parasitic anti-parallel diode but without an external diode connected in parallel to the parasitic diode, hybrid device 607 operates as follows. In a first mode of operation, when voltage at the drain 623 of the hybrid device (i.e., the drain 616 of D-mode transistor 608) is higher than voltage at the source 621 of the hybrid device (i.e., the source 611 of E-mode transistor 609) and the gate 622 of the hybrid device (i.e., the gate of E-mode transistor 609) is biased relative to the source 621 at a voltage below the threshold voltage of E-mode transistor 609 (i.e., the gate is biased OFF), the hybrid device 607 blocks the drain-source voltage that is across the device. In this mode of operation, the drain source voltage may be as high as (Vs2)/2, and can be even higher immediately after switching due to ringing. In a second mode of operation, when voltage at the drain 623 of the hybrid device is higher than voltage at the source 621 of the hybrid device, and the gate 622 of the hybrid device is biased relative to the source 621 at a voltage above the threshold voltage of E-mode transistor 609 (i.e., the gate is biased ON), the hybrid device conducts substantial current from the drain 623 of the hybrid device to the source 621 of the hybrid device (i.e., in a first direction) through the channels of both transistors 608 and 609. In a third mode of operation, when voltage at the drain 623 of the hybrid device is lower than voltage at the source 621 of the hybrid device, and the gate 622 is biased relative to the source 621 at a voltage below the transistor threshold voltage (i.e., the gate is biased OFF), the hybrid device conducts substantial current from the source 621 of the hybrid device to the drain 623 of the hybrid device (i.e., in a second direction). In this mode of operation, the current conducts through the channel of D-mode transistor 608 and through the parasitic diode of E-mode transistor 609. Since E-mode transistor 609 is a low voltage device, conduction and switching losses incurred due to switching on of the parasitic diode are not as high as those incurred for conduction through a parasitic diode of a high voltage transistor. However, this third mode of operation can still result in conduction losses being too high, and so a fourth mode of operation can be achieved as follows. While the hybrid device is operated in the third mode of operation described above, the gate 622 of the hybrid device is switched ON (i.e., to a voltage that is greater than the hybrid device threshold voltage relative to the voltage at its source). In this fourth mode of operation, current continues to flow through the channel of the D-mode transistor 608 in the second direction, but current in the E-mode transistor 609 flows through the transistor channel rather than through the parasitic diode. Hence, conduction losses are reduced relative to the third mode of operation.
[0039] In a hybrid device in which an external diode is connected anti-parallel to the channel (not shown), the external diode performs the same function as the parasitic diode in the four modes of operation described above.
[0040] In FIGS. 6A and 6B , D-mode transistor 608 can be a III-Nitride transistor, such as a III-N HEMT, and E-mode transistor 609 can be a Silicon-based device, such as a Si MOSFET. Alternatively, E-mode transistor 609 can be a III-N transistor as well. Because E-mode transistor 609 is a low-voltage device, and therefore does not need to be capable of blocking the entire circuit high voltage, it can be made to switch much faster than a high-voltage device formed of the same material.
[0041] Referring back to FIG. 4 , in order to properly sense the inductor current, the bandwidth of the amplifier in the control circuit 430 typically needs to be greater than the switching frequency of switches 136 and 138, for example at least three times the switching frequency of switches 136 and 138. As previously described, it can be preferable for switches 136 and 138 to be switches at high frequencies. For example, the switching frequency of switches 136 and 138 can be at least 50 kHz, and the amplifier of the control circuit 430 can have a bandwidth of at least 120 kHz or at least 150 kHz. However, the larger the bandwidth of the amplifier, the higher the noise. Higher levels of noise require the current sensing resistor 404 to be larger, which can lead to higher losses in the circuit, as further described below.
[0042] It is generally preferable for the current sensing resistor 404 to be as small as possible in order to reduce power loss through the resistor 404. However, in order for the current to be properly sensed, the resistor 404 must be large enough that the root mean squared (rms) voltage across the resistor (which is equal to the product of the resistance of resistor 404 and the rms inductor current) can be accurately measured by the control circuit 430. For a given bandwidth of the amplifier of control circuit 430 (which is selected according to the switching frequency of switches 136 and 138), there is a minimum rms voltage across resistor 404 that can be accurately measured by control circuit 430. Selecting a higher bandwidth amplifier for control circuit 430 increases the noise in the system, and thus necessitates a larger rms voltage drop across resistor 404 in order to obtain an accurate measurement of the inductor current.
[0043] As an example, for a bridgeless PFC circuit in which the switches 136 and 138 are switched at a frequency of 50 kHz, the amplifier in control circuit 430 has a bandwidth of 150 kHz, and the rms inductor current during operation of the circuit is 0.2 Amps, the resistor 404 can typically be in the range of about 2 milli-ohms to 20 milli-ohms, for example about 10 milli-ohms, resulting in an rms voltage across the resistor 404 of between 0.4 mV and 4 mV, for example about 2 mV. If a resistor smaller than about 2 milli-ohms is used, the control circuit 430 may not be capable of accurately sensing the inductor current. If a larger resistor is used, than additional power loss through the resistor 430 is incurred. If a larger rms current is used, for example because the PFC circuit is designed to deliver higher power to the load 146, than a smaller resistor 404 may also be used.
[0044] If the amplifier in control circuit 430 is selected to have a higher bandwidth, which may be necessary if higher switching frequencies for switches 136 and 138 are used, than the minimum rms voltage across resistor 404 that can be accurately measure will be larger, and thus for the same rms current, a larger resistor 404 must be used. In some implementations of the circuit of FIG. 4 , switches 136 and 138 are switched at a frequency of at least 50 kHz, and the resistance of resistor 404 is less than 50 milli-ohms, for example between 5 and 50 milli-ohms.
[0045] The entire circuit of FIG. 4 can be formed on a single printed circuit board (PCB), for example a 4-layer PCB or a 6-layer PCB. An example 4-layer PCB board 700 on which the circuit of FIG. 4 can be formed is illustrated in FIG. 7 . The PCB board 700 includes 4 metal layers 702, 704, 706, and 708, separated from one another by insulating material. Although not shown, layers 702 and 704 can be patterned to form metal trace interconnects between components mounted on the top and/or the bottom of the PCB board. Layer 708 can be a DC power plane, and can be electrically connected to node 124 of FIG. 4 . A trench can be etched through layer 706, which separates layer 706 into two planes (labeled 706 and 706′) which are electrically isolated from one another. Plane 706 can serve as a first ground plane for reference ground 122 in FIG. 4 , and plane 706′ can serve as a second ground plane for reference ground 422 in FIG. 4 .
[0046] Although not shown in FIG. 4 , the circuit can be rearranged such that the connections to reference ground 422 and to the control circuit 430 are reversed. That is, the reference ground 422 could alternatively be connected to the node between the resistor 404 and the inductive component 142, with the control circuit 430 coupled to the node between the resistor 404 and the AC voltage supply 102.
[0047] Using a similar configuration to that of FIG. 4 , current can also be sensed in a two-phase or three-phase interleaved Totem Pole PFC circuit. Such a configuration for a two-phase PFC is shown in FIG. 8 . As seen in FIG. 8 , the reference ground 822 for the current sensing circuit (labeled GND1) is connected to a pair of current sensing resistors 804 and 806, each of which is connected to its own inductive component 142 and 842, respectively. The first inductive component 142 is connected to the node 128 between switches 136 and 138, while the second inductive component 842 is connected to the node 830 between switches 850 and 852. The node 854 between the first inductive component 142 and its associated resistor 804, as well as the node 856 between the second inductive component 842 and its associated resistor 806, are both coupled to the control circuit, which is used to sense the currents passing through both inductors.
[0048] Another way to sense the inductor current in a Totem Pole PFC circuit is to sense the high-frequency pulse currents in switches 136 and 138. By summing these current waveforms, the boost inductor current can be reconstructed. This configuration is illustrated in FIGS. 9-10 . As seen in FIG. 9 , AC current sensors 902 and 904 (e.g., current transformers or Rogowski Coils) can be connected in series with each of switches 136 and 138. Because the currents flowing through switches 136 and 138 are high frequency current pulses, the AC current sensors 902 and 904 can be small sized high frequency AC current sensors. As shown in FIG. 9 , the two sensors can be placed on the drain side of their respective switches 136 and 138, so that the inductance on the sensing coil does not interfere with the driving circuit.
[0049] However, the sensor placement of FIG. 9 may not work in a III-N HEMT-based diode-free bridge. First of all, due to the extremely fast switching speed of III-N based switching devices 136 and 138, unlike conventional power switches (MOSFET, IGBT), the III-N HEMT based bridge may not be able to tolerate excessive inductance introduced by the sensors. The III-N HEMT based bridge may not function properly and/or may not switch properly in such an arrangement. Secondly, high reverse recovery current will flow through the current sensor for a few nanoseconds during the reverse recovery time of the III-N HEMTs. This short, high reverse recovery current pulse may disrupt the proper function of the current sensors.
[0050] An alternative configuration for sensing the high-frequency pulse currents in switches 136 and 138 is shown in FIG. 10 . One or more high frequency decoupling capacitors 912 (CHF) are placed very close to the III-N HEMT based switches, with one end of the capacitor(s) 912 connected to the drain of 136 and an opposite end of capacitor(s) 912 connected to the source of switch 138. The AC current sensors 902 and 904 are placed outside of this high frequency DC-link. In this configuration, the switching of the III-N HEMT based switches is not affected by the parasitic inductances introduced by the two current sensors, as the high reverse recovery pulse currents are drawn from the high frequency decoupling capacitor(s) 912 so that the current sensors will not pick up this high disruptive current. The current sensors 902 and 904, however, sense all the switching frequency current for control purposes. The high frequency capacitor(s) 912 can have a substantially smaller capacitance than the DC output capacitor 914 (labelled Cbulk in FIGS. 9-10 ).
[0051] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.
Claims
What is claimed is:
1. An electronic circuit, comprising:
a first switch and a second switch, wherein a source of the first switch is coupled to a first reference ground and a drain of the second switch is coupled to a DC high voltage node; and
an inductive component connected in series with a resistor and coupled to a node between the first and second switches; and
a first side of the resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the resistor is coupled to a control circuit, the control circuit also being coupled to the second reference ground; wherein
the first switch or the second switch is a III-N based hybrid device.
2. The electronic circuit of claim 1, wherein the III-N based hybrid device comprises a high voltage depletion mode transistor and a low voltage enhancement mode transistor.
3. The electronic circuit of claim 2, wherein the high voltage depletion mode transistor comprises a III-N HEMT and the low voltage enhancement mode transistor comprises a Si MOSFET.
4. The electronic circuit of claim 2, wherein a source electrode of the depletion mode transistor is electrically connected to a drain of the enhancement mode transistor.
5. The electronic circuit of claim 4, wherein the enhancement mode transistor is mounted directly on top of the source electrode of the depletion mode transistor, and the drain of the enhancement mode transistor is directly contacting the source electrode of the depletion mode transistor.
6. The electronic circuit of claim 1, wherein the electronic circuit is a power factor correction circuit.
7. The electronic circuit of claim 1, wherein the control circuit is configured to measure current flowing through the inductive component during operation of the electronic circuit.
8. The electronic circuit of claim 1, wherein the control circuit is configured to measure voltage at the second side of the resistor relative to the second reference ground.
9. The electronic circuit of claim 1, further comprising a printed circuit board including a first metal layer between a second metal layer and a third metal layer, wherein a trench is formed in the first metal layer, the trench separating the first metal layer into first and second portions which are electrically isolated from one another.
10. The electronic circuit of claim 9, wherein the first portion of the first metal layer serves as a ground plane for the first reference ground, and the second portion of the first metal layer serves as a ground plane for the second reference ground.
11. The electronic circuit of claim 1, wherein a resistance of the resistor is less than 50 milli-ohms.
12. The electronic circuit of claim 11, wherein the first and second switches are each capable of blocking 300V or higher.
13. The electronic circuit of claim 1, wherein the control circuit comprises an amplifier powered by a voltage supply which is coupled to the second reference ground.
14. The electronic circuit of claim 13, wherein the amplifier has a bandwidth that is greater than a switching frequency of each of the first and second switches.
15. A method of sensing current in a power factor correction circuit, the power factor correction circuit comprising:
a first switch and a second switch, wherein a source of the first switch is coupled to a first reference ground and a drain of the second switch is coupled to a DC high voltage node; wherein
the first switch or the second switch is a III-N based hybrid device; and
an inductive component connected in series with a resistor and coupled to a node between the first and second switches, wherein a first side of the resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the resistor is coupled to a control circuit, the control circuit including an amplifier which is also coupled to the second reference ground and has a bandwidth that is greater than a switching frequency of each of the first and second switches; the method comprising
amplifying a voltage across the resistor; and
having the control circuit measure the voltage across the resistor.
16. The method of claim 15, wherein a resistance of the resistor is less than 50 milli-ohms.
17. The method of claim 16, wherein the first and second III-N based switches are each configured to be switched at a frequency of at least 50 kHz.
18. The method of claim 17, wherein the amplifier has a bandwidth that is greater than the switching frequency of each of the first and second III-N based switches.
19. The method of claim 15, wherein the III-N based hybrid device comprises a high voltage depletion mode III-N transistor and a low voltage enhancement mode Si MOSFET transistor.
20. The method of claim 19, wherein the enhancement mode transistor is mounted directly on top of a source electrode of the depletion mode transistor, and a drain of the enhancement mode transistor is directly contacting and electrically connected to the source electrode of the depletion mode transistor.
Patent Citations (180)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4321489(A) | 1982-03-01 | Higuchi et al. | Applicant |
| US4384287(A) | 1983-05-01 | Sakuma | Applicant |
| US4665508(A) | 1987-05-01 | Chang | Applicant |
| US4728826(A) | 1988-03-01 | Einzinger et al. | Applicant |
| US4808853(A) | 1989-02-01 | Taylor | Applicant |
| US4864479(A) | 1989-09-01 | Steigerwald et al. | Applicant |
| US5198964(A) | 1993-03-01 | Ito et al. | Applicant |
| US5379209(A) | 1995-01-01 | Goff | Applicant |
| US5493487(A) | 1996-02-01 | Close et al. | Applicant |
| US5637922(A) | 1997-06-01 | Fillion et al. | Applicant |
| US5767573(A) | 1998-06-01 | Noda et al. | Applicant |
| US5789951(A) | 1998-08-01 | Shen et al. | Applicant |
| US5952856(A) | 1999-09-01 | Horiguchi et al. | Applicant |
| US6008684(A) | 1999-12-01 | Ker et al. | Applicant |
| US6107844(A) | 2000-08-01 | Berg | Examiner |
| US6130831(A) | 2000-10-01 | Matsunaga | Applicant |
| US6172550(B1) | 2001-01-01 | Gold et al. | Applicant |
| US6333617(B1) | 2001-12-01 | Itabashi et al. | Applicant |
| US6395593(B1) | 2002-05-01 | Pendharkar et al. | Applicant |
| US6434019(B2) | 2002-08-01 | Baudelot et al. | Applicant |
| US6455905(B1) | 2002-09-01 | Perugupalli et al. | Applicant |
| US6521940(B1) | 2003-02-01 | Vu et al. | Applicant |
| US6556053(B2) | 2003-04-01 | Stanley | Applicant |
| US6633195(B2) | 2003-10-01 | Baudelot et al. | Applicant |
| US6650169(B2) | 2003-11-01 | Faye et al. | Applicant |
| US6781423(B1) | 2004-08-01 | Knoedgen | Applicant |
| US6864131(B2) | 2005-03-01 | Thornton | Applicant |
| US6876235(B2) | 2005-04-01 | Li et al. | Applicant |
| US6900657(B2) | 2005-05-01 | Bui et al. | Applicant |
| US6975023(B2) | 2005-12-01 | Oliver et al. | Applicant |
| US7116567(B2) | 2006-10-01 | Shelton et al. | Applicant |
| US7193396(B2) | 2007-03-01 | Orr | Applicant |
| US7199636(B2) | 2007-04-01 | Oswald et al. | Applicant |
| US7199640(B2) | 2007-04-01 | De Cremoux et al. | Applicant |
| US7212063(B2) | 2007-05-01 | Münzer et al. | Applicant |
| US7227198(B2) | 2007-06-01 | Pavier et al. | Applicant |
| US7239108(B2) | 2007-07-01 | Best | Applicant |
| US7304331(B2) | 2007-12-01 | Saito et al. | Applicant |
| US7348687(B2) | 2008-03-01 | Aichriedler et al. | Applicant |
| US7368980(B2) | 2008-05-01 | Benelbar et al. | Applicant |
| US7375407(B2) | 2008-05-01 | Yanagihara et al. | Applicant |
| US7378883(B1) | 2008-05-01 | Hsueh | Applicant |
| US7382001(B2) | 2008-06-01 | Beach | Applicant |
| US7417257(B2) | 2008-08-01 | Beach et al. | Applicant |
| US7443648(B2) | 2008-10-01 | Cutter et al. | Applicant |
| US7449730(B2) | 2008-11-01 | Kuraguchi | Applicant |
| US7453107(B1) | 2008-11-01 | Kapoor | Applicant |
| US7465997(B2) | 2008-12-01 | Kinzer et al. | Applicant |
| US7477082(B2) | 2009-01-01 | Fukazawa | Applicant |
| US7482788(B2) | 2009-01-01 | Yang | Applicant |
| US7501669(B2) | 2009-03-01 | Parikh et al. | Applicant |
| US7522435(B2) | 2009-04-01 | Kohnotoh et al. | Applicant |
| US7538366(B2) | 2009-05-01 | Saito et al. | Applicant |
| US7547964(B2) | 2009-06-01 | Pavier et al. | Applicant |
| US7548112(B2) | 2009-06-01 | Sheppard | Applicant |
| US7550781(B2) | 2009-06-01 | Kinzer et al. | Applicant |
| US7612602(B2) | 2009-11-01 | Yang et al. | Applicant |
| US7639064(B2) | 2009-12-01 | Hsiao et al. | Applicant |
| US7701009(B2) | 2010-04-01 | Koyama | Applicant |
| US7714360(B2) | 2010-05-01 | Otsuka et al. | Applicant |
| US7719055(B1) | 2010-05-01 | McNutt et al. | Applicant |
| US7745930(B2) | 2010-06-01 | Connah et al. | Applicant |
| US7746020(B2) | 2010-06-01 | Schnetzka et al. | Applicant |
| US7755108(B2) | 2010-07-01 | Kuraguchi | Applicant |
| US7782099(B2) | 2010-08-01 | Kawamura | Applicant |
| US7800215(B2) | 2010-09-01 | Satou et al. | Applicant |
| US7804328(B2) | 2010-09-01 | Pentakota et al. | Applicant |
| US7811872(B2) | 2010-10-01 | Hoshi et al. | Applicant |
| US7825435(B2) | 2010-11-01 | Machida et al. | Applicant |
| US7851825(B2) | 2010-12-01 | Suh et al. | Applicant |
| US7851909(B2) | 2010-12-01 | Mishra et al. | Applicant |
| US7852137(B2) | 2010-12-01 | Machida et al. | Applicant |
| US7855401(B2) | 2010-12-01 | Sheppard et al. | Applicant |
| US7863877(B2) | 2011-01-01 | Briere | Applicant |
| US7875907(B2) | 2011-01-01 | Honea et al. | Applicant |
| US7875914(B2) | 2011-01-01 | Sheppard | Applicant |
| US7884395(B2) | 2011-02-01 | Saito | Applicant |
| US7893676(B2) | 2011-02-01 | Hanna | Applicant |
| US7893791(B2) | 2011-02-01 | Ma et al. | Applicant |
| US7898004(B2) | 2011-03-01 | Wu et al. | Applicant |
| US7898509(B2) | 2011-03-01 | Iida et al. | Applicant |
| US7902809(B2) | 2011-03-01 | Briere et al. | Applicant |
| US7906837(B2) | 2011-03-01 | Cabahug et al. | Applicant |
| US7915643(B2) | 2011-03-01 | Suh et al. | Applicant |
| US7920013(B2) | 2011-04-01 | Sachdev et al. | Applicant |
| US7932539(B2) | 2011-04-01 | Chen et al. | Applicant |
| US7965126(B2) | 2011-06-01 | Honea et al. | Applicant |
| US7973335(B2) | 2011-07-01 | Okamoto et al. | Applicant |
| US7982242(B2) | 2011-07-01 | Goto | Applicant |
| US8013580(B2) | 2011-09-01 | Cervera et al. | Applicant |
| US8018056(B2) | 2011-09-01 | Hauenstein | Applicant |
| US8054110(B2) | 2011-11-01 | Wang et al. | Applicant |
| US8063616(B2) | 2011-11-01 | Bahramian et al. | Applicant |
| US8084783(B2) | 2011-12-01 | Zhang | Applicant |
| US8089139(B2) | 2012-01-01 | Shi et al. | Applicant |
| US8114710(B2) | 2012-02-01 | Muto et al. | Applicant |
| US8188596(B2) | 2012-05-01 | Otremba | Applicant |
| US8193559(B2) | 2012-06-01 | Haeberlen et al. | Applicant |
| US8193562(B2) | 2012-06-01 | Suh et al. | Applicant |
| US8258622(B2) | 2012-09-01 | Lee et al. | Applicant |
| US8264003(B2) | 2012-09-01 | Herman | Applicant |
| US8289065(B2) | 2012-10-01 | Honea et al. | Applicant |
| US8363437(B2) | 2013-01-01 | Wang et al. | Applicant |
| US8384243(B2) | 2013-02-01 | Adest et al. | Applicant |
| US8441128(B2) | 2013-05-01 | Domes | Applicant |
| US8530904(B2) | 2013-09-01 | Treu et al. | Applicant |
| US8592974(B2) | 2013-11-01 | Wu | Applicant |
| US8681518(B2) | 2014-03-01 | Callanan et al. | Applicant |
| US8742460(B2) | 2014-06-01 | Mishra et al. | Applicant |
| US8786327(B2) | 2014-07-01 | Honea | Examiner |
| US9059076(B2) | 2015-06-01 | Wu | Examiner |
| US9543940(B2) | 2017-01-01 | Wang | Examiner |
| US9590494(B1) | 2017-03-01 | Zhou | Examiner |
| US2004/0120090(A1) | 2004-06-01 | Galli | Examiner |
| US2006/0175627(A1) | 2006-08-01 | Shiraishi | Applicant |
| US2007/0164428(A1) | 2007-07-01 | Elbanhawy et al. | Applicant |
| US2007/0210329(A1) | 2007-09-01 | Goto | Applicant |
| US2008/0017998(A1) | 2008-01-01 | Pavio | Applicant |
| US2008/0231211(A1) | 2008-09-01 | Bauman et al. | Applicant |
| US2008/0248634(A1) | 2008-10-01 | Beach | Applicant |
| US2009/0050936(A1) | 2009-02-01 | Oka | Applicant |
| US2009/0072269(A1) | 2009-03-01 | Suh et al. | Applicant |
| US2009/0085219(A1) | 2009-04-01 | Bayerer | Applicant |
| US2009/0278513(A1) | 2009-11-01 | Bahramian et al. | Applicant |
| US2010/0079192(A1) | 2010-04-01 | Strzalkowski | Applicant |
| US2010/0328833(A1) | 2010-12-01 | Frisch et al. | Applicant |
| US2011/0169549(A1) | 2011-07-01 | Wu | Applicant |
| US2011/0298383(A1) | 2011-12-01 | Muehlschlegel | Applicant |
| US2012/0306464(A1) | 2012-12-01 | Hirler et al. | Applicant |
| US2013/0033240(A1) | 2013-02-01 | Ye | Applicant |
| US2013/0222045(A1) | 2013-08-01 | Wu | Applicant |
| US2016/0006428(A1) | 2016-01-01 | Wang | Examiner |
| CN1682445 | 2005-10-01 | Applicant | |
| CN1921148 | 2007-02-01 | Applicant | |
| CN101978589 | 2011-02-01 | Applicant | |
| CN102165694 | 2011-08-01 | Applicant | |
| CN102308387 | 2012-01-01 | Applicant | |
| CN103477543 | 2013-12-01 | Applicant | |
| EP2188842 | 2010-05-01 | Applicant | |
| EP2243213 | 2010-10-01 | Applicant | |
| EP2394303 | 2011-12-01 | Applicant | |
| JP5-075040 | 1993-03-01 | Applicant | |
| JP6-067744 | 1994-03-01 | Applicant | |
| JP2000-101356 | 2000-04-01 | Applicant | |
| JP2000-124358 | 2000-04-01 | Applicant | |
| JP2003-243612 | 2003-08-01 | Applicant | |
| JP2003-244943 | 2003-08-01 | Applicant | |
| JP2003-338742 | 2003-11-01 | Applicant | |
| JP2004-281454 | 2004-10-01 | Applicant | |
| JP2006-033723 | 2006-02-01 | Applicant | |
| JP2006-173754 | 2006-06-01 | Applicant | |
| JP2006-223016 | 2006-08-01 | Applicant | |
| JP2007-036218 | 2007-02-01 | Applicant | |
| JP2007-215331 | 2007-08-01 | Applicant | |
| JP2007-252055 | 2007-09-01 | Applicant | |
| JP2007-294769 | 2007-11-01 | Applicant | |
| JP2008-187167 | 2008-08-01 | Applicant | |
| JP2008-198735 | 2008-08-01 | Applicant | |
| JP2008-199771 | 2008-08-01 | Applicant | |
| JP2009-218475 | 2009-09-01 | Applicant | |
| JP2010-539712 | 2010-12-01 | Applicant | |
| JP2011-512119 | 2011-04-01 | Applicant | |
| JP2012-517699 | 2012-08-01 | Applicant | |
| KR10-1998-0021826 | 1998-06-01 | Applicant | |
| TW200941920 | 2009-10-01 | Applicant | |
| TW201027912 | 2010-07-01 | Applicant | |
| TW201036155 | 2010-10-01 | Applicant | |
| TW201126686 | 2011-08-01 | Applicant | |
| TW201143017 | 2011-12-01 | Applicant | |
| TW201332085 | 2013-08-01 | Applicant | |
| TW201347143 | 2013-11-01 | Applicant | |
| WO2009/036181 | 2009-03-01 | Applicant | |
| WO2009/036266 | 2009-03-01 | Applicant | |
| WO2009/102732 | 2009-08-01 | Applicant | |
| WO2010/039463 | 2010-04-01 | Applicant | |
| WO2010/090885 | 2010-08-01 | Applicant | |
| WO2011/053981 | 2011-05-01 | Applicant | |
| WO2011/085260 | 2011-07-01 | Applicant | |
| WO2011/097302 | 2011-08-01 | Applicant | |
| WO2013/085839 | 2013-06-01 | Applicant |
Non-Patent Literature (49)
- Authorized officer Keon Hyeong Kim, International Search Report and Written Opinion in PCT/US2008/076160 dated Mar. 18, 2009, 11 pages.Applicant
- Authorized officer Simin Baharlou, International Preliminary Report on Patentability in PCT/US2008/076160, dated Mar. 25 2010, 6 pages.Applicant
- Authorized officer Jae Woo Wee, International Search Report and Written Opinion in PCT/US2009/033699, dated Sep. 21, 2009, 11 pages.Applicant
- Authorized officer Dorothée Mülhausen, International Preliminary Report on Patentability in PCT/US2009/033699, dated Aug. 26, 2010, 6 pages.Applicant
- Authorized officer Sung Hee Kim, International Search Report and the Written Opinion in PCT/US2009/057554, dated May 10, 2010, 13 pages.Applicant
- Authorized Officer Gijsbertus Beijer, International Preliminary Report on Patentability in PCT/US2009/057554, dated Mar. 29, 2011, 7 pages.Applicant
- Authorized officer Sung Chan Chung, International Search Report and Written Opinion for PCT/US2010/021824, dated Aug. 23, 2010, 9 pages.Applicant
- Authorized officer Beate Giffo-Schmitt, International Preliminary Report on Patentability in PCT/US2010/021824, dated Aug. 18, 2011, 6 pages.Applicant
- Authorized officer Bon Gyoung Goo, International Search Report and Written Opinion in PCT/US2010/055129, dated Jul. 1, 2011, 11 pages.Applicant
- Authorized officer Yolaine Cussac, International Preliminary Report on Patentability in PCT/US2010/055129, dated May 18, 2012, 6 pages.Applicant
- Authorized officer Sung Joon Lee, International Search Report and Written Opinion in PCT/US2011/020592, dated Sep. 19, 2011, 9 pages.Applicant
- Authorized officer Philippe Bécamel, International Preliminary Report on Patentability in PCT/US2011/020592, dated Jul. 19, 2012, 7 pages.Applicant
- Authorized officer Kee Young Park, International Search Report and Written Opinion in PCT/US2011/023485, dated Sep. 23 2011, 10 pages.Applicant
- Authorized officer Nora Lindner, International Preliminary Report on Patentability in PCT/US2011/023485, dated Aug. 16, 2012, 7 pages.Applicant
- Authorized officer Kwak In Gu, International Search Report and Written Opinion in PCT/US2012/026810, dated Jan. 23, 2013, 10 pages.Applicant
- Authorized officer Lingfei Bai, International Preliminary Report on Patentability in PCT/US2012/026810, dated Sep. 12, 2013, 6 pages.Applicant
- Authorized officer Sang Won Choi, International Search Report and Written Opinion in PCT/US2013/027294, dated Jun. 26, 2013, 10 pages.Applicant
- Authorized officer Kihwan Moon, International Preliminary Report on Patentability in PCT/US2013/027294, dated Sep. 4, 2014, 7 pages.Applicant
- Authorized officer Sung Gon Kim, International Search Report and Written Opinion in PCT/US2014/032241, dated Aug. 11, 2014, 12 pages.Applicant
- Authorized officer Hye Lyun Park, International Search Report and Written Opinion in PCT/US2014/045137, dated Oct. 16, 2014, 9 pages.Applicant
- Search Report and Action in TW Application No. 098132132, dated Dec. 6, 2012, 8 pages.Applicant
- Search Report and Action in TW Application No. 098141930, dated Jul. 10, 2014, 7 pages.Applicant
- Chinese Third Office Action in Application No. 200980110230.0, dated Jan. 24, 2014, 18 pages.Applicant
- Japanese Office Action in Application No. 2010-546867, dated Sep. 24, 2013, 14 pages.Applicant
- Chen et al., “Single-Chip Boost Converter Using Monolithically Integrated AlGan/GaN Lateral Field-Effect Rectifier and Normally Off HEMT,” IEEE Electron Device Letters, May 2009, 30(5):430-432.Applicant
- Choi et al., “AN-9005 Driving and Layout Design for Fast Switching Super-junction MOSFETs,” 0 2013 Fairchild Corporation, 13 pages.Applicant
- Huselstein et al., “Use of the MOSFET Channel Reverse Conduction in an Inverter for Suppression of the Integral Diode Recovery Current” 1993, The European Power Electronics Association, pp. 431-436.Applicant
- Napierala et al., “Selective GaN Epitaxy on Si(111) Substrates Using Porous Aluminum Oxide Buffer Layers,” Journal of the Electrochemical Society, 2006. 153(2):G125-G127, 4 pages.Applicant
- Rodriguez et al, “Tutorial on Multilevel Converters,” International Conference on Power Electronics and Intelligent Control for Energy Conservation, Warsaw, Poland, Oct. 17-19, 2005, 148 pages.Applicant
- Wu et al., “A 97.8% Efficient GaN HEMT Boost Converter with 300-W Output Power at 1 MHz,” Electronic Device Letters, 2008, IEEE, 29(8):824-826.Applicant
- Jenkins et al., “The Impact of Parallel GaN HEMTs on Efficiency of a 12-to-1 V Buck Converter,” Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2013 IEEE, pp. 197-200.Applicant
- Liu et al., Design of a 2 MW DC Supply Using a 4-stage Interleaved DC-DC Converter, In Proc. Energy Conversion Congress and Exposition Sep. 2014 IEEE, pp. 964-970.Applicant
- Liu et al., “Design and Evaluation of GaN-based Dual-phase Interleaved MHz Critical Mode PFC Converter,” In Proc. Energy Conversion Congress and Exposition (ECCE), Sep. 2014 IEEE, pp. 611-616.Applicant
- Liu et al., “Topology, Cost and Efficiency Comparisons of a 2 MW DC Supply Using Interleaved DC-DC Converter,” In Proc. IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG), Jun. 2014, 6 pages.Applicant
- Reusch and Strydom, “Improving Performance of High Speed GaN Transistors Operating in Parallel for High Current Applications,” PCIM Europe May 20-22, 2014; In Proc. International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management pp. 302-309.Applicant
- Silicon Labs, Datasheet of Si823x (2015) [online]; available at www.silabs.com, 57 pages.Applicant
- Waffler and Kolar, “Efficiency Optimization of an Automotive Multi-phase Bi-directional DC-DC Converter,” In Proc. 6th International Power Electronics and Motion Control Conference IPEMC '09, May 17-20, 2009, pp. 566-572.Applicant
- Wang et al., “Investigation of Driver Circuits for GaN HEMTs in Leaded Packages,” Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2014 IEEE, pp. 81-87.Applicant
- Wu, “Paralleling High-speed GaN Power HEMTs for Quadrupled Power Output,” Applied Power Electronics Conference and Exposition (APEC), 2013, pp. 211-214.Applicant
- Wu et al., “High-frequency, GaN Diode-free Motor Drive Inverter with Pure Sine Wave Output,” PCIM Europe 2012, Conference Digest, pp. 40-43.Applicant
- Wu et al., “Total GaN Solution to Electrical Power Conversion,” the 69th IEEE Device Research Conference, Conference Digest, Jun. 20-22, 2011, pp. 217-218.Applicant
- Xu et al., “Investigation of 600 V GaN HEMTs for High Efficiency and High Temperature Applications,” Applied Power Electronics Conference and Exposition (APEC), Apr. 2014, pp. 131-136.Applicant
- Zhang et al., “Common-mode Circulating Current Control of Paralleled Interleaved Three-phase Two-level Voltage-source Converters with Discontinuous Space-vector Modulation,” IEEE Transactions on Power Electronics, Dec. 2011, 26(12):3925-3935.Applicant
- Zhang et al., “Evaluation of 600 V Cascode GaN HEMT in Device Characterization and All-GaN-based LLC Resonant Converter,” In Proc. Energy Conversion Congress and Exposition (ECCE), Sep. 2013 IEEE, pp. 3571-3578.Applicant
- Zhang et al., “Gate Drive Design Considerations for High Voltage Cascode GaN HEMT,” Applied Power Electronics Conference and Exposition (APEC), Mar. 2014, pp. 1484-1489.Applicant
- Zhang et al., “Impact of Interleaving on AC Passive Components of Paralleled Three-phase Voltage-source Converters,” IEEE Transactions on Industry Applications, May/Jun. 2010, 46(3): 1042-1054.Applicant
- Zhou and Wu, “99% Efficiency True-bridgeless Totem-pole PFC Based on GaN HEMTs,” PCIM Europe May 14-16, 2013, pp. 1017-1022.Applicant
- Authorized officer Athina Nickitas-Etienne, International Preliminary Report on Patentabililty in PCT/US2014/032241, dated Oct. 15, 2015, 9 pages.Applicant
- Authorized officer Agnès Wittmann-Regis, International Preliminary Report on Patentability in PCT/US2014/045137, dated Jan. 21, 2016, 6 pages.Applicant