US 8,895,423 B2Grant

Method for making semiconductor diodes with low reverse bias currents

Issue Date:2014-11-25

•39 Claims

•13 Drawing Sheets

Abstract

A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Metadata

Assignee

Transphorm Inc.

Inventor

Yuvaraj Dora

Application Information

Application Number:US 14/288,682

Filing Date:2014-05-28

Priority Date:2011-03-04

Art Unit:2898

Classifications

IPC:

H01L21/28H01L21/322H01L21/44H01L29/66H01L29/47

Field of Search:

H01L 21/28008H01L 21/28H01L 21/283

Patent Drawings (13 sheets)

Description

Cross-Reference to Related Application

[0001] This application is a continuation application of U.S. patent application Ser. No. 13/040,524, filed Mar. 4, 2011, the disclosure of which is hereby incorporated by reference in its entirety.

Technical Field

[0002] This invention relates to semiconductor electronic devices, specifically diodes based on semiconductor heterojunctions.

Background

[0003] Diodes are used in a wide range of electronic circuits. Diodes used in circuits for high voltage switching applications ideally require the following characteristics. When biased in the reverse direction (i.e., the cathode is at a higher voltage than the anode), the diode should be able to support a large voltage while allowing as little current as possible to pass through. The amount of voltage that must be supported depends on the application; for example, many high power switching applications require diodes that can support a reverse bias of at least 600V or at least 1200V without passing a substantial amount of current. When current flows through the diode in the forward direction (from anode to cathode), the forward voltage drop across the diode V_onshould be as small as possible to minimize conduction losses, or in other words the diode's on-resistance R_onshould be as small as possible. Finally, the amount of charge stored in the diode when it is reverse biased should be as small as possible to reduce transient currents in the circuit when the voltage across the diode changes, since reduced transient currents result in reduced switching losses.

[0004] In diodes, there is typically a trade-off between the various characteristics described above. For example, silicon Schottky diodes can typically exhibit excellent switching speed and on-state performance, but suffer from large reverse leakage currents, making them unsuitable for high voltage applications. Conversely, high voltage Si PIN diodes can support large reverse bias voltages with low leakage, but typically exhibit high conduction and switching losses. Further, reverse recovery currents in PIN diodes add to these losses when the PIN diodes are incorporated into circuits.

[0005] FIG. 1 shows a cross-sectional view of a prior art III-N semiconductor heterostructure diode. As used herein, the terms III-N or III-Nitride materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula Al_xIn_yGa_zN, where x+y+z is about 1. The diode structure includes a substrate 20, a first III-N semiconductor layer 22 on top of the substrate, and a second III-N semiconductor layer 24 on top of the first III-N layer. III-N layers 22 and 24 have different compositions from one another, the compositions selected such that a two-dimensional electron gas (2DEG) 26 (illustrated by a dashed line) is induced in the first III-N layer 22 near the interface between the first and second III-N layers 22 and 24. An anode contact 27 (or a plurality of anode contacts, not shown) are formed on top of surface 25 of the second III-N layer 24, and a single cathode contact 28 is formed which contacts the 2DEG 26. The anode contact 27 is a Schottky contact, and the single cathode contact 28 is an ohmic contact.

[0006] Anode and cathode contacts 27 and 28, respectively, may be any arbitrary shape, although the shape can be optimized to minimize the on-resistance R_onof the device. Further, the choice of metals for the contacts, especially that of the anode contact 27, can affect the forward operating voltage V_on(also known as the on-voltage) of the device. It is desirable to provide diodes for which high blocking voltages and low reverse leakage currents can be achieved while at the same time maintaining lower on-resistance and control of the forward operating voltage. Diode structures which can easily be integrated with other circuit components, such as transistors, are desirable for process integration and cost reduction.

Summary

[0007] In one aspect, a diode is described that includes a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, and a dielectric layer. The first terminal is an anode adjacent to the III-N material structure, and the second terminal is a cathode in ohmic contact with the electrically conductive channel. The dielectric layer is over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer, the intermediary electrically conductive structure reducing a shift in an on-voltage or reducing a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer.

[0008] In another aspect, a diode having a threshold voltage is described. The diode includes a III-N material structure, an anode and a cathode on the III-N material structure, and a dielectric encapsulation layer over at least a portion of the anode. A reverse bias current of the diode per unit width of the anode is less than 1 microamp/mm during reverse bias operation.

[0009] In yet another aspect, a diode is described that includes a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, and a dielectric encapsulation layer. The first terminal is an anode adjacent to the III-N material structure, and the second terminal is a cathode in ohmic contact with the electrically conductive channel. The dielectric encapsulation layer is over at least a portion of the anode, a portion of the cathode, and a surface of the III-N material structure between the anode and the cathode. The dielectric encapsulation layer protects the diode from contaminants in the surrounding environment. A shift in an on-voltage of the diode resulting from inclusion of the dielectric encapsulation layer is less than 0.1V.

[0010] In still another aspect, a diode is described that includes a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, and a dielectric encapsulation layer. The first terminal is an anode adjacent to the III-N material structure, and the second terminal is a cathode in ohmic contact with the electrically conductive channel. The dielectric encapsulation layer is over at least a portion of the anode, a portion of the cathode, and a surface of the III-N material structure between the anode and the cathode. The dielectric encapsulation layer serves to protect the diode from contaminants in the surrounding environment, and a reverse bias current of the diode is less than ten times that of a similar diode which lacks the dielectric encapsulation layer.

[0011] Implementations may include one or more of the following features. The III-N material structure can include a first III-N material layer and a second III-N material layer, and the electrically conductive channel can be a 2DEG channel induced in a region of the first III-N material layer adjacent the second III-N material layer as a result of a compositional difference between the first III-N material layer and the second III-N material layer. The first III-N material layer can be GaN. The second III-N material layer can be AlGaN or AlInGaN. The diode can include a third III-N material layer between the first III-N material layer and the second III-N material layer. The third III-N material layer can be AlN. The first III-N material layer and the second III-N material layer can be group III-face or [0 0 0 1] oriented or group-III terminated semipolar layers, and the second III-N material layer can be between the first III-N material layer and the dielectric layer. The first III-N material layer and the second III-N material layer can be N-face or [0 0 0 1bar] oriented or nitrogen-terminated semipolar layers, and the first III-N material layer can be between the second III-N material layer and the dielectric layer. The diode can include a recess in the III-N material structure, wherein at least a portion of the anode is in the recess. The recess can extend through the 2DEG channel. The recess can extend at least 30 nanometers into the III-N material structure. The diode can include an electrode-defining layer which is on a side of the recess and is between the III-N material structure and the dielectric layer. The electrode-defining layer can be SiN. The diode can include a dielectric passivation layer between the III-N material structure and the electrode-defining layer, the dielectric passivation layer contacting a surface of the III-N material structure between the anode and the cathode. The dielectric passivation layer can be SiN. The diode can include an additional insulating layer between the dielectric passivation layer and the electrode-defining layer. The additional insulating layer can be AlN. The additional insulating layer can be less than about 20 nanometers thick. The anode can include an extending portion which is over a surface of the electrode-defining layer. The recess in the electrode-defining layer can include a step, and the anode is over the step. The extending portion of the anode can function as a field plate. The diode can include a field plate connected to the anode. The dielectric layer can be SiN_x. The dielectric layer can be between about 0.2 microns and 20 microns thick. The dielectric layer can include a first dielectric layer and a second dielectric layer on a side of the first dielectric layer opposite the III-N material structure. The second dielectric layer can be SiO_yN_z. The diode can include a dielectric passivation layer between the III-N material structure and the dielectric layer, the dielectric passivation layer contacting a surface of the III-N material structure between the anode and the cathode. The dielectric passivation layer can be SiN. The diode can include an additional insulating layer between the dielectric layer and the dielectric passivation layer. The additional insulating layer can be AlN. There can be a shift in the on-voltage of the diode resulting from inclusion of the dielectric layer, and the shift can be to a lower on-voltage. The intermediary electrically conductive structure can result in reduced reverse bias current in the diode compared to a similar diode lacking the intermediary electrically conductive structure. The first metal layer can include a material selected from the group consisting of nickel, platinum, titanium, and tungsten. The first metal layer can be nickel and the second metal layer can be gold. The intermediary electrically conductive structure can include a metal layer. The intermediary electrically conductive structure can include a stack of at least two metals. Each of the at least two metals can be selected from the group consisting of titanium, nickel, and gold. The stack can consist of a layer of gold, a layer of nickel, and a layer of titanium, wherein the layer of gold is adjacent to the first metal layer and the layer of titanium is adjacent to the second metal layer. The diode can include an electrode-defining layer between the III-N material structure and the dielectric layer, wherein the electrode-defining layer includes an aperture with at least a portion of the anode in the aperture. The electrode-defining layer can be SiN_x. The anode can include a portion extending over a surface of the electrode-defining layer. The aperture in the electrode-defining layer can include a step, and the anode is over the step. The portion of the anode extending over the surface of the electrode-defining layer can function as a field plate. The diode can be a high-voltage device. The threshold voltage of the diode can be about 0.7V or less, or about 0.55V or less. A voltage across the diode can be about 1.25V or less, or about 1.1V or less, for a forward bias current per unit width of the anode of about 50 mA/mm. The reverse bias current of the diode per unit width of the anode can be about 0.1 microamps/mm or less during reverse bias operation. A reverse bias current of the diode can be less than ten times that of a similar diode which lacks the dielectric encapsulation layer. An increase in reverse bias current of the diode per unit width of the anode resulting from inclusion of the dielectric encapsulation layer can be less than 0.9 microamps/mm.

[0012] Diodes with low on-resistance and high breakdown voltage are described. The techniques and structures described here may result in superior control of shifts in the on-voltage of the device, as well as reduced reverse leakage. The details of one or more implementations of the invention are set forth in the accompanying drawings and description below. Other features and advantages of the invention will be apparent from the description and drawings, and from the claims.

Description of Drawings

[0013] FIG. 1 is a cross-sectional view of a diode device of the prior art.

[0014] FIG. 2 is a cross-sectional view of one implementation of a III-N diode.

[0015] FIG. 3 is a plan view of the electrode layout of a III-N diode.

[0016] FIG. 4 is a representative plot of current versus voltage for a III-N diode.

[0017] FIG. 5 is a representative plot of reverse current as a function of threshold voltage for a III-N diode.

[0018] FIG. 6 is a cross-sectional view of the layer structure of an anode electrode in a III-N diode.

[0019] FIG. 7 is a representative plot of reverse current as a function of threshold voltage for a III-N diode.

[0020] FIG. 8 is a cross-sectional view of another implementation of a III-N diode.

[0021] FIG. 9 is a representative plot of reverse current as a function of both threshold voltage and depth of the anode contact for a III-N diode.

[0022] FIG. 10 is a cross-sectional view of another implementation of a III-N diode.

[0023] FIG. 11 is a cross-sectional view of another implementation of a III-N diode.

[0024] FIG. 12 is a cross-sectional view of another implementation of a III-N diode.

[0025] Like reference symbols in the various drawings indicate like elements.

Detailed Description

[0026] Diodes based on III-N heterostructures that can support high reverse-bias voltages with low reverse leakage, and at the same time exhibit low on-resistance, are described. The III-N diodes described herein can be high-voltage devices suitable for high voltage applications. That is, when they are reverse biased, they are at least capable of supporting all voltages less than or equal to the high-voltage in the application in which they are used, which for example may be 100V, 300V, 600V, 1200V, or 1700V. When they are forward biased, they are able to conduct substantial current with a low on-voltage. The maximum allowable value of the on-voltage is the maximum voltage that can be sustained in the application in which the diodes are used. The III-N diodes each include a dielectric layer over the surface of the diode that serves to encapsulate the device in order to protect it from contaminants and prevent other adverse effects, such as variations in output characteristics due to changes in humidity or other environmental factors. While the dielectric layer improves device reliability, it can also result in shifts in the device's on-voltage as well as increased reverse leakage, possibly caused by additional stress induced in the anode contact of the diode. These deleterious effects can be mitigated by including an intermediary electrically conductive structure in the anode contact, or by choosing a material for the dielectric layer that provides sufficient protection to the device without substantially shifting the on-voltage or increasing reverse leakage.

[0027] As shown in FIG. 2, the illustrated III-N diode includes a substrate 20, a first III-N layer 22 on top of the substrate, and a second III-N layer 24 on top of the first III-N layer. III-N layers 22 and 24 have different compositions from one another, the compositions selected such that a two-dimensional electron gas (2DEG) 26 (illustrated by a dashed line), i.e., a conductive channel, is induced in the first III-N layer 22 near the interface between the first and second III-N layers 22 and 24. An anode contact 40, or a plurality of such contacts (only one is shown in FIG. 2) are formed on top of surface 25 of the second III-N layer 24. A single cathode contact 28 is formed which contacts the 2DEG 26 and is in close proximity to at least a portion of anode contact 40. The anode contact 40 is a Schottky contact, and the single cathode contact 28 is an ohmic contact.

[0028] As used herein, the term “single cathode contact” refers to either a single metallic contact which serves as a cathode, or to a plurality of contacts serving as cathodes which are electrically connected such that the electric potential at each contact is about the same, or is intended to be the same, during device operation. In the cross-sectional view of FIG. 2, while there appear to be two cathode contacts, the two contacts are in fact electrically connected so as to form a single cathode contact 28. As used herein, two or more contacts or other elements are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other elements is about the same, or is intended to be the same, at all times during operation.

[0029] The anode contact 40 in FIG. 2 has a different metal layer structure than the anode contact 27 in FIG. 1, as will be described below. The diode further includes a dielectric layer 31 over the surface of the device that serves as an encapsulation layer to protect the device from contaminants and prevent other adverse effects, such as variations in output characteristics due to changes in humidity or other environmental factors. The diode may also optionally include a passivation layer 30 which contacts the III-N material surface at least between the anode and cathode contacts 40 and 28, respectively, or an additional dielectric layer 32 over the dielectric layer 31, or both. The device may also include additional III-N layers (not shown), for example a III-N buffer layer between the first III-N layer 22 and the substrate 20, or a III-N layer such as AlN between the first III-N layer 22 and the second III-N layer 24.

[0030] The diode in FIG. 2 operates as follows. When the voltage at the anode contact 40 is less than that at the cathode contact 28, such that the Schottky junction between anode contact 40 and III-V layer 24 is reverse biased, the diode is in the OFF state with only a small reverse bias current flowing between the anode and cathode. Ideally, the reverse bias current is as small as possible. When the voltage at the anode contact 40 is greater than that at the cathode contact 28, the Schottky junction between anode contact 40 and III-V layer 24 is forward biased, and the diode is in the ON state. In this state, a substantial electron current flows from the cathode contact 28 predominantly through the 2DEG 26 and then through the forward biased Schottky junction into the anode contact 40. That is, at least 99% of the total forward bias current flows from the anode to the cathode through the Schottky barrier and through the 2DEG channel. A small amount of leakage current can flow through other paths, such as along the surface of the device.

[0031] As stated earlier, III-N layers 22 and 24 have different compositions from one another. The compositions are selected such that the second III-N layer 24 has a larger bandgap than the first III-N layer 22, which helps enable the formation of 2DEG 26. If III-N layers 22 and 24 are composed of III-N material oriented in a non-polar or semi-polar orientation, then doping all or part of the second semiconductor layer 24 with an n-type impurity may also be required to induce the 2DEG 26. If the III-N layers 22 and 24 are oriented in a polar direction, such as the [0 0 0 1] (i.e., group III-face) orientation, then 2DEG 26 may be induced by the polarization fields without the need for any substantial doping of either of the III-N layers, although the 2DEG sheet charge concentration can be increased by doping all or part of the second III-N layer 24 with an n-type impurity. Increased 2DEG sheet charge concentrations can be beneficial in that they can reduce the diode on-resistance, but they can also lead to lower reverse breakdown voltages. Hence the 2DEG sheet charge concentration must be optimized to a suitable value for the application in which the diode is used.

[0032] III-N materials can be used for layers 22 and 24, wherein the compositions of the layers are chosen such that the requirements for layers 22 and 24 are satisfied. As an example, III-N layer 22 can be GaN and III-N layer 24 AlGaN or AlInGaN, whereas layer 24 can be n-doped or can contain no significant concentration of doping impurities. In the case that layer 24 is undoped, the induced 2DEG results from the difference in polarization fields between layers 22 and 24. The III-N material configurations for the diode described above can also be used in a III-N HEMT device. Hence, the diodes described herein can be integrated with III-N HEMT devices onto a single chip, thereby simplifying the fabrication process and reducing cost.

[0033] Substrate 20 can be any suitable substrate upon which III-N layers 22 and 24 can be formed, for example silicon carbide (SiC), silicon, sapphire, GaN, AlN, or any other suitable substrate upon which III-N devices can be formed. In some implementations, a III-N buffer layer (not shown) such as AlGaN or AlN is included between substrate 20 and semiconductor layer 22 to minimize material defects in layers 22 and 24.

[0034] As previously mentioned, the device of FIG. 2 also includes a dielectric layer 31, and optionally an insulating layer 30 and a second dielectric layer 32. Insulating layer 30, formed of an insulating dielectric material such as a layer of SiN, atop the second III-N layer 24, maintains effective passivation of the uppermost III-N surface of the device, i.e., the surface 25 of the second III-N layer 24. As used herein, a “passivation layer” refers to any layer or combination of layers grown or deposited on a surface of a semiconductor layer in a semiconductor device which can prevent or suppress voltage fluctuations at the surface during device operation. For example, a passivation layer may prevent or suppress the formation of surface/interface states at the uppermost III-N surface, or it may prevent or suppress the ability of surface/interface states to trap charge during device operation. In some implementations, insulating layer 30 is omitted, and dielectric layer 31 maintains effective passivation of the uppermost III-N surface of the device.

[0035] Dielectric layer 31 is deposited on top of insulating layer 30, cathode contact 28, and anode contact 40, encapsulating the uppermost surface of the device. As such, dielectric layer 31 is over at least a portion of the anode contact 40. Dielectric layer 31 is formed of a dielectric material, such as silicon nitride, aluminum nitride, silicon oxide, alumina, a polymeric dielectric, an inorganic or organic dielectric, or any combination of these dielectric materials. Dielectric layer 31 can be grown or deposited by methods such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, spinning, or other method. Dielectric layer 31 protects the device during operation, preventing or suppressing effects such as dispersion and arcing, as well as protecting the device from environmental factors such as humidity.

[0036] Dispersion refers to a difference in observed current-voltage (I-V) characteristics when the device is operated under RF or switching conditions as compared to when the device is operated under DC conditions. In III-N devices, effects such as dispersion are often caused by voltage fluctuations at uppermost III-N surfaces, often caused by the charging of surface states during device operation. Dielectric layer 31 can be sufficiently thick to protect the device from these effects. Accordingly, the thickness of dielectric layer 31 can be about 0.2 microns or thicker, such as between about 0.2 microns and 2 microns, or between about 0.2 microns and 10 microns, or between about 0.2 microns and 20 microns. When insulating layer 30 is included, dielectric layer 31 in combination with insulating layer 30 maintains effective passivation of the uppermost III-N surface of the device. In some implementations, an additional insulating layer (not shown), such as AlN is included between the insulating layer 30 and the dielectric layer 31. In this case, the additional insulating layer may need to be made thin enough, such as thinner than about 20 nm, thinner than about 10 nm, or thinner than about 5 nm, to ensure that effective passivation of the uppermost III-N surface is still maintained. Too thick an additional insulating layer, such as greater than about 20 nm, can degrade the passivation effects of layers 30 and 31.

[0037] Anode contact 40, formed upon surface 25 of semiconductor layer 24, forms a Schottky contact to layer 24. Cathode contact 28 contacts the 2DEG in ohmic region 29, forming a contact which is a substantially ohmic contact. Cathode contact 28 can be made to contact the 2DEG in a number of ways. For example, a metal or combination of metals can be deposited in ohmic region 29 upon the surface of layer 24, followed by a thermal anneal which results in the deposited metal forming a metallic alloy with the underlying semiconductor material. Other methods by which the 2DEG can be contacted include, but are not limited to, ion implantation of n-type dopants into ohmic region 29, followed by a metal deposition atop this region, or by etching away the material in ohmic region 29 and regrowing n-type material, followed by a metal deposition atop this region. Anode contact 40 and cathode contact 28 may be any arbitrary shape, although the shape is ideally optimized to minimize the device area required for a given forward current.

[0038] FIG. 3 is a plan view (top view) of an electrode configuration that may be used in the device of FIG. 2, and includes alternating “fingers” of cathode contact 28 and anode contact 40, connected to cathode and anode contact pads shown on the top and bottom, respectively, of FIG. 3. Additional cathode and anode fingers can be included with those shown in FIG. 3.

[0039] Conventional anode contacts, such as anode 27 in the structure of FIG. 1, typically include two metal layers. The first metal layer, which contacts the underlying III-N materials, forms a Schottky contact with the III-N materials. Preferably, the Schottky barrier height is as large as possible in order to minimize reverse bias currents. A layer of nickel is commonly used for the first contacting metal layer. The second metal layer, which is atop the first metal layer opposite the III-N materials, is typically thick and has a large electrical conductivity, in order to reduce lateral resistances in the anode contact.

[0040] Referring again to FIG. 2, it has been found that after the deposition of dielectric layer 31 over the surface of a III-N diode device, the forward operating voltage V_onof the device shifts to a lower value. For a given diode, the V_onof the device is defined for a specific current density I_on, as illustrated in FIG. 4. It is conventional in the art for V_onto be defined as the voltage across the device terminals at a current density I_onof 50 mA/mm. The diode also has a threshold voltage V_T, also illustrated in FIG. 4. V_Tis found by fitting a straight line to the linear portion of the I-V characteristics, and then extending the line to the voltage axis, as shown. V_Tis the point at which the extended line intersects the voltage axis. Shifts in V_onare accompanied by equal shifts in V_T. That is, for a shift of X volts in V_on, V_Talso shifts by X volts.

[0041] The reduction in V_onand V_Tafter deposition of dielectric layer 31 is accompanied by an increase in the reverse bias current (or similarly the reverse current density or reverse current) in the device, indicating that the effective Schottky barrier height between the anode contact and the adjacent III-N material is being reduced, possibly as a result of stress induced by the dielectric layer 31 in the portion of the anode contact that contacts the III-N material.

[0042] FIG. 5 shows a representative plot of the reverse current density (I_reverse), which is the current density that flows through the device while the device is in the OFF state, as a function of the threshold voltage V_Tof the device of FIG. 1 for a given material structure of anode contact 27. Point A on the plot corresponds to a device that does not include dielectric insulating layer 31, as in FIG. 1. The V_Tat point A can be between about 0.7 Volts and 0.75 Volts, corresponding to a Von between about 1.05 Volts and 1.25 Volts, and the I_reversecan be about 0.1 microamps/mm (μA/mm), when the portion of anode contact 27 adjacent to the III-N device layers is nickel. When a dielectric layer 31, such as SiN, is deposited over the device, covering at least a portion of the anode contact, the on-voltage shifts to a lower value, and the reverse bias current becomes correspondingly larger. Point B in the plot of FIG. 5 corresponds to the device of FIG. 1 after deposition of a dielectric layer, such as dielectric layer 31 from FIG. 2, over the device of FIG. 1.

[0043] When the portion of anode contact 27 adjacent to the III-N device layers is nickel, the V_Tat point B can be between about 0.55 Volts and 0.6 Volts, corresponding to a V_onbetween about 0.9 Volts and 1.1 Volts, and the I_reversecan be as high as 1 μA/mm, which is ten times the value of I_reverseprior to deposition of dielectric layer 31. Therefore, the inclusion of dielectric layer 31 results in a reduction of V_Tand V_onof the device by about 0.1 to 0.15 Volts. It has further been found that when the portion of anode contact 27 adjacent to the III-N device layers is nickel and the dielectric layer 31 is SiN, the thickness of dielectric layer 31 has little or no effect on the magnitude of the shift in V_Tor V_on, i.e., a shift of about 0.1 to 0.15 Volts has been observed for all devices that include a SiN dielectric layer 31 which is at least about 3500 Angstroms thick. Therefore it is desirable that dielectric layer 31 be thicker in order to most effectively protect the device as well as prevent dispersion and other deleterious effects as described above.

[0044] Further, the thickness of dielectric layer 31 can be chosen so that it is possible to fabricate the device such that its electrodes, which are under dielectric layer 31, may be accessed. For example, the electrodes may be accessed by etching through a portion of dielectric layer 31. If dielectric layer 31 is too thick, it may be difficult or not possible to etch the entire thickness of dielectric layer 31 and to access the electrodes. If dielectric layer 31 is too thick, the layer may cause substantial stress in the III-N layers which can lead to cracking of the III-N layers or result in undesirable device performance. Accordingly, dielectric layer 31 can be between about 0.2 microns and 20 microns thick, as stated above.

[0045] It has been found that the inclusion of additional intermediary electrically conductive layers in the anode contact 40, as compared to the metal layers used in the anode contacts of conventional III-N devices such as that of FIG. 1, can serve to control shifts in the forward operating voltage V_on, and equivalently in the threshold voltage V_T, of the device. As previously discussed, conventional anode electrodes, such as anode 27 in the structure of FIG. 1, typically include two metal layers. Commonly used metals are nickel (Ni), platinum (Pt), titanium (Ti), or tungsten (W) for the first metal layer, and a thicker second metal on top of the first metal layer, such as gold (Au).

[0046] FIG. 6 shows a schematic illustration of the metal layer structure of anode contact 40 in the device of FIG. 2. The layer structure of anode 40 includes an additional intermediary electrically conductive structure 45 as compared to the conventional anode contact 27 of FIG. 1. The layer structure of anode contact 40 includes a first metal layer 10, such as Ni, which can be about 600 Angstroms thick, a second metal layer 14, such as Au, which can be between about 2 and 3 microns thick, and an intermediary electrically conductive structure 45 between the first metal layer 10 and the second metal layer 14. Intermediary electrically conductive structure 45 includes at least one electrically conductive layer, which for example can be titanium (Ti), platinum (Pt), tungsten (W), aluminum (Al), chromium (Cr), NiCr, germanium (Ge), copper (Cu), nickel (Ni), gold (Au), or combinations therein. In the implementation shown in FIG. 6, the intermediary electrically conductive structure 45 includes three layers 11, 12, and 13. Layer 11 is Au and can be between about 3500 and 7500 Angstroms thick, layer 12 is Ni and can be about 300 Angstroms thick, and layer 13 is titanium (Ti) and can be about 300 Angstroms thick.

[0047] It has been found that the inclusion of the intermediary electrically conductive structure 45 between the first and second metal layers 10 and 14 reduces the shift in the forward operating voltage V_on, the shift in the threshold voltage V_T, and the shift in reverse bias current I_reverseof devices as compared to devices that do not include intermediary electrically conductive structure 45. This is illustrated in the representational plot of FIG. 7. FIG. 7 is the same as FIG. 5, but further includes a Point C corresponding to the threshold voltage V_Tand reverse bias current I_reverseof the device of FIG. 2 after deposition of dielectric layer 31. Prior to deposition of dielectric layer 31, the threshold voltage V_Tand reverse bias current I_reverseof the device of FIG. 2 is similar to that of FIG. 1 and is also represented by Point A in FIG. 7. The V_Tof the device of point A is between 0.7 Volts and 0.75 Volts, corresponding to a Von between about 1.05 Volts and 1.25 Volts. As seen in FIG. 7, the shift in the threshold voltage V_Tof the device of FIG. 2 after deposition of dielectric layer 31 and the inclusion of electrically conductive structure 45 in anode contact 40, where the thickness of layer 11 in electrically conductive structure 45 is 5000 Angstroms, is about 0.025V. This is about 4 times less than the shift in the device of FIG. 1. This fourfold reduction results from the inclusion of electrically conductive structure 45 in anode contact 4. Accordingly, the V_Tat Point C is between 0.675 Volts and 0.725 Volts, corresponding to a Von between about 1.025 Volts and 1.225 Volts, and the reverse current per unit anode width at Point C is less than 1 μA/mm, such as less than 0.6 μA/mm or less than 0.3 μA/mm. The I_reverseat Point C can be less than 10 times the I_reverseat Point A, such as less than 5 times or less than 3 times the I_reverseat Point A.

[0048] When the structure shown in FIG. 6 is used for anode contact 40, where layer 11 is Au, layer 12 is Ni, and layer 13 is Ti, the shift in the forward voltage and the threshold voltage of the device can be controlled by varying the thickness of metal layer 11. For example, if metal layer 11 is thicker, the resulting shift in V_onand V_Tis greater. Likewise, if metal layer 11 is thinner, the resulting shift in V_onand V_Tis smaller. The reverse bias current I_reverseis also reduced as a result of inclusion of electrically conductive structure 45. It is predicted that the shift in forward operating voltage and threshold voltage of the III-N diode device following deposition of dielectric layer 31, as shown in FIG. 5, is due to stress or strain in the anode contact caused by the dielectric layer 31, resulting in a reduction of the effective Schottky barrier height between the anode contact and the adjacent III-N material.

[0049] Referring again to FIG. 2, the second dielectric layer 32, which is optionally included, is formed of a dielectric material such as silicon oxy-nitride (SiO_xN_y), and can be grown or deposited using PECVD or another method listed above. The thickness of second dielectric layer 32 can be about 3 microns or thicker. Second dielectric layer 32 provides additional protection for the device during operation. In some cases, the second dielectric layer 32 is formed of a material that is more effective than dielectric layer 31 at preventing environmental factors such as humidity from affecting device performance, but would not alone serve as a suitable passivation layer without the inclusion of dielectric layer 31.

[0050] Another implementation is shown in FIG. 8. The device in FIG. 8 is similar to that of FIG. 2, but further includes an electrode-defining layer 23. A recess is included in the electrode-defining layer 23, the recess extending into the III-N materials at least through the 2DEG 26, and the anode contact 50 is in the recess. The diode also includes a field plate 21 connected to the anode contact 50. Electrode-defining layer 23 is an insulator, such as SiN, and serves to shape the field plate. The shape of the field plate is determined by the profile of the aperture through electrode-defining layer 23. Electrode-defining layer 23 also serves as a suitable passivation layer either on its own or in combination with passivation layer 30.

[0051] An additional insulating layer (not shown), such as AlN, may also be included between the electrode-defining layer 23 and the passivation layer 30. The additional insulating layer can aid in fabrication of the device by serving as an etch-stop layer. The material layer structure of the anode contact 50 is the same as that shown in FIG. 6 for anode contact 40 of FIG. 2. That is, anode contact 50 includes a first metal layer such as Ni adjacent to the III-N material structure, a second metal layer such as Au, and an intermediary electrically conductive structure between the first metal layer and the second metal layer serving to reduce the shift in on-voltage of the diode that results from deposition of the dielectric layer 31, as previously described.

[0052] The field plate 21 in this diode of FIG. 8 reduces the peak electric field at the edge of the anode, thereby increasing the reverse-bias breakdown voltage while having no substantial impact on the on-resistance or other on-state characteristics. In particular, slant field plates, such as those described in U.S. patent application Ser. No. 11/841,476, filed Aug. 20, 2007, and assigned to the same assignee as the described invention, are especially desirable. Or, as shown in FIG. 8, stepped field plate structures with at least one step, at least two steps, or at least three steps can be used. Additionally, multiple field plate structures can be used.

[0053] The depth of the recess containing anode contact 50 in FIG. 8 (that is, how deep below the 2DEG 26 the recess extends) can control or vary shifts in the threshold voltage V_Tand the forward operating voltage V_on, and correspondingly the reverse bias current I_reverse, of the device. This is because changing the depth of the aperture modifies the electric field profile in the III-N materials near the portion of 2DEG 26 which is modulated by the voltage on the anode contact 50. A deeper recess reduces the peak electric field in this region in much the same way as a conventional field plate, thereby leading to devices with higher threshold voltages V_Tand forward operating voltages V_on, but also lower reverse bias currents I_reverse, as well as higher reverse breakdown voltages.

[0054] FIG. 9 shows a representative plot of the reverse bias current (I_reverse) as a function of both the threshold voltage V_Tof the device (lower axis) and the depth of the aperture (upper axis), where the depth of the aperture is measured from the upper surface of the III-N materials to the bottom of the aperture. Point D in FIG. 9 corresponds to an aperture with a depth of 0.1 microns, while Point E corresponds to an aperture depth of 0.2 microns. For both the devices of points D and E, the thickness of the second III-N layer 24 (i.e., the approximate depth of the 2DEG 26 below the upper surface of the III-N materials) is 0.027 microns. As such, the depth of the recess can be at least 30 nm, at least 0.1 microns, or at least 0.2 microns in order for the recess to extend through the 2DEG 26. The threshold voltages V_Tat points D and E are 0.55 and 0.7 Volts, respectively, which corresponds to a shift in the threshold voltage V_Tand forward voltage V_onof about 0.15 Volts from Point D to Point E. The reverse bias current per unit width of anode contact I_reverseat points D and E is approximately 1 μA/mm and 0.1 μA/mm, respectively. Therefore the depth of the anode contact 50 can provide additional control of the forward operating voltage (and consequently the reverse bias current) of the device.

[0055] More implementations of the described devices are shown in FIGS. 10, 11 and 12. FIG. 10 shows a cross-sectional view of a diode similar to the device in FIG. 2, but which is fabricated on III-N semiconductor material that is either oriented in the N-polar [0 0 0 1bar] direction or is a nitrogen-terminated semipolar material. That is, the face of the III-N materials furthest from the substrate is either a [0 0 0 1bar] face or is a nitrogen-terminated semipolar face. The device includes a substrate 200 which is suitable for growth of N-polar or semipolar III-N materials. Layer 201 is a buffer layer, such as GaN or AlN, which reduces the defect density in the overlying III-N material. In some cases, it is possible to omit layer 201 and grow III-N layer 204 directly on the substrate 200. The composition of III-N layers 204 and 202 are chosen such that a 2DEG 26 can be induced in layer 202 near the interface between layers 202 and 204. For example, layer 204 can be AlGaN or AlInGaN, and layer 202 can be GaN. Anode contact 40 is formed on the surface of III-N layer 202 opposite the substrate 200, and a single cathode contact 28 is formed which contacts the 2DEG 26 and is in close proximity to at least a portion of anode contact 40. The anode contact 40 is a Schottky contact, and the single cathode contact 28 is an ohmic contact. As with previous implementations, the layer structure of the anode contact 40 is similar to or the same as that shown in FIG. 6 and includes an intermediary electrically conductive structure between a first metal layer and a second metal layer, the intermediary electrically conductive structure serving to reduce a shift in the on-voltage and threshold voltage of the diode resulting from inclusion of dielectric layer 31 over the device. Also as with previous implementations, the device of FIG. 10 can optionally include a passivation layer 30 and/or an additional dielectric layer 32 over dielectric layer 31.

[0056] FIG. 11 shows a cross-sectional view of a diode similar to the device of FIG. 8, but which is fabricated on III-N semiconductor material that is either oriented in the N-polar [0 0 0 1bar] direction or is a nitrogen-terminated semipolar material. The device includes a substrate 200 which is suitable for growth of N-polar or semipolar III-N materials. Layer 201 is a buffer layer, such as GaN or AlN, which reduces the defect density in the overlying III-N material. In some cases, it is possible to omit layer 201 and grow III-N layer 204 directly on the substrate. The composition of III-N layers 204 and 202 are chosen such that a 2DEG 26 can be induced in layer 202 near the interface between layers 202 and 204. For example, layer 204 can be AlGaN or AlInGaN, and layer 202 can be GaN. The device also includes an electrode-defining layer 23.

[0057] A recess is included in the electrode-defining layer 23, the recess extending into the III-N materials at least through the 2DEG 26, and the anode contact 50 is in the recess. The diode also includes a field plate 21 connected to the anode contact 50. Electrode-defining layer 23 in FIG. 8 is an insulator, such as SiN, and serves to shape the field plate. The shape of the field plate is determined by the profile of the aperture through electrode-defining layer 23. Electrode-defining layer 23 also serves as a suitable passivation layer either on its own or, when passivation layer 30 is included, in combination with passivation layer 30. An additional insulating layer (not shown), such as a layer of AlN, may also be included between the electrode-defining layer 23 and the passivation layer 30. The additional layer can aid in fabrication of the device by serving as an etch-stop layer. The material layer structure of the anode contact 50 is the same as that shown in FIG. 6 for anode contact 40 of FIG. 2. That is, anode contact 50 includes a first metal layer such as Ni adjacent to the III-N material structure, a second metal layer such as Au, and an intermediary electrically conductive structure between the first metal layer and the second metal layer serving to reduce the shift in the on-voltage and threshold voltage of the diode that results from deposition of the dielectric layer 31, as previously described.

[0058] The diode of FIG. 12 is similar to that shown in FIG. 1, but further includes a dielectric encapsulation layer 61 and optionally an additional dielectric layer 62. Dielectric encapsulation layer 61 differs from dielectric layer 31 in FIG. 2 in that it does not cause as large a reduction in the on-voltage, or correspondingly as large an increase in the reverse bias current, of the device as compared to dielectric layer 31. For example, the shift in the on-voltage of the diode resulting from inclusion of the dielectric encapsulation layer 61 can be less than 0.1V, less than 0.08V, less than 0.06V, or less than 0.05V. The increase in the reverse bias current of the diode per unit width of the anode contact 27 resulting from inclusion of the dielectric encapsulation layer 61 can be less than 0.9 μA/mm, such as less than 0.5 μA/mm or less than 0.2 μA/mm. For example, the reverse bias current of the diode per unit width of the anode contact 27 prior to deposition of the dielectric encapsulation layer 61 can be about 0.1 μA/mm, and the reverse bias current of the diode per unit width of the anode contact 27 after deposition of the dielectric encapsulation layer 61 can be less than 1 μA/mm, such as less than 0.6 μA/mm or less than 0.3 μA/mm. That is, the reverse bias current of the diode per unit width of the anode contact 27 after deposition of dielectric encapsulation layer 61 can be less than 10 times, less than 6 times, or less than 3 times the reverse bias current of the diode per unit width of the anode contact 27 prior to deposition of dielectric encapsulation layer 61.

[0059] Dielectric encapsulation layer 61 can be formed of a material that does not cause as much strain on the anode contact 27 as does a conventional material used for encapsulation layers, thereby allowing for use of a conventional anode contact 27 in the device. For example, the dielectric encapsulation layer 61 can be benzocyclobutene (commonly referred to as BCB), spin-on glass, or a combination of SiN_x, SiO_yN_z, and SiO_w. Or, the dielectric encapsulation layer 61 can be formed of a conventional material used for encapsulation layers, such as SiN_xor SiO_yN_z, but can be deposited by a method that results in less or different strain induced in the underlying anode contact 27 as compared to when the material is deposited by conventional methods or under conventional deposition conditions. The additional dielectric layer 62 further helps to protect the diode from contaminants in the environment. As in other diode implementations, the diode of FIG. 12 can also include a passivation layer 30 contacting the surface of the III-N materials between the anode contact 27 and the cathode contact 28. The diode can also include an electrode-defining layer, a recess in the III-N materials containing at least a portion of the anode contact 27, and a field plate, for example such as those shown in the diode of FIG. 8.

[0060] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. Features shown in each of the implementations may be used independently or in combination with one another. For example, the diodes of FIGS. 2, 10, and 12 may also include a field plate and/or an electrode-defining layer such as those of FIGS. 8 and 11. Accordingly, other implementations are within the scope of the following claims.

Claims

What is claimed is:

1. A method of forming a diode, comprising:

providing a III-N material structure having an electrically conductive channel therein;

forming two terminals, wherein a first terminal is an anode adjacent to the III-N material structure, and a second terminal is a cathode in ohmic contact with the electrically conductive channel; and

depositing a dielectric layer over at least a portion of the anode; wherein

the anode comprises a first metal layer comprising nickel adjacent to the III-N material structure, a second metal layer comprising gold, and an intermediary electrically conductive structure between the first metal layer and the second metal layer, the intermediary electrically conductive structure comprising a layer of gold adjacent to the first metal layer and a layer of nickel between the layer of gold and the second metal layer.

2. The method of claim 1, wherein the III-N material structure comprises a first III-N material layer and a second III-N material layer, and wherein the electrically conductive channel is a 2DEG channel induced in a region of the first III-N material layer adjacent the second III-N material layer as a result of a compositional difference between the first III-N material layer and the second III-N material layer.

3. The method of claim 2, wherein the first III-N material layer includes GaN.

4. The method of claim 3, wherein the second III-N material layer includes AlGaN or AlInGaN.

5. The method of claim 2, further comprising forming a third III-N material layer between the first III-N material layer and the second III-N material layer.

6. The method of claim 5, wherein the third III-N material layer comprises AlN.

7. The method of claim 2, wherein the first III-N material layer and the second III-N material layer are group III-face or [0 0 0 1] oriented or group-III terminated semipolar layers, and the second III-N material layer is between the first III-N material layer and the dielectric layer.

8. The method of claim 2, wherein the first III-N material layer and the second III-N material layer are N-face or [0 0 0 1bar] oriented or nitrogen-terminated semipolar layers, and the first III-N material layer is between the second III-N material layer and the dielectric layer.

9. The method of claim 1, further comprising forming a field plate connected to the anode.

10. The method of claim 1, wherein the dielectric layer comprises SiN_x.

11. The method of claim 1, wherein the dielectric layer is between about 0.2 microns and 20 microns thick.

12. The method of claim 1, wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer on a side of the first dielectric layer opposite the III-N material structure.

13. The method of claim 12, wherein the second dielectric layer comprises SiO_yN_z.

14. The method of claim 1, further comprising a dielectric passivation layer between the III-N material structure and the dielectric layer, the dielectric passivation layer contacting a surface of the III-N material structure between the anode and the cathode.

15. The method of claim 14, wherein the dielectric passivation layer comprises SiN.

16. The method of claim 14, further including forming an additional insulating layer between the dielectric layer and the dielectric passivation layer.

17. The method of claim 16, wherein the additional insulating layer comprises AlN.

18. The method of claim 1, wherein the intermediary electrically conductive structure consists of the layer of gold, the layer of nickel and a layer of titanium, wherein the layer of titanium is between the layer of nickel and the second metal layer.

19. The method of claim 1, further comprising forming an electrode-defining layer between the III-N material structure and the dielectric layer, wherein the electrode-defining layer comprises an aperture with at least a portion of the anode in the aperture.

20. The method of claim 19, wherein the electrode-defining layer comprises SiN_x.

21. The method of claim 19, wherein the anode includes a portion extending over a surface of the electrode-defining layer.

22. The method of claim 21, wherein the aperture in the electrode-defining layer includes a step, and the extending portion of the anode is over the step.

23. The method of claim 21, wherein the portion of the anode extending over the surface of the electrode-defining layer functions as a field plate.

24. The method of claim 1, wherein the second metal layer is thicker than the first metal layer.

25. The method of claim 24, wherein the layer of gold in the intermediary conductive structure is between about 3500 and 7500 Angstroms thick.

26. A method of forming a diode, comprising:

providing a III-N material structure having an electrically conductive channel therein;

forming a recess in the III-N material structure;

forming two terminals, wherein a first terminal is an anode adjacent to the III-N material structure, and a second terminal is a cathode in ohmic contact with the electrically conductive channel; and

depositing a dielectric layer over at least a portion of the anode; wherein

at least a portion of the anode is in the recess; and

the anode includes a first metal layer comprising nickel adjacent to the III-N material structure, a second metal layer comprising gold, and an intermediary electrically conductive structure between the first metal layer and the second metal layer, the intermediary electrically conductive structure comprising a layer of gold adjacent to the first metal layer and a layer of nickel between the layer of gold and the second metal layer.

27. The method of claim 26, wherein the III-N material structure comprises a first III-N material layer and a second III-N material layer, the electrically conductive channel is a 2DEG channel induced in a region of the first III-N material layer adjacent the second III-N material layer as a result of a compositional difference between the first III-N material layer and the second III-N material layer, and forming the recess causes the recess to extend through the 2DEG channel.

28. The method of claim 26, wherein forming the recess causes the recess to extend at least 30 nanometers into the III-N material structure.

29. The method of claim 26, further comprising forming an electrode-defining layer between the III-N material structure and the dielectric layer.

30. The method of claim 29, wherein the electrode-defining layer comprises SiN.

31. The method of claim 29, further comprising forming a dielectric passivation layer between the III-N material structure and the electrode-defining layer, the dielectric passivation layer contacting a surface of the III-N material structure between the anode and the cathode.

32. The method of claim 31, wherein the dielectric passivation layer comprises SiN.

33. The method of claim 31, further comprising forming an additional insulating layer between the dielectric passivation layer and the electrode-defining layer.

34. The method of claim 33, wherein the additional insulating layer comprises AlN.

35. The method of claim 33, wherein the additional insulating layer is less than about 20 nanometers thick.

36. The method of claim 29, wherein the anode includes an extending portion which is over a surface of the electrode-defining layer.

37. The method of claim 36, wherein the recess is in the electrode-defining layer and includes a step, and the extending portion of the anode is over the step.

38. The method of claim 36, wherein the extending portion of the anode functions as a field plate.

39. The method of claim 26, wherein the intermediary conductive structure further includes a layer of titanium.

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Abstract