Cycle by cycle synchronous buck converter control based on external clock

[0001] This application is based on and claims priority to U.S. Provisional Patent Application Ser. No. 60/863,235, filed on Oct. 27, 2006 and entitled CYCLE BY CYCLE SYNCHRONOUS BUCK CONVERTER CONTROL BASED ON EXTERNAL CLOCK, the entire disclosure of which is hereby incorporated by reference.

[0002] The present invention relates to DC-DC converters and more particularly to a circuit to step-down output voltage to a lower voltage and power level.

[0003] Isolated DC-DC converters, whether part of a complete AC-DC system or just pure DC-DC system, often require several output voltages at different power levels. These output voltages are normally obtained through multiplication of a transformer's secondary windings for each output at higher power level, e.g., 30 W and up, while simple buck converters are often used for step-down stages to a lower voltage and lower power level, generally less than 30 W, from one of the output voltages.

[0004] FIG. 1 illustrates a DC-DC converter 10 having a primary stage 12 having a DC bus as input and an output connected to a primary coil L_P of a transformer 14. The transformer includes first and second secondary coils L_S1 and L_S2 series connected at a node. The first and second secondary coils LS1 and L_S2 are connected to first and second output rectification circuits 16 and 18. Each rectification circuit 16 and 18 has an Output 1 and 2, respectively including a capacitor Cout1 and Cout2, respectively.

[0005] The DC-DC converter 10 further includes a synch buck control circuit 20 for controlling a third switching stage 22 with Output 3. The switching stage 22 includes high- and low-side switches M1 and M2 connected in series at a switching node. The high-side switch M1 is further connected to the output of the output rectification circuit 18 and the low-side switch M2 is farther connected to ground. Additionally, a first terminal of an inductor L1 is connected to the switched node VS and its second terminal, in a local feed back loop, to the synch buck control circuit 20. Further, a capacitor Cout3 is connected between the second terminal of the inductor L1 and ground.

[0006] It is an object of the present invention to provide step-down stages that are simple, compact, and are implemented in less space and at lower cost than a supplemental secondary winding and output rectification system.

[0007] It is another object of the present invention to provide step-down stages that are autonomous and include a high power outputs feedback converter on the primary side while the step-down stages close their loops entirely on the secondary side.

[0008] Provided is a DC-DC voltage converter having a switching stage including high and low-side switches connected in series at a switched node across a DC voltage bus; a control circuit; and a feedback loop connected between an output of the switching stage and an input of the control circuit, the control circuit having a clock signal input and including an error processing circuit coupled to the input for detecting an output of the feedback loop, the control circuit turning OFF the low-side switch and turning ON the high-side switch when the clock signal is detected. The control circuit operates in a cycle by cycle operation generating PWM modulation synchronous to the external clock source.

[0009] Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings.

[0015] The present invention offers a simple, cost effective, externally synchronizable buck converter that can operate independent from the primary side. The inventive converter dispenses with amplifiers and oscillators and therefore reduces the area of the control IC.

[0016] The converter control of the invention operates synchronous with the main converter's secondary coil, therefore providing EMI spectrum reduction and more effective usage of capacitors, i.e., output capacitors for the main converter and input capacitors for the synchronous buck converter.

[0017] The inventive circuit can be easily coupled with controller products that are clocked by the operations of the secondary side, for example, a family of SmartRectifier™ ICs manufactured and sold by the International Rectifier Corporation.

[0018] As illustrated in FIG. 2, the present invention realizes a step-down converter 30 control by integrating a control circuit 32 that utilizes any available secondary clock source 34, e.g., control circuit outputs, auxiliary windings, power windings, etc.; closing the buck converter feedback loop through a standard shunt regulator 36 acting as an error amplifier; and implementing a new concept of PWM modulation based on the external clock and the obtained error signal.

[0019] As shown, the control circuit 32 controls the high- and low-side switches M1 and M2 of the switching stage. The control circuit 32 has HO and LO pins to control the high- and low-side switches; a VS pin to receive voltage sense from the switched node VS; a VB pin to receive floating supply boot strap voltage; a COM pin connected to the common; a CK pin to receive a clock; a VCC pin to receive a voltage supply; and an Err pin to receive a feedback signal from the shunt regulator 36. As an input, the control circuit 32 requires only the voltage supply at the VCC pin and the clock signal at the CK pin.

[0020] The shunt regulator 36 provides a reliable voltage reference and acts as error amplifier through dedicated compensation networks. The shunt regulator 36 includes first and second compensation circuits, a shunt regulator break-over device QS, first and second series connected resistors R1 and R2 and a capacitor C1. The resistor R1 is also parallel connected to the capacitor C1 and in series to the resistor R2. A second terminal of the resistor R2 is grounded. A second terminal of the resistor R1 is connected to an input terminal of the capacitor Cout. The first and second compensation circuits and a cathode of QS are connected to Err pin of the control circuit 32. The second compensation circuit and the anode of QS are connected to the ground. The first compensation circuit and a control electrode of QS are connected to a node between the resistors R1 and R2.

[0021] The invention will now be described using FIG. 3, which shows the step-down converter 30 using an exemplary embodiment of the control circuit 32. The control is achieved in accordance with the following steps. The clock signal from the clock source 34 is detected at CK pin, i.e., using the falling, or rising edges of the signal. The detected signal will set a flip-flop circuit 40 to signal a bridge logic circuit 42 to turn OFF the low-side switch M2 and turn ON the high-side switch M1.

[0022] An error processing circuit 44 detects the voltage and current received from the feedback loop. The Err input presents a resistive behavior, and thus the shunt regulator 36 will drain a current, which is inversely proportional to the output voltage error. A mirrored current will start charging an internal capacitor C2. As the capacitor C2 charges, its voltage is compared by a comparator 46 with the voltage at Err pin. When the voltage on the internal capacitor C2 reaches the larger of the voltage at Err pin and an internal reference voltage, the dedicated comparator 46 will reset the flip-flop circuit 40 to signal the bridge logic circuit 42 to turn OFF the high-side switch M1 and to turn ON the low-side switch M2 for the duration of time it takes a switch Q1, triggered by the flip-flop circuit 40, to discharge the ramp capacitor C2. The above is performed in a cycle by cycle operation causing PWM modulation to be generated, synchronous to the external clock source 34.

[0023] FIG. 4 shows a more detailed implementation of the circuit of FIGS. 2 and 3 using a standard controller circuit IRS2004, manufactured and sold by International Rectifier Corporation, and external components in a converter circuit 50 as illustrated in FIG. 4. The converter circuit 50 has a 10-14V input, 5V, 30 W output controlled by a synchronous buck converter control circuit 52. The control circuit 52 is connected to a high-side switch M4 via a resistor Rg3 and to the low-side switch M3 via a resistor Rg4. The switches M4 and M3 are coupled to form a switching stage having a switching node. The high-side switch is connected to a circuit of parallel coupled capacitors C56, C57, C58, C59, and C60. Three capacitors C58, C59, and C60 are 1 uF/25V and the capacitors C56 and C57 are 500 uF/25V.

[0024] The low-side switch M3 is connected to a circuit that include two series coupled inductors L3 and L4 connected to the switched node, capacitors C64, C65 and C66 that are 100 uF/16 v and a capacitor C5 resistor R12 combination that is parallel connected to the switch M3.

[0025] The driver IC 52 includes VS, VB, HO, LO, VCC, and COM pins as discussed above, additionally it includes IN connected to an external clock source (CK), and SHDN inverse pin tied to VCC. The node between R15 and C9 acts as Err pin, and switch Q2 is a reset switch across a ramp capacitor C8. R11 is a roughly approximated current generator. The comparator and bridge logic circuits are included in the driver IC 52. A fixed or adaptive dead-time logic needs to be implemented at the half bridge driving level.

[0026] FIGS. 5A-5F illustrate the waveforms obtained by the above-discussed circuit 50 of FIG. 4. In the Figures, g1 indicates the inductor current, g2 indicates voltage Vgs of the high side switch, g3 indicates voltage at Err pin i.e., the node at the register R15 and the capacitor C9, and g4 indicates ramp capacitor voltage at IN pin.

[0027] Tests of the circuit of FIG. 4 prove the concept of the invention. The following Case 1 and Case 2 tables show the regulation characteristics and step down voltage outputs for voltage inputs between 7V and 13V:

[0028]

CASE 1: CK = 100 kHz
No load test		Vin = 8 V	Vin = 9 V	Vin = 10 V	Vin = 11 V	Vin = 12 V
Vin	Vout	lout	Vout	Vout	Vout	Vout	Vout
[V]	[A]	[A]	[V]	[V]	[V]	[V]	[V]
7	4.99	0.1	4.99	4.997	4.999	5	5.002
8	4.99	0.5	4.98	4.992	4.996	4.998	5
9	4.99	1	4.98	4.991	4.996	4.998	4.997
10	4.99	1.5	4.97	4.99	4.995	4.997	4.996
11	5.001	2	4.97	4.989	4.994	4.996	4.995
12	5.002	2.5	4.94	4.986	4.992	4.995	4.994
13	5.002	3	4.9	4.983	4.989	4.993	4.992
		3.5		4.981	4.987	4.991	4.99
		4				4.988	4.986
		4.5					4.984

[0029]

CASE 2: variable CK
		fsw = 150 kHz	fsw = 200 kHz	fsw = 250 kHz
Vin	lout	Vout	Vout	Vout
[V]	[A]	[V]	[V]	[V]
9	0	4.98	4.83	4.84
13	0	4.996	4.99	4.984
13	4	4.98	4.89	4.9

[0030] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention not be limited by the specific disclosure herein.