Method and apparatus for customizing of a power supply based on load characteristic data

[0001] The present invention relates to power supplies, and in particular, to power supplies for providing low voltage, high current power to such devices as portable computers such as notebook and laptop computers.

[0002] Multi-phase buck converter switching power supplies are now in use for providing low voltage, high current, high efficiency power supplies for such applications as portable computers, for example, laptops and notebook computers.

[0003] The present invention relates to a power supply wherein the output voltage or other power supply characteristic, for example, over voltage protection limit, can be set depending on load characteristic data, such as digital voltage data codes known as VID codes received from the load microprocessor being powered by the power supply. In particular, the various microprocessor manufacturers, such as Intel, AMD etc., provide tables of the voltage power inputs for their microprocessors depending on operating conditions. The microprocessor issues voltage identification (VID) codes which contain digital bits that specify the input voltage required at a particular instant, depending on the processor activity. This enables the processor to conserve energy when the load requirements are low and receive more power when requirements are high. Each manufacturer uses different VID codes and the VID codes may be different for different processor chips made by the same manufacturer.

[0004] In the past, power supplies for computer systems required dedicated power supplies capable of interpreting the VID codes for a particular processor. However, these power supplies were not capable of interpreting the VID codes for processors other than the processor for which they were designed.

[0005] It is accordingly an object of the present invention to provide a power supply that is capable of responding to load characteristic data such as VID codes of a plurality of processor types and providing the required voltages and/or other requirements, such as over voltage protection limits in accordance with the load characteristics data.

[0006] The above and other objects of the invention are achieved by a power supply for powering an electrical load, the electrical load generating load characteristic data that determines a power supply characteristic to be provided to the electrical load from the power supply, the power supply comprising a voltage regulator for generating an output voltage to be provided as the input voltage for powering the electrical load, the voltage regulator being responsive to a reference signal for setting a characteristic of the power supply, and a control circuit for generating the reference signal for the regulator, the control circuit being responsive to the load characteristic data from the electrical load and to a selection input for selecting the type of electrical load from a plurality of electrical load types, whereby the selection input determines the type of electrical load to enable the load characteristic data to be evaluated by the control circuit to generate the reference signal for the regulator.

[0007] The above and other objects are furthermore achieved by a power supply for powering a microprocessor load, the microprocessor load generating digital voltage identification (VID) codes that determine the input voltage to be provided to the microprocessor load from the power supply, the power supply comprising a voltage regulator for generating an output voltage to be provided as the input voltage for powering the microprocessor load, the voltage regulator being responsive to a reference voltage for setting the output voltage; and a VID control circuit for generating the reference voltage for the regulator, the VID control circuit being responsive to the digital VID codes from the microprocessor load and to a selection input for selecting the type of microprocessor load from a plurality of microprocessor load types, whereby the selection input determines the type of microprocessor load to enable the VID codes to be evaluated by the VID control circuit to generate the reference voltage for the regulator.

[0008] The objects of the invention are also achieved by a method for powering an electrical load, the electrical load generating load characteristic data that determines a power supply characteristic to be provided to the electrical load from the power supply, the method comprising generating an output voltage to be provided as the input voltage for powering the electrical load in response to a reference signal for setting a characteristic of the power supply, and generating the reference signal for the regulator in response to the load characteristic data from the electrical load and to a selection input for selecting the type of electrical load from a plurality of electrical load types, whereby the selection input determines the type of electrical load to enable the load characteristic data to be evaluated to generate the reference signal for the regulator.

[0009] The above and other objects are also achieved by a method for powering a microprocessor load, the microprocessor load generating digital voltage identification (VID) codes that determine the input voltage to be provided to the microprocessor load from the power supply, the method comprising generating an output voltage to be provided as the input voltage for powering the microprocessor load in response to a reference voltage for setting the output voltage; and generating the reference voltage for the regulator in response to the digital VID codes from the microprocessor load and to a selection input for selecting the type of microprocessor load from a plurality of microprocessor load types, whereby the selection input determines the type of microprocessor load to enable the VID codes to be evaluated to generate the reference voltage for the regulator.

[0010] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.

[0017] With reference to FIG. 1, the block diagram for a two-phase buck converter switching regulator power supply is shown. A control chip 10, whose block diagram is described with respect to FIG. 2 in more detail, receives a number of digital inputs VID0-VID5 referenced with 12 in FIG. 1. The VID inputs are received from the microprocessor being powered and are digital bits that will set the voltage output of the converter under various conditions. For example, for an Intel VR-10 chip, the output voltage varies between 0.8375V and 1.6000V depending on the setting of the digital bits on VID0 to VID5, as determined by the chip manufacturer. A pin VID_SEL (13) is used to indicate which processor chip is being powered, and this will enable control chip 10 to interpret the VID codes. For example, if VID SEL is grounded, the processor chip is an INTEL VR-10 and the VID codes will be interpreted to provide the proper voltage for this chip. If VID_SEL is at VCC, the processor is an AMD ATHLON. If VID_SEL is left open, the processor is an AMD HAMMER. For the ATHLON chip, the Vout range is from 1.100 to 1.850V. For the AMD HAMMER chip, the VOUT range is from 0.800 TO 1.550V. For all three processors, when all VID bits are 1, VOUT is disabled or OFF. In FIG. 1, VID_SEL is illustratively connected to ground, so control chip 10 will interpret he VID codes for the Intel VR-10 chip.

[0018] Returning to FIG. 1, power is provided at VIN from a suitable power source, typically a battery or an AC-DC transformer/rectifier. The control chip 10 has outputs GATE H1 and GATE L1 for driving the high side and low side transistors, respectively, of a first phase 14 of the multi-phase converter. Transistor H1 is the high side transistor and transistor L1 is the low side transistor.

[0019] Outputs GATE H2 and GATE L2 drive the second phase 16 comprising a high side transistor H2 and a low side transistor L2. Each set of transistors are arranged in a half bridge arrangement and their common connection is provided to respective output inductors L10 and L20. The other ends of inductors L10 and L20 are coupled together at a common output node VOUT+. The output is taken across an output capacitor COUT coupled between VOUT+ and ground (VOUT−).

[0020] The output voltage is sensed between VOUTSNS+ and VOUTSNS− which are respectively applied to a feedback FB input and VOSNS− input of the control chip 10. Current senses for each phase are provided at inputs CSINP1 and CSINP2, respectively. The current is sensed through lossless average inductor current sensing. The series resistor RCS1 and capacitor CCS1 for phase one are connected in series across the inductor L10. The voltage across the capacitor is sensed. The resistor RCS1 and capacitor CCS1 are chosen so that the time constant of RCS1 and CCS1 equals the time constant of the inductor which is the inductance of L10 divided by the inductor DC resistance. When the two time constants match, the voltage across CCS1 is proportional to the current in L10 and the sense circuit can be treated as if only a sense resistor with the value of RL (the DC resistance of L10) was used. A mismatch of the time constants does not affect the measurement of inductor DC current but affects the AC component of the inductor current. The advantage of sensing the inductor current verses high side or low side sensing is that actual output current being delivered to the load is sensed rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). The other phase two has a sensing resistor RCS2 and capacitor CCS2 and functions in the same way.

[0021] The block diagram of the control chip 10 is shown in more detail in FIG. 2. Voltage mode control with trailing edge modulation is used. A high gain, wide bandwidth voltage type error amplifier 50 is used in a voltage control loop. Output voltage sensing is provided at input FB which is provided to the inverting input of the error amplifier. The other, noninverting input is coupled to a voltage reference VDAC, which is set by the VID and VID_SEL pins as shown and described with reference to FIG. 1 above. The VID_SEL pin in FIG. 1 is shown grounded for the Intel VR10 chip. For other processors, for example, the AMD HAMMER or ATHLON processors, the VID_SEL pin is connected to a different potential or left open. For the AMD HAMMER processor, VID_SEL is open. For the AMD ATHLON chip, VID_SEL is connected to VCC. The setting of VDAC will determine the reference voltage VDAC for the error amplifier 50, and thus set the output voltage.

[0022] The control chip 10 includes an oscillator 60 which is programmable using an external resistor ROSC. The oscillator generates an internal 50 percent duty cycle sawtooth signal as shown in FIG. 3A. The 50 percent duty cycle sawtooth signal of FIG. 3A is used to generate two 180° out of phase timing pulse signals that set the phase 1 and phase 2 RS Flip Flops 70 and 80. The timing pulses are shown in FIGS. 3B and 3C and indicated in FIG. 2 as CLK1 and CLK2.

[0023] With reference to FIGS. 2 and 3, each flip flop 70 and 80, upon receiving a clock pulse, is set. Furthermore, a respective ramp voltage is provided to respective PWM comparators 90 and 100 at their non-inverting inputs. The error amplifier 50 output is provided to the inverting inputs of each of the PWM comparators. The PWM comparator 90 is provided with a fixed slope ramp voltage provided by current charging through a capacitor 10 from a current source IROSC/2. When the flip flop 70 is set, the low side switch L1 is turned off and the high side switch H1 is turned on. See also FIGS. 4A, C and D. A switch SW1 across capacitor 110 is opened by the QB output of Flip Flop 70, allowing the capacitor 10 to begin charging to provide the ramp voltage to PWM comparator 90. Likewise, in the other phase controlled by flip flop 80, the low side driver is turned off and the high side driver turned on upon receiving a clock pulse and a capacitor 120 begins to charge when a switch SW2 is opened by the QB output of flip flop 80.

[0024] For phase 1, the capacitor 10 is charged by a current source that is proportional to the switching frequency resulting in a fixed slope ramp rate of approximately 57 milivolts per percent duty cycle. For example, the steady state operating switch mode duty cycle is 10 percent and the internal ramp amplitude is typically 570 milivolts from the starting point to the time when the ramp crosses the output voltage of the error amplifier EAOUT as shown in FIG. 3D. In FIG. 3D, the fixed slope ramp signal provided to the non-inverting input of PWM comparator 90 is shown in the first and third quadrants of the graph.

[0025] In contrast, the PWM comparator 100 for the second phase is provided with a variable slope ramp voltage which is shown in the second and fourth quadrants of FIG. 3D and which will be explained in further detail below. For phase 1, when the PWM ramp voltage exceeds the error amplifier output voltage, the flip flop 70 is reset. This turns off the high side switch H 1 and turns on the low side switch L1 and discharges the PWM ramp to 0.7V until the next clock pulse. Flip Flop 80 and comparator 100 of phase 2 operate in similar fashion, although, as explained below, the slope of the ramp signal provided to the non-inverting input of comparator 100 is variable.

[0026] Each flip flop 70, 80 is reset dominant, allowing both phases to go to zero duty cycle within a few tens of nano-seconds in response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock voltage. An error amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement ensures that the error amplifier 50 is always in control and can demand 0-100% duty cycle if required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients.

[0027] This control method is designed to provide a single cycle transient response where the inductor current changes in response to load transients within a single switching cycle, maximizing the effectiveness of the power supply and minimizing the output capacitor requirements.

[0028] As discussed above, the ramp signals to the comparators 90 and 100 are different. The PWM comparator 90 receives a fixed slope ramp voltage as shown in quadrants 1 and III of FIG. 3D. The PWM comparator 100, in contrast, receives a variable slope ramp voltage as sown in Quadrants II and IV of FIG. 3D at its non-inverting input. This variable slope ramp voltage is adjusted by a share adjust error amplifier 130 in response to inputs CSINP1 and CSINP2.

[0029] The current sharing between the two phases is achieved by a master-slave current share loop topology. The output of the phase 1 current sense amplifier 140 sets a variable reference for the share adjust error amplifier 130. The share adjust error amplifier will then adjust the duty cycle of the PWM ramp 2 by adjusting its slope, as shown in FIG. 3D by the dashed lines, to force the input error of the share adjust amplifier to zero, resulting in accurate current sharing between the two phases.

[0030] The maximum and minimum duty cycle adjust range of ramp 2 compared to ramp 1 in the preferred embodiment is limited to 0.5× and 2.0× the master or fixed slope (phase 1) ramp signal. This is shown by the slope of the ramp voltage provided to the phase 2 PWM comparator 100 in FIG. 3D. Minimum duty cycle is shown by the ramp signal with the highest slope in FIG. 3D. The maximum duty cycle is shown by the ramp with the lowest slope in FIG. 3D.

[0031] The cross-over frequency of the current share loop can be programmed with a capacitor at the SCOMP input terminal so that the share loop does not interact with the output voltage loop. The SCOMP capacitor is driven by a transconductance stage capable of sourcing and sinking 25 microramps. The duty cycle of ramp 2 inversely tracks the voltage on the SCOMP pin. If the voltage SCOMP increases, the slope of the ramp provided to PWM comparator 100, that is, the phase 2 comparator, will increase and the respective duty cycle will decrease resulting in a reduction in the output current of phase 2. Due to the limited 25 microamp source current, an SCOMP precharge circuit is included to precondition V(SCOMP) so that the duty cycle of the ramp signal provided to PWM comparator 100 is equal to the duty cycle of ramp 1 prior to any gate pulses provided to the high side transistors.

[0032] As shown in FIGS. 2 and 3, the fixed ramp charges from a current source IROSC/2. The variable slope ramp charges at IROSC, but is shunted by a variable current sink 190, that sinks current in a range from 0 to IROSC x3/4. Thus, the range of current charging capacitor 120 ranges from IROSC to IROSC/4, that is, from 2× to ½ the charging rate of capacitor 110 in the fixed slope ramp generator circuit.

[0033] FIG. 4 depicts the PWM operating waveforms under various conditions for the first phase. The second phase is similar, except that the PWM ramp 2, unlike PWM ramp 1, has a variable slope. The CLK1 pulses are shown being provided to the flip flop 70. The error amplifier 50 output voltage EAOUT is shown in FIG. 4B for various load conditions. As shown in the left hand portion of FIG. 4B, when the ramp voltage to PWM comparator 90, herein identified as PWM ramp 1, equals the error amplifier 50 output voltage, the high side transistor is turned off and the low side transistor is turned on as shown in FIGS. 4C and 4D. At the next clock pulse (CLK1), the error amplifier output has increased, indicating that the output voltage has dropped due to higher current demands. Accordingly, the ramp voltage will equal the error amplifier voltage only after the ramp voltage has increased to a higher voltage level. This will ensure that the high side transistor has an increased duty cycle, that is, the pulse width is longer as shown in FIG. 4C, thus increasing the output current supplied to the phase 1 inductor. Correspondingly, the low side transistor will be off for a longer period of time as shown in FIG. 4D.

[0034] By the third clock pulse, as shown in FIG. 4, the error amplifier input is nearly zero, thus indicating that the current demands have decreased or there is a fault. If the error amplifier's output voltage drops below 0.55 volts, a zero percent duty cycle comparator 160 (FIG. 2) also turns off the low side transistor. As shown, the high side transistor is also off during this period.

[0035] By the fourth clock pulse of FIG. 4, the error amplifier output voltage has again increased and the ramp is shown in FIG. 4B and the gate drives are as shown in FIGS. 4C and 4D.

[0036] As shown in FIG. 3C, the circuit allows sharing of current by adjusting the slope of the ramp voltage to at least one, but not all of the PWM comparators. For a two phase converter, the slope of the ramp for only one phase is adjusted. For a three phase converer, two ramp slopes are adjusted. The slope of the ramp provided to the first comparator 90 provided at its non-inverting input is always constant as shown by fixed ramp 1 in FIG. 3D. For example, if the current demanded in phase I increases, this will be sensed at the node of resistor RCS1 and CCS1. The increased current will be reflected at the non-inverting input of amplifier 140, which is added to voltage VDAC by a summing stage 170. The increased output of the summing stage 170 is provided to the non-inverting input of the share adjust error amplifier 130, increasing the output of the share adjust error amplifier. This will increase the current through the current source 190, shunting current away from the capacitor 120, thereby increasing the time required to charge capacitor 120. The slope will flatten out as shown in FIG. 3D by the ramp 2 waveform having a longer duty cycle. This will cause the output of the PWM comparator 100 to stay low longer, thus ensuring that the flip flop 80 will remain set, keeping the high side transistor H2 on for a longer period of time, thus increasing the current available from the second phase. Thus, the second phase matches an increased current demanded by the first phase. As the second phase current increases, the first phase will compensate by decreasing until both phase currents are equal. This will occur because the error amplifier output will also decrease as the current supplied by the second phase increases.

[0037] Similarly, should the current in the second phase increase as sensed by the sense voltage CSINP2, the output of amplifier 150 will increase and hence the inverting input to the share adjust error amplifier 130 will increase, decreasing the output of the share adjust error amplifier. This will decrease the current shunted by current source 190, allowing capacitor 120 to charge more quickly and thus the ramp 2 voltage has a higher slope as indicated in FIG. 3D. Thus, the PWM comparator output will go high more quickly, resetting flip flop 80 and thereby turning off the high side transistor H2 thereby decreasing the current supplied by the second phase. At the same time, the error amplifier 50 output will have increased, thus lengthening the on time of the high side transistors of both phases. To compensate for the decreased current caused by the reduced ramp 2 slope, the first phase will supply current to match the reduced current supplied by the second phase. The current supplied by the two phases will be driven such that the error across the share adjust error amplifier inputs is driven to zero.

[0038] Conversely, should the current in phase 1 decrease, the non-inverting input of amplifier 130 will decrease, causing the output of amplifier 130 to decrease, resulting in capacitor 120 charging more quickly, turning off the high side transistor of phase 2 more quickly, reducing the phase 2 current to match phase 1.

[0039] Should the current in phase 2 decrease, the voltage at the inverting input of amplifier 130 will decrease, causing capacitor 120 to charge less quickly, increasing the current supplied by the phase 2 transistors. The phase 1 transistors will compensate by decreasing the current they supply to match the phase 2 transistors. Once the amplifier 130 inputs are equal, the output phase currents will be equal.

[0040] In all cases, although the error amplifier 50 output tracks the output current demands (it increases when the output current demand increases and decreases when the output current demand decreases), the share adjust amplifier 130 operates to equalize the currents in the plurality of phases. Accordingly, although the error amplifier 50 will operate to increase or decrease the current in all phases, as demanded by the load, the share adjust amplifier will operate to increase or decrease the currents supplied by the phases having PWM comparators driven by variable slope ramp signals to equalize the load currents in all the phases.

[0041] FIG. 5 shows details of the VID control circuitry for setting the output voltage of the converter.

[0042] The VID codes are received from the microprocessor at the VID inputs 12. The VID inputs 12 are each pulled up by respective current sources 300, for example, 18 μA current sources that pull up the inputs to 4.9 V, as shown by voltage source 301. Block 310 comprises a plurality of VID input comparators 310A to 310F (one for each VID input) having a threshold voltage 312. Only comparator 310A is shown. The threshold voltage 312 is determined by the input on VID_SEL. For the Intel VR-10 processor (HAMMER OR ATHLON), the threshold is 0.6V and for the AMD processors, the threshold is 1.5V for the AMD chips. When VID_SEL is open or at VCC, the threshold will be 1.5V. When VID_SEL is at ground, the threshold will be set to 0.6V for the Intel VR-10 Chip.

[0043] When VID_SEL is at ground potential, the outputs of comparators 320 and 330 will both be low, and this will inform Digital to Analog Converter (DAC) 340 that the VID codes should be interpreted for the Intel VR-10 chip. When inputs 350 and 360 are both low, the DAC 340 defaults to the Intel VR-10 chip VID codes. The low output of comparator 330 will also select the 0.6V threshold via switch 311.

[0044] When VID_SEL is open, the comparator 320 output will be low. When VID-SEL is open, the current source 321 will pull up VID-SEL to a voltage below the 3.3V reference for comparator 320, so its output will be low. However, the output of comparator 330, which has a 1.2V reference will be high, and thus input 360 will be high, instructing DAC 340 to interpret the VID codes for the AMD HAMMER Chip. At the same time, the high output of comparator 330 selects, via switch 311, the 1.5V threshold for the VID input comparators 310.

[0045] If VID_SEL is at VCC, then the outputs of comparators 320 and 330 are both high, thus informing DAC 340 that the VID codes should be interpreted for an AMD ATHLON processor chip. The high output of comparator 330 also selects the 1.5V threshold for VID input comparators 310.

[0046] Depending on the input VID bits, as decoded by comparators 310, DAC 340 will provide a reference voltage VDAC 380 via trans-conductance DAC buffer 360 to the error amplifier 50, described in connection wit FIGS. 2-4, to set the converter output voltage. The VDAC voltage is trimmed to the Error Amplifier output voltage with EAOUT tied to FB via an accurate resistor. This compensates DAC Buffer input offset, Error Amplifier input offset, and errors in the generation of the FB bias current which is based on R_ROSC. This trim method provides a 0.5% system accuracy.

[0047] The VID control circuit of FIG. 5 can accept changes in the VID code while operating and vary the VDAC voltage accordingly. The circuit detects a VID change and blanks the DAC 340 output response for 400 ns via blanking circuit 370 to verify the new code is valid and not due to skew or noise. The sink/source capability of the VDAC buffer amp 362 is programmed by the same external resistor that sets the oscillator frequency, R_ROSC, described previously. The slew rate of the voltage at the VDAC pin 380 can be adjusted by an external capacitor CDAC between VDAC pin and the VOSNS− pin. See FIG. 1. A RDAC resistor connected in series with this capacitor is used to compensate the VDAC buffer amplifier. See FIG. 1. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage.

[0048] Adaptive voltage positioning is used to reduce output voltage deviations during load transients and power dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in FIG. 2. Resistor RFB is connected between the inverting input of error amplifier 50 (pin FB) and the converter output voltage. An internal current source 200 whose value is programmed by the same external resistor that programs the oscillator frequency, R_ROSC, pumps current out of the FB pin. The FB bias current develops a positioning voltage drop across RFB which forces the converter's output voltage lower to V(VDAC)-I(FB)* RFB to maintain a balance at the error amplifier 50 inputs. RFB is selected to program the desired amount of fixed offset voltage below the DAC voltage.

[0049] The voltage at the VDRP pin is an average of both phase current sense amplifiers 140 and 150 and represents the sum of the VDAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor RDRP. The error amplifier 50 forces the voltage on the FB pin to equal VDAC through the power supply loop. Therefore, the current through RDRP is equal to (VDRP-VDAC)/R_DRP. As the load current increases, the VDRP voltage increases accordingly, which results in an increased RFB current, further positioning the output regulated voltage lower, thus making the output voltage reduction proportional to an increase in load current. The droop impedance or output impedance of the converter can thus be programmed by the resistor RDRP. The offset and slope of the converter output impedance are independent of the VDAC voltage.

[0050] AMD specifies the acceptable power supply regulation window as ±50 mV around AMD's specified VID table voltages. The VID table voltages are available in specifications from the chip manufacturers. Intel, for the VR-10.0, specifies the VID table voltages at the absolute maximum power supply voltage. In order to have all three DAC options, the HAMMER and ATHLON DAC output voltages are pre-positioned 50 mV higher than listed in AMD specifications. During testing, a series resistor is placed between EAOUT and FB to cancel the additional 50 mV out of the digital to analog converter. The FB bias current, equal to IROSC, develops the 50 mV cancellation voltage. Trimming the VDAC voltage by monitoring V(EAOUT) with this 50 mV cancellation resistor in circuit also trims out errors in the FB bias current.

[0051] The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can be retrieved by subtracting the VDAC voltage form the VDRP voltage.

[0052] FIG. 5 shows that the invention can determine or set other characteristics of the power supply in addition to the power supply output voltage. For example, the invention can be used to set the OVP (over-voltage protection) limit. Referring to FIG. 1, the control chip 10 has an OVP input 8. OVP input 8 sets the over-voltage protection limit for the power supply. For Intel chips, the OVP limit is 150 mV above VDAC. For AMD, it is 450 mV above VDAC. To accomplish this, an OVP comparator 390 is provided responsive to voltage FB (the output voltage of the power supply) and a selected voltage VDAC+150 mV or VDAC+450 mV. If VID_SEL is either at VCC or floating, line 360 will be high, meaning the load is an AMD chip, so switch 400 selects reference voltage 410 (450 mV). If line 360 is low, the load is as Intel VR-10.0 chip and reference voltage 420 (150 mV) is selected. Although the invention has been illustrated with reference to controlling the output voltage and OVP limit, it should be appreciated that other outputs or characteristics of the power supply can be similarly customized to the load by the invention.

[0053] Although the present invention has been described with reference to a 2 phase converter, the invention is also applicable to any type of power supply, for example, a single phase converter or converter having more than 2 phases or a non-converter power supply.

[0054] Also, although the invention has been described with reference to selecting between three load types (Intel VR-10.0, AMD ATHLON and AMD HAMMER), those of skill in the art will appreciate that the invention can be expanded to four or more load types, for example, four or more different microprocessor types. This can be accomplished by suitably designing the selection circuitry responsive to the VID-SEL pin so that it can discriminate between 4 or more procesor types. For example, as shown in FIG. 5, the VID-SEL pin provides three levels to the selection circuitry; ground, VCC and floating. To expand the circuit to accommodate four load types, a fourth level on VID-SEL can be provided (for example, a voltage level VBIAS between ground and VCC) and the selection circuitry appropriately redesigned, for example, by adding a further comparator or comparators.

[0055] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore, the present invention should be limited not by the specific disclosure herein, but only by the appended claims.