Method and apparatus for 3D interconnect

[0001] 1. Field of the Invention

[0002] The present invention relates to a method and apparatus for providing electrical interconnects. More specifically, the present invention relates to fabricating connective structures within defined areas of a substrate such as a semiconductor wafer, a semiconductor chip, a multichip module, or a printed wiring assembly. Further, the present invention relates to embodiments of electrically reactive interconnect components.

[0003] 2. Background of the Invention

[0004] Creating electrical interconnections is a challenging and essential part of manufacturing compact electronic components and systems, particularly in the field of manufacturing integrated circuits. Over time, automated methods have been developed to deposit conductive materials on substrates, in layers of substrates, or through cavities such as trenches, holes, and vias of a substrate. Deposition of materials in such cavities provides for electrical interconnections between conductive traces on multiple layers of a substrate, essentially connecting components and terminals in various locations of the substrate to create an integrated circuit or system. More specifically, in typical integrated circuits, multiple levels of interconnect networks extend laterally with respect to the substrate surface. Interconnects formed in parallel substrate interlayers can thus be electrically connected using vias or cavities filled with conductive materials.

[0005] In a typical integrated circuit fabrication process, first an insulating interlayer is formed on a semiconductor substrate. Patterning and etching processes (such as those incorporating reactive ion etching (RIE)) are employed to form features such as trenches, vias, and cavities in the insulating layer. Then a conductive material such as copper is deposited to fill the cavities by processes such as sputtering, CVD, electrodeposition, electroless plating, or a combination of those approaches. Once the conductive material is applied, a conventional process such as chemical-mechanical polishing/planarization (CMP) is employed to remove the excess conductive material that was deposited above the top surface of the substrate. This removal results in an essentially flat surface, which is substantially planar with the top surface of the remainder of the substrate. These processes are repeated multiple times to manufacture multi-layer interconnects.

[0006] Recently, research has been applied in the semiconductor fields to three-dimensional (3D) wafer- and package-level integration, which is becoming an increasingly important enabling technology for integrated circuits and packages. Three-dimensional integration offers potentials for higher device and package performance, greater interconnectivity and functionality, heterogeneous systems integration, reductions in packaging size and cost, and improvements in device and/or package reliability. One of the proposed approaches to implement 3D interconnection utilizes arrays of vias or cavities, which may vary dramatically in size within the same substrate.

[0007] Exemplary embodiments of prior art processes may be explained though review of FIGS. 1A, 1B, 2, and 3. Referring to FIG. 1A, a substrate 130 forms the mechanical support for an electrical interconnect system such as an integrated circuit 100, which is shown with a smaller via/cavity 110 and a substantially larger via/cavity 120. The illustrated vias or cavities 110, 120 may have been created by conventional processes such as patterning and etching. The vias or cavities such as the larger via 120 may include a void area in the substrate 130, having sidewalls 123 and a bottom 124. FIG. 1B depicts an exemplary cross section of the integrated circuit substrate 130 shown in FIG. 1A, the cross section being taken through line formed between points A-A′ in FIG. 1A. A conducting layer 140 is shown conformally coating the vias or cavities 110, 120 and the top surface 133 of the substrate 130, which may include an insulating layer such as SiO₂. The conducting layer 140 often comprises a barrier layer 155, and may also comprise a seed layer 157 which may be deposited on the barrier layer 155. Depending on the particular process used, the seed layer may range from 20 to 4000 angstroms in thickness. The barrier layer 155 coats the insulating layer to ensure good adhesion and acts as a barrier material to prevent diffusion of conductive materials such as copper into the insulating layers and into semiconductor devices fabricated in the substrate 130. The seed layer 157 forms a conductive material base for metal crystal growth such as when copper is used during subsequent metal depositions.

[0008] The illustrations in FIG. 1A and FIG. 1B show that some cavities or vias such as the larger via 120 may range in diameter 121 from 5 μm to 2000 μm or more. The depth 122 of vias or cavities 110, 120, may range between 20 to 1000 μm. More importantly perhaps, the dimensions of vias or cavities 110, 120 may vary substantially with respect to one another. This variation creates complications in implementing a cost- and time-efficient integrated circuit fabrication system.

[0009] In prior art systems, providing electrical conductivity through vias or cavities 110, 120 usually involves selectively applying a plating process to deposit conductive substances on or within the cavities or vias 110, 120. When depositing conductive material over the substrate 130, it is desirable to overfill the cavities to, for example, 20% to 200% of the via or cavity depth 122 in order to minimize defects in the wiring structure. However, when the dimensions of vias or cavities 110, 120 vary substantially within in the same substrate 130, the procedures required to consistently and reliably fill cavities of such varying sizes results in an expensive and high-cost production process. For example, with respect to FIG. 2, for a substrate 230 containing vias 210, 220 with diameters varying between 5 μm to 500 μm and approximately 50 μm deep, the smallest vias such as the illustrated 5 μm diameter via 210 may be completely filled with a conductive material 250 in 15 minutes by conventional electrocoating methods, while larger cavities such as the illustrated 30 μm and larger via 220 are substantially under-filled. To completely fill all vias 210, 220, as is shown in FIG. 3, a conductive material 250 (such as a copper film) is deposited (such as by electroplating) onto the conducting layer 140, and the conductive material 250 quickly fills the small via 110 but coats the wide via 220 and the surface of the substrate 230 in a conformal manner. For practical purposes, the metal deposition process may be required to operate for more than two hours to completely fill the 500 μm via 220 depicted in FIG. 3. After the larger via 220 is filled, a substantial overburden 240 is also deposited on the substrate 230. The maximum thickness of the overburden 240 that overlies the top surface 133 of the substrate 230 is related to the depth (FIG. 1B, 122) of the feature with the largest width (FIG. 1B, 121), to be filled on the substrate 230, which is in this example the cavity or via 220. As cavities or vias are filled, the thickness of overburden varies. For example, the deposited overburden 240 is thicker above over areas of the substrate 230 without vias or cavities, and the overburden 240b is thinner above areas such as the wide via or cavity 220. The substantial range of thicknesses in overburden (240, 240b) is problematic in many ways, particularly in planarization of the top surface of the substrate 230.

[0010] The overburden 240 must ultimately be removed with a conventional process such as a chemical-mechanical planarization (CMP) procedure, by an electro-chemical mechanical polishing/planarization procedure (eCMP), by a wet etch procedure, or by their various combinations. Polishing to remove such a large range of overburden depths is time consuming and expensive. In an exemplary prior art process, such extensive planarization processes have a throughput of less than one-third wafer per hour. Apart from higher process costs, device yields after such extensive deposition and etching steps may be negatively impacted, resulting in large variations in desirable device parameters. For example, when attempting to remove an overburden with wide ranges of thicknesses (240a, 240b), the areas over vias or cavities such as the large cavity 220 in FIG. 3 may be subject to dishing, or the excessive removal of material resulting in the creation of a non-planar surface above vias or cavities. What is needed, then, is a process for efficiently filling cavities in a substrate, particularly when cavities in a substrate vary in size with respect to one another. What is also needed is a method for filling vias or cavities within a substrate while minimizing the range thicknesses of overburden deposited above all areas of the substrate. What is also needed is a process and apparatus to form electrically conductive or electrically reactive components within a cavity in a substrate. What is further needed is a method to form bonding pads utilizing conductive structures within cavities or vias.

[0011] Terminology

[0012] The terms, chip, integrated circuit, monolithic device, semiconductor device or component, microelectronic device or component, and similar terms and expressions, are often used interchangeably in this field. The present invention is applicable to all the above as they are generally understood in the field, as well as to printed circuit boards, printed wiring boards, and printed wiring assemblies, also which may be used interchangeably.

[0013] The terms metal line, trace, wire, conductor, signal path and signaling medium are all related. These terms are generally interchangeable, and appear in order from specific to general. In this field, metal lines are sometimes referred to as traces, wires, lines, interconnects, conductive materials, or simply metal. The term vertical, as used herein, means substantially perpendicular to the major surface of a substrate. The term horizontal, as used herein, means substantially parallel to the major surface of a substrate.

[0014] The terms “cavity” and “via” both refer to structures providing electrical connection of conductors from different interconnect levels within a substrate, or from within a substrate to a next higher level assembly. Vias and trenches are forms of cavities typically used to provide for interconnection within a device. Cavities that are filled to provide electrical connections between a plurality of levels may be considered vias. Cavities that are filled to provide electrical connections within the same level may be referred to as trenches. These terms are sometimes used in the art to describe both an opening in an insulator in which the structure will be completed, and the completed structure itself.

[0015] As used herein, the term “filled” also means “substantially filled.”

[0016] Summary

[0017] The present invention discloses methods for depositing a material, particularly a conductive material, in cavities of a substrate and forming bonding contacts or pads thereon. Also provided are embodiments for interconnection structures using filled cavities, along with electrically reactive structures which may include capacitors fabricated within a substrate.

[0018] One embodiment includes a method for filling a cavity defined within a substrate, where the cavity has sidewalls, and optionally, a bottom. The method involves placing an intracavity structure within the cavity, the intracavity structure partitioning the cavity into a plurality of subcavities and substantially filling the subcavities with a conductive deposition material. As defined herein, partitioning may include a partial partitioning, that is, partitioning the cavity into subcavities that remain partially connected within the volume defined within the cavity. The intracavity structure may be fabricated outside the cavity and then placed within the cavity, or the intracavity structure may be fabricated within the cavity, by processes such as photolithography and etching.

[0019] The intracavity structure may comprise any suitable shape. In exemplary embodiments, structural elements of the intracavity structure may include an array of shaped elements such as hexagonal elements, conic elements, rectanguloid elements, cubic elements, trianguloid elements, torroidial elements, rhomboid elements, and combinations of those elements. In an alternate embodiment, the intracavity structure may comprise a plurality of elements that do not interconnect with one another, but provide structural support to the sidewalls and/or the bottom of a cavity or via. In another embodiment, the shaped elements of the intracavity structure, when aligned, form a substantially planar arrangement. In another embodiment, once the intracavity structure is placed within the cavity, at least part of the intracavity structure is reduced through a process such as etching, bringing the vertical dimension of the intracavity structure to an amount less than a predetermined vertical dimension of the sidewalls of the cavity.

[0020] In one embodiment, a barrier layer may be deposited on at least part of the intracavity structure, the bottom surface of the cavity, and/or the sidewalls of the cavity, for example, after the intracavity structure has been placed within the cavity. The barrier layer may be used to coat the sidewalls and/or bottom of the cavity to ensure good adhesion of further fill materials, and may act as a barrier material to prevent diffusion of conductive fill materials such as copper into the elements of the substrate such as insulating layers and semiconductor devices. The barrier layer may comprise any appropriate material, such as Ta, TaN, WCN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, NbN, AlN, or combinations of those materials.

[0021] In another embodiment, a seed layer may be deposited within at least a portion of the cavity. The seed layer forms a base for growth of a conductive material such as crystalline copper during subsequent conductive material deposition steps. In an alternate implementation, a second conductive layer may be deposited on the first layer of conductive deposition material in an amount sufficient to fill the cavity and create an overfilled volume above the tops of the cavity sidewalls. At least part of the second conductive layer may be removed to form a substantially planar surface with a top surface of the substrate by processes such as a CMP process, an eCMP process, or a milling process and other various combinations of these processes. The conductive material and the second conductive layer material deposited in the cavity, the subcavities, or on the substrate may comprise Cu, Ni, W, Au, Ag, Al, along with their alloys and other combinations of conductive materials.

[0022] In one implementation, a bonding layer, a barrier layer, or a combination of the two may be deposited on at least a portion of the surface of the planarized second conductive layer material. The barrier layer material may be any appropriate material such as CoP, NiP, CoBP, CoWP, along with their alloys and other combinations. The bonding layer may comprise indium, gold, copper, or other appropriate bonding materials.

[0023] In an alternate embodiment, functional components such as electrically reactive components may be formed within cavities by methods of the present invention. For example, but not by way of limitation, steps to form a reactive component such as a capacitor include depositing a conformal insulator within the cavity, depositing a conductive electrode layer on the conformal insulator, filling the remaining unoccupied volume of the cavity with a filling insulator; and planarizing the filling insulator to form a substantially planar surface with the substrate. The planarizing may be accomplished by processes such as a CMP process, an eCMP process, or a milling process, and combinations of these processes. The conductive electrode layer may be selected from materials such as Pt, Rh, WCN, and alpha-Ta.

[0024] In another implementation, methods of the present invention provide for partitioning the cavity into a plurality of subcavities, each of the subcavities having a respective predetermined subcavity volume. An initial conductive layer is deposited within at least one of the subcavity volumes, where the barrier layer is for electrical communication with a conductive element in the substrate. A conductive material may then be deposited within the plurality of subcavities. In one embodiment, the conductive material substantially fills at least one of the subcavity volumes to a predetermined amount. A second conducive material may be deposited proximate to the cavity defined within the substrate; and part of the second conductive material removed to form a substantially planar surface between the second conductive layer and a surface of the substrate such as the top of the substrate. In alternate embodiments, the predetermined subcavity volume is less than a volume of a second cavity defined within the substrate, where the cavity defined within the substrate and the second cavity are separated by at least part of the substrate.

[0025] In another embodiment, there is provided a method for filling a cavity defined within a substrate, the cavity having a bottom and sidewalls. The method includes placing a pre-formed structure within the cavity where the pre-formed structure partitions the cavity into a plurality of subcavities. The preformed structure may comprise any suitable material, but in certain embodiments may form conductive materials such as copper, aluminum, nickel, tungsten, silver, gold, or suitable alloys. The preformed structure may also, in alternate embodiments, comprise memory metals, or other composite substances such as alumina. In certain embodiments, the preformed structure has a predetermined vertical dimension less than a height dimension of the sidewalls and has a predetermined footprint area (e.g, the cross sectional area of a projection through the vertical dimension of the structure) that is less than or equal to an area of the bottom of the cavity. A metal layer is deposited within at least one of the subcavity volumes, where the metal layer is for electrical communication with a conductive element in the substrate such as a via or other conductive trace, and the subcavities are substantially filled with a conductive deposition material.

[0026] Another embodiment of the present invention provides for an interconnection feature that has a volume defined within a cavity in a substrate, one or more intracavity structures partitioning the volume into a plurality of subcavities; and a deposited metal layer substantially filling at least one of the plurality of subcavities. In one implementation, at least a portion of the deposited metal layer is for electrical communication with a conductive element of the substrate, such as a metal trace, a terminal of a component, or a via.

[0027] Embodiments of the present invention also provide for a substrate having electrically reactive component, such as a capacitor. The substrate, in one implementation, includes a cavity defined within the substrate, the cavity having a bottom and sidewalls. The substrate also has one or more intracavity structures residing within the cavity that partition the cavity into a plurality of subcavities, a conformal insulator coating the one or more intracavity structures, and a conductive electrode layer deposited within the cavity and in proximity to the conformal insulator. Embodiments further include a high-dielectric constant insulator deposited within the cavity and in communication with the conductive electrode layer, where the high-dielectric constant insulator substantially fills the volume in the cavity that is not occupied by the intracavity structures, the conformal insulator, and conductive electrode layer and forms a substantially planar surface with the substrate. Such an electrically reactive component may be fabricated in a variety of shapes and sizes, using geometries and materials (such as the choice of the high dielectric constant insulator) that are selected to achieve a desired electrical performance characteristic such as capacitance. In one embodiment, the substrate includes a cavity defined within the substrate, the cavity having sidewalls but no bottom and no top. In this embodiment, an intracavity structure may be inserted to begin the plating or deposition process, and at some point during the plating process, the intracavity structure may be removed from either the top or the bottom of the cavity, and once removed, plating process may be continued until the cavity has been filled to a desired amount. Removal of the intracavity structure may be by any appropriate means, such as mechanical force, chemical etching, RIE processes, or other techniques.

[0028] In another embodiment, there is provided a method for filling a cavity defined within a substrate, the cavity having sidewalls, including the steps of placing a pre-formed structure within the cavity, the pre-formed structure partitioning the cavity into a plurality of subcavities; depositing a metal layer within at least one of the subcavity volumes, wherein the metal layer is for electrical communication with a conductive element in the substrate; and substantially filling the subcavities with a conductive deposition material. In one implementation, the cavity further includes a bottom; and the pre-formed structure comprises a conductive material, has a predetermined vertical dimension less than a height dimension of the sidewalls, and has a predetermined footprint area less than or equal to an area of the bottom of the cavity. In an embodiment, the pre-formed structure comprises a non-conductive material; and has a predetermined footprint area less than or equal to an area of the bottom of the cavity. The pre-formed structure may reside entirely within, inside, or partially outside the via or cavity during application of a conductive material to the substrate, and after subcavities in the via or cavity are at least partially filled with a conductive deposition material, the pre-formed structure may be removed from the cavity and the substrate. Then a second conductive layer may be deposited on the previously deposited the conductive deposition material, the second conductive layer deposited in an amount sufficient to fill the cavity and create an overfill above a top surface of the substrate. At least a portion of the second conductive layer may then be removed to form a substantially planar surface including at least the second conductive layer and the substrate. In another embodiment, a second conductive layer may be deposited on a bottom surface of the substrate, the second conductive layer deposited in an amount sufficient to fill voids within the conductive deposition material; and then at least a portion of the second conductive layer may be removed to form a substantially planar surface on the bottom surface of the substrate. Further, an amount of conductive deposition material sufficient to fill the cavity and create an overfill above a top surface of the substrate may be deposited on a top side of the substrate; and at least a portion of the conductive deposition material may be removed to form a substantially planar surface including at least the conductive deposition material and a top surface of the substrate.

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.

[0061] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

[0062] Introduction

[0063] While systems and methods consistent with the present invention are implemented using a semiconductor substrate such as a chip or wafer, at least as described below with reference to FIG. 4A, those skilled in the art understand that embodiments consistent with the present invention may be employed more generally. For example, a method or apparatus consistent with the present invention may be implemented with any assembly, flexible or rigid, that can be energized to convey electrical signals, including but not by way of limitation, wafers, flat panels, magnetic film heads, integrated circuits, electronic devices, semiconducting chips, and packaging substrates. While vias, cavities, voids, and volumes described herein are shown in the drawings generally with rectanguloid or cylindrical shapes, those of skill in the art appreciate that any shape that is suitable to retain an electrical interconnect within a substrate may be used to implement aspects of the present invention. Additionally, aspects of the present invention may be employed with any process for manufacturing integrated circuits, substrates, electronic assemblies, or printed wiring boards that currently exists or is later developed, as long as such processes are capable of depositing and removing elements of a conductive interconnect structure within a cavity in a substrate.

[0064] Description

[0065] Reference will now be made in detail to the present exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings.

[0066] Embodiments of the present invention address the problems encountered in depositing conductive materials on substrates with deep cavities, especially where the opening dimension of the cavities vary greatly. In some implementations, the dimensions of the cavities are such that the large cavities on the substrate may be only filled by conformal electrodeposition process. The present invention discloses a structure and process that improves device yield and throughput.

[0067] One embodiment of a method of the present invention includes placing one or more intracavity structures within a cavity prior to deposition of a conductive material. With reference to FIG. 4A, elements of the intracavity structure 400 are shown within a large cavity 120 in a partial view of a substrate 130. The substrate may be part of a semiconductor integrated circuit or other electronic assembly 100. The smaller via or cavity 110 may or may not include a similar structure to the illustrated intracavity structure 400, although those of skill in the art that any number of cavities within a substrate 130 may include such structures.

[0068] In one embodiment, the intracavity structure 400 is placed in the cavity 120 by fabrication. The intracavity structure 400 may be fabricated by use of one or more conventional lithographic steps and etching processes to create a recessed substructure within large cavities in the substrate. The material comprising the structure may include conductors such as copper, aluminum, nickel, tungsten, silver, gold, or suitable alloys, or may comprise nonconductors including aluminum oxide, epoxy-based or non-epoxy based resins. In another embodiment, an expendable intracavity structure 400 may comprise one or more high temperature waxes or other materials that could be readily dissolved in a suitable solvent. The expendable intracavity structure may be pre-formed and placed within the via or cavity 120, or fluidly deposited in the via or cavity 120 by patterning, extrusion, adhesion, or any appropriate technique, and such fluidly deposited expendable intracavity structure may form a desired shape comprising subcavities. In this embodiment, the expendable intracavity structure 400 may be dissolved or otherwise removed after the via or cavity 120 has been partially plated, and then the plating process continued until a desired amount of fill has been achieved within the via or cavity 120.

[0069] The intracavity structure 400 may also be partially or completely pre-fabricated outside of the cavity. The intracavity structure 400 may be prefabricated by conventional means including, but not limited to such manufacturing techniques as lithography, RIE, forging, stamping, casting, welding, or other automated fabrication process. Referring to FIG. 4B, the prefabricated intracavity structure 400 is shown being inserted into the cavity or via 120, the prefabricated intracavity structure 400 being dimensioned to fit within the volume defined by the cavity 120. The structure 400 may be inserted into the cavity, and aligned within the cavity by any conventional means such as optical, mechanical, electronic, or any other alignment means. Once inserted, the intracavity structure 400 may be adhered to one or more of the sidewalls 123, and if the cavity 120 has a defined bottom 124 as shown in FIG. 4B, the intracavity structure 400 may be adhered to the bottom 124 of the cavity 120. Alternatively, the intracavity structure 400 may be sized so as to be set back from each of the sidewalls 123 and adhered to the bottom 124 of the via or cavity 120. Adhesion may be accomplished through a pressure/friction fit, an ultrasonic weld, surface tension, or an adhesive, or may be simply retained by gravity until a further deposition step secures the structure within the cavity. Whether the intracavity structure 400 is fabricated within the cavity 120 or prefabricated and inserted into the cavity 120, those of skill in the art appreciate that elements of the intracavity structure 400 may abut the walls 123 of the cavity 120, or may be physically disjoint from connection with the cavity walls 123. Those of skill in the art also appreciate that while the elements of the intracavity structure 400 are generally shown as rectangularly shaped in cross section, different cross-sectional profiles may result from the manufacturing or deposition process that creates the elements of the intracavity structure 400, including both linear, trapezoidal, and curvilinear profiles.

[0070] The structure 400 may be fabricated from silicon wafer by lithographic and RIE techniques. The patterned silicon substrate may then be oxidized to form SiO₂ layer over its surfaces. Using this approach, selected plating substances such as copper will not adhere to the SiO₂ but will adhere to conductive silicon. Similar approaches may be used on an intracavity structure 400 that is intended to be removed from a cavity or via 120 after the via or cavity is partially or fully filled (see, e.g., FIGS. 13-19).

[0071] Referring to FIGS. 6A-6E, different embodiments of intracavity structure 400 are shown from a plan view in relation to embodiments of a cavity or via 120. As mentioned above, the elements of the intracavity structure 400 may or may not come into contact with sidewalls (not shown) of the cavity 120. Elements of the intracavity structure 400 may consist of curvilinear and non-curvilinear geometrical elements or combination of both. When placed within a via or cavity, the geometrical elements of the intracavity structure 400 wholly or partially partition the volume of the cavity into subcavities 410. Embodiments of the intracavity structure 400 may comprise elongate elements that do not touchingly engage one another (FIG. 6A); formations of elements that intersect in a substantially orthogonal manner (FIG. 6B), arrays of elements that are disposed to form triangularly-arranged subcavities (FIG. 6C, 410), and arrays of elements that are disposed to form an array of heaxgonoid-bounded subcavities (FIG. 6D, 410). As mentioned elsewhere herein, embodiments of the present invention do not limit vias or cavities to rectanguloid shapes. For example, FIGS. 6E and 6F show cylinder-shaped vias or cavities 120 from a plan view, and elements of intracavity structures 400 in a non-curvilinear arrangement (FIG. 6E) and a curvilinear arrangement (FIG. 6F). In each embodiment, the intracavity space is wholly or partially partitioned into subcavities 410. Those of skill in the art should recognize that other shapes may be used, and that combinations of shapes of elements may be utilized in varying embodiments of the present invention.

[0072] With reference to FIG. 4C, a cross section of the substrate 130 is shown, where the cross section was taken along a witness line extended between points B and B′ in FIG. 4A. FIGS. 5 and 7-12 also show similar cross sectional depictions. In an exemplary embodiment, a horizontal dimension of a subcavity 410 is defined by the geometry and placement of elements of a intracavity structure 400, and may range, for example, between 5 to 20 microns, and in one embodiment, the thickness 420 of each element of an intracavity structure 400 is smaller than the distance or width 430 between adjacent elements of the intracavity structure 400. Alternatively, the thickness 420 of each element of an intracavity structure 400 may vary, and may be selected to comprise suitable dimensions to ensure even and efficient fill of a subcavity 410. For example but not by way of limitation, in one embodiment the thickness 420 of each element of an intracavity structure 400 may exceed the distance 430 between adjacent elements of the intracavity structure 400. In another embodiment, the placement of elements in the intracavity structure 400 is selected to create a subcavity width 430 that is substantially the same width as a smaller via 110. In one embodiment illustrated in FIG. 5, elements of the intracavity structure 400 are reduced in height by a predetermined amount 510 so that the reduced height 522 of the intracavity structure 400 is less than the depth 122 of the via or cavity 120. In one embodiment, elements of the intracavity structure are reduced in height by less than 50% of their originally fabricated height. In another embodiment, elements of the intracavity structure are reduced in height by a predetermined amount 510 that is equal to the final deposited thickness of the conductive substance (see, e.g., 800, FIG. 9). Height adjustment of the intracavity structure 400 may be followed by appropriate cleaning steps to remove residues. Those of skill in the relevant arts should appreciate that pre-fabricated intracavity structures 400 may also be fabricated to any desired height such as a height equal to or less than the depth 122 of the via or cavity 120 with or without a separate height reduction step.

[0073] As shown in FIG. 7 after the intracavity structure 400 is formed or deposited within the cavity or via 120, in one embodiment the substrate 130 is coated with a suitable barrier layer and/or seed layer 700 before deposition of a conductive material. The barrier and/or seed layer 700 also conformally coats the interior spaces of the via or cavity 120 as well as the intracavity structure 400.

[0074] With reference to FIG. 8, a conductive material 800 is shown deposited on the barrier and/or seed layer 700 on the substrate 130, coating and at least partially filling the cavities 110, 120, and subcavities 410. In one embodiment, the deposition process includes coating with a conductive material such as a metal using a plating bath containing superfilling additives and an adequate plating process to produce void-free depositions in the small cavity 110. The partitioned large cavity 120 with the recessed intracavity structure 400 is thus substantially filled while the small cavity 110 is filled. As FIG. 8 shows when compared to prior art FIG. 2, processes of the present invention produce a dramatic decrease in the amount of conductive material deposited in a single step without buildup of a substantial overburden, minimizing material and process costs.

[0075] With reference to FIG. 9, when additional conductive material completely fills the large cavity, an overburden 940 is created that is substantially smaller than the overburden resulting from prior art processes shown in FIG. 3 (240). The smaller total overburden and overburden range greatly improves the throughput of any subsequent metal removal steps in the present invention.

[0076] In various embodiments, various materials may be used as the conductive material 800 to fill cavities or vias 110, 120. These materials include, but are not limited to copper, nickel, tungsten, silver, aluminum or suitable metal or alloys. Although embodiments discussed in regards to the present invention identify such materials as “conductive materials,” those of ordinary skill in the arts appreciate that other substances, including nonconductive substances, may be used in a similar manner to completely or partially fill cavities or vias 110, 120 to achieve a desired result.

[0077] In certain embodiments, partitioning the large cavities 120 into subcavities 410 dramatically reduces the conductive material coating times from more than 120 minutes to less than 20 minutes. Further, methods of the present invention produce a dramatic reduction in conductive material overburden 940 from more than 50 μm for prior art approaches to less than 5 μm in certain implementations. The smaller overburden or other undesired substances may be easily removed by conventional processes such as CMP or eCMP methods. With reference to FIG. 10, the polished structure within the dashed box 1000 (the dashed box is for illustration purposes only and does not comprise part of the disclosed invention) includes conductive material-filled subcavities, separated by a now integrated intracavity structure 400. In an alternate embodiment, the volume above 1022 the integrated intracavity structure 400 is filled with a contiguous conductive material 800. In certain embodiments, the intracavity structure 400 acts as a stiffening member, especially in alternate implementations where the sidewalls are coated with high modulus barrier materials such as Ta, TaN, TaN/Ta, and WCN. The top surface 1020 of the polished structure 1000 forms a substantially planar surface with the polished top 1030 of the substrate 130, and the polished top 1010 of the smaller cavity or via 110. The deposited conductive material 800 may also be bonded to other structures.

[0078] For some applications, where the cavity depth (FIG. 5, 122) may range, for example, from 100 μm to more than 200 μm, by using methods of the present invention, the metal overburden may be reduced to less than 20 μm. Reducing or polishing a thick metal overburden is expensive and time consuming. In certain embodiments it is possible to remove most of the excess conductive material by a high precision, low force, high speed, and high throughput milling machine using a polyether phosphate solution as lubricant and a metal passivating agent. After the conductive material milling step is completed, any remaining unwanted metal or conductive material is removed by a conventional eCMP or CMP method.

[0079] With reference to FIG. 11, in alternate embodiments of this invention, the conductive material 800 deposited over the intracavity structure 400 may be selectively coated with a suitable barrier material 1110. For example, but not by way of limitation, CoWP and NiP may be deposited over the contiguous conductive material 800 by a method such as an electroless plating method. In an alternate embodiment, for bonding applications, the barrier material 1110 (such as NiP or CoWP) is preferably coated with gold by electroless methods to form a bonding layer 1120. Several desirable gold coated surfaces can be aligned and bonded at low temperatures. In alternate implementations, other barrier layers 1110 or films using materials such as CoBP and CoWP may be applied over the contiguous conductive material region of the filled via or cavity 120.

[0080] As shown in FIG. 12, in another embodiment of this invention, a thin layer 1220 (for example, but not by way of limitation, from 10 nm to 5000 nm in thickness) of a material such as indium may be selectively deposited over the conductive material 800 that fills the via or cavity 120. The indium layer 1220 may be used as a bonding layer at temperatures below 400 degrees Celsius. For improved device yields, in various embodiments it may be preferable to recess or remove portions of the substrate 130. This reduction or recess process may be accomplished by a process such as an RIE process followed by a possible cleaning step. In some embodiments, the reduction/recess steps may be conducted before the thin layer 1220 is deposited on the conductive material 800. This embodiment creates a new surface 1210 that causes any bond pads formed on the layer 1220 to be elevated above the substrate surface 1210.

[0081] Those of skill in the art also appreciate that the intracavity structures 400 of the present invention provide structural strength in the finished conductive element that results from filling the via or cavity 120 with a conductive material. Such strength may be desired when, for example, a bonding pad is to be fabricated on a surface of the filled via or cavity, and a significant mechanical force is required to be applied to the surface of the filled via or cavity to bond a device such as a bond wire to the bonding pad.

[0082] In another embodiment of this invention, the externally fabricated structure 400 may be inserted into the large cavities or vias 120 in the substrate 130. The conductive material is then plated substantially onto the substrate. The deposition step is momentarily stopped then the fabricated structure 400 is carefully removed. The substrate may be rinsed briefly to remove any residues or particulates before plating to complete the filling of the features of interest, such as a via or cavity 120. As discussed in more depth below, alternative embodiments allow from insertion of the pre-formed intracavity structure into either the top of the via or cavity 120, or through the bottom of a bottomless via or cavity 120.

[0083] As shown in cross section in FIG. 13 and by perspective in FIG. 23, a via or cavity 120 may be formed in the substrate 130 without a bottom. An intracavity structure 400 is inserted to the via or cavity 120 through a bottom side of the substrate 130. In various embodiments, the intracavity structure 400 may be insertable and removable, and may be reusable, dissolvable, or disposable. Those of skill in the art appreciate that the intracavity structure 400 may comprise any suitable shape to allow definition of subcavities within the via or cavity 120, and the relative thickness (see, e.g., 420 in regards to FIG. 4C) of the tines 1300 shown on the intracavity structure 400 may vary depending on desired fill rates of subcavity volumes. As FIGS. 13-21 are shown in cross section, the view of the intracavity structure 400 is also shown in cross section. While the tines 1300 are shown in rectilinear shape in FIGS. 13 and 23, those of skill in the art appreciate that the tines may comprise any suitable cross section, including a trapezoidal cross section with the broad end of the trapezoid adjacent to the base 1310 of the intracavity structure 400, whereby extraction of the intracavity structure 400 from a deposited conductive material may be facilitated.

[0084] Referring to FIG. 14, the intracavity structure 400 is fully inserted into the via or cavity 120, and in the illustrated embodiment, by approximating a bottom surface 1400 of the substrate 130, a surface of the intracavity structure defines a temporary bottom 1410 for the via or cavity 120, and similarly to the approach discussed in regards to FIG. 4C, the via or cavity 120 is thereby fully or partially partitioned into a plurality of subcavities 410. As discussed in regards to FIGS. 7-9, the via or cavity 120 may be partially or completely filled with a conductive material 800. FIG. 15 shows the via or cavity 120 coated with barrier/seed layer 700 and filled with conductive deposition material 800, and the intracavity structure 400 being withdrawn, (or alternatively, dissolved or otherwise removed) from the filled via or cavity 120. The intracavity structure 400 is shown fully withdrawn in FIG. 16, leaving defined voids 1600 within the filled cavity or via 120. Those of skill in the art appreciate that the voids 1600 may be left in place, or in one embodiment, additional conductive or nonconductive deposition material may then be deposited on the bottom side 1400 of the substrate 130 to fill the voids 1600, and if desired, additional planarization steps may be undertaken to remove any overburden from the bottom side 1400 of the substrate 130.

[0085] In another embodiment shown in cross section in FIG. 17 and by perspective in FIG. 22, the pre-formed intracavity structure 400 is partially or completely inserted into a via or cavity 120 in the substrate 130, the via or cavity 120 having a bottom 124. As shown in FIG. 18, the substrate 130 is optionally coated with a suitable barrier layer and/or seed layer 700 before deposition of a conductive material 800, and conductive material 800 is deposited, partially filling the via 110 and the via or cavity 120. During this step, additional conductive material creating an overburden may be deposited on exposed surfaces such as the top surface of the substrate 130, but for purposes of clarity, such overburden is omitted from FIGS. 18 and 19. Those of skill in the art recognize that the amount of conductive material 800 initially deposited may slightly fill, partially fill, substantially fill, completely fill, or overfill the via 110 and via or cavity 120.

[0086] FIG. 19 shows the intracavity structure 400 being withdrawn (or alternatively dissolved or otherwise removed) from the partially filled via or cavity 120, leaving behind voids 1900 in the conductive material. In a subsequent step shown in FIG. 20, additional conductive material 800 is deposited, completely filling the via 110, the via or cavity 120, and the voids 1900 (the now-filled voids 2010 and the prior fill level 2000 are shown for comparative purposes in dashed lines). IN another embodiment, the structure 400 may be selectively removed or dissolved through application of a suitable solvent or other removal process. As discussed in regards to other embodiments of the present invention and as illustrated in FIG. 21, a planarization process may be implemented to remove the deposited overburden 2020, and produce a substantially planar top surface 2100 of the substrate 130.

[0087] In still other embodiments of the present invention, an electrically reactive component may be formed within a cavity or via 120. In this embodiment, the walls of the subcavity may be coated with a conformal insulator. The insulator may be coated by a suitable metal such as platinum, rhodium. WCN, or alpha-Ta (i.e. the low resistivity crystalline phase of Tantalum). The remaining gap is the filled with a suitable insulator, preferably a high dielectric constant insulator. After the filling step, the substrate is planarized to form a high performance capacitor. Such device structure may find applications in such practices as high precision timing elements.

[0088] In another embodiment, methods of the present invention may be utilized to deposit traces or signal lines with embedded void areas that have purposely been left unfilled, or filled with a nonconductor or dielectric. Those of skill in the relevant arts appreciate that high frequency signals tend to travel toward the surface of a conductor, and the higher the frequency, the less the signal penetrates into the cross section of the conductor (also known as the “skin effect”). This effect allows high frequency signals to propagate through these void-embedded or dielectric-filled signal lines substantially unimpeded. Further, this use of intentionally fabricated voids or dielectric-filled trace or signal lines may also be desirable to obtain a desired characteristic impedance of the trace or signal lines, where higher frequency signals may effectively propagate, while lower frequency signals are selectively impeded. Embodiments of such void-containing traces or signals lines may also provide for a filtered signal line, such as provided by a passive high-pass filter. Selection of the geometry and aspect of the signal lines with respect to the embedded voids or dielectric fills provides for flexibility of selecting characteristic impedance or transmission line performance.

[0089] Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. Any combination and/or subset of the elements of the methods described herein may be practiced in any suitable order and in conjunction with any system, device, and/or process. The methods described herein can be implemented in any suitable manner, such as through software operating on one or more computer systems or fabrication equipment controlled by computer systems. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.