US 7,863,187 B2Grant
Microfeature workpieces and methods for forming interconnects in microfeature workpieces
Issue Date:2011-01-04
•39 Claims
•7 Drawing Sheets
Abstract
Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.
Metadata
Assignee
- Micron Technology, Inc.
Inventors
- William M. Hiatt
- Ross S. Dando
Application Information
Application Number:US 11/217,169
Filing Date:2005-09-01
Priority Date:2005-09-01
Art Unit:2891
Classifications
IPC:
H01L21/44
Patent Drawings (7 sheets)
Description
TECHNICAL FIELD
[0001] The present invention relates to methods for forming interconnects in microfeature workpieces and microfeature workpieces formed using such methods.
BACKGROUND
[0002] Microelectronic devices, micromechanical devices, and other devices with microfeatures are typically formed by constructing several layers of components on a workpiece. In the case of microelectronic devices, a plurality of dies are fabricated on a single workpiece, and each die generally includes an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The dies are separated from each other and packaged to form individual microelectronic devices that can be attached to modules or installed in other products.
[0003] One aspect of fabricating and packaging such dies is forming interconnects that electrically couple conductive components located in different layers. In some applications, it may be desirable to form interconnects that extend completely through the dies or through a significant portion of the dies. Such interconnects electrically couple bond-pads or other conductive elements proximate to one side of the dies to conductive elements proximate to the other side of the dies. Through-wafer interconnects, for example, are constructed by forming deep vias on the front side and/or backside of the workpiece and in alignment with corresponding bond-pads at the front side of the workpiece. The vias are often blind vias in that they are closed at one end. The blind vias are then filled with a conductive fill material. After further processing, the workpiece is thinned to reduce the thickness of the final dies. Solder balls or other external electrical contacts are subsequently attached to the through-wafer interconnects at the backside and/or the front side of the workpiece. The solder balls or external contacts can be attached either before or after singulating the dies from the workpiece.
[0004] Conventional processes for forming external contacts on through-wafer interconnects include (a) depositing a dielectric layer on the backside of the workpiece, (b) forming a photoresist on the dielectric layer, (c) patterning and developing the photoresist, (d) etching the dielectric layer to form holes aligned with corresponding interconnects, (e) removing the photoresist from the workpiece, and (f) forming conductive external contacts in the holes in the dielectric layer. One concern with forming external contacts on the backside of a workpiece is that conventional processes are relatively expensive because patterning the photoresist requires a mask. Masks are expensive and time-consuming to construct because they require very expensive photolithography equipment to achieve the tolerances required in semiconductor devices. Accordingly, there is a need to reduce the cost of forming external contacts on workpieces with through-wafer interconnects.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIGS. 1A-1I illustrate stages of a method for forming interconnects in a microfeature workpiece in accordance with one embodiment of the invention.
[0006] FIG. 1A is a schematic side cross-sectional view of a portion of the workpiece at an intermediate stage after partially forming a plurality of interconnects.
[0007] FIG. 1B is a schematic side cross-sectional view of the area 1B shown in FIG. 1A with the workpiece flipped over.
[0008] FIG. 1C is a schematic side cross-sectional view of the portion of the workpiece after thinning the substrate from the second side.
[0009] FIG. 1D is a schematic side cross-sectional view of the portion of the workpiece after selectively removing additional material from the second side of the substrate so that the interconnect projects from the substrate.
[0010] FIG. 1E is a schematic side cross-sectional view of the area 1E shown in FIG. 1D after forming a recess in the second end portion of the interconnect.
[0011] FIG. 1F is a schematic side cross-sectional view of the portion of the workpiece after forming a dielectric structure across the second side of the substrate and the second end portion of the interconnect.
[0012] FIG. 1G is a schematic side cross-sectional view of the portion of the workpiece after removing sections of the interconnect and the dielectric structure.
[0013] FIG. 1H is a schematic side cross-sectional view of the portion of the workpiece after removing the section of the first dielectric layer from the recess in the interconnect.
[0014] FIG. 1I is a schematic side cross-sectional view of the portion of the workpiece after forming a conductive member at the second end portion of the interconnect.
[0015] FIGS. 2A-2C illustrate stages in a method for forming interconnects in a microfeature workpiece in accordance with another embodiment of the invention.
[0016] FIG. 2A is a schematic side cross-sectional view of a portion of the workpiece at an intermediate stage after partially forming an interconnect.
[0017] FIG. 2B is a schematic side cross-sectional view of the portion of the workpiece after removing sections of the interconnect and the dielectric structure.
[0018] FIG. 2C is a schematic side cross-sectional view of the portion of the workpiece after forming the conductive member on the exposed surface of the interconnect.
[0019] FIGS. 3A-3C illustrate stages in a method for forming interconnects in a microfeature workpiece in accordance with another embodiment of the invention.
[0020] FIG. 3A is a schematic side cross-sectional view of a portion of the workpiece at an intermediate stage after partially forming an interconnect.
[0021] FIG. 3B is a schematic side cross-sectional view of the portion of the workpiece after removing sections of the interconnect and the dielectric structure.
[0022] FIG. 3C is a schematic side cross-sectional view of the workpiece after forming a conductive member on the exposed surface of the interconnect.
DETAILED DESCRIPTION
A. Overview
[0023] The following disclosure describes several embodiments of methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects. One aspect of the invention is directed to methods of forming an interconnect in a microfeature workpiece having a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. An embodiment of one such method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate. The material can be removed from the second side of the substrate by thinning the substrate so that a surface of the interconnect is exposed and selectively etching the substrate so that the portion of the interconnect projects from the substrate.
[0024] In another embodiment, a method includes providing a microfeature workpiece having (a) a substrate with a first side and a second side opposite the first side, (b) a terminal carried by the first side of the substrate, and (c) an electrically conductive interconnect extending from the terminal through the substrate and projecting from the second side of the substrate. The method further includes applying a dielectric layer to the second side of the substrate and the portion of the interconnect projecting from the second side of the substrate, and removing a section of the dielectric layer to expose a surface of the interconnect with the interconnect intersecting a plane defined by the remaining section of the dielectric layer.
[0025] In another embodiment, a method includes forming an electrically conductive interconnect having a first portion at the terminal and a second portion at an intermediate depth in the substrate. The electrically conductive interconnect is electrically connected to the terminal. The method further includes thinning the substrate from the second side to at least the second portion of the interconnect, applying a dielectric layer to the second side of the substrate and the second portion of the interconnect, and exposing a surface of the second portion of the interconnect without photolithography.
[0026] Another aspect of the invention is directed to microfeature workpieces. In one embodiment, a microfeature workpiece includes a substrate and a microelectronic die formed in and/or on the substrate. The substrate has a first side and a second side opposite the first side. The die includes a terminal at the first side of the substrate and an integrated circuit operably coupled to the terminal. The workpiece further includes an electrically conductive interconnect extending from the terminal through the substrate such that a portion of the interconnect projects from the second side of the substrate. The interconnect is electrically coupled to the terminal.
[0027] In another embodiment, a microfeature workpiece includes a substrate and a microelectronic die formed in and/or on the substrate. The substrate has a first side and a second side opposite the first side. The die includes a terminal at the first side of the substrate and an integrated circuit operably coupled to the terminal. The workpiece further includes (a) a hole extending through the terminal and the substrate, (b) a dielectric layer on the second side of the substrate defining a plane, and (c) an electrically conductive interconnect. The interconnect includes a conductive fill material in the hole and a conductive layer in the hole between the conductive fill material and the substrate. Both the conductive fill material and the conductive layer are electrically coupled to the terminal and extend from the terminal through the substrate. Moreover, both the conductive fill material and the conductive layer project from the substrate such that the conductive fill material and the conductive layer intersect the plane.
[0028] Specific details of several embodiments of the invention are described below with reference to interconnects extending from a terminal proximate to the front side of a workpiece, but the methods and interconnects described below can be used for other types of interconnects within microelectronic workpieces. Several details describing well-known structures or processes often associated with fabricating microelectronic devices are not set forth in the following description for purposes of clarity. Also, several other embodiments of the invention can have different configurations, components, or procedures than those described in this section. A person of ordinary skill in the art, therefore, will accordingly understand that the invention may have other embodiments with additional elements, or the invention may have other embodiments without several of the elements shown and described below with reference to FIGS. 1A-3C .
[0029] The term “microfeature workpiece” is used throughout to include substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, optics, and other features are fabricated. For example, microfeature workpieces can be semiconductor wafers, glass substrates, dielectric substrates, or many other types of substrates. Many features on such microfeature workpieces have critical dimensions less than or equal to 1 μm, and in many applications the critical dimensions of the smaller features are less than 0.25 μm or even less than 0.1 μm. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from other items in reference to a list of at least two items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is used throughout to mean including at least the recited feature(s) such that any greater number of the same features and/or types of other features and components are not precluded.
B. Embodiments of Methods for Forming Interconnects in Microfeature Workpieces
[0030] FIGS. 1A-1I illustrate stages of a method for forming interconnects in a microfeature workpiece 100 in accordance with one embodiment of the invention. FIG. 1A , for example, is a schematic side cross-sectional view of a portion of the workpiece 100 at an intermediate stage after partially forming a plurality of interconnects 140. The workpiece 100 can include a substrate 110 and a plurality of microelectronic dies 120 formed in and/or on the substrate 110. The substrate 110 has a first side 112 and a second side 114 opposite the first side 112. The substrate 110 is generally a semiconductor wafer, and the dies 120 are arranged in a die pattern on the wafer. The individual dies 120 include integrated circuitry 122 (shown schematically) and a plurality of terminals 124 (e.g., bond-pads) electrically coupled to the integrated circuitry 122. The terminals 124 shown in FIG. 1A are external features at the first side 112 of the substrate 110. In other embodiments, however, the terminals 124 can be internal features that are embedded at an intermediate depth within the substrate 110. Moreover, in additional embodiments, the dies 120 can have different features to perform different functions. For example, the individual dies may further include an image sensor (e.g., CMOS image sensor or CCD image sensor) for capturing pictures or other images in the visible spectrum, or detecting radiation in other spectrums (e.g., IR or UV ranges).
[0031] In previous processing steps, a first dielectric layer 130 was applied to the first side 112 of the substrate 110, and the interconnects 140 were partially formed in the workpiece 100. The first dielectric layer 130 can be a polyimide material or other suitable nonconductive materials. For example, the first dielectric layer 130 can be parylene, a low temperature chemical vapor deposition (low temperature CVD) material such as silicon nitride (Si3N4), silicon oxide (SiO2), and/or other suitable materials. The foregoing list of dielectric materials is not exhaustive. The conductive interconnects 140 extend from the first dielectric layer 130 to an intermediate depth in the substrate 110. As described in greater detail below with regard to FIG. 1B , the conductive interconnects 140 can include several layers of conductive material that are electrically coupled to corresponding terminals 124. Suitable methods for forming the portion of the interconnects 140 illustrated in FIG. 1A are disclosed in U.S. patent application Ser. Nos. 10/713,878; 10/867,352; 10/879,398; 11/027,443; 11/056,211; 11/169,546; 11/217,877; and 11/218,243, which are incorporated herein by reference. After partially forming the interconnects 140, the workpiece 100 can optionally be attached to a support member 190 with an adhesive 192 to provide rigidity to the workpiece 100 during subsequent processing steps.
[0032] FIG. 1B is a schematic side cross-sectional view of the area 1B shown in FIG. 1A with the workpiece 100 flipped over. The workpiece 100 includes an interconnect hole 180 extending from the terminal 114 to an intermediate depth in the substrate 110, a second dielectric layer 132 in the interconnect hole 180, and a vent hole 182 extending from the interconnect hole 180 to the second side 114 of the substrate 110. The second dielectric layer 132 electrically insulates components in the substrate 110 from the interconnect 140. The second dielectric layer 132 can be an ALD (atomic layer deposition) aluminum oxide material applied using a suitable deposition process or another suitable low temperature CVD oxide. In another embodiment, the second dielectric layer 132 can include a silane-based and/or an aluminum-based oxide material. In still further embodiments, the second dielectric layer 132 can include other suitable dielectric materials.
[0033] The illustrated interconnect 140 is formed in the interconnect hole 180 and has a first end portion 142 at the first dielectric layer 130 and a second end portion 144 at an intermediate depth in the substrate 110. The illustrated interconnect 140 includes a diffusion barrier layer 150 deposited over the second dielectric layer 132 in the hole 180, a seed layer 152 formed over the barrier layer 150 in the hole 180, a conductive layer 154 deposited over the seed layer 152 in the hole 180, and a conductive fill material 152 formed over the conductive layer 154 in the hole 180. The diffusion barrier layer 150 can be a layer of tantalum that is deposited onto the workpiece 100 using physical vapor deposition (PVD) and has a thickness of approximately 150 Angstroms. In other embodiments, the barrier layer 150 may be deposited onto the workpiece 100 using other vapor deposition processes, such as CVD, and/or may have a different thickness. In either case, the barrier layer 150 is not limited to tantalum, but rather may be composed of tungsten or other suitable materials that help contain the conductive fill material 156 in the interconnect hole 180.
[0034] The seed layer 152 can be deposited using vapor deposition techniques, such as PVD, CVD, atomic layer deposition, and/or plating. The seed layer 152 can be composed of Cu or other suitable materials. The thickness of the seed layer 152 may be about 2000 Angstroms, but could be more or less depending on the depth and aspect ratio of the hole 180. The conductive layer 154 can be Cu that is deposited onto the seed layer 152 in an electroless plating operation, electroplating operation, or another suitable method. The thickness of the conductive layer 154 can be about 1 micron, however, in other embodiments the conductive layer 154 can have a different thickness and/or include other suitable materials. In additional embodiments, the workpiece 100 may include a second conductive layer (not shown) that is deposited over the conductive layer 154 in the hole 180. The second conductive layer can be Ni or other suitable materials that function as a wetting agent for facilitating deposition of subsequent materials into the hole 180.
[0035] The conductive fill material 156 can include Cu, Ni, Co, Ag, Au, SnAgCu solder, AuSn solder, a solder having a different composition, or other suitable materials or alloys of materials having the desired conductivity. The conductive fill material 156 may be deposited into the hole 180 using plating processes, solder wave processes, screen printing processes, reflow processes, vapor deposition processes, or other suitable techniques. In other embodiments, the interconnects may have a different structure. For example, the interconnects may have additional layers in lieu of or in addition to the layers described above.
[0036] FIG. 1C is a schematic side cross-sectional view of the portion of the workpiece 100 after thinning the substrate 110 from the second side 114. The substrate 110 can be thinned by grinding, dry etching, chemical etching, chemical polishing, chemical-mechanical polishing, or other suitable processes. The thinning process may also remove a section of the second end portion 114 of the interconnect 140. For example, in one embodiment, the initial thickness of the substrate 110 is approximately 750 microns and the interconnect 140 extends to an intermediate depth of approximately 150 microns in the substrate 110, and the post-thinning thickness T of the substrate 110 is approximately 140 microns. These thicknesses can be different in other embodiments. After thinning the workpiece 100, the illustrated interconnect 140 includes an exposed surface 146 at the second end portion 144.
[0037] FIG. 1D is a schematic side cross-sectional view of the portion of the workpiece 100 after selectively removing additional material from the second side 114 of the substrate 110 so that the interconnect 140 projects from the substrate 110. The additional material can be removed via a plasma etch with SF6 or another suitable etchant that is selective to silicon. Alternatively, the additional material can be removed with other processes. In either case, after thinning the substrate 110, the second end portion 144 of the interconnect 140 projects a first distance D1 from the second side of the substrate 110. In several embodiments, the first distance D1 is between approximately 5 and 10 microns, although the first distance D1 can be less than 5 microns or more than 10 microns in other embodiments. The first distance D1 is selected based on the subsequent processing and application requirements.
[0038] FIG. 1E is a schematic side cross-sectional view of the area 1E shown in FIG. 1D after forming a recess 158 in the second end portion 144 of the interconnect 140. In the illustrated embodiment, the recess 158 is formed by removing a portion of the conductive fill material 156 from the interconnect 140. The conductive fill material 156 can be removed by a wet etch process with an etchant that is selective to the conductive fill material 156 and, consequently, removes the conductive fill material 156 at a faster rate than the seed and/or conductive layers 152 and/or 154. The illustrated recess 158 extends from the surface 146 of the interconnect 140 to a surface 157 of the conductive fill material 156, and has a depth D2 less than the first distance D1. The depth D2 of the recess 158 is selected based on the subsequent processing and application requirements. In other embodiments, such as the embodiments described below with reference to FIGS. 2A-3C , the interconnects may not include a recess in the second end portion 144.
[0039] FIG. 1F is a schematic side cross-sectional view of the portion of the workpiece 100 after forming a dielectric structure 170 across the second side 114 of the substrate 110 and the second end portion 144 of the interconnect 140. The illustrated dielectric structure 170 includes a first dielectric layer 172 and a second dielectric layer 174 deposited on the first dielectric layer 172. The first dielectric layer 172 can be parylene HT and have a thickness of approximately 0.5 micron. In other embodiments, other dielectric materials can be used and/or have different thicknesses. The second dielectric layer 174 can be an oxide such as silicon oxide (SiO2) and/or other suitable materials that are deposited by chemical vapor deposition and/or other suitable processes. In additional embodiments, the dielectric structure 170 can include a different number of layers.
[0040] FIG. 1G is a schematic side cross-sectional view of the portion of the workpiece 100 after removing sections of the interconnect 140 and the dielectric structure 170. The sections of the interconnect 140 and the dielectric structure 170 can be removed by grinding, dry etching, chemical etching, chemical polishing, chemical-mechanical polishing, or other suitable processes. In the illustrated embodiment, the workpiece 100 is polished to remove portions of the second dielectric layer 132, the barrier layer 150, the seed layer 152, the conductive layer 154, the first dielectric layer 172, and the second dielectric layer 174. The volume of material removed is selected so that (a) the recess 158 in the interconnect 140 has a desired depth D3, and (b) the interconnect 140 projects a desired distance D4 from an exterior surface 175 of the dielectric structure 170. In other embodiments, such as the embodiment described below with reference to FIGS. 3A-3C , the interconnect may not project from the exterior surface 175 of the dielectric structure 170. In either case, the interconnect 140 intersects a plane defined by the dielectric structure 170.
[0041] FIG. 1H is a schematic side cross-sectional view of the portion of the workpiece 100 after removing the section of the first dielectric layer 172 from the recess 158 in the interconnect 140. The section of the first dielectric layer 172 can be removed from the recess 158 by a plasma etching process (e.g., O2 plasma) or another suitable method that selectively removes the first dielectric layer 172 without significantly effecting the dielectric structure 170 formed on the substrate 110.
[0042] FIG. 1I is a schematic side cross-sectional view of the portion of the workpiece 100 after forming a conductive member 160 on the second end portion 144 of the interconnect 140. The illustrated conductive member 160 is a cap disposed in the recess 158 and extending over the barrier layer 150, the seed layer 152, and the conductive layer 154. The cap projects a desired distance D5 from the substrate 110 and forms an external contact for connection to an external device. The conductive member 160 can be electrolessly plated onto the second end portion 144 of the interconnect 140 or formed using other suitable processes. The conductive member 160 can include Ni or other suitable conductive materials. In other embodiments, the interconnect 140 may not include the conductive member 160. For example, the second end portion 144 of the interconnects 140 can be attached directly to an external device, or a conductive coupler (e.g., a solder ball) can be attached directly to the second end portion 144.
[0043] One feature of the method illustrated in FIGS. 1A-1I is that the interconnect 140 projects from the substrate 110. As a result, the section of the dielectric structure 170 covering the interconnect 140 can be removed by a simple polishing process without exposing the backside of the substrate 110. The resulting exposed surface 146 on the interconnect 140 may form an external contact to which an external device can be attached. Alternatively, the conductive member 160 can be disposed on the exposed surface 146 and form the external contact. In either case, an advantage of this feature is that the illustrated method does not require expensive and time-consuming photolithography processes to form external contacts on the backside of the workpiece 100.
[0044] Another advantage of the method illustrated in FIGS. 1A-1I is that the interconnect 140 can be sized to project a desired distance from the external surface 175 of the dielectric structure 170. The distance can be selected based on the application requirements for the die 110. For example, in applications in which the die 110 is stacked on another die, the distance may be selected to provide a desired gap between the two dies.
C. Additional Embodiments of Methods for Forming Interconnects in Microfeature Workpieces
[0045] FIGS. 2A-2C illustrate stages in a method for forming interconnects in a microfeature workpiece 200 in accordance with another embodiment of the invention. FIG. 2A , for example, is a schematic side cross-sectional view of a portion of the workpiece 200 at an intermediate stage after partially forming an interconnect 240. The illustrated workpiece 200 is generally similar to the workpiece 100 described above with reference to FIGS. 1A-1F . For example, the illustrated workpiece 200 includes a substrate 110, an interconnect 240 extending through and projecting from the substrate 110, and a dielectric structure 270 formed over the substrate 110 and the interconnect 240. The illustrated interconnect 240, however, does not include a recess at the second end portion 244.
[0046] FIG. 2B is a schematic side cross-sectional view of the portion of the workpiece 200 after removing sections of the interconnect 240 and the dielectric structure 270. The sections of the interconnect 240 and the dielectric structure 170 can be removed by grinding, dry etching, chemical etching, chemical polishing, chemical-mechanical polishing, or other suitable processes. The volume of the material removed is selected so that the interconnect 240 projects a desired distance D6 from an exterior surface 275 of the dielectric structure 270. The illustrated interconnect 240 includes a generally planar exposed surface 246 extending across the barrier layer 150, the seed layer 152, the conductive layer 154, and the conductive fill material 156.
[0047] FIG. 2C is a schematic side cross-sectional view of the portion of the workpiece 200 after forming a conductive member 260 on the generally planar exposed surface 246 of the interconnect 240. The conductive member 260 forms part of the electrically conductive interconnect 240 and, accordingly, is electrically coupled to the terminal 114 (FIG. 1B ).
[0048] FIGS. 3A-3C illustrate stages in a method for forming interconnects in a microfeature workpiece 300 in accordance with another embodiment of the invention. FIG. 3A , for example, is a schematic side cross-sectional view of a portion of the workpiece 300 at an intermediate stage after partially forming an interconnect 340. The illustrated workpiece 300 is generally similar to the workpiece 200 described above with reference to FIG. 2A . For example, the illustrated workpiece 300 includes a substrate 110, an interconnect 340 extending through and projecting from the substrate 110, and a dielectric structure 370 formed over the substrate 110 and the interconnect 340.
[0049] FIG. 3B is a schematic side cross-sectional view of the portion of the workpiece 300 after removing sections of the interconnect 340 and the dielectric structure 370. The sections of the interconnect 340 and the dielectric structure 370 are removed to form a generally planar surface across the workpiece 300 such that an exposed surface 346 of the interconnect 340 is generally coplanar with an exterior surface 375 of the dielectric structure 370.
[0050] FIG. 3C is a schematic side cross-sectional view of the workpiece 300 after forming a conductive member 360 on the exposed surface 346 of the interconnect 340. The conductive member 360 forms part of the electrically conductive interconnect 340 and, accordingly, is electrically coupled to the terminal 114 (FIG. 1B ).
[0051] From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. For example, many of the elements of one embodiment can be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the invention is not limited except as by the appended claims.
Claims
We claim:
1. A method for forming an interconnect in a microfeature workpiece, the microfeature workpiece including a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side, the method comprising:
constructing an electrically conductive interconnect with a barrier material insulating the interconnect from the substrate and covering an end of the interconnect, the interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal;
removing material from the second side of the substrate and from the barrier material so that a portion of the interconnect projects from the substrate and the interconnect has an exposed, conductive surface at the end of the interconnect;
depositing a first dielectric layer composed of a first material onto the exposed, conductive surface of the portion of the interconnect that projects from the substrate and thereby covering the portion of the interconnect that projects from the substrate; and
depositing a second dielectric layer composed of a second material onto the first dielectric layer such that the second dielectric layer covers the first dielectric layer, wherein the first material is different than the second material, and wherein the first material is removable by a removal process that generally does not affect the second dielectric layer.
2. The method of claim 1 wherein:
constructing the electrically conductive interconnect comprises forming an interconnect having a conductive fill material in a hole in the substrate and a conductive layer in the hole between the conductive fill material and the substrate, with the conductive fill material and the conductive layer extending from the terminal to the at least intermediate depth in the substrate;
removing material from the second side of the substrate comprises (a) thinning the substrate from the second side so that a section of the interconnect is exposed, and (b) selectively etching the substrate so that the portion of the interconnect projects from the substrate; and
the method further comprises (a) removing a section of the conductive fill material from the portion of the interconnect so that the conductive fill material is recessed relative to the conductive layer, (b) applying a dielectric layer to the second side of the substrate and the portion of the interconnect after removing the section of the conductive fill material, (c) removing at least a section of the dielectric layer covering the portion of the interconnect to expose a section of the interconnect, and (d) forming a conductive member on the section of the interconnect.
3. The method of claim 1 wherein removing material from the second side of the substrate comprises:
thinning the substrate from the second side so that a section of the interconnect is exposed; and
selectively etching the substrate so that the portion of the interconnect projects from the substrate.
4. The method of claim 1 wherein:
constructing the electrically conductive interconnect comprises forming an interconnect having a conductive fill material in a hole in the substrate and a conductive layer in the hole between the conductive fill material and the substrate, with the conductive fill material and the conductive layer extending from the terminal to the at least intermediate depth in the substrate; and
the method further comprises removing a section of the conductive fill material from the portion of the interconnect so that the conductive fill material is recessed relative to the conductive layer.
5. The method of claim 1 wherein the first material comprises parylene HT and the second material comprises silicon oxide (SiO2).
6. The method of claim 1 wherein depositing at least one of the first and second dielectric layers comprises depositing by chemical vapor deposition.
7. The method of claim 1, further comprising forming a conductive member on the portion of the conductive interconnect.
8. The method of claim 1, further comprising plating a conductive cap onto the portion of the conductive interconnect.
9. The method of claim 3 wherein selectively etching comprises etching the substrate so that the portion of the interconnect projects between approximately 5 and 10 microns from the substrate.
10. The method of claim 3 wherein thinning the substrate comprises at least one of grinding, chemical-mechanical polishing, mechanical polishing, or chemical polishing the substrate.
11. The method of claim 1 wherein removing material from the second side of the substrate occurs after constructing the electrically conductive interconnect.
12. A method for forming an interconnect in a microfeature workpiece, the method comprising:
providing a microfeature workpiece having (a) a substrate with a first side and a second side opposite the first side, (b) a terminal carried by the first side of the substrate, and (c) an electrically conductive interconnect extending from the terminal through the substrate and projecting from the second side of the substrate;
applying a first dielectric layer composed of a first material to the second side of the substrate and to an uncoated, conductive surface of the portion of the interconnect projecting from the second side of the substrate;
applying a second dielectric layer composed of a second material to the first dielectric layer such that the second dielectric layer covers, wherein the first material and the second material are different materials, and wherein the first material is removable by a first process and the second material is removable by a second process;
removing a section of the first and second dielectric layers to expose a surface of the interconnect with the interconnect intersecting a plane defined by the remaining section of the dielectric layers.
13. The method of claim 12 wherein providing the microfeature workpiece comprises:
constructing the electrically conductive interconnect in the substrate with the interconnect extending from the terminal to at least an intermediate depth in the substrate; and
removing material from the second side of the substrate so that the portion of the interconnect projects from the substrate.
14. The method of claim 12 wherein at least one of applying the first dielectric layer and applying the second dielectric layer comprises depositing parylene.
15. The method of claim 12 wherein at least one of the first and second processes polishing the workpiece.
16. The method of claim 12, further comprising forming a conductive member on the exposed surface of the interconnect.
17. The method of claim 12 wherein at least one of the first and second processes comprises removing the section of the respective dielectric layer without photolithography.
18. The method of claim 12 wherein removing the section of the first and second dielectric layers comprises:
removing a portion of the section of the second dielectric layer in a first process; and
removing a portion of the remaining dielectric layer in a second process different than the first process.
19. A method for forming an interconnect in a microfeature workpiece, the microfeature workpiece including a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side, the method comprising:
forming an electrically conductive interconnect having a first portion at the terminal and a second portion at an intermediate depth in the substrate, the electrically conductive interconnect being electrically connected to the terminal;
thinning the substrate from the second side to at least the second portion of the interconnect;
applying a first dielectric layer composed of a first material to the second side of the substrate and thereby covering the second portion of the interconnect after thinning the substrate;
applying a second dielectric layer composed of a second material to at least a portion of the first dielectric layer such that the second dielectric layer covers at least a portion of the first dielectric layer that covers the second portion of the interconnect, wherein the first and second materials are different materials, and wherein the first material is susceptible to etching and the second material is resistant to etching.
20. The method of claim 19 wherein thinning the substrate comprises removing material from the second side of the substrate so that the second portion of the interconnect projects from the substrate.
21. The method of claim 19, further comprising selectively etching the substrate so that the second portion of the interconnect projects from the substrate.
22. The method of claim 19 wherein:
forming the electrically conductive interconnect comprises constructing an interconnect having a conductive fill material in a hole in the substrate and a conductive layer in the hole between the conductive fill material and the substrate, with the conductive fill material and the conductive layer extending from the terminal to the at least intermediate depth in the substrate; and
the method further comprises removing a section of the conductive fill material from the portion of the interconnect so that the conductive fill material is recessed relative to the conductive layer.
23. The method of claim 19, further comprising forming a conductive member on the exposed surface of the conductive interconnect.
24. The method of claim 19 wherein removing a portion of the second dielectric layer comprises at least one of grinding, chemical-mechanical polishing, mechanical polishing, or chemical polishing.
25. The method of claim 1 wherein depositing the first dielectric layer comprises depositing through a first process, and depositing the second dielectric layer comprises depositing through a second process different from the first process.
26. The method of claim 12 wherein applying the first dielectric layer comprises applying through a first process, and
applying the second dielectric layer to the first dielectric layer comprises applying through a second process, wherein the first process is different from the second process.
27. The method of claim 19 wherein applying the dielectric layer to the second side of the substrate comprises applying through a first process, and
applying the second dielectric layer to at least a portion of the first dielectric layer comprises applying through a second process, wherein the first process is different from the second process, and at least one of the first and second processes comprises chemical vapor deposition.
28. A method for constructing an interconnect in a microfeature workpiece with an initial dielectric layer attached to a first side of a substrate, the method comprising:
forming an interconnect extending through the initial dielectric layer and extending to at least an intermediate depth in the substrate;
thinning the substrate by removing material from a second side of the substrate and from the interconnect;
removing additional material from the second side of the substrate using a selective etchant such that a portion of the interconnect protrudes from the second side of the substrate;
forming a recess in the portion of the interconnect by removing a portion of material from the portion of the interconnect;
forming a dielectric structure over the portion of the interconnect, the dielectric structure comprising a first dielectric layer and a second dielectric layer on the first dielectric layer, wherein the first and second dielectric layers are composed of different materials;
removing sections of the dielectric structure and the portion of the interconnect such that the second dielectric layer is removed to expose the first dielectric layer; and
removing the first dielectric layer from the portion of the interconnect to form a recess in the portion of the interconnect to expose conductive fill material in the interconnect.
29. The method of claim 28 wherein forming the interconnect comprises insulating the interconnect from the substrate with dielectric material.
30. The method of claim 28 wherein forming the interconnect comprises forming a conductive fill material separated from the substrate by dielectric material, a diffusion barrier, a seed layer, and a conductive layer.
31. The method of claim 28 wherein forming the dielectric structure comprises using at least one of atomic layer deposition, physical vapor deposition, and chemical vapor deposition.
32. The method of claim 28 wherein forming the interconnect comprises forming a conductive fill material using at least one of plating processes, solder wave processes, screen printing processes, reflow processes, and vapor deposition processes.
33. The method of claim 28 wherein removing sections of the dielectric structure comprises using an etchant that is selective to at least one of the first and the second dielectric layers.
34. The method of claim 28 wherein thinning the substrate by removing material comprises removing material by at least one of grinding, dry etching, chemical etching, chemical polishing, and chemical-mechanical polishing.
35. The method of claim 28 wherein removing additional material comprises removing the additional material using a plasma etching process.
36. The method of claim 1, further comprising exposing a portion of the first dielectric layer through the second dielectric layer over the portion of the interconnect.
37. The method of claim 1, further comprising removing the exposed portion of the first dielectric layer through the selective removal process.
38. The method of claim 19, further comprising removing a portion of the second dielectric layer covering the portion of the first dielectric layer.
39. The method of claim 19, further comprising exposing a surface of the second portion of the interconnect using an etching process that does not substantially affect the second dielectric layer.
Patent Citations (524)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US2821959(A) | 1958-02-01 | Franz | Applicant |
| US3006318(A) | 1961-10-01 | Monroe, Jr. et al. | Applicant |
| US3345134(A) | 1967-10-01 | Heymer et al. | Applicant |
| US3865298(A) | 1975-02-01 | Allen et al. | Applicant |
| US3902036(A) | 1975-08-01 | Zaleckas | Applicant |
| US4040168(A) | 1977-08-01 | Huang | Applicant |
| US4368106(A) | 1983-01-01 | Anthony | Applicant |
| US4534100(A) | 1985-08-01 | Lane | Applicant |
| US4581301(A) | 1986-04-01 | Michaelson | Applicant |
| US4608480(A) | 1986-08-01 | Bizot et al. | Applicant |
| US4614427(A) | 1986-09-01 | Koizumi et al. | Applicant |
| US4627971(A) | 1986-12-01 | Ayer | Applicant |
| US4660063(A) | 1987-04-01 | Anthony | Applicant |
| US4756765(A) | 1988-07-01 | Woodroffe | Applicant |
| US4768291(A) | 1988-09-01 | Palmer | Applicant |
| US4818728(A) | 1989-04-01 | Rai et al. | Applicant |
| US4907127(A) | 1990-03-01 | Lee | Applicant |
| US4959705(A) | 1990-09-01 | Lemnios et al. | Applicant |
| US4964212(A) | 1990-10-01 | Deroux-Dauphin et al. | Applicant |
| US4984597(A) | 1991-01-01 | McConnell et al. | Applicant |
| US5006922(A) | 1991-04-01 | McShane et al. | Applicant |
| US5024966(A) | 1991-06-01 | Dietrich et al. | Applicant |
| US5026964(A) | 1991-06-01 | Somers et al. | Applicant |
| US5027184(A) | 1991-06-01 | Soclof | Applicant |
| US5037782(A) | 1991-08-01 | Nakamura et al. | Applicant |
| US5098864(A) | 1992-03-01 | Mahulikar | Applicant |
| US5102829(A) | 1992-04-01 | Cohn | Applicant |
| US5123902(A) | 1992-06-01 | Muller et al. | Applicant |
| US5144412(A) | 1992-09-01 | Chang et al. | Applicant |
| US5145099(A) | 1992-09-01 | Wood et al. | Applicant |
| US5158911(A) | 1992-10-01 | Quentin et al. | Applicant |
| US5200366(A) | 1993-04-01 | Yamada et al. | Applicant |
| US5219344(A) | 1993-06-01 | Yoder, Jr. | Applicant |
| US5233448(A) | 1993-08-01 | Wu et al. | Applicant |
| US5237148(A) | 1993-08-01 | Aoki et al. | Applicant |
| US5289631(A) | 1994-03-01 | Koopman et al. | Applicant |
| US5291062(A) | 1994-03-01 | Higgins, III | Applicant |
| US5292686(A) | 1994-03-01 | Riley et al. | Applicant |
| US5294568(A) | 1994-03-01 | McNeilly et al. | Applicant |
| US5304743(A) | 1994-04-01 | Sen et al. | Applicant |
| US5378312(A) | 1995-01-01 | Gifford et al. | Applicant |
| US5378313(A) | 1995-01-01 | Pace | Applicant |
| US5380681(A) | 1995-01-01 | Hsu | Applicant |
| US5402435(A) | 1995-03-01 | Shiono et al. | Applicant |
| US5406630(A) | 1995-04-01 | Piosenka et al. | Applicant |
| US5424573(A) | 1995-06-01 | Kato et al. | Applicant |
| US5438212(A) | 1995-08-01 | Okaniwa et al. | Applicant |
| US5447871(A) | 1995-09-01 | Goldstein | Examiner |
| US5464960(A) | 1995-11-01 | Hall et al. | Applicant |
| US5481483(A) | 1996-01-01 | Ebenstein | Applicant |
| US5485039(A) | 1996-01-01 | Fujita et al. | Applicant |
| US5496755(A) | 1996-03-01 | Bayraktaroglu | Applicant |
| US5515167(A) | 1996-05-01 | Ledger et al. | Applicant |
| US5518956(A) | 1996-05-01 | Liu et al. | Applicant |
| US5550403(A) | 1996-08-01 | Carichner | Applicant |
| US5585308(A) | 1996-12-01 | Sardella | Applicant |
| US5585675(A) | 1996-12-01 | Knopf | Applicant |
| US5614743(A) | 1997-03-01 | Mochizuki | Applicant |
| US5618752(A) | 1997-04-01 | Gaul | Examiner |
| US5624437(A) | 1997-04-01 | Freeman et al. | Applicant |
| US5627106(A) | 1997-05-01 | Hsu | Examiner |
| US5646067(A) | 1997-07-01 | Gaul | Examiner |
| US5654221(A) | 1997-08-01 | Cronin et al. | Applicant |
| US5673846(A) | 1997-10-01 | Gruber | Applicant |
| US5684642(A) | 1997-11-01 | Zumoto et al. | Applicant |
| US5690841(A) | 1997-11-01 | Elderstig et al. | Applicant |
| US5718791(A) | 1998-02-01 | Spengler et al. | Applicant |
| US5723904(A) | 1998-03-01 | Shiga et al. | Applicant |
| US5726493(A) | 1998-03-01 | Yamashita et al. | Applicant |
| US5734555(A) | 1998-03-01 | McMahon | Applicant |
| US5771158(A) | 1998-06-01 | Yamagishi et al. | Applicant |
| US5773359(A) | 1998-06-01 | Mitchell et al. | Applicant |
| US5776824(A) | 1998-07-01 | Farnworth et al. | Applicant |
| US5807439(A) | 1998-09-01 | Akatsu et al. | Applicant |
| US5811799(A) | 1998-09-01 | Wu | Applicant |
| US5821532(A) | 1998-10-01 | Beaman et al. | Applicant |
| US5825080(A) | 1998-10-01 | Imaoka et al. | Applicant |
| US5826628(A) | 1998-10-01 | Hamilton | Applicant |
| US5847454(A) | 1998-12-01 | Shaw et al. | Applicant |
| US5851845(A) | 1998-12-01 | Wood et al. | Applicant |
| US5857963(A) | 1999-01-01 | Pelchy et al. | Applicant |
| US5861654(A) | 1999-01-01 | Johnson | Applicant |
| US5870289(A) | 1999-02-01 | Tokuda et al. | Applicant |
| US5870823(A) | 1999-02-01 | Bezama et al. | Applicant |
| US5893828(A) | 1999-04-01 | Uram | Applicant |
| US5904499(A) | 1999-05-01 | Pace | Applicant |
| US5969422(A) | 1999-10-01 | Ting et al. | Applicant |
| US5998240(A) | 1999-12-01 | Hamilton et al. | Applicant |
| US5998292(A) | 1999-12-01 | Black et al. | Applicant |
| US6004867(A) | 1999-12-01 | Kim et al. | Applicant |
| US6008070(A) | 1999-12-01 | Farnworth | Applicant |
| US6008914(A) | 1999-12-01 | Sasagawa et al. | Applicant |
| US6080291(A) | 2000-06-01 | Woodruff et al. | Applicant |
| US6097087(A) | 2000-08-01 | Farnworth et al. | Applicant |
| US6103547(A) | 2000-08-01 | Corisis et al. | Applicant |
| US6107180(A) | 2000-08-01 | Munroe et al. | Applicant |
| US6107186(A) | 2000-08-01 | Erb | Applicant |
| US6107679(A) | 2000-08-01 | Noguchi et al. | Applicant |
| US6110825(A) | 2000-08-01 | Mastromatteo et al. | Applicant |
| US6114240(A) | 2000-09-01 | Akram et al. | Applicant |
| US6119335(A) | 2000-09-01 | Park et al. | Applicant |
| US6124634(A) | 2000-09-01 | Akram et al. | Applicant |
| US6130141(A) | 2000-10-01 | Degani et al. | Applicant |
| US6133622(A) | 2000-10-01 | Corisis et al. | Applicant |
| US6137163(A) | 2000-10-01 | Kim et al. | Applicant |
| US6137182(A) | 2000-10-01 | Hause et al. | Applicant |
| US6140604(A) | 2000-10-01 | Somers et al. | Applicant |
| US6143588(A) | 2000-11-01 | Glenn | Applicant |
| US6148509(A) | 2000-11-01 | Schoenfeld et al. | Applicant |
| US6159764(A) | 2000-12-01 | Kinsman et al. | Applicant |
| US6180518(B1) | 2001-01-01 | Layadi et al. | Applicant |
| US6184060(B1) | 2001-02-01 | Siniaguine | Examiner |
| US6184465(B1) | 2001-02-01 | Corisis | Applicant |
| US6187615(B1) | 2001-02-01 | Kim et al. | Applicant |
| US6191487(B1) | 2001-02-01 | Rodenbeck et al. | Applicant |
| US6203539(B1) | 2001-03-01 | Shimmick et al. | Applicant |
| US6221769(B1) | 2001-04-01 | Dhong et al. | Applicant |
| US6222136(B1) | 2001-04-01 | Appelt et al. | Applicant |
| US6222270(B1) | 2001-04-01 | Lee et al. | Applicant |
| US6228687(B1) | 2001-05-01 | Akram et al. | Applicant |
| US6229202(B1) | 2001-05-01 | Corisis | Applicant |
| US6235552(B1) | 2001-05-01 | Kwon et al. | Applicant |
| US6246108(B1) | 2001-06-01 | Corisis et al. | Applicant |
| US6252300(B1) | 2001-06-01 | Hsuan et al. | Applicant |
| US6268114(B1) | 2001-07-01 | Wen et al. | Applicant |
| US6271580(B1) | 2001-08-01 | Corisis | Applicant |
| US6277757(B1) | 2001-08-01 | Lin et al. | Applicant |
| US6291894(B1) | 2001-09-01 | Farnworth et al. | Applicant |
| US6294837(B1) | 2001-09-01 | Akram et al. | Applicant |
| US6297155(B1) | 2001-10-01 | Simpson et al. | Applicant |
| US6324253(B1) | 2001-11-01 | Yuyama et al. | Applicant |
| US6326689(B1) | 2001-12-01 | Thomas | Applicant |
| US6326697(B1) | 2001-12-01 | Farnworth | Applicant |
| US6329632(B1) | 2001-12-01 | Fournier et al. | Applicant |
| US6341009(B1) | 2002-01-01 | O'Connor et al. | Applicant |
| US6344976(B1) | 2002-02-01 | Schoenfeld et al. | Applicant |
| US6359254(B1) | 2002-03-01 | Brown | Applicant |
| US6359328(B1) | 2002-03-01 | Dubin | Applicant |
| US6372548(B2) | 2002-04-01 | Bessho et al. | Applicant |
| US6388208(B1) | 2002-05-01 | Kiani et al. | Applicant |
| US6391770(B2) | 2002-05-01 | Kosaki et al. | Applicant |
| US6406636(B1) | 2002-06-01 | Vaganov | Applicant |
| US6432821(B1) | 2002-08-01 | Dubin et al. | Applicant |
| US6433303(B1) | 2002-08-01 | Liu et al. | Applicant |
| US6433304(B2) | 2002-08-01 | Okumura et al. | Applicant |
| US6437284(B1) | 2002-08-01 | Okamoto et al. | Applicant |
| US6437441(B1) | 2002-08-01 | Yamamoto et al. | Applicant |
| US6441487(B2) | 2002-08-01 | Elenius et al. | Applicant |
| US6444576(B1) | 2002-09-01 | Kong | Applicant |
| US6448106(B1) | 2002-09-01 | Wang et al. | Applicant |
| US6452270(B1) | 2002-09-01 | Huang et al. | Applicant |
| US6455425(B1) | 2002-09-01 | Besser et al. | Applicant |
| US6457515(B1) | 2002-10-01 | Vafai et al. | Applicant |
| US6459039(B1) | 2002-10-01 | Bezama et al. | Applicant |
| US6459150(B1) | 2002-10-01 | Wu et al. | Applicant |
| US6468889(B1) | 2002-10-01 | Iacoponi et al. | Applicant |
| US6486083(B1) | 2002-11-01 | Mizuno et al. | Applicant |
| US6486549(B1) | 2002-11-01 | Chiang et al. | Applicant |
| US6521516(B2) | 2003-02-01 | Monzon et al. | Applicant |
| US6521530(B2) | 2003-02-01 | Peters et al. | Applicant |
| US6534192(B1) | 2003-03-01 | Abys et al. | Applicant |
| US6534863(B2) | 2003-03-01 | Walker et al. | Applicant |
| US6545563(B1) | 2003-04-01 | Smith | Applicant |
| US6555782(B2) | 2003-04-01 | Isaji et al. | Applicant |
| US6560047(B2) | 2003-05-01 | Choi et al. | Applicant |
| US6569711(B1) | 2003-05-01 | Susko et al. | Applicant |
| US6569777(B1) | 2003-05-01 | Hsu et al. | Applicant |
| US6572606(B2) | 2003-06-01 | Kliewer et al. | Applicant |
| US6576531(B2) | 2003-06-01 | Peng et al. | Applicant |
| US6580174(B2) | 2003-06-01 | McCormick et al. | Applicant |
| US6582987(B2) | 2003-06-01 | Jun et al. | Applicant |
| US6582992(B2) | 2003-06-01 | Poo et al. | Applicant |
| US6593644(B2) | 2003-07-01 | Chiu et al. | Applicant |
| US6599436(B1) | 2003-07-01 | Matzke et al. | Applicant |
| US6606251(B1) | 2003-08-01 | Kenny, Jr. et al. | Applicant |
| US6614033(B2) | 2003-09-01 | Suguro et al. | Applicant |
| US6620031(B2) | 2003-09-01 | Renteln | Applicant |
| US6620731(B1) | 2003-09-01 | Farnworth et al. | Applicant |
| US6621045(B1) | 2003-09-01 | Liu et al. | Applicant |
| US6638410(B2) | 2003-10-01 | Chen et al. | Applicant |
| US6653236(B2) | 2003-11-01 | Wai et al. | Applicant |
| US6658818(B2) | 2003-12-01 | Kurth et al. | Applicant |
| US6660622(B2) | 2003-12-01 | Chen et al. | Applicant |
| US6660630(B1) | 2003-12-01 | Chang et al. | Applicant |
| US6664129(B2) | 2003-12-01 | Siniaguine | Examiner |
| US6664485(B2) | 2003-12-01 | Bhatt et al. | Applicant |
| US6667551(B2) | 2003-12-01 | Hanaoka et al. | Applicant |
| US6680459(B2) | 2004-01-01 | Kanaya et al. | Applicant |
| US6699787(B2) | 2004-03-01 | Mashino et al. | Applicant |
| US6703310(B2) | 2004-03-01 | Mashino et al. | Applicant |
| US6708405(B2) | 2004-03-01 | Hasler et al. | Applicant |
| US6746971(B1) | 2004-06-01 | Ngo et al. | Applicant |
| US6750144(B2) | 2004-06-01 | Taylor | Applicant |
| US6756564(B2) | 2004-06-01 | Tian | Applicant |
| US6770958(B2) | 2004-08-01 | Wang et al. | Applicant |
| US6774486(B2) | 2004-08-01 | Kinsman | Applicant |
| US6777244(B2) | 2004-08-01 | Pepper et al. | Applicant |
| US6780749(B2) | 2004-08-01 | Masumoto et al. | Applicant |
| US6790775(B2) | 2004-09-01 | Fartash | Applicant |
| US6797616(B2) | 2004-09-01 | Kinsman | Applicant |
| US6809025(B2) | 2004-10-01 | Sandhu et al. | Applicant |
| US6809421(B1) | 2004-10-01 | Hayasaka et al. | Examiner |
| US6818464(B2) | 2004-11-01 | Heschel et al. | Applicant |
| US6825127(B2) | 2004-11-01 | Ouellet et al. | Applicant |
| US6825557(B2) | 2004-11-01 | DiBattista et al. | Applicant |
| US6828175(B2) | 2004-12-01 | Wood et al. | Applicant |
| US6828223(B2) | 2004-12-01 | Chuang | Applicant |
| US6838377(B2) | 2005-01-01 | Tonami et al. | Applicant |
| US6841849(B2) | 2005-01-01 | Miyazawa | Examiner |
| US6847109(B2) | 2005-01-01 | Shim | Applicant |
| US6852621(B2) | 2005-02-01 | Hanaoka et al. | Applicant |
| US6856023(B2) | 2005-02-01 | Muta et al. | Applicant |
| US6858891(B2) | 2005-02-01 | Farnworth et al. | Applicant |
| US6864172(B2) | 2005-03-01 | Noma et al. | Applicant |
| US6864457(B1) | 2005-03-01 | Alexander et al. | Applicant |
| US6867390(B2) | 2005-03-01 | Clauer et al. | Applicant |
| US6873054(B2) | 2005-03-01 | Miyazawa et al. | Applicant |
| US6882030(B2) | 2005-04-01 | Siniaguine | Examiner |
| US6885107(B2) | 2005-04-01 | Kinsman | Applicant |
| US6903012(B2) | 2005-06-01 | Geefay et al. | Applicant |
| US6903442(B2) | 2005-06-01 | Wood et al. | Applicant |
| US6903443(B2) | 2005-06-01 | Farnworth et al. | Applicant |
| US6910268(B2) | 2005-06-01 | Miller | Applicant |
| US6913952(B2) | 2005-07-01 | Moxham et al. | Applicant |
| US6916725(B2) | 2005-07-01 | Yamaguchi | Examiner |
| US6936536(B2) | 2005-08-01 | Sinha | Applicant |
| US6939343(B2) | 2005-09-01 | Sumiya | Applicant |
| US6943056(B2) | 2005-09-01 | Nemoto et al. | Applicant |
| US6946325(B2) | 2005-09-01 | Yean et al. | Applicant |
| US6951627(B2) | 2005-10-01 | Li et al. | Applicant |
| US6953748(B2) | 2005-10-01 | Yamaguchi et al. | Applicant |
| US6962867(B2) | 2005-11-01 | Jackson et al. | Applicant |
| US6970775(B2) | 2005-11-01 | Lederle et al. | Applicant |
| US6982487(B2) | 2006-01-01 | Kim et al. | Applicant |
| US7022609(B2) | 2006-04-01 | Yamamoto et al. | Applicant |
| US7023090(B2) | 2006-04-01 | Huang et al. | Applicant |
| US7029937(B2) | 2006-04-01 | Miyazawa et al. | Applicant |
| US7033927(B2) | 2006-04-01 | Cohen et al. | Applicant |
| US7037836(B2) | 2006-05-01 | Lee et al. | Applicant |
| US7041598(B2) | 2006-05-01 | Sharma | Applicant |
| US7045015(B2) | 2006-05-01 | Renn et al. | Applicant |
| US7083425(B2) | 2006-08-01 | Chong et al. | Applicant |
| US7084073(B2) | 2006-08-01 | Lee et al. | Applicant |
| US7091124(B2) | 2006-08-01 | Rigg et al. | Applicant |
| US7092284(B2) | 2006-08-01 | Braun et al. | Applicant |
| US7094677(B2) | 2006-08-01 | Yamamoto et al. | Applicant |
| US7109068(B2) | 2006-09-01 | Akram et al. | Applicant |
| US7111149(B2) | 2006-09-01 | Eilert | Applicant |
| US7129112(B2) | 2006-10-01 | Matsuo | Examiner |
| US7151009(B2) | 2006-12-01 | Kim et al. | Applicant |
| US7164565(B2) | 2007-01-01 | Takeda | Applicant |
| US7166247(B2) | 2007-01-01 | Kramer | Applicant |
| US7170183(B1) | 2007-01-01 | Kim et al. | Applicant |
| US7183176(B2) | 2007-02-01 | Sankarapillai et al. | Applicant |
| US7183653(B2) | 2007-02-01 | Myers et al. | Applicant |
| US7186650(B1) | 2007-03-01 | Dakshina-Murthy | Applicant |
| US7190061(B2) | 2007-03-01 | Lee | Applicant |
| US7199050(B2) | 2007-04-01 | Hiatt | Applicant |
| US7214615(B2) | 2007-05-01 | Miyazawa | Examiner |
| US7217596(B2) | 2007-05-01 | Cobbley et al. | Applicant |
| US7217888(B2) | 2007-05-01 | Sunohara et al. | Applicant |
| US7223634(B2) | 2007-05-01 | Yamaguchi | Examiner |
| US7232754(B2) | 2007-06-01 | Kirby et al. | Applicant |
| US7256073(B2) | 2007-08-01 | Noma et al. | Applicant |
| US7262134(B2) | 2007-08-01 | Kirby et al. | Applicant |
| US7262495(B2) | 2007-08-01 | Chen et al. | Applicant |
| US7265052(B2) | 2007-09-01 | Sinha | Applicant |
| US7271482(B2) | 2007-09-01 | Kirby | Applicant |
| US7279776(B2) | 2007-10-01 | Morimoto | Applicant |
| US7291911(B2) | 2007-11-01 | Usami | Examiner |
| US7300857(B2) | 2007-11-01 | Akram et al. | Applicant |
| US7317256(B2) | 2008-01-01 | Williams et al. | Applicant |
| US7378726(B2) | 2008-05-01 | Punzalan et al. | Applicant |
| US7408265(B2) | 2008-08-01 | Holscher et al. | Applicant |
| US7449098(B1) | 2008-11-01 | Mayer et al. | Applicant |
| US7491582(B2) | 2009-02-01 | Yokoyama et al. | Examiner |
| US7498661(B2) | 2009-03-01 | Matsuo | Examiner |
| US7589009(B1) | 2009-09-01 | Kar-Roy et al. | Examiner |
| US2001/0020739(A1) | 2001-09-01 | Honda | Applicant |
| US2002/0005583(A1) | 2002-01-01 | Harada et al. | Applicant |
| US2002/0020898(A1) | 2002-02-01 | Vu et al. | Applicant |
| US2002/0027293(A1) | 2002-03-01 | Hoshino | Applicant |
| US2002/0057468(A1) | 2002-05-01 | Segawa et al. | Applicant |
| US2002/0059722(A1) | 2002-05-01 | Murakami | Applicant |
| US2002/0060208(A1) | 2002-05-01 | Liu et al. | Applicant |
| US2002/0094607(A1) | 2002-07-01 | Gebauer et al. | Applicant |
| US2002/0096729(A1) | 2002-07-01 | Tu et al. | Applicant |
| US2002/0130390(A1) | 2002-09-01 | Ker et al. | Applicant |
| US2002/0190371(A1) | 2002-12-01 | Mashino et al. | Applicant |
| US2003/0014895(A1) | 2003-01-01 | Lizotte | Applicant |
| US2003/0042564(A1) | 2003-03-01 | Taniguchi et al. | Applicant |
| US2003/0119308(A1) | 2003-06-01 | Geefay et al. | Applicant |
| US2003/0148597(A1) | 2003-08-01 | Tan et al. | Applicant |
| US2003/0216023(A1) | 2003-11-01 | Wark et al. | Applicant |
| US2004/0004280(A1) | 2004-01-01 | Shibata | Applicant |
| US2004/0018712(A1) | 2004-01-01 | Plas et al. | Applicant |
| US2004/0023447(A1) | 2004-02-01 | Hirakata et al. | Applicant |
| US2004/0041261(A1) | 2004-03-01 | Kinsman | Applicant |
| US2004/0043607(A1) | 2004-03-01 | Farnworth et al. | Applicant |
| US2004/0046251(A1) | 2004-03-01 | Lee | Applicant |
| US2004/0073607(A1) | 2004-04-01 | Su et al. | Applicant |
| US2004/0087441(A1) | 2004-05-01 | Bock et al. | Applicant |
| US2004/0094389(A1) | 2004-05-01 | Boyce | Applicant |
| US2004/0137661(A1) | 2004-07-01 | Murayama | Applicant |
| US2004/0137701(A1) | 2004-07-01 | Takao | Applicant |
| US2004/0141536(A1) | 2004-07-01 | Liu et al. | Applicant |
| US2004/0159668(A1) | 2004-08-01 | Vasiadis | Applicant |
| US2004/0159958(A1) | 2004-08-01 | Funaki | Applicant |
| US2004/0178491(A1) | 2004-09-01 | Akram et al. | Applicant |
| US2004/0180539(A1) | 2004-09-01 | Yamamoto et al. | Applicant |
| US2004/0188260(A1) | 2004-09-01 | Bonkabeta et al. | Applicant |
| US2004/0192033(A1) | 2004-09-01 | Hara | Examiner |
| US2004/0198033(A1) | 2004-10-01 | Lee et al. | Applicant |
| US2004/0198040(A1) | 2004-10-01 | Geefay et al. | Applicant |
| US2004/0219342(A1) | 2004-11-01 | Boggs et al. | Applicant |
| US2004/0219763(A1) | 2004-11-01 | Kim et al. | Applicant |
| US2004/0222082(A1) | 2004-11-01 | Gopalraja et al. | Applicant |
| US2004/0245649(A1) | 2004-12-01 | Imaoka | Applicant |
| US2004/0255258(A1) | 2004-12-01 | Li | Applicant |
| US2004/0262753(A1) | 2004-12-01 | Kashiwazaki | Applicant |
| US2004/0265562(A1) | 2004-12-01 | Uzoh et al. | Applicant |
| US2005/0026443(A1) | 2005-02-01 | Goo et al. | Applicant |
| US2005/0037608(A1) | 2005-02-01 | Andricacos et al. | Applicant |
| US2005/0046002(A1) | 2005-03-01 | Lee et al. | Applicant |
| US2005/0064707(A1) | 2005-03-01 | Sinha | Applicant |
| US2005/0067620(A1) | 2005-03-01 | Chan et al. | Applicant |
| US2005/0069782(A1) | 2005-03-01 | Elenius et al. | Applicant |
| US2005/0101054(A1) | 2005-05-01 | Mastromatteo et al. | Applicant |
| US2005/0101116(A1) | 2005-05-01 | Tseng | Applicant |
| US2005/0104228(A1) | 2005-05-01 | Rigg et al. | Applicant |
| US2005/0106834(A1) | 2005-05-01 | Andry et al. | Applicant |
| US2005/0110095(A1) | 2005-05-01 | Shih et al. | Applicant |
| US2005/0110889(A1) | 2005-05-01 | Tuttle et al. | Applicant |
| US2005/0127478(A1) | 2005-06-01 | Hiatt et al. | Applicant |
| US2005/0136646(A1) | 2005-06-01 | Larnerd et al. | Applicant |
| US2005/0139390(A1) | 2005-06-01 | Kim et al. | Applicant |
| US2005/0150683(A1) | 2005-07-01 | Farnworth et al. | Applicant |
| US2005/0151228(A1) | 2005-07-01 | Tanida et al. | Examiner |
| US2005/0164500(A1) | 2005-07-01 | Lindgren | Applicant |
| US2005/0184219(A1) | 2005-08-01 | Kirby | Applicant |
| US2005/0189637(A1) | 2005-09-01 | Okayama et al. | Applicant |
| US2005/0191861(A1) | 2005-09-01 | Verhaverbeke | Applicant |
| US2005/0194169(A1) | 2005-09-01 | Tonomura | Applicant |
| US2005/0208766(A1) | 2005-09-01 | Kirby et al. | Applicant |
| US2005/0227382(A1) | 2005-10-01 | Hui | Applicant |
| US2005/0230805(A1) | 2005-10-01 | Miyazawa | Examiner |
| US2005/0231626(A1) | 2005-10-01 | Tuttle et al. | Applicant |
| US2005/0236708(A1) | 2005-10-01 | Farnworth et al. | Applicant |
| US2005/0247894(A1) | 2005-11-01 | Watkins et al. | Applicant |
| US2005/0253213(A1) | 2005-11-01 | Jiang et al. | Applicant |
| US2005/0254133(A1) | 2005-11-01 | Akram et al. | Applicant |
| US2005/0258530(A1) | 2005-11-01 | Vindasius et al. | Applicant |
| US2005/0272221(A1) | 2005-12-01 | Yen et al. | Applicant |
| US2005/0275048(A1) | 2005-12-01 | Farnworth et al. | Applicant |
| US2005/0275049(A1) | 2005-12-01 | Kirby et al. | Applicant |
| US2005/0275051(A1) | 2005-12-01 | Farnworth et al. | Applicant |
| US2005/0275750(A1) | 2005-12-01 | Akram et al. | Applicant |
| US2005/0277293(A1) | 2005-12-01 | Kim et al. | Applicant |
| US2005/0282374(A1) | 2005-12-01 | Hwang et al. | Applicant |
| US2005/0285154(A1) | 2005-12-01 | Akram et al. | Applicant |
| US2006/0003566(A1) | 2006-01-01 | Emesh | Applicant |
| US2006/0011809(A1) | 2006-01-01 | Farnworth et al. | Applicant |
| US2006/0014313(A1) | 2006-01-01 | Hall et al. | Applicant |
| US2006/0023107(A1) | 2006-02-01 | Bolken et al. | Applicant |
| US2006/0024856(A1) | 2006-02-01 | Derderian et al. | Applicant |
| US2006/0035402(A1) | 2006-02-01 | Street et al. | Applicant |
| US2006/0035415(A1) | 2006-02-01 | Wood et al. | Applicant |
| US2006/0038183(A1) | 2006-02-01 | Oliver | Applicant |
| US2006/0038272(A1) | 2006-02-01 | Edwards | Applicant |
| US2006/0040421(A1) | 2006-02-01 | Farnworth et al. | Applicant |
| US2006/0040428(A1) | 2006-02-01 | Johnson | Applicant |
| US2006/0042952(A1) | 2006-03-01 | Oliver et al. | Applicant |
| US2006/0043262(A1) | 2006-03-01 | Akram | Applicant |
| US2006/0043509(A1) | 2006-03-01 | Watkins et al. | Applicant |
| US2006/0043512(A1) | 2006-03-01 | Oliver et al. | Applicant |
| US2006/0043569(A1) | 2006-03-01 | Benson et al. | Applicant |
| US2006/0043599(A1) | 2006-03-01 | Akram et al. | Applicant |
| US2006/0044433(A1) | 2006-03-01 | Akram | Applicant |
| US2006/0046332(A1) | 2006-03-01 | Derderian et al. | Applicant |
| US2006/0046438(A1) | 2006-03-01 | Kirby | Applicant |
| US2006/0046468(A1) | 2006-03-01 | Akram et al. | Applicant |
| US2006/0046471(A1) | 2006-03-01 | Kirby et al. | Applicant |
| US2006/0046537(A1) | 2006-03-01 | Chong et al. | Applicant |
| US2006/0057776(A1) | 2006-03-01 | Tao | Applicant |
| US2006/0057836(A1) | 2006-03-01 | Nagarajan et al. | Applicant |
| US2006/0071347(A1) | 2006-04-01 | Dotta | Applicant |
| US2006/0148250(A1) | 2006-07-01 | Kirby | Applicant |
| US2006/0151880(A1) | 2006-07-01 | Tang et al. | Applicant |
| US2006/0154153(A1) | 2006-07-01 | Chiang et al. | Applicant |
| US2006/0160367(A1) | 2006-07-01 | Wai et al. | Applicant |
| US2006/0177959(A1) | 2006-08-01 | Boettiger et al. | Applicant |
| US2006/0177999(A1) | 2006-08-01 | Hembree et al. | Applicant |
| US2006/0180941(A1) | 2006-08-01 | Kirby et al. | Applicant |
| US2006/0186097(A1) | 2006-08-01 | Watkins et al. | Applicant |
| US2006/0186492(A1) | 2006-08-01 | Boettiger et al. | Applicant |
| US2006/0191882(A1) | 2006-08-01 | Watkins et al. | Applicant |
| US2006/0195729(A1) | 2006-08-01 | Huppenthal et al. | Applicant |
| US2006/0199363(A1) | 2006-09-01 | Kirby et al. | Applicant |
| US2006/0204651(A1) | 2006-09-01 | Wai et al. | Applicant |
| US2006/0208360(A1) | 2006-09-01 | Yiu et al. | Applicant |
| US2006/0216862(A1) | 2006-09-01 | Rigg et al. | Applicant |
| US2006/0223301(A1) | 2006-10-01 | Vanhaelemeersch et al. | Applicant |
| US2006/0240687(A1) | 2006-10-01 | Chong et al. | Applicant |
| US2006/0249849(A1) | 2006-11-01 | Cohen | Applicant |
| US2006/0252254(A1) | 2006-11-01 | Basol | Applicant |
| US2006/0252262(A1) | 2006-11-01 | Kazemi | Applicant |
| US2006/0255443(A1) | 2006-11-01 | Hwang et al. | Applicant |
| US2006/0264041(A1) | 2006-11-01 | Rigg et al. | Applicant |
| US2006/0270108(A1) | 2006-11-01 | Farnworth et al. | Applicant |
| US2006/0278979(A1) | 2006-12-01 | Rangel | Applicant |
| US2006/0278980(A1) | 2006-12-01 | Trezza et al. | Examiner |
| US2006/0278988(A1) | 2006-12-01 | Trezza et al. | Applicant |
| US2006/0278989(A1) | 2006-12-01 | Trezza | Examiner |
| US2006/0278994(A1) | 2006-12-01 | Trezza | Examiner |
| US2006/0278995(A1) | 2006-12-01 | Trezza | Examiner |
| US2006/0281224(A1) | 2006-12-01 | Edelstein et al. | Applicant |
| US2006/0281243(A1) | 2006-12-01 | Trezza | Applicant |
| US2006/0289967(A1) | 2006-12-01 | Heck et al. | Applicant |
| US2006/0289968(A1) | 2006-12-01 | Sulfridge | Applicant |
| US2006/0290001(A1) | 2006-12-01 | Sulfridge | Applicant |
| US2006/0292877(A1) | 2006-12-01 | Lake | Applicant |
| US2007/0004079(A1) | 2007-01-01 | Geefay et al. | Applicant |
| US2007/0012655(A1) | 2007-01-01 | Kwon et al. | Applicant |
| US2007/0020805(A1) | 2007-01-01 | Kim et al. | Applicant |
| US2007/0020935(A1) | 2007-01-01 | Taylor et al. | Applicant |
| US2007/0023121(A1) | 2007-02-01 | Jones et al. | Applicant |
| US2007/0032061(A1) | 2007-02-01 | Farnworth et al. | Applicant |
| US2007/0035033(A1) | 2007-02-01 | Ozguz et al. | Applicant |
| US2007/0037379(A1) | 2007-02-01 | Enquist et al. | Applicant |
| US2007/0042598(A1) | 2007-02-01 | Park | Applicant |
| US2007/0045120(A1) | 2007-03-01 | Tiwari et al. | Applicant |
| US2007/0045388(A1) | 2007-03-01 | Farnworth et al. | Applicant |
| US2007/0045515(A1) | 2007-03-01 | Farnworth et al. | Applicant |
| US2007/0045632(A1) | 2007-03-01 | Oliver et al. | Applicant |
| US2007/0045779(A1) | 2007-03-01 | Hiatt | Applicant |
| US2007/0045806(A1) | 2007-03-01 | Hsuan | Applicant |
| US2007/0045812(A1) | 2007-03-01 | Heng | Applicant |
| US2007/0045826(A1) | 2007-03-01 | Lee et al. | Applicant |
| US2007/0045834(A1) | 2007-03-01 | Chong et al. | Applicant |
| US2007/0048896(A1) | 2007-03-01 | Andry et al. | Applicant |
| US2007/0048994(A1) | 2007-03-01 | Tuttle | Applicant |
| US2007/0049016(A1) | 2007-03-01 | Hiatt et al. | Applicant |
| US2007/0049019(A1) | 2007-03-01 | Wai et al. | Applicant |
| US2007/0057028(A1) | 2007-03-01 | Lake et al. | Applicant |
| US2007/0077753(A1) | 2007-04-01 | Iwatake et al. | Applicant |
| US2007/0082427(A1) | 2007-04-01 | Shirahama et al. | Applicant |
| US2007/0096263(A1) | 2007-05-01 | Furukawa et al. | Applicant |
| US2007/0099395(A1) | 2007-05-01 | Sridhar et al. | Applicant |
| US2007/0111386(A1) | 2007-05-01 | Kim et al. | Applicant |
| US2007/0122940(A1) | 2007-05-01 | Gautham | Applicant |
| US2007/0138562(A1) | 2007-06-01 | Trezza | Applicant |
| US2007/0145563(A1) | 2007-06-01 | Punzalan et al. | Applicant |
| US2007/0152342(A1) | 2007-07-01 | Tsao et al. | Applicant |
| US2007/0155997(A1) | 2007-07-01 | Li et al. | Applicant |
| US2007/0158839(A1) | 2007-07-01 | Trezza | Applicant |
| US2007/0158853(A1) | 2007-07-01 | Sinha | Applicant |
| US2007/0161235(A1) | 2007-07-01 | Trezza | Applicant |
| US2007/0166991(A1) | 2007-07-01 | Sinha | Applicant |
| US2007/0166997(A1) | 2007-07-01 | Knorr | Applicant |
| US2007/0167004(A1) | 2007-07-01 | Trezza | Applicant |
| US2007/0170574(A1) | 2007-07-01 | Lauxtermann et al. | Applicant |
| US2007/0178694(A1) | 2007-08-01 | Hiatt | Applicant |
| US2007/0182020(A1) | 2007-08-01 | Trezza et al. | Applicant |
| US2007/0190803(A1) | 2007-08-01 | Singh et al. | Applicant |
| US2007/0197013(A1) | 2007-08-01 | Trezza | Applicant |
| US2007/0202617(A1) | 2007-08-01 | Hembree | Applicant |
| US2007/0222050(A1) | 2007-09-01 | Lee et al. | Applicant |
| US2007/0222054(A1) | 2007-09-01 | Hembree | Applicant |
| US2007/0228576(A1) | 2007-10-01 | Trezza | Applicant |
| US2007/0228926(A1) | 2007-10-01 | Teo et al. | Applicant |
| US2007/0262424(A1) | 2007-11-01 | Hiatt | Applicant |
| US2007/0267138(A1) | 2007-11-01 | White et al. | Applicant |
| US2007/0281473(A1) | 2007-12-01 | Clark et al. | Applicant |
| US2007/0293040(A1) | 2007-12-01 | Emesh et al. | Applicant |
| US2008/0006850(A1) | 2008-01-01 | Ribnicek et al. | Applicant |
| US2008/0050904(A1) | 2008-02-01 | Lake | Applicant |
| US2008/0050911(A1) | 2008-02-01 | Borthakur | Applicant |
| US2008/0054444(A1) | 2008-03-01 | Tuttle | Applicant |
| US2008/0057620(A1) | 2008-03-01 | Pratt | Applicant |
| US2008/0079120(A1) | 2008-04-01 | Foster et al. | Applicant |
| US2008/0079121(A1) | 2008-04-01 | Han | Applicant |
| US2008/0081386(A1) | 2008-04-01 | Raravikar et al. | Applicant |
| US2008/0081398(A1) | 2008-04-01 | Lee et al. | Applicant |
| US2008/0265933(A1) | 2008-10-01 | Tanioka et al. | Applicant |
| US2008/0299759(A1) | 2008-12-01 | Chatterjee et al. | Applicant |
| US2008/0299762(A1) | 2008-12-01 | Mathew et al. | Applicant |
| US2008/0318361(A1) | 2008-12-01 | Han et al. | Applicant |
| US2009/0007934(A1) | 2009-01-01 | Hutto | Applicant |
| US2009/0014859(A1) | 2009-01-01 | Jeung et al. | Applicant |
| US2009/0057912(A1) | 2009-03-01 | Kheng | Applicant |
| US2009/0091962(A1) | 2009-04-01 | Chung et al. | Applicant |
| US2009/0127668(A1) | 2009-05-01 | Choi | Applicant |
| US2009/0146312(A1) | 2009-06-01 | Sulfridge | Applicant |
| US2009/0166846(A1) | 2009-07-01 | Pratt et al. | Applicant |
| US2009/0180257(A1) | 2009-07-01 | Park et al. | Applicant |
| US2009/0224405(A1) | 2009-09-01 | Chiou et al. | Applicant |
| US2009/0283898(A1) | 2009-11-01 | Janzen et al. | Applicant |
| US2009/0315154(A1) | 2009-12-01 | Kirby et al. | Applicant |
| US2009/0321947(A1) | 2009-12-01 | Pratt | Applicant |
| DE10205026(C1) | 2003-05-01 | Applicant | |
| EP127946 | 1984-12-01 | Applicant | |
| EP1154474(A1) | 2001-11-01 | Applicant | |
| EP1415950(A2) | 2004-05-01 | Applicant | |
| JP63052432 | 1988-03-01 | Applicant | |
| JP1252308(A) | 1989-10-01 | Applicant | |
| JP2235589(A) | 1990-09-01 | Applicant | |
| JP5104316(A) | 1993-04-01 | Applicant | |
| JP2001077496 | 2001-03-01 | Applicant | |
| JP2001082931(A) | 2001-03-01 | Applicant | |
| JP2001298147 | 2001-10-01 | Applicant | |
| JP2002018585(A) | 2002-01-01 | Applicant | |
| JP2005093980 | 2005-04-01 | Applicant | |
| JP2005310817 | 2005-11-01 | Applicant | |
| KR20010018694 | 2001-03-01 | Applicant | |
| KR20020022122 | 2002-03-01 | Applicant | |
| KR20020061812 | 2002-07-01 | Applicant | |
| TW250597(B) | 2006-03-01 | Applicant | |
| WO2004109770(A2) | 2004-12-01 | Applicant | |
| WO2005022965 | 2005-03-01 | Applicant | |
| WO2005036940 | 2005-04-01 | Applicant | |
| WO2006053036 | 2006-05-01 | Applicant | |
| WO2006124597 | 2006-11-01 | Applicant | |
| WO2007025812 | 2007-03-01 | Applicant | |
| WO2007043718 | 2007-04-01 | Applicant |
Non-Patent Literature (45)
- Amazawa, T. et al., “Planarized Multilevel Interconnection Using Chemical Mechanical Polishing of Selective CVD-AI Via Plugs,” IEEE Transactions on Electron Devices, vol. 45, No. 4, pp. 815-820, Apr. 1998.Applicant
- Armacost, M. et al., “Plasma-Etching Processes for ULSI Semiconductor Circuits,” IBM J. Res. Develop., vol. 43, No. 1/2, pp. 39-72, Jan./Mar. 1999, <http://www.research.ibm.com/journal/rd/431/armacost.pdf>.Applicant
- Blackburn, J.M. et al., “Deposition of Conformal Copper and Nickel Films from Supercritical Carbon Dioxide,” Science, vol. 94, Oct. 2001, pp. 141-145.Applicant
- De Boer, M.J. et al., “Micromachining of Buried Micro Channels in Silicon,” Journal of Microelectromechanical Systems, vol. 9, No. 1, Mar. 2000, IEEE, ISSN: 1057-7157.Applicant
- Gutmann, R.J., “Wafer-Level Three-Dimensional Monolithic Integration for Heterogeneous Silicon ICs,” 2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, IEEE, Sep. 8-10, 2004, pp. 45-48.Applicant
- Jang, D.M. et al., “Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV),” Proceedings of the 57th Electronic Components and Technology Conference, IEEE, May 29, 2007-Jun. 1, 2007, pp. 847-852, ISBN: 1-4244-0985-3.Applicant
- Kada, M. et al., “Advancements in Stacked Chip Scale Packaging (S-CSP) Provides System-in-a-Package Functionality for Wireless and Handheld Applications,” Future Fab Intl., vol. 9, Jan. 7, 2000.Applicant
- Keigler, A. et al., “Enabling 3-D Design,” Semiconductor International, Aug. 2007.Applicant
- Kim, J.Y. et al., “S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) Technology for 70nm DRAM Feature Size and Beyond,” 2005 Symposium on VLSI Technology, Digest of Technical Papers, Jun. 14-16, 2005, pp. 34-35, IEEE, ISBN: 4-900784-02-8.Applicant
- Kuhn, Markus and Jose A. Rodriguez, “Adsorption of sulfur on bimetallic surfaces: Formation of copper sulfides on Pt (111) and Ru(001),” J. Vac. Sci. Technol. A 13(3), pp. 1569-1573, May/Jun. 1995.Applicant
- Kurita, Y. et al., “A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology,” 2007 IEEE Electronic Components and Technology Conference, pp. 821-829, May 29-Jun. 1, 2007, ISBN 1-4244-0985-3.Applicant
- Lee, H.M. et al., Abstract of “Abatement of Sulfur Hexaflouride Emissions from the Semiconductor Manufacturing Process by Atmospheric-Pressure Plasmas,” 1 page, Aug. 2004, <http:www.awma.org/journal/ShowAbstract.asp?Year=&PaperID=1256>.Applicant
- Moffat, T.P., et al. “Superconformal film growth; Mechanism and quantification,” IBM J. Res. & Dev., vol. 49, No. 1, pp. 19-36, Jan. 2005.Applicant
- Morrow, P.R. et al., “Three-Dimensional Wafer Stacking Via Cu-Cu Bonding Integrated With 65-nm Strained-Si/Low-k CMOS Technology,” IEEE Electron Device Letters, vol. 27, No. 5, pp. 335-337, May 2006, ISBN: 0741-3106.Applicant
- Pienimaa, S.K. et al., “Stacked Thin Dice Package,” Proceedings of the Electronic Components and Technology Conference, 2001, pp. 361-366, IEEE.Applicant
- Solberg, V., “Innovative 3-D Solutions for Multiple Die Packaging,” SMTA International Conference, Sep. 21, 2003.Applicant
- Takahashi, K. et al., “Current Status of Research and Development for Three-Dimensional Chip Stack Technology,” Jpn. J. Appl. Phys., vol. 40 (2001), pp. 3032-3037, Part 1, No. 4B, Apr. 30, 2001, abstract.Applicant
- Thomas, D.J. et al., “Etching of Vias and Trenches Through Low k Dielectrics with Feature Sizes Down to 0.1 mm Using M0RIO High Density Plasmas,” presented at the 197th Meeting of The Electrochemical Society, Toronto 2000, <http://www.trikon.com/pdfs/ECS2b.pdf>.Applicant
- Vereecken, P.M. et al., “The chemistry of additives in damascene copper plating,” IBM J. Res. & Dev., vol. 49, No. 1, pp. 3-18, Jan. 2005.Applicant
- Aachboun, S. and P. Ranson, “Cryogenic etching of deep narrow trenches in silicon,” J. Vac. Sci. Technol. A 18 (4), Jul./Aug. 2000, pp. 1848-1852.Applicant
- Aachboun, S. and P. Ranson, “Deep anisotropic etching of silicon,” J. Vac. Sci. Technol. A 17(4), Jul./Aug. 1999, pp. 2270-2273.Applicant
- Arunasalam, P. et al., “Thermo-Mechanical Analysis of Thru-Silicon-Via Based High Density Compliant Interconnect,” Electronic Components and Technology Conference, 2007, ECTC '07, Proceedings, 57th, May 29, 2007-Jun. 1, 2007, pp. 1179-1185.Applicant
- Bernstein, K. et al., “Interconnects in the Third Dimension: Design Challenges for 3D ICs,” Design Automation Conference, 2007, DAC '07, 44th ACM/IEEE, Jun. 4-8, 2007, pp. 562-567.Applicant
- Cheung, T.S.D. et al., “On-Chip Interconnect for mm-Wave Applications Using an All-Copper Technology and Wavelength Reduction,” 2003 IEEE International Solid-State Circuits Conference.Applicant
- Chou, Bill et al., “Ultra Via Substrate for Advanced BGA Applications,” Pan Pacific Symposium, Jan. 25, 2000, <http://www.smta.org/files/PanPac00-ChouBill.pdf>.Applicant
- Hirafune, S. et al., “Packaging Technology for Imager Using Through-hole Interconnection in Si Substrate,” Proceeding of HDP'04, IEEE, pp. 303-306, Jul. 2004.Applicant
- Kyocera Corporation, Memory Package, 1 page, retrieved from the Internet on Dec. 3, 2004, <http://global.kyocera.com/prdct/semicon/ic—pkg/memory—p.html>.Applicant
- Lee, Rex A. et al., “Laser Created Silicon Vias for Stacking Dies in MCMs,” IEEE/CHMT IEMT Symposium, 1991, pp. 262-265.Applicant
- Lee, T.K. et al., “A Novel Joint-in-Via Flip-Chip Chip-Scale Package,” IEEE Transactions on Advanced Packaging, vol. 29, No. 1, pp. 186-194, Feb. 2006.Applicant
- Rasmussen, F.E., et al., “Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications,” The 12th International Conference on Solid State Sensors, Actuators and Microsystems, Boston, Jun. 8-12, 2003.Applicant
- Savastiouk, S. et al., “Thru-silicon interconnect technology,” 26th IEEE/CPMT International Electronics Manufacturing Technology Symposium, 2000, abstract.Applicant
- Schaper, L. et al., “Integrated System Development for 3-D VLSI,” Electronic Components and Technology Conference, 2007, ECTC '07, Proceedings, 57th, May 29, 2007-Jun. 1, 2007, pp. 853-857.Applicant
- Takahashi, K. et al., “Through Silicon Via and 3-D Wafer/Chip Stacking Technology,” 2006 Symposium on VLSI Circuits Digest of Technical Papers.Applicant
- Takizawa, T. et al., “Conductive Interconnections Through Thick Silicon Substrates for 3D Packaging,” The Fifteenth International Conference on Micro Electro Mechanical Systems, Las Vegas, Jan. 20-24, 2002.Applicant
- Tezcan, D.S. et al., “Sloped Through Wafer Vias for 3D Wafer Level Packaging,” Electronic Components and Technology Conference, 2007, ECTC '07, Proceedings, 57th, May 29, 2007-Jun. 1, 2007, pp. 643-647.Applicant
- Trigas, C., “System-In-Package or System-On-Chip?,” EE Times, Sep. 19, 2003, <http://www.eetimes.com/story/OEG20030919S0049>.Applicant
- Xsil, Via Applications, 1 page, <http://www.xsil.com/viaapplications/index.htm>, retrieved from the Internet on Jul. 22, 2003.Applicant
- Xsil, Vias for 3D Packaging, 1 page, <http://www.xsil.com/viaapplications/3dpackaging/index.htm>, retrieved from the Internet on Jul. 22, 2003.Applicant
- XSiL, xise200 for vias and micro-machining, <http://www.xsil.com/products/index/html>, retrieved from the Internet on Aug. 16, 2003.Applicant
- Yamamoto, S. et al., “Si Through-Hole Interconnections Filled with Au-Sn Solder by Molten Metal Suction Method,” pp. 642-645, IEEE, MEMS-03 Kyoto, The Sixteenth Annual International Conference on Micro Electro Mechanical Systems, Jan. 2003, ISBN 0-7803-7744-3.Applicant
- U.S. Appl. No. 11/774,419, Hutto.Applicant
- U.S. Appl. No. 11/848,836, Jeung et al.Applicant
- U.S. Appl. No. 11/863,579, Lee.Applicant
- U.S. Appl. No. 11/951,751, Sulfridge.Applicant
- U.S. Appl. No. 11/966,824, Pratt et al.Applicant