Area array semiconductor package and 3-dimensional stack thereof

[00002] This U.S. nonprovisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application 2002-58056 filed on Sep. 25, 2002, the entire contents of which are hereby incorporated by reference.

[00003] 1. Field of the Invention

[00004] The present invention generally relates to semiconductor package assembly technology and, more particularly, to an area array type semiconductor package and 3-dimensional stack of area array type packages.

[00005] 2. Description of the Prior Art

[00006] The electronic industry continues to seek products that are lighter, faster, smaller, multi-functional, more reliable and more cost-effective. In an effort to meet such requirements, package assembly techniques have been developed for multi-chip packages (MCP) and chip stack packages. These types of packages combine two or more semiconductor chips in a single package, thereby realizing increased memory density, multi-functionality and/or reduced package footprint.

[00007] The use of several chips in a single package does, however, tend to reduce both reliability and yield. If, during post assembly testing, just one chip in the multi-chip or chip stack package fails to meet the functional or performance specifications, the entire package fails, causing the good chip(s) to be discarded along with the failing chip. As a result, multi-chip and chip stack package tend to lower the productivity from the assembly process.

[00008] A 3-dimensional package stack addresses this yield problem by stacking several assembled packages that each contain a single chip and that have already passed the necessary tests, thereby improving the yield and reliability of the final composite package. However, package stacks have tended to use lead frame type packages rather than area array type packages. Lead frame type packages typically utilize edge-located terminals such as outer leads, whereas area array type packages typically utilize surface-distributed terminals such as solder balls. Area array type package may therefore provide larger terminal counts and/or smaller footprints when compared with corresponding lead frame type packages.

[00009] Exemplary embodiments of the invention include an area array type semiconductor package that may be incorporated into a package stack.

[00010] Exemplary embodiments of the invention include 3-dimensional package stacks of area array type semiconductor packages having improved package interconnections.

[00011] Exemplary embodiments of the invention include semiconductor packages having solder posts connected to surface-distributed solder balls in a one-to-one correspondence. Each solder post may provide for direct interconnection between a solder ball of an upper package and a lower package during the formation of a package stack.

[00012] An exemplary embodiment of the invention is a semiconductor package having a tape circuit board, a semiconductor chip, bonding wires, an encapsulation body, solder posts, and solder balls. The tape circuit board includes a flexible base tape, a chip mounting pad, and a circuit pattern. The chip mounting pad and the circuit pattern may be formed on an upper surface of the flexible base tape. Additionally, the circuit pattern surrounds the chip mounting pad and has interconnection pads and ball mounting pads. The interconnection pads are located near the chip mounting pad, and the ball mounting pads are connected to the interconnection pads. In particular, via holes are formed to expose the ball mounting pads on a lower surface of the flexible base tape.

[00013] The semiconductor chip may be attached to the chip mounting pad and bonding wires may be used to form an electrical connection between the interconnection pads and the semiconductor chip. The encapsulation body is formed on the tape circuit board to encapsulate the semiconductor chip and the bonding wires. The encapsulation body may be formed with connecting holes that open to corresponding ball mounting pads or the connecting holes may be formed in a process separate from the formation of the encapsulation body. The connecting holes may be filled with solder to form solder posts that are electrically connected to the ball mounting pad. Solder balls may be formed on the opposite side of the ball mounting pads that are exposed through the corresponding via holes.

[00014] The solder balls and the solder posts may be aligned to form a generally vertical arrangement having a one-to-one correspondence between the solder posts and solder balls. The diameter of the connecting holes may also be sized to approximate the diameter of the corresponding via holes. In addition, the solder posts may be formed by reflowing solder balls provided on the connecting holes or by filling the connecting holes with solder paste using a process such as screen printing and then reflowing the solder paste.

[00015] A package stack according to an exemplary embodiment of the invention may be provided by stacking at least two of semiconductor packages described above. In such a package stack, the solder posts of a lower package may be directly conjoined and electrically connected to the solder balls of an upper package.

[00026] Exemplary embodiments of the invention will be described below with reference to accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein; rather, these exemplary embodiments are provided so that this disclosure is thorough and complete, and conveys the concept of the invention to those skilled in the art. In the drawings, the thickness and spacing of layers and regions may be enlarged or reduced for clarity and are not intended to be to scale. When a layer is referred to as being “on” another layer or substrate, the layer may be directly on the other layer or substrate, or intervening layers may also be present.

[00027] FIG. 1 is a cross-sectional view of an exemplary embodiment of the invention showing an area array type semiconductor package 100. Referring to FIG. 1, a plurality of solder balls 60 may be formed on the lower surface of semiconductor package 100, with a plurality of solder posts 50 provided through an encapsulation body 40 to establish an one-to-one electrical connection between the solder balls 60 and an area exposed on an upper surface of semiconductor package 100. The solder posts 50, as well as the solder balls 60, may then be used for establishing connections between adjacent packages in a semiconductor stack package.

[00028] As illustrated in FIG. 3, a circuit pattern 17 may be provided on the upper side of a flexible base tape 13 such as a polyimide tape. The circuit pattern 17 may be provided around a centrally located chip mounting pad 15 on the upper surface of the flexible base tape 13. Additionally, the circuit pattern 17 may include interconnection pads 12 provided near the chip mounting pad 15, and ball mounting pads 14 that may be connected to the interconnection pads 12 by internal wires 16. Via holes 18 (not shown) may be formed in the flexible base tape 13 to enable the solder balls 60 to be connected to the ball mounting pads 14.

[00029] As illustrated in FIG. 4, a semiconductor chip 20 may be attached to the chip mounting pad 15 of the unit tape circuit board 11. The interconnection pads 12 and the semiconductor chip 20 may then be electrically connected to each other using bonding wires 30. As illustrated in FIG. 5, in order to protect the semiconductor chip 20, the bonding wires 30 and the circuit pattern 17, an encapsulation body 40 may be formed on the upper surface of the tape circuit board 11. The encapsulation body 40 may be formed from a variety of materials such as resin.

[00030] As illustrated in FIG. 6, in order to establish electrical connection between the stacked semiconductor packages, a plurality of connecting holes 42 may be provided through the encapsulation body 40 above the ball mounting pads 14. Solder posts 50 may then be formed by filling the connecting holes 42 with solder. As illustrated in FIG. 7, solder balls 60 may then be formed on the portions of the ball mounting pads 14 that are exposed through the via holes 18 of the unit circuit board 11. The solder balls 60 and the solder posts 50 provided on opposite sides of the ball mounting pads 14 may be arranged in vertical alignment to simplify the stacking and connection of multiple semiconductor packages 100. The diameter of the connecting holes 42 may also be sized to approximate the diameter of the corresponding via holes 18.

[00031] A process for making the semiconductor package 100 shown in FIG. 1 will be further described with reference to FIGS. 2-8. A tape circuit board 10 may be prepared as shown in FIG. 2. The tape circuit board 10 will typically include a plurality of the unit tape circuit boards 11 described above for producing a plurality of semiconductor packages simultaneously. The tape circuit board 10 itself may be produced and supplied to the manufacturing operation using conventional techniques.

[00032] A semiconductor chip 20 may then be attached to the chip mounting pad 15 of each of the unit tape circuit board 11 as illustrated in FIGS. 2-4. Once mounted on the unit tape circuit board 11, the semiconductor chip 20 may be electrically connected to interconnection pads 12 using bonding wires 30.

[00033] An encapsulation body 40 may then be formed over the semiconductor chip 20 and bonding wires 30 as shown in FIG. 5. For example, the encapsulation body 40 may be formed using a molding method in which a liquid resin is supplied on the upper surface of the unit tape circuit board 11 and then cured. The encapsulation body 40 may encapsulate each unit tape circuit board 11 individually or may encapsulate a plurality of adjacent unit tape circuit boards arranged on the tape circuit board 10. If more than one unit tape circuit board 11 is included in a single encapsulation body 40, the unit circuit boards 11 may be separated during the package separation step described below.

[00034] The encapsulation body 40 includes or is provided with connecting holes 42 through which the ball mounting pads 14 are exposed. If the encapsulation body 40 is formed with a resin molding process, the connecting holes 42 may be formed during the molding process. This may be accomplished by providing an upper mold die having protrusions or other obstacles arranged to prevent the liquid resin from filling the area above the ball mounting pads 14. When resin is cured and the upper mold die is removed, the connecting holes 42 will remain in the encapsulation body 40.

[00035] Solder posts 50 may then be formed by filling the connecting holes 42 with solder as illustrated in FIG. 6. The solder posts 50 may be formed, for example, from an initial solder ball or from solder paste. In the solder ball method, a solid solder ball (such as the solder balls 60 used as terminals) may be provided above each connecting hole 42 and then reflowed, allowing the solder from the solder ball to flow into and fill the connecting hole 42. In solder paste method, a quantity of solder paste may be applied to encapsulating body to fill the connecting holes 42 using a method such as screen-printing. This solder paste may then be reflowed to form the solder posts 50.

[00036] Solder balls 60 may then be formed as illustrated in FIG. 7. The solder balls 60 may be formed on the lower side of the ball mounting pads 14 that have been exposed through the via holes 18. A flux is typically applied to the ball mounting pads 14 before the solder balls 60 are formed. The solder balls 60 may then be mounted on the pads 14 and reflowed. Similarly, solder ball may also be provided on the upper surfaces of the solder posts 50 to produce a semiconductor package having solder balls arranged on both the upper and lower surfaces. Nickel (Ni), gold (Au) and their alloys may also be used to form the solder balls 60.

[00037] Individual semiconductor packages 100 may then be separated from the tape circuit board 10 using a conventional cutting tool such as a blade wheel or laser to form a separation 70 between adjacent semiconductor packages. If the encapsulation body 40 covers more than one of the unit tape circuit boards 11, the encapsulation body 40 will also typically be divided into portions covering a single unit circuit board 11 during the package separation process. Although this exemplary embodiment was described with reference to a tape circuit board, those of ordinary skill in the art will appreciate that a printed circuit board may be utilized as an alternative with post mounting pads provided on the upper side of the printed circuit board and aligned with the ball mounting pads.

[00038] Packages 100a and 100b fabricated using the process described above may then be stacked to produce a package stack 200 as shown in FIG. 9. As illustrated in FIG. 9, the upper semiconductor package 100b may be electrically connected to the lower semiconductor package 100a by a direct joint formed between the solder post 50a of the lower package 100a and the corresponding solder ball 60b of the upper package 100b. In the process of making such a connection, the solder balls 60b of the upper package 100b are arranged above and aligned with the corresponding the solder posts 50a of the lower package 100a and then reflowed to form a solder joint. The connection using the solder posts and solder balls can allow pin-to-pin interconnection between the packages 100a and 100b. That is, since the solder balls 60a and 60b and the solder posts 50a and 50b are vertically aligned, a direct electrical connection may be made between the corresponding terminals of each of the packages included in the stack to produce a 3-dimensional stack of area array type packages.

[00039] In the exemplary embodiment 3-dimensional package stack of the invention, the solder balls 60a of the lower package 100a may be used as external terminals of the package stack 200 for final assembly of the package stack onto another electronic device such as a mother board. In addition, the solder posts 50b of the upper package 100b may also be accessed for testing purposes after the package stack 200 is assembled on the electronic device. Although an exemplary embodiment of the invention has been described with reference to two stacked semiconductor packages, those of ordinary skill in the art will appreciate that the process described may also be utilized to form stack packages of three of more semiconductor packages.

[00040] While the present invention has been particularly shown and described with reference to certain exemplary embodiments, it should be understood that the scope of the present invention is defined by the claims provided below and is not restricted to the exemplary embodiments. In addition, it is obvious that, guided by the present disclosure, one of ordinary skill in the art may be able to make various deviations from and modifications to the exemplary embodiments without departing from the scope of the invention.