US 7,482,245 B1Grant
Stress profile modulation in STI gap fill
Issue Date:2009-01-27
•22 Claims
•7 Drawing Sheets
Abstract
High density plasma (HDP) techniques form silicon oxide films having sequentially modulated stress profiles. The HDP techniques use low enough temperatures to deposit silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve partially filling a trench on a substrate with a portion of deposited dielectric using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric and can be repeated until the trench is filled. Transistor strain can be generated in NMOS or PMOS devices using stress profile modulation in STI gap fill.
Metadata
Assignee
- Novellus Systems, Inc.
Inventors
- Jengyi Yu
- Chi-I Lang
- Judy H. Huang
Application Information
Application Number:US 11/471,958
Filing Date:2006-06-20
Priority Date:2006-06-20
Art Unit:2894
Classifications
IPC:
H01L21/76
Patent Drawings (7 sheets)
Description
Field of the Invention
[0001] This invention relates to high density plasma (HDP) deposition techniques for forming silicon oxide films. The methods can be used to tailor stress in deposited silicon oxide films in transistor architectures to control channel strain.
Background
[0002] As transistors are scaled to smaller dimensions there is a need for higher switching speeds. One solution to increase transistor speed is to strain the silicon in the channel. Adding a small amount of strain to the silicon lattice structure promotes higher electron and hole mobilities, which increase transistor drain current and device performance.
[0003] When the lattice is under tensile strain, its physical symmetry is broken, and with it the electronic symmetry. The lowest energy level of the conduction band is split, with two of the six original states dropping to a lower energy level and four rising to a higher energy level. This renders it more difficult for the electrons to be ‘scattered’ between the lowest energy states by a phonon, because there are only two states to occupy. Whenever electrons scatter, it randomizes their motion. Reducing scatter increases the average distance an electron can travel before it is knocked off course, increasing its average velocity in the conduction direction. Also, distorting the lattice through tensile strain can distort the electron-lattice interaction in a way that reduces the electron's effective mass, a measure of how much it will accelerate in a given field. As a result, electron transport properties like mobility and velocity are improved and channel drive current for a given device design is increased in a strained silicon channel, leading to improved transistor performance.
[0004] High tensile films have recently been introduced to the transistor device manufacturing process. For example, highly tensile silicon nitride capping layers have been used in NMOS structures to induce tensile strain in the NMOS channel region. The stress from this capping layer is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in the NMOS channel. However, highly tensile silicon nitride capping layers are generally deposited using thermal CVD processes, which may consume too much of thermal budget for advanced transistor architectures. In addition, silicon nitride capping layers are not appropriate for use in PMOS structures where it is preferable to have compressive strain in the PMOS channel region.
[0005] Additionally, biaxial strained silicon may also be achieved through the deposition of Si and silicon germanium (SiGe) epilayers, but is a costly process. Moreover, strained Si on SiGe epilayers utilize thick, complex, and defect containing buried SiGe layers (such as graded buffer layers where the Ge content is increased from 0% up to the targeted Ge concentration, typically 20%) in order to provide a template for a relaxed SiGe layer of constant Ge content. This layer becomes a virtual substrate for the strained Si epitaxy of which Ge diffusion, strain relaxation, and creation and propagation of misfit and threading dislocations are only some of the limitations that prevent it from being flexible for strain engineering.
[0006] Accordingly, new transistor architectures and fabrication processes for generating and modulating channel strain are needed.
Summary of the Invention
[0007] The present invention addresses this need by providing methods for forming silicon oxide films using high density plasma (HDP) CVD techniques. The methods can be used to tailor stress in deposited dielectric films in transistor architectures to generate and modulate channel strain without adversely impacting the efficiency of the transistor fabrication process.
[0008] In preferred embodiments, the methods involve partially filling a trench on a substrate with a portion of deposited dielectric using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric having the different stress condition and can be repeated until the trench is filled. Transistor strain can be generated in NMOS or PMOS devices using stress profile modulation in STI gap fill. Example applications include high tensile stress silicon oxides for use in shallow trench isolation structures, pre-metal dielectric layer and silicon on insulator substrates.
[0009] Modulation of the stresses in the deposited dielectric may be achieved by varying the substrate temperature during deposition. The substrate temperature can be controlled by varying the backside helium pressure or through the use of resistive heating and coolant. By varying the substrate temperature during the deposition, the hydrogen content in the deposited film and silicon lattice of the substrate are modulated accordingly to achieve tensile stress in the deposited film after post deposition treatments. The pressure may be varied in any known manner, such as a step-by-step variation and/or gradually ramped in each stress profile modulation layer to achieve the desired stress condition.
[0010] These and other aspects and advantages of the invention are described further below and with reference to the drawings.
Brief Description of the Drawings
[0011] FIG. 1 is a flowchart illustrating a method of forming an STI feature in accordance with the present invention.
[0012] FIG. 2 illustrates various embodiments for modulating stress profiles in an STI in accordance with embodiments of the present invention.
[0013] FIG. 3 is a graph illustrating the relationship of the backside helium pressure to compression and tensile stress in accordance with embodiments of the present invention.
[0014] FIG. 4 is a diagram comparing the various stresses on an STI in accordance with embodiments of the present invention.
[0015] FIG. 5 illustrates a simple transistor architecture in accordance with embodiments of the present invention.
[0016] FIGS. 6A-6B is a schematic representation of high density plasma apparatus suitable for methods in accordance with embodiments of the invention.
Detailed Description of the Invention
[0017] Reference will now be made in detail to specific embodiments of the invention. Examples of the specific embodiments are illustrated in the accompanying drawings. While the invention will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to such specific embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
[0018] Methods of the invention can be used to produce high tensile stress oxide films useful in semiconductor wafer fabrication, especially in applications for improving strained silicon transistor architectures. Some specific example transistor applications are described below with reference to FIG. 5 . Methods of the invention, however, are not limited to these transistor applications, or any other particular application. Note that to the extent that the invention applies to semiconductor wafer fabrication, the words “wafer”, “wafer substrate” and “substrate” will be used interchangeably and the words “film” and “layer” will be used interchangeably herein.
[0019] Methods of the invention are especially useful in front-end-of-line (FEOL) processes in semiconductor wafer fabrication. Examples include dielectric gap fill applications such as shallow-trench isolation (STI) structures and pre-metal dielectric (PMD) layers, as well as silicon-on-insulator (SOI) dielectric applications.
[0020] High density plasma chemical vapor deposition (HDP-CVD or HDP) techniques are typically the method of choice for many gap fill deposition applications because they can provide void-free high-quality dielectric films, even in high aspect ratio device structures. The basis for the improved gap filling capability is that HDP sources can provide a high density of low energy ions to the wafer surface. The ions can simultaneously sputter the film during CVD deposition. The sputtering can remove material from some regions on the wafer surface more rapidly than other regions, resulting in films that can fill narrow gaps with no voids.
[0021] HDP methods are not only used in gap filling depositions. In many traditional HDP applications, gap fill or otherwise, silicon oxide films are deposited with the goal of attaining dense films. Unlike other deposition processes, HDP techniques can be used to produce dense films. For example, HDP methods can produce silicon oxide films as dense as thermally deposited silicon oxide. These dense films can be produced because the ion bombardment aspect of HDP has the effect of densifying growing film. Any voids formed on the surface regions of the film during deposition are forced out by the energy of the bombarding ions. With densification comes compressive stress. Compressive stress is created by the compaction of the silicon oxide network of the film.
[0022] Methods of the present invention focus on using HDP methods to modulate and control the stress produced in dielectric films, including producing films with regions of high tensile stress. The deposited dielectric film can be silicon dioxide, silicon nitride, silicon oxynitride, or doped silicon oxide materials (e.g., PSG, FSG). In contrast to compressive stress, tensile stress is the stress state of a material leading to expansion of the internal atomic network. For silicon oxide films, tensile stress leads to the expansion of the silicon oxide network. However, since HDP methods are used to deposit the film, the densifying effects of the high density plasma still produce a relatively dense film compared to films produced using standard CVD or PECVD deposition techniques. Thus, the present invention allows one to produce relatively dense silicon oxide films that possess a range of stresses, from highly compressive to highly tensile.
[0023] Tensile and compressive stress can be measured in force divided by units of area, usually dynes/cm2 or N/cm2, and are well defined within the art and will not be discussed in detail herein. Any suitable method for measuring compressive and tensile stress may be used. For example, standards for measuring compressive and tensile stress of materials described by the American Society for Testing and Materials (ASTM) may be used. Measures of compressive and tensile stress presented herein may be made with any suitable apparatus including a KLA-Tencor Flix or FSM stress gauge device.
[0024] In accordance with the present invention, a STI feature with a modulated stress profile is provided by an HDP-CVD based technique. The method of forming a STI feature includes a substrate with a trench to be filled in an HDP reaction chamber. The trench may be partially filled with a portion of deposited dielectric using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric having the different stress condition and can be repeated to produce additional dielectric until the trench is filled.
[0025] The stress conditions applied to the deposited dielectric may either be compressive stress or tensile stress as described above. Additionally, the stresses may be sequentially modulated such that a user may apply a stress in any profile desired. For exemplary purposes only and not intended to be limiting, the first stress condition applied may be compressive stress and a second stress condition applied may be tensile stress or vice versa. However, the stress profile may also apply the same type of stress (e.g., tensile or compressive) in different degrees for the first and second stress conditions. The stress conditions may be alternating or repeating profiles until the trench is filled. For example, the first stress condition applied may be tensile stress, the second stress condition may be compressive stress, and the third stress condition may be tensile stress, with each stress condition alternating until the trench is filled.
[0026] In another embodiment, the stress in the trench may be gradually modulated from any depth of the trench, such as from the middle to the top of the trench. Compressive stress may occur in the middle of the trench while gradually applying tensile stress through to the top of the trench. Alternatively, tensile stress may occur in the middle and compressive stress may be applied gradually to the top of the trench. There are various different alternative modulated stress profiles that may be applied whereby the STI structure has sequentially modulated stress in the vertical axis of the trench.
[0027] Modulation of the stresses in the STI may be achieved by varying the backside helium pressure to control the substrate temperature during STI deposition. By varying the substrate temperature during the STI deposition, the hydrogen content in the deposited film and silicon lattice of the substrate are modulated accordingly to achieve tensile stress in the deposited STI film after post deposition treatments. The pressure may be varied in any known manner, such as a step-by-step variation and/or gradually ramped in each stress profile modulation layer to achieve the desired stress condition.
[0028] A more detailed description of the method of forming an STI feature will be described below with reference to FIG. 1 .
[0029] Process
[0030] FIG. 1 is a flowchart illustrating a method of forming an STI feature in accordance with the present invention. This flowchart is representative and may not encompass all possible embodiments. The following is a detailed description of the processes outlined in the flowchart.
[0031] A substrate, having a trench to be filled, is positioned in an HDP reaction chamber at 100. The STI aspect ratio (depth of trench/width of trench) may be less than about 5:1, less than about 7:1, or even about 10:1 or more. The trench is partially filled with a portion of deposited dielectric at 102 using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric at 104. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric at 106. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric having the different stress condition at 108 and can be repeated at 110 until the trench is filled.
[0032] FIG. 2 illustrates various embodiments for modulating stress profiles in an STI in accordance with embodiments of the present invention. The stress conditions applied to the deposited dielectric may either be compressive stress or tensile stress as described above. Additionally, the stresses may be sequentially modulated such that a user may apply a stress in any profile desired. For exemplary purposes only and not intended to be limiting, the first stress condition applied may be compressive stress 202 and a second stress condition applied may be tensile stress 204 as illustrated in Stress Profile 1 or vice versa as illustrated at Stress Profile 2. However, the stress profile may also apply the same type of stress (e.g., tensile or compressive) in different degrees for the first and second stress conditions. The stress conditions may be alternating or repeating profiles until the trench is filled. For example, the first stress condition applied may be tensile stress, the second stress condition may be compressive stress, and the third stress condition may be tensile stress, with each stress condition alternating until the trench is filled.
[0033] In another embodiment, the stress in trench 208, 210 may be gradually modulated from any depth of the trench, such as from the middle 212 to the top 214 of trench 208, 210. As illustrated with Stress Profile 3, compressive stress may occur in the middle 212 with tensile stress gradually applied through to the top 214 of the trench 208. Alternatively, as illustrated with Stress Profile 4, tensile stress may occur in the middle 212 and compressive stress may be gradually applied through to the top 214. As will now be realized, there are various different alternative modulated stress profiles that may be applied whereby the STI structure has sequentially modulated stress in the vertical axis of the trench.
[0034] In general for HDP methods, hydroxyl formation increases with decreasing substrate temperature. Alternatively, hydroxyl formation may also be increased by decreasing low frequency RF (LFRF) source power, decreasing high frequency RF (HFRF) power and/or increasing substrate to inductive coil distance. In specific embodiments, stress profile modulation in accordance with the present invention can be achieved by modifying the substrate temperature during dielectric deposition. HDP deposition occurring at temperatures in excess of 400° C., for example about 500-700° C., results in the formation of films having compressive stress. HDP CVD conducted at lower temperatures, below 400° C., e.g., below 250° C., for example about 150° C., results in the formation of films which incorporate hydroxyl (OH) groups. In general, the lower the temperature, the more OH groups are incorporated in the deposited film. Post-deposition annealing of the low temperature deposited film, for example by thermal or plasma-based treatment, removes OH groups thereby generating tensile stress. Variance of the deposition temperature and anneal conditions can be used to control the ultimate stress in the completed film. In specific embodiments, deposited film stress is controlled by substrate temperature that is in turn controlled by backside helium pressure. Alternatively, the substrate temperature can be controlled by resistive heating and coolant cooling of the chuck.
[0035] HDP CVD conditions are described in general in a variety of commonly assigned issued and pending applications, such as Ser. Nos. 10/316,987, 10/890,655 and 10/991,890. The details of HDP CVD deposition processes disclosed in these applications is incorporated herein by reference and provide guidance with regard to the other basic conditions to be used in suitable HDP CVD processes in accordance with the present invention.
[0036] In general, the deposition process gas will include a dielectric precursor such as SiH4, SiF4, Si2H6, TEOS (tetraethyl orthosilicate), TMCTS (tetramethyl-cyclotetrasiloxane), OMCTS (octamethyl-cyclotetrasiloxane), methyl-silane, dimethyl-silane, 3MS (trimethylsilane), 4MS (tetramethylsilane), TMDSO (tetramethyl-disiloxane), TMDDSO (tetramethyl-diethoxyl-disiloxane), DMDMS (dimethyl-dimethoxyl-silane) and mixtures thereof. During deposition, the process decomposes the silicon-containing reactant to form a silicon-containing gas and plasma phase species, which can react on the surface of the substrate. Oxygen to form the silicon oxide or other dielectric material may be provided by the silicon-containing precursor itself or from another process gas such as elemental oxygen (O2), nitric oxide (NO), and/or nitrous oxide (N2O).
[0037] Typical flow rate ranges for deposition process gases are listed below.
[0038]
| Gas | Flow Rate (sccm) | |
|---|---|---|
| SiH4 | 10-250 | |
| O2 | 10-1000 | |
| H2 | 0-1500 | |
| He | 0-500 | |
| Ar | 0-100 | |
[0039] Generally, other oxygen and silicon-containing compounds can be substituted for those listed in this table. Depending upon the atom counts in the precursor gases, the flow rate ranges may have to be changed. While there are no precise rules for modifying flow rates as a function of molecular structure, generally the flow rate of the silicon-containing precursor may be reduced by a factor corresponding to the number of silicon atoms in the molecule. So, for example, if the molecule contains two silicon atoms, one may expect to reduce the flow rate of the silicon-containing precursor to a level of between about 5 and 125 sccm.
[0040] For doped dielectrics, the process gas may include a dopant precursor such as a boron-containing gas, a phosphorus-containing gas, or a mixture thereof. In a specific embodiment, the gas includes one or more boron-containing reactants and one or more phosphorus-containing reactants and the dielectric film includes a phosphorus- and boron-doped silicon oxide glass (BPSG). Examples of suitable boron and phosphorus precursor gases include the following: B2H6 and PH3.
[0041] If the dielectric is to contain an oxyfluoride (e.g., silicon oxyfluoride), then the process gas preferably includes a fluorine-containing reactant such as silicon hexafluoride (SiF4). If the dielectric is to contain an oxynitride (e.g., silicon oxynitride), then the process gas preferably includes a nitrogen-containing reactant such as N2, NH3, NF3, NO, N2O, and mixtures thereof.
[0042] Reactor pressure is held at a value necessary to sustain the high-density plasma. Preferably the process vessel is maintained at a pressure of at most about 100 mTorr. In some cases, the process chamber pressure is maintained below 1 mTorr. For many applications, however, the pressure is maintained between about 1 and 100 mTorr; most preferably between about 1 and 30 mTorr.
[0043] The low frequency power applied to the upper electrode (for generating the plasma) typically varies from 1 kW to 20 kW, and the high frequency power (for biasing the wafer) typically reaches at least about 0.2 W/cm2 (preferably varying from about 0.5 kW to 10 kW) depending on the substrate size (e.g., 200 or 300 mm diameter) and the requirements of the specific process being used.
[0044] As indicated above, the bias applied to the substrate is typically a radio frequency bias. Applying radio frequency bias to the substrate involves supporting the substrate on a substrate holder having an electrode supplying a radio frequency bias to the substrate. For many embodiments, the radio frequency bias applied to the substrate is at the frequency range of between about 100 kHz and 27 MHz. The frequency range applied to the upper, plasma-generating electrode is typically between about 300 kHz and 27 MHz.
[0045] The temperature within the process vessel should be maintained sufficiently high to ensure that the dielectric deposition reaction proceeds efficiently. Hence, the temperature preferably resides at values between about 30 and 1000° C. This temperature will vary depending upon the types of precursors employed in the reaction and the extant to which hydroxyl incorporation in the deposited dielectric is desired. Further, the temperature may be limited by process constraints, such as thermal budget limitations that preclude temperatures above 700-750° C. Such constraints become increasingly common with advanced technologies and corresponding smaller feature sizes. As noted above, HDP deposition occurring at temperatures in excess of 400° C., for example about 500-700° C., results in the formation of films having compressive stress. HDP CVD conducted at lower temperatures, below 400° C., e.g., below 250° C., for example about 150° C., results in the formation of films which incorporate hydroxyl (OH) groups. In general, the lower the temperature, the more OH groups are incorporated in the deposited film. Post-deposition annealing of the low temperature deposited film, for example by thermal or plasma-based treatment, removes OH groups thereby generating tensile stress.
[0046] FIG. 3 is a graph illustrating the relationship of the backside helium pressure to tensile stress and shrinkage in deposited oxide in accordance with embodiments of the present invention. Modulation of the stresses in a deposited dielectric (e.g., STI) may be achieved by varying the backside helium pressure to control the substrate temperature during dielectric deposition. The pressure may be varied in any known manner, such as a step-by-step variation and/or gradually ramped in each stress profile modulation layer to achieve the desired stress condition. The temperature of the substrate will decrease as the backside helium pressure increases. In accordance with the invention, the substrate temperature during the tensile film deposition is well below 400° C., e.g., below 250° C., and perhaps about 150° C.
[0047] As illustrated in FIG. 3 , as the pressure increases (e.g., to about 5-9 Torr) and therefore the substrate temperature decreases, so does the oxide shrinkage and associated tensile stress in the oxide filling the trench. At a lower substrate temperature, the silicon lattice of the substrate shrinks and there is additional hydroxyl content in the deposited film. Upon a subsequent post-deposition treatment, such as a thermal or plasma-based anneal, additional hydroxyl content is released from the deposited film. Therefore, the deposited film shrinks and produces a tensile stress in the STI, for example.
[0048] Any of a number of suitable methods or combination of methods may be used to remove hydroxyl groups from the dielectric film to create a film having tensile stress, including plasma methods, thermal methods, radiation exposure methods or a combination thereof. In preferred embodiments, a high density plasma or a thermal method is used. This is in part because HDP and thermal methods can typically performed in the same chamber as the previous deposition process and will thereby save time.
[0049] If a post-deposition HDP treatment is used, the HFRF power will preferably be off or very low so as to prevent ion bombardment of the deposition film. Conditions that allow too much ion bombardment can cause the film to revert to a compressive film by adding further Si—O bonds in the film via a bond insertion mechanism. The low frequency (LFRF) power is also preferably low enough to prevent too much ion bombardment but should be high enough to efficiently remove water. For a 200 mm wafer, the LFRF will typically be between about 7000 and 8000 Watts. Treatment times may vary depending upon the LFRF power and substrate temperature. For example, a treatment using a substrate temperature between about 500 and 600° C. and LFRF power between about 7000 and 8000 Watts will typically require a treatment time less than about 60 seconds. A treatment using a substrate temperature no more than about 400° C. and LFRF power between about 7000 and 8000 Watts will typically require a treatment time no more than about 180 seconds. The high density plasma is preferably comprised of inert gas/gases such as helium, argon CO2, N2 or a combination thereof. In preferred embodiments, the substrate temperature ranges between about 300 and about 800° C.
[0050] For embodiments where a thermal process is used to remove water, the substrate temperature preferably ranges between about 300 and about 1000° C. In preferred embodiments, the thermal treatment can occur in an inert environment such as under vacuum or in the presence of an inert gas such as helium, argon, CO2, N2 or a combination thereof. Alternatively, the thermal treatment can occur in the presence of a non-reducing gas, for example in the presence of oxygen. It is preferable that reducing gases, such as hydrogen, not be used since they may react with the film. The use of an inert or non-reducing gas can inhibit the water removal process. While not wishing to be bound by theory, it is believed that the gas lingers and effectively creates a seal over the substrate and reduces water removal efficiency. Oxygen, in particular, has been found to have a relatively strong suppression effect. Thus, one can tune the amount and/or rate of water removal (i.e., tune the amount of stress induced in the film) by controlling the amount of inert or non-reducing gas. The duration of the thermal treatment can vary broadly depending upon substrate temperature, gas pressures, other process conditions and desired resultant film stress. Preferable treatment times are less than about 2 hours, more preferably less than about 1 hour.
[0051] FIG. 4 is a diagram comparing the various stresses on a STI in accordance with embodiments of the present invention. Strain-free Si lattice 402 and conventional compressive strained STI 404 are illustrated. These conventional stresses on STI structures impose undesired strain on the silicon that degrades the electron mobility. However, the present invention provides for an STI with sequentially modulated stress and shrinkage 406 in the vertical direction to enable uniaxial strain engineering on adjacent silicon islands where the transistors are built. Gap fill capabilities in tensile STI structures of the present invention have been demonstrated down to 45 nm node designs.
[0052] Applications
[0053] As mentioned previously, methods of the invention may be used to produce sequentially modulated stress profiles in oxide films in a number of front-end-of-line (FEOL) integrated circuit applications. Using methods of the invention, STI stress profiles may be modulated to create global strain (uniform strain throughout the device) or local strain (selected regions of strain), as well as uniaxial strain (stress imparted in one surface direction) or biaxial strain (stress imparted in both surface directions). It is generally desirable to impart tensile stress, in the channel region of NMOS structures since this increases electron mobility while it is generally desirable to impart compressive stress in the channel region of PMOS structures since this increases hole mobility. Thus, a user may modulate the stresses of an STI to impart tensile and compressive strain in channel regions of NMOS and PMOS transistors to optimize device performance.
[0054] The following description, along with FIG. 5 provides a specific example application of the present invention. FIG. 5 illustrates a CMOS device with STI structures having sequentially modulated stress profiles. The following implementations may be used alone or in combination. For example, methods of the invention may be used to form one or more STI structures, PMD layers and SOI structures in one device. These example applications are provided to exemplify and more clearly illustrate aspects of the present invention and is in no way intended to be limiting.
[0055] FIG. 5 illustrates a simple transistor architecture of CMOS device 500 in accordance with the present invention. The CMOS device 500 has NMOS transistor 502 over epitaxial oxide 504. NMOS transistor 502 is composed of an p-doped well 506, a conductive gate 508 separated from the p-doped well 506 by a gate dielectric 510, a n-doped source 512 and a n-doped drain 514. A np-type channel region 516 lies under gate 508. There may also be sidewall spacers 518 on gate 508. The source 512, drain 514 and gate 508 are covered with a layer of self-aligned silicide (salicide) 520. Note that in some cases salicide 520 may additionally be covered with a silicon nitride capping layer (not shown). STI structures 522 and 524 lie on either side of NMOS transistor 502 and isolate NMOS transistor 502 from wells 526 and 528 and source 532 and drain 530 of adjacent transistor structures. STI structures 522 and 524 may also have thin thermal oxide trench liners 536 and 538 that were deposited prior to deposition of the oxides 532 and 534. STI structures 522 and 524 comprise oxides 532 and 534, respectively, having sequentially modulated stress profiles. Oxides 532 and 534 were deposited using the HDP methods in accordance with embodiments of the invention. By modifying the HDP method as described above, sequentially modulated compressive and/or tensile strain may be created in the vertical axis of oxides 532 and 534 thereby allowing a fine degree of control and mobility of electrons in the channel region 516.
[0056] Apparatus
[0057] The present invention is implemented in a high density plasma chemical vapor deposition (HDP-CVD) reactor. Such a reactor may take many different forms. Generally, the apparatus will include one or more chambers or “reactors” (sometimes including multiple stations) that house one or more wafers and are suitable for wafer processing. Each chamber may house one or more wafers for processing. The one or more chambers maintain the wafer in a defined position or positions (with or without motion within that position, e.g. rotation, vibration, or other agitation). In some embodiments, silicon oxide deposition and treatment occur in one reactor. In other embodiments, a wafer undergoing silicon oxide deposition and treatment is transferred from one station to another within the reactor during the process. While in process, each wafer is held in place by a pedestal, wafer chuck and/or other wafer holding apparatus. For certain operations in which the wafer is to be heated, the apparatus may include a heater such as a heating plate. Examples of suitable reactors include the Speed™ reactor, available from Novellus Systems of San Jose, Calif., and the Ultima™ reactor, available from Applied Materials, Inc. of Santa Clara, Calif.
[0058] The principal components of most suitable reactors include a reaction chamber, a process gas delivery system, a support for the substrate, one or more electrodes or radio frequency power source coupled to an induction coil to generate an inductively coupled plasma, and a bias source for the substrate. A temperature control system is typically used to heat the substrate. Suitable plasma processing reactors are described, for example, in U.S. Pat. Nos. 5,346,578, 5,405,480 and 5,605,599, the disclosures of which are incorporated by reference herein in their entirety and for all purposes.
[0059] FIGS. 6A-6B is a schematic representation of high density plasma apparatus suitable for methods in accordance with embodiments of the invention. FIG. 6A is a vertical cross-section block diagram depicting some components of a suitable plasma processing reactor suitable for conducting a gap fill on semiconductor wafers. As shown, the reactor 601 includes a process chamber 603 which encloses other components of the reactor and serves to contain the plasma generated by the radio frequency power source coupled to the induction coil 605, which surrounds the chamber on or embedded in the chamber walls. In one example, the process chamber walls are made from aluminum, aluminum oxide, and/or other suitable material. The coil 605 is powered by a “low frequency” radio frequency (RF) source 606. The power and frequency supplied by source 606 is sufficient to generate high-density plasma from the process gas.
[0060] Within the reactor, a wafer pedestal 607 supports a substrate 609. The pedestal typically includes a chuck (sometimes referred to as a clamp) to hold the substrate in place during the deposition reaction. The chuck may be an electrostatic chuck, a mechanical chuck or various other types of chuck as are available for use in the industry and/or research.
[0061] A heat transfer subsystem including a line 611 for supplying a heat transfer gas controls the temperature of substrate 609. In some embodiments, the heat transfer fluid comprises at least one of helium and argon gas. The heat transfer fluid is supplied to a space 613 between the surface of the substrate and a surface of the chuck.
[0062] A “high frequency” RF source 615 serves to electrically bias substrate 609 and draw charged precursor species onto the substrate for the deposition reactions. Electrical energy from source 615 is coupled to substrate 609 via an electrode or capacitive coupling, for example. Note that the bias applied to the substrate need not be an RF bias. Other frequencies and DC bias may be used as well. In a specific embodiment, source 615 supplies a radio frequency bias to the substrate with a power ranges from 0.5 kW to 10 kW.
[0063] The process gases are introduced via one or more chamber inlets 617. The gases may be premixed or not. Other sources of dielectric precursor gases and carrier gases are also provided. Preferably, the process gas is introduced through a gas supply inlet mechanism including orifices. In some embodiments, at least some of the orifices orient the process gas along an axis of injection intersecting an exposed surface of the substrate at an acute angle. Further, the gas or gas mixture may be introduced from a primary gas ring, which may or may not direct the gas toward the substrate surface. In this embodiment, a ring inlet(s) 618 is connected to the primary gas ring 619 to supply gas or gas mixture into the chamber via the chamber inlets 617. This arrangement is further illustrated in the horizontal cross-section of FIG. 6B which depicts a ring inlet and eight chamber inlets for process gas. Note that inlets, gas rings or other mechanisms for supplying process gas to the reactor process chamber are not critical to this invention. The sonic front caused by the gas entering the chamber will itself cause the gas to rapidly disperse in all directions—including toward the substrate.
[0064] The process gas exits the chamber 603 via an outlet or outlets 620. A vacuum pump (e.g., a turbomolecular pump) or pumps 622 typically draws the gas out and maintains a suitably low pressure within the reactor.
[0065] As noted above, the gap fill process of the present invention is preferably accomplished in a single reactor process chamber, but it may also be accomplished in a plurality of processing chambers. When more than one processing chamber is used, a pressure controlled transfer module should be used to transfer the wafers from one chamber to another. Such transfer modules and procedures are known to those skilled in the art.
[0066] Reactor pressure is held at a value necessary to sustain the high-density plasma. Preferably the process vessel is maintained at a pressure of at most about 30 mTorr. For many applications, however, the pressure is maintained between about 3 and 20 mTorr; most preferably between about 5 and 20 mTorr. In one embodiment of the invention, the pressure is maintained at about 15 mTorr during the deposition process and about 5 mTorr during the post-deposition treatment.
[0067] For a typical apparatus, the low frequency power applied to the upper electrode (for generating the plasma) can typically vary from 1 kW to 20 kW, and the high frequency power (for biasing the wafer) can typically reach at least about 0.1 W/cm2. Note that preferred RF power will depend on the substrate size (e.g., 200 or 300 mm diameter) and the requirements of the specific process being used.
[0068] The bias applied to the substrate is typically a radio frequency bias. Applying radio frequency bias to the substrate involves supporting the substrate on a substrate holder having an electrode supplying a radio frequency bias to the substrate. For many embodiments, the radio frequency bias applied to the substrate is at the frequency range of between about 100 kHz and 27 MHz. The frequency range applied to the upper, plasma-generating electrode is typically between about 100 kHz and 27 MHz.
Example
[0069] A series of HDP CVD SiO2 layers were deposited with conditions progressively changed to generate compressive to tensile stress in the resulting composite film. For layer 1, no backside He flow was used and the wafer temperature exceeded 400° C. Six additional layers were applied on the first layer with stepwise increases in the backside He pressure as follows: Layer 2, 1 Torr; layer 3, 2 Torr; layer 4, 3 Torr; layer 5, 4 Torr; layer 6, 5 Torr; and layer 7, 6 Torr. The lower layers exhibited compressive stress while the topmost layers exhibited tensile stress.
Conclusion
[0070] Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing both the process and compositions of the present invention. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein. All references cited herein are incorporated by reference for all purposes.
Claims
The invention claimed is:
1. A method of forming a shallow trench isolation (STI) feature, the method comprising:
(a) providing a substrate having a trench to be filled in a reaction chamber, the reaction chamber capable of maintaining a high density plasma;
(b) partially filling the trench on the substrate with a first portion of deposited dielectric using a high density plasma chemical vapor deposition process having conditions configured to produce a first stress condition in the first portion of deposited dielectric;
(c) modifying a deposition process condition to produce a different stress condition in deposited dielectric; and
(d) further filling the partially-filled trench using the modified deposition process to produce additional dielectric;
whereby the STI feature having sequentially modulated stress in the axis of the trench results.
2. The method of claim 1, wherein the deposition process condition is modified discretely from operations (b) to (d).
3. The method of claim 1, wherein the deposition process condition is modified gradually from operations (b) to (d).
4. The method of claim 1, wherein the further filing of operation (d) fills the trench.
5. The method of claim 1, further comprising repeating operations (c) and (d) until the trench is filled.
6. The method of claim 5, wherein the different stress condition in repeated operation (d) is the same as the first stress condition.
7. The method of claim 5, wherein the different stress condition in repeated operation (d) is different from the first stress condition.
8. The method of claim 1, wherein the modified process condition comprises a substrate temperature.
9. The method of claim 8, wherein the substrate temperature is controlled by resistive heating and coolant cooling of the chuck.
10. The method of claim 8, wherein the substrate temperature is controlled by a backside helium pressure wherein the substrate temperature decreases as the backside helium pressure increases.
11. The method of claim 10, wherein as the backside helium pressure increases, the stress condition of the deposited dielectric is more tensile in character.
12. The method of claim 1, wherein one or more of the HDP CVD processes comprises a post-deposition anneal that imparts a stress condition to the deposited dielectric that is more tensile in character.
13. The method of claim 1, wherein the first stress condition is compressive stress and the different stress condition is tensile stress.
14. The method of claim 13, wherein the first stress condition and the different stress condition are repeated until the trench is filled.
15. The method of claim 1, wherein the first stress condition is tensile stress and the different stress condition is compressive stress.
16. The method of claim 15, wherein the first stress condition and the different stress condition are repeated until the trench is filled.
17. The method of claim 6, wherein the different stress condition and the first stress condition are both tensile stress, each tensile stress having a different degree of stress.
18. The method of claim 6, wherein the different stress condition and the first stress condition are both compressive stress, each compressive stress having a different degree of stress.
19. The method of claim 1, wherein the STI feature is integrated with a metal oxide semiconductor (MOS) transistor device such that the STI feature applies a uniaxial strain on a channel region of the MOS transistor.
20. The method of claim 1, wherein the trench has an aspect ratio of at least 5:1.
21. The method of claim 1, wherein the dielectric is silicon oxide.
22. The method of claim 1, wherein the dielectric is selected from the group consisting of silicon nitride, silicon oxynitride, or doped silicon oxide materials.
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