Dry polymer and oxide veil removal for post etch cleaning

[0007] 1. Field of Invention

[0008] The invention relates to a dry method for removing polymer and oxide veils for vias disposed on a Tungsten layer resulting from etching and controlling or partially removing the tungsten base or interface layer to create an undercut of the via to provide better plug adhesion when the via is filled.

[0009] 2. Description of the Prior Art

[0010] During the making of a semiconductor chip structure in which a tungsten layer is deposited on a substrate material, and in which an oxide is deposited on the tungsten layer as an interlevel dielectric (ILD), and on which a photoresist is subsequently placed on the interlevel dielectric, followed by etching and photolithographic resist removal, veils are created in the vias and on the tungsten layer. This is so because the vias are etched through insulators and the etch progress stops on the tungsten.

[0011] Unfortunately, the etch process causes organic-metal oxides, veils, and other materials to form on the tungsten as well as on the sidewalls of the vias. Additionally, there is a thin-oxide formed on the tungsten during etching and photolithographic resist removal that must be penetrated.

[0012] Removal of these veil materials has historically been accomplished using wet chemistries and therefore encumbered by the disadvantages associated with these wet chemistries.

[0013] FIG. 1 depicts a typical starting semiconductor structure wherein a substrate material 10 has a tungsten layer 11 deposited for subsequent patterning. An oxide layer as an interlevel dielectric (ILD) 12 is deposited on top of the tungsten layer, and a photoresist 13 is deposited on top of the ILD layer. In the process of forming this basic structure that is well known in the art, the oxide layer is patterned using photolithography and a typical photoresist, whereupon the oxide etch is performed using a plasma generated etching method employing various wet chemistries. However, during this etch, polymer veils 14 and oxide veils 15 are formed that are made up of metals, carbon, and oxide-based materials.

[0014] Nevertheless, when the resist is stripped using known plasma based or chemical based processes, these processes do not remove the veils formed during the etch. The problems encountered by virtue of these oxide and polymer veils are well known in the art.

[0015] Accordingly, there is a need in the art of stripping resist following etch of a semiconductor chip structure in which a tungsten layer is deposited on a substrate material, to be able to remove polymer and oxide veils from sidewalls of vias, to remove the thin oxide formed on the tungsten layer, and to control the tungsten interface and therefore high contact resistance after etch and photolithographic resist removal, by other than the wet chemistries now used.

[0016] One object of the present invention is to provide a dry process for removal of polymer and oxide veils from sidewalls of vias and on the interface of a tungsten layer of a semiconductor following oxide etch of an interlevel dielectric.

[0017] Another object of the present invention is to provide a RIE (reactive ion etching) method for removal of polymer and oxide veil's from sidewalls of vias and on the interface of a tungsten layer of a semiconductor following oxide etch of an interlevel dielectric.

[0018] A further object of the present invention is to provide a dry process for removal of polymer and oxide veils from sidewalls of vias and on the interface of a tungsten layer of a semiconductor following oxide etch of an interlevel dielectric in a manner so as to avoid the high contact resistance when an insulator interface is not removed from the tungsten surface and to limit the attack on tungsten to avoid unacceptable tungsten loss.

[0019] A yet further object of the present invention is to provide improved C1 contact adhesion after C1 polymer removal to obtain a better surface for the tungsten contact to adhere to, as a result of the undercut of the C1 via.

[0020] In general, the invention process is accomplished by:

[0021] depositing tungsten on a substrate material and patterning the tungsten;

[0022] depositing an interlevel dielectric of an oxide on the tungsten layer;

[0023] depositing a photoresist on the oxide layer and patterning the oxide layer using photolithography and photo resist;

[0024] performing an oxide etch using a plasma generated etching method, wherein oxide veils are formed of metals, and carbon and oxide based materials; and

[0025] removing the veil materials by RIE (reactive ion etching) to provide a dry polymer clean.

[0026] FIG. 1 depicts a prior art basic starting structure of a semiconductor upon which polymer veils, and oxide veils are formed on the walls and the tungsten interface of the via from plasma etching.

[0027] FIG. 2 is a photograph of magnification 1000× showing a TEM of a thin insulating layer of an oxide interface.

[0028] FIG. 3 is a photo of magnification—showing attack of the oxide interface of the tungsten layer at the bottom of the contact when the oxide interface is penetrated with too aggressive fluorine chemistry to create a void.

[0029] FIG. 4 is a plot of contact resistance versus CF₄, wherein total gas flow was held at 200 sccm.

[0030] FIG. 5 is a plot of contact resistance versus CF₄wherein the total gas flow was held at 200 sccm and the data for region 1 from FIG. 4 was removed.

[0031] FIG. 6 is a graph showing the effect of total flow on contact resistance when holding the power, pressure, and CF₄flow constant, and wherein the flow is in sccm.

[0032] FIG. 7 is a graph showing the available process window when holding the power at 275 W and the pressure constant at 0.3 Torr.

[0033] FIG. 8 is a graph showing the effect of power on the contact resistance.

[0034] FIG. 9 is a photo showing typical process results after the tungsten fill of the via.

[0035] FIG. 10 is a photo showing a semiconductor in which a tungsten via fill interface is provided at increased strength after the undercut serves to strengthen the tungsten fill process subsequent to falling out of the tungsten plug during a cross-sectioning process.

[0036] In its essence, the invention pertains to a polymer veil removal method for vias that are landed on tungsten, that is, the vias are etched through insulators and the etch stops on the tungsten layer.

[0037] The normal etch process causes organic-metal oxides, and veils to form on the tungsten and on the sidewalls of the vias. This is graphically depicted in FIG. 1, which shows a prior art semiconductor structure wherein a substrate material 10 having a tungsten layer 11 deposited thereon is subsequently subjected to patterning. An oxide layer 12 is deposited on the tungsten layer as an interlevel dielectric (ILD), and a photoresist 13 is deposited on top of the ILD oxide layer.

[0038] In the prior art process of forming this basic semiconductor structure, the oxide layer is patterned using photolithography and a typical photoresist whereupon the oxide etch is performed using a plasma generated etching method employing various chemistries. An attendant disadvantage resulting from the etch is that polymer veils 14 and oxide veils 15 are formed that are made up of metals, carbon, and oxide-based materials in general. An additional thin oxide layer (not shown) is formed on the tungsten during the etch and photolithographic resist removal that must be penetrated in order to ensure that the contact resistant is not too high; however, care must be taken that removal of the thin oxide interface insulator does not also remove tungsten in amounts greater than that which is acceptable.

[0039] In any case, removal of the veils on the sidewalls and the thin oxide formed on the tungsten during etch has historically been accomplished with wet chemistries and therefore encumbered by the known disadvantages associated with the use of these wet chemistries.

[0040] In accordance with the process of the present invention process parameters are utilized for removal of the veils in sidewalls of the vias coupled with the control of the tungsten interface to ensure that only an acceptable level of tungsten loss is obtained when the tungsten is attacked during the veil removal process.

[0041] It has been found that there are two limiting factors or boundary conditions controlling the process window when removing veils and penetrating the thin oxide formed on the tungsten during etch and photolithographic resist removal. The first boundary condition is high contact resistance that is experienced when an insulator interface is not removed from the tungsten surface. The second boundary condition is that, upon removing the insulator interface the amount of the tungsten attacked must be such that only an acceptable tungsten loss is obtained.

[0042] The present invention accomplishes these objectives by utilizing a dry polymer removal process that uses a RIE (reactive ion etching) to affect dry polymer cleaning. This dry polymer removal or cleaning is performed at elevated temperatures so that the resist can be stripped and the polymer can be removed in the same step. In this connection, fluorine based chemistries are used at elevated temperatures in a manner so that attack of the tungsten results in distinct process windows that are dependent on total flow, fluorine source to reducing ambient ratio, and the amount of power. Accordingly, the invention process establishes the process windows and operating parameters determined experimentally to overcome the two limiting factors when removing polymer veils and the thin oxide formed on the tungsten during etch and lithographic resist removal.

[0043] Veil Removal

[0044] Typical Tool Configuration

[0045] The veil removal is done in a vacuum chamber using microwave downstream plasma and reactive ion etching capabilities operating at radio frequencies not limited to but typically 13.56 mHz. The wafers are positioned on a heated platen for improved process control. Process gases for deveiling include fluorine based gases (CF₄, NF₃) and reducing gases such as forming gas (N₂[100%−X%}/H₂{X%}, argon, nitrogen or helium.

[0046] The process is restricted between two device failure criteria. First is the oxidation of the tungsten and second is the attack on the tungsten at elevated temperatures.

[0047] Boundary Condition 1: Interfacial Insulator Penetration. At high gas flows there exists a region of oxidation of the tungsten which inhibits the contact resistance from 2× to 1000×.

[0048] Boundary Condition 1 is sensitive to the flow of total reactants, fluorine source (NF₃or CF₄); power and clean time. This process boundary condition follows the following basic trends:

[0049] 1) If the Fluorine source is diluted too much, the insulator interface is not penetrated. As the total gas flow is increased, the process window widens;

[0050] 2) Increasing the radicalized fluorine eliminates this interface. Increase the microwave power or RF power source removes this interface;

[0051] 3) As fluorine concentration is decreased, the power required for penetrating the insulator increases; and

[0052] 4) Clean time in the fluorine ambient affects the penetration of the insulator interface but is secondary to power and gas flows.

[0053] Reference is now made to FIG. 2, which shows the oxide interface insulator penetration. At high gas flows there exists a region of oxidation of the tungsten, which inhibits the contact resistance from 2× to 1,000×. The oxide interface in FIG. 2 is a TEM which shows an insulating layer approximately 1 nm thick. This formation occurs at pressures between 0.5 and 0.1 Torr at high flow rates. To eliminate this condition, a gas which forms more radicalized fluorine, such as NF₃may be used.

[0054] Another embodiment of veil removal for removing the remaining resist layer as well as the polymer deposited during the via etch is through use of a chemistry including O₂, N₂, and H₂. After the resist is removed, polymer removal is affected using CF₄, N₂, and H₂. It is during this polymer removal step that the tungsten layer is etched to provide the undercut. This process results in a via shaped as shown in FIG. 3. In FIG. 3, attack of the tungsten at the bottom of the contact may be seen.

[0055] Boundary condition 2 is one, which limits the process parameters due to rapid tungsten metal attack. The tungsten attack is by the fluorine chemistry. As may be seen in FIG. 3, when the oxide interface is penetrated with too aggressive of a chemistry, the tungsten is attacked, thereby leaving a void. The attack of the tungsten is most affected by the following: high fluorine concentration; too high power (W); and too high temperatures that increase the etch rate of the resist that also increase the etch rate of the tungsten.

[0056] The invention process has developed optimization over a wide range of flows, powers, pressure and time variation to affect dry polymer and oxide veil removal and C1 polymer removal that provides a better surface for the tungsten contact to adhere to.

[0057] In the context of the invention, there is a maximum and minimum total fluorine source flow that varies with total gas flow and fluorine source. The fluorine source of CF₄works best and was chosen to prepare graphs to show the process window vs. total gas flow and CF₄flow.

[0058] FIG. 4 is a graph showing the effect of CF₄flow on contact resistance when holding the power, pressure, and total gas flow constant at 200 sccm. FIG. 5 is the same graph with region 1 removed from the data set.

[0059] Region 1 is the area where an interfacial insulator causes extremely high contact resistance and causes the lots to not operate.

[0060] Region 2, as seen in FIG. 5 is where only slight amounts of the tungsten are attacked and thereby causes contact resistances similar to that obtained by wet chemistries. As the tungsten is attacked, region 3 occurs due to an extremely high amount of tungsten etching. Region 3 saturates at a given contact resistance until the tungsten experiences failures.

[0061] In the graph of FIG. 5, where contact resistance vs. CF₄, the total gas flow was held at 200 sccm and the data for region 1 was removed.

[0062] As the total flow is increased and the CF₄to reducing gas ratio is held constant at 0.5, the contact resistance increases as seen in the graph of FIG. 6. Therefore, for CF₄, there exists a process window to work within when holding power constant and pressure constant that is bound by the two boundary conditions previously described. As maybe seen, the process window for CF₄increases as the total flow is increased.

[0063] Referring now to FIG. 7, a graph is shown of the available process window when holding the power (275 W) and pressure constant (0.3 Torr). In FIG. 7, boundary conditions 1 and 2 define the available process window. The flows are in sccm.

[0064] In the context of the invention process window, the power effects are significant and the specific role that power plays in the process window is shown in FIG. 8. In this figure, the effect of power on contact resistance is such that, increasing the power decreases the contact resistance. Most of the resistance change is consuming tungsten. Further, the spread in the data is associated with variations in the CF₄used in the test. Once an appropriate CF₄flow is determined, power follows the typical response by increasing the amount of etch of the oxide barrier and tungsten. Power needs to be tuned with the CF₄flow until an appropriate contact resistance is achieved.

[0065] Typical process conditions for storing source flow of CF₄and NF₃are shown in Tables I and II.

[0066] In the invention aspect of providing improved C1 contact adhesion after removal of the polymer, the C1 polymer removal process provides a better surface for the tungsten contact to adhere to. That is, in the polymer veil removal process for vias landed on tungsten, the tungsten base layer is partially removed, thereby resulting in an undercut of the via. The undercutting of the via provides better plug adhesion when the via is filled. While not wishing to be bound by any theory, it is believed that the better surface topography for the contact interface is achieved. In this connection, reference is again made to prior art FIG. 1 which depicts the basic starting structure in which there are polymer veils and a tungsten interface. It is this veil material removal and the control of the tungsten interface that is the focus of the invention process.

[0067] The resist is removed using a chemistry including O₂, N₂, and H₂. After the resist is removed, the polymer removal entails using CF₄, N₂, and H₂. During the polymer removal step the tungsten layer is etched to provide the undercut.

[0068] FIG. 9 shows typical process results after the via has been filled with tungsten, and the shape of the via provides a good foundation for the tungsten plug.

[0069] A typical tungsten via fill interface is shown in FIG. 10, which demonstrates the benefit of this alternative process. In this figure, a tungsten plug has fallen out during the cross-sectioning process. However, the interface between the tungsten fill and the base tungsten layer can still be clearly seen. This demonstrates that the undercut serves to strengthen the tungsten fill process. As a result, fewer contacts are lost during normal wafer processing due to the increased strength of the tungsten interface.

[0070] TABLE III shows the process parameters for this alternative aspect of the invention.

[0071] A result of this alternative process, a unique undercut of the tungsten based layer is achieved and this provides fewer contacts lost during normal wafer processing due to the increased strength of the tungsten interface.