Method of removing photoresist and reducing native oxide in dual damascene copper process

[0002] 1. Field of the Invention

[0003] The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing metallic interconnects.

[0004] 2. Description of the Related Art

[0005] As the level of integration of integrated circuit devices increases, the number of devices in a silicon chip increases and hence the number of interconnects necessary for linking semiconductor devices also increases. Consequently, integrated circuits, in particular metallic interconnects, are becoming harder to manufacture. In fact, how to produce quality conductive lines with ideal operating properties within the confines of a small contact area is a goal that all semiconductor manufacturers are actively pursuing.

[0006] Due to a reduction of line width through miniaturization, current density sustained by each metallic line increases correspondingly. Passing a high current through a narrow conventional aluminum metal line results in electromigration and subsequently leads to a device reliability problem.

[0007] To reduce electromigration, especially for sub-micron devices, copper is a better choice of material than aluminum for forming interconnects. Copper has a low resistivity and a higher resistance to electromigration. Moreover, a copper layer can be deposited by chemical vapor deposition or electroplating. However, copper is also highly resistant towards most conventional gaseous etchants, and hence copper lines are difficult to produce by conventional methods. Typically, copper lines are usually manufactured by a dual damascene process.

[0008] FIGS. 1A through 1C are schematic cross-sectional views showing the progression of steps in a conventional dual damascene process.

[0009] As shown in FIG. 1A, a substrate having a copper line 102 therein is provided. A top surface 102aof the copper line 102 is exposed. An inter-metal dielectric layer 104 is formed over the substrate 100. The inter-metal dielectric layer 104 is formed, for example, by sequentially depositing a silicon oxide, a silicon nitride and a silicon oxide layer over the substrate 100. Silicon oxide and silicon nitride have different etching rates with respect to an etchant. Silicon nitride may also be deposited over the substrate 100 to form a silicon nitride layer prior (not shown) to the formation of the inter-metal dielectric layer 104. This has the advantage of preventing copper atoms from diffusing into the inter-metal dielectric layer 104 leading to device malfunction or undesired bridging between metallic interconnects.

[0010] As shown in FIG. 1B, a dual damascene opening consisting of a trench 106 and a contact opening 110 is formed in the inter-metal dielectric layer 104 with the contact opening 110 located under the trench 106. To form the dual damascene opening, a patterned photoresist layer (not shown) is formed over the inter-metal dielectric layer 104. The inter-metal-dielectric layer 104 is etched using the patterned photoresist as an etching mask and the silicon nitride layer as an etching stop layer. Hence, the trench 106 is first formed in the inter-metal dielectric layer 104. The patterned photoresist layer is removed, and then another patterned photoresist layer 108 is formed over the inter-metal dielectric layer 104. Using the patterned photoresist layer 108 as a mask, the inter-metal dielectric layer 104 is etched again to form the contact opening 110 that exposes the surface 102aof the copper line 102.

[0011] As shown in FIG. 1C, the photoresist layer 108 is removed by ashing using oxygen plasma. The plasma ashing is carried out at a high temperature with oxygen flowing at a rate of about 2000 to 3000 sccm. Oxygen plasma oxidizes organic molecules inside the photoresist material, which contains carbon (C), hydrogen (H), nitrogen (N) and oxygen (O), into gaseous carbon dioxide (CO₂), water (H₂O) and nitrogen oxides (NO_x). The resulting gaseous products including carbon dioxide, water and nitrogen oxide are pumped away. High temperature is used to facilitate the oxidation of the photoresist material and accelerate photoresist removal.

[0012] Typically, the ashing chamber for removing photoresist material is raised to a temperature of about 250° C. However, at such a high temperature, the exposed surface 102aof the copper line 102 is also attacked by oxygen plasma. A portion of the copper near the surface 102ais oxidized into loose cupric oxide (Cu₂O) or copper oxide (CuO). Hence, electrical conductivity of the copper line decreases and contact resistance at the contact opening increases.

[0013] Although the oxides of copper can be dissolved in an alkali solvent, voids 112 are often formed on the surface 102aof the copper line 102. When a barrier layer and a seed layer are subsequently formed over the exposed sidewalls of the trench 106 and the contact opening 110, these voids 112 will result in a highly irregular profile. The irregular profile creates a high stress in subsequently deposited seeding layer during high temperature annealing, and may lead to an open contact due to surface tension. In a subsequent copper electroplating or copperless electroplating process, no copper adheres to the area where there is a break in the seeding layer. Hence, copper will not grow evenly inside the dual damascene opening, and a high contact resistance will result.

[0014] The invention provides a dual damascene process. A substrate having a copper line therein is provided. An inter-metal dielectric layer is formed over the substrate and the copper line. A patterned photoresist layer is formed over the inter-metal dielectric layer. The inter-metal dielectric layer is etched to from a contact opening and a trench that exposes a portion of the copper line with the contact opening located under the trench. At a low temperature and using N₂H₂(H₂:4%)/O₂as a gaseous mixture for producing a plasma, the photoresist layer is removed. Due to the presence of oxygen plasma, a surface layer of copper on the copper line is oxidized into copper oxide. Using the N₂H₂(H₂:4%) as a gaseous source, the copper oxide layer on the surface of the copper line is reduced back into copper. A barrier layer conformal to the trench and contact opening profile is formed. Copper is deposited to form a conformal first copper layer over the trench and the contact opening. Using the first copper layer as a seeding layer, a copper or a copperless electroplating is carried out to form a second copper layer. The second copper plug layer includes a trench line and a contact.

[0015] This invention also provides a dual damascene process that uses a gaseous mixture N₂H₂(H₂:4%)/O₂to produce a plasma for removing photoresist material at a low temperature so that the oxidation of copper on the surface of copper lines is greatly reduced.

[0016] This invention also provides a dual damascene process that uses a gas N₂H₂(H₂:4%) to reduce the copper oxide formed after the removal of photoresist material back into copper so that lowering of electrical conductivity of metallic interconnects and increase of contact resistance are prevented.

[0017] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0018] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0019] FIGS. 1A through 1C are schematic cross-sectional views showing the progression of steps in a conventional dual damascene process; and

[0020] FIGS. 2A through 2D are schematic cross-sectional views showing the progression of steps in a dual damascene process according to the invention.

[0021] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0022] FIGS. 2A through 2D are schematic cross-sectional views showing the progression of steps in a dual damascene process according to the invention. As shown in FIG. 2A, a substrate 200 having a copper line 202 therein is provided. The upper surface 202aof the copper line 202 is exposed. An inter-metal dielectric layer 204 is formed over the substrate 200 and the copper line 202. The inter-metal dielectric layer 204 is formed, for example, by depositing a silicon oxide layer, a silicon nitride layer and a silicon oxide layer in sequence over the substrate 200. The silicon oxide layer and the silicon nitride layer have different etching rates with respect to a particular etchant. In this embodiment, an additional silicon nitride layer may be formed over the substrate 200 prior to the formation of the inter-metal dielectric layer 204. This silicon nitride layer serves as a barrier preventing the diffusion of copper atoms into the inter-metal dielectric layer 204 that would lead to device malfunction or unwanted bridging between metallic interconnects. The inter-metal dielectric layer 204 is preferably planarized.

[0023] As shown in FIG. 2B, a dual damascene opening 211 is formed in the inter-metal dielectric layer 204. The dual damascene opening 211 includes a trench 206 and a contact opening 210, wherein the contact opening 210 is formed under the trench 206.

[0024] Typically, the dual damascene opening 211 is formed by depositing photoresist material over the inter-metal dielectric layer 204 to form a photoresist layer (not shown), and then patterning the photoresist layer. Using the patterned photoresist layer as an etching mask and the silicon nitride layer as an etching stop layer, the inter-metal dielectric layer 204 is etched to form the trench 206. The patterned photoresist layer is removed, and then another patterned photoresist layer 208 is formed over the inter-metal dielectric layer 204. Using the patterned photoresist layer 208 as a mask, the inter-metal dielectric layer 204 is again etched to form the contact opening 210 that exposes the surface 202aof the copper line 202.

[0025] The aforementioned method of forming the dual damascene opening 211 is only one of the preferred embodiments of this invention. Alternatively, the contact opening 210 is formed in the inter-metal dielectric layer 204 before the trench 206 is formed. Moreover, the inter-metal dielectric layer 204 can simply be a silicon oxide layer or a low dielectric constant dielectric layer. If the inter-metal dielectric layer 204 is a silicon oxide or a low dielectric constant layer, depth of the trench can be controlled by a timing model. In addition, the method of forming a damascene opening can also be applied to the invention.

[0026] As shown in FIG. 2C, the photoresist 208 is removed by a low-temperature ashing method. In other words, the photoresist layer 208 is removed by placing the substrate 200 in an ashing chamber, introducing N₂H₂at a rate of 100 to 300 sccm and oxygen O₂at a rate of 200 to 600 sccm, heating the chamber to a temperature of about 30 to 90° C., setting the pressure inside the chamber to about 200 to 600 mT, and applying a source power of about 800 to 1300 Watts (2.54 GHz) and a radio frequency (RF) of about 100 to 400 Watts (13.56 MHz). A plasma mixture of N₂H₂(H₂:4%)/O₂is produced to carry out low-temperature ashing of the photoresist layer 208.

[0027] Although a low-temperature ashing for the removal of the photoresist layer 208 using a plasma mixture of N₂H₂(H₂:4%)/O₂can reduce the amount of oxidation of the copper line 202, a portion of copper on the surface 202astill reacts with oxygen plasma to form loose copper oxide leading to a lowering of electrical conductivity of the metal line and an increase in contact resistance. Therefore, after the photoresist layer 208 is removed, the copper oxide on the surface 202aof the copper line 202 is reduced back to copper by the introduction of gaseous N₂H₂into the chamber. Reduction is carried out by introducing N₂H₂(H2:4%) at a rate of 100 to 300 sccm, heating the chamber to a temperature of about 30 to 90° C., setting the pressure inside the chamber to 200 to 600 mT, and applying a source power of about 800 to 1300 Watts (2.54 GHz) and a radio frequency (RF) of about 100 to 400 Watts (13.56 MHz). Thereafter, electrical conductivity of the metal line can be restored and contact resistance can be reduced.

[0028] Furthermore, after the copper oxide on the copper line 202 is reduced back to copper, a cleaning solvent can be applied to remove any residual particles.

[0029] A conformal barrier layer 212 is formed over the inter-metal dielectric layer 204 and the interior surface of the trench 206 and the contact opening 210. The barrier layer 212 is formed using a material that can prevent copper atoms from diffusing into the inter-metal dielectric layer 204. Consequently, the barrier layer 212 is preferably a tantalum silicide layer formed, for example, by chemical vapor deposition. Because tantalum silicide is very effective in stopping the diffusion of copper atoms, the diffusion of copper atoms into the inter-metal dielectric layer 204 is blocked.

[0030] A conformal copper layer 214 is formed over the barrier layer 212. The copper layer 214 serves as a seeding layer for growing a copper layer. The copper layer 214 can be formed, for example, by physical vapor deposition or chemical vapor deposition. Using the inter-metal dielectric layer 204 as a polishing stop layer, the copper layer 214 and the barrier layer 212 above the inter-metal dielectric layer 204 are removed, forming a structure as shown in FIG. 2C.

[0031] In the invention, since copper oxide on the surface 202aof the copper line 202 is reduced back to copper by the introduction of N₂H₂gas, voids are no longer formed as in the conventional process. In the absence of voids on the copper line 202, a smooth copper layer 214 conformal to the surface profile of the trench 206 and the contact opening 210 is formed. Hence, seeding layer breakage due to subsequent high-temperature annealing can be prevented.

[0032] As shown in FIG. 2D, a copper or a copperless electroplating is carried out using the copper layer 214 as a seeding layer. Copper grows anisotropically over the copper layer 214 to form a second copper layer 216 that fills the trench 206 and the contact opening 210. The second copper layer 216 can be regarded as comprising of a trench line 216band a contact 216a.

[0033] Since the seeding copper layer 214 is deposited over the interior surface of the trench 206 and the contact opening 210, the second copper layer 216 grows only in these areas. In other words, no second copper layer 216 forms over the barrier layer 212 during a copper or copperless electroplating due to the absence of seeding copper thereon.

[0034] In summary, photoresist material is removed by a low-temperature plasma derived from a gaseous mixture N₂H₂(H₂:4%)/O₂so that only small amount of copper oxide is formed. Moreover, the copper oxide is immediately reduced back to copper by the introduction of gaseous N₂H₂(H₂:4%). Hence, voids are not formed on the exposed copper line and the subsequent breakage of seeding layer resulting in a lowering of conductivity and an increase in contact resistance is prevented.

[0035] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.