Shallow trench isolation (STI) module to improve contact etch process window

[0002] The present invention relates generally to semiconductor fabrication and more specifically to fabrication of shallow trench isolation (STI) structures.

[0003] After formation of conventional shallow trench isolation structures (STIs), if the subsequent contact photolithography process is misaligned to the OD (active region) layer, the contact etch may attack the STI profile and induce leakage issues.

[0004] U.S. Pat. No. 6,297,128 B1 to Kim et al. describes an STI trench filled with multiple layers including high density plasma (HDP) oxide.

[0005] U.S. Pat. No. 6,100,160 to Hames describes an STI process using HDP oxide and a nitration step.

[0006] U.S. Pat. No. 5,930,645 to Lyons et al. describes an STI process using HDP oxide.

[0007] U.S. Pat. No. 6,306,725 to Nag et al. describes an STI trench filled with two layers including HDP oxide.

[0008] Accordingly, it is an object of one or more embodiments of the present invention to provide an STI structure that minimizes the deleterious effects of unlanded contact windows.

[0009] Other objects will appear hereinafter.

[0010] It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having an STI opening formed therein is provided. An HDP silicon oxide layer portion is formed within the STI opening, partially filling the STI opening. A planarized HDP silicon-rich-oxide cap layer is formed upon the HDP silicon oxide layer portion, filling the STI opening to form the dual-oxide STI, whereby any unlanded contact window formed through an overlying interlevel dielectric layer exposing a portion of the dual-oxide STI only exposes a portion of the HDP silicon-rich-oxide cap layer.

[0011] The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:

[0012] FIGS. 1 to 8 schematically illustrates a preferred embodiment of the present invention.

[0013] Initial Structure

[0014] As shown in FIG. 1, structure 10 has an overlying pad oxide layer 12 formed thereover formed to a thickness of preferably from about 100 to 150 Å.

[0015] Structure 10 is preferably understood to possibly include a semiconductor wafer or substrate, and is preferably either a silicon wafer or a silicon substrate.

[0016] A hard mask layer 14 is formed over pad oxide layer 12 to a thickness of preferably from about 1000 to 1500 Å. Hard mask layer 14 is preferably formed of silicon nitride (SiN) or silicon oxynitride (SiON) and is more preferably SiN as will be used for illustrative purposes hereafter.

[0017] Shallow Trench Isolation Opening Etch

[0018] As shown in FIG. 2, SiN hard mask layer 14, pad oxide layer 12 and silicon substrate 10 are etched to form shallow trench isolation (STI) opening 16 within silicon substrate 10.

[0019] SiN layer 14, pad oxide layer 12 and silicon substrate 10 may be etched using an overlying patterned mask layer 18 that is preferably comprised of photoresist as shown in FIG. 2.

[0020] Formation of Dual Layer Oxide Layers 20, 22

[0021] As shown in FIG. 3, a high density plasma (HDP) silicon oxide layer 20 is formed within STI opening 16, partially filling STI opening 16, and over etched SiN layer 14′ to a thickness of preferably from about 3300 to 3700 Å and more preferably from about 3400 to 3600 Å and most preferably about 3500 Å.

[0022] Then, an HDP silicon-rich-oxide (SRO) layer 22 is formed over the HDP-oxide layer 20 to a thickness of preferably from about 2800 to 3200 Å and more preferably from about 2900 to 3100 Å and most preferably about 3000 Å. HDP-SRO layer 22 has a refractive index (RI) greater than about 1.5.

[0023] HDP-SRO layer 22 has a silicon concentration of preferably from about 33.3 to 40.0%, more preferably from about 33.4 to 36.0% and most preferably about 35.0%.

[0024] Planarization of HDP-Oxide Layer 20 and HDP-SRO Layer 22 to Form Dual-Oxide STI 25

[0025] As shown in FIG. 4, HDP-SRO layer 22 and HDP-oxide layer 20 are planarized to remove the excess of HDP-SRO layer 22 and HDP-oxide layer 20 from over SiN layer 14 to form a dual-oxide STI 25. Dual-oxide STI 25 includes an underlying HDP-oxide layer portion 20′ with an overlying HDP-SRO cap layer 22′. The underlying HDP-oxide layer portion 20′ has a thickness of preferably from about 3300 to 3700 Å and more preferably from about 3400 to 3600 Å and most preferably about 3500 Å. The overlying HDP-SRO cap layer 22′ has a thickness of preferably from about 2800 to 3200 Å, more preferably from about 2900 to 3100 Å and most preferably about 3000 Å.

[0026] Removal of Etched SiN Layer 14′ and Etched Pad Oxide Layer 12′

[0027] As shown in FIG. 5, etched SiN layer 14′ is removed preferably using an H₃PO₄chemical wet etch process. The structure may be cleaned as necessary. Etched pad oxide layer 12′ is then removed from over silicon substrate 10 preferably using an HF chemical wet etch.

[0028] Growth of Gate Oxide Layer 24

[0029] Well implants (not shown) may then be performed.

[0030] As shown in FIG. 6, a gate oxide layer 24 is then grown over silicon substrate 10 to a thickness of preferably from about 25 to 35 Å and more preferably from about 28 to 32 Å.

[0031] LDD implants (not shown) may then be performed, spacers (not shown) may be formed and source/drain (S/D) implants 23 may then be performed. After the S/D implants 23 are formed, the gate oxide layer 24 may be converted to co-silicide layer 24′.

[0032] A contact etch-stop layer 26 is then formed over gate oxide/co-silicide layer 24 and over HDP-SRO cap layer 22′ of dual-oxide STI 25 to a thickness of preferably from about 200 to 400 Å and more preferably from about 250 to 350 Å. Contact etch-stop layer 26 is preferably formed of silicon oxynitride (SiON).

[0033] Formation of Planarized Interlayer Dielectric (ILD) Layer 28

[0034] As shown in FIG. 7, a planarized interlayer dielectric (ILD) layer 28 is formed over contact etch-stop layer 26 to a thickness of preferably from about 200 to 400 Å and more preferably from about 250 to 350 Å.

[0035] Formation of Contact Window 30

[0036] As shown in FIG. 8, ILD layer 28 is etched to form a contact window 30 which, as shown in FIG. 8, may be unlanded, i.e. exposing a portion 32 of dual-oxide STI 25. It is noted that any such unlanded contact window 30 exposes only a portion 32 of HDP-SRO cap layer 22′.

[0037] In accordance with the present invention, the formation of HDP-SRO cap layer 22′ over HDP-oxide layer 20′ to form dual oxide STI 25 causes the ILD layer 28 etch to contact HDP-SRO cap layer 22′ so that the ILD layer etch selectivity ensures that any unlanded contact windows 30 do not cause large junction leakage issues that would otherwise occur. $O.E.\mathrm{selectivity}=\frac{\mathrm{etch}\mathrm{rate}\mathrm{SiON}}{\mathrm{etch}\mathrm{rate}\mathrm{silicide}}\frac{1000}{10}$ $O.E.\mathrm{selectivity}=\frac{\mathrm{etch}\mathrm{rate}\mathrm{SiON}}{\mathrm{etch}\mathrm{rate}\mathrm{HDP}\text{-}\mathrm{SRO}\mathrm{oxide}}\frac{100}{10}$

[0038] Where “O.E.” is an abbreviation for over etch.

[0039] Advantages of the Present Invention

[0040] The advantages of one or more embodiments of the present invention include improved contact etch process window.

[0041] While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.