US 7,344,996 B1Grant

Helium-based etch process in deposition-etch-deposition gap fill

Issue Date:2008-03-18

•10 Claims

•8 Drawing Sheets

Abstract

Plasma etch processes incorporating helium-based etch chemistries can remove dielectric a semiconductor applications. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate helium as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

Metadata

Assignee

Novellus Systems, Inc.

Inventors

Chi-I Lang
Wenxian Zhu
Ratsamee Limdulpaiboon
Judy H. Huang

Application Information

Application Number:US 11/159,834

Filing Date:2005-06-22

Priority Date:2005-06-22

Art Unit:2823

Classifications

IPC:

H01L21/302H01L21/461

Patent Drawings (8 sheets)

Description

Background of the Invention

[0001] This invention relates to semiconductor device fabrication processes. More specifically, the invention relates to plasma-based chemical vapor deposition and etch processes for forming dielectric layers, particularly in high aspect ratio, narrow width recessed features.

[0002] It is often necessary in semiconductor processing to fill high aspect ratio gaps with insulating material. This is the case for shallow trench isolation, inter-metal dielectric layers, passivation layers, etc. As device geometries shrink and thermal budgets are reduced, void-free filling of narrow width, high aspect ratio (AR) spaces (e.g., AR>3:1) becomes increasingly difficult due to limitations of existing deposition processes.

[0003] The deposition of silicon dioxide (SiO₂) assisted by high-density plasma chemical vapor deposition (HDP CVD)—a directional (bottom-up) CVD process—has become the preferred method for high aspect ratio gap fill. The method deposits more material at the bottom of a high aspect ratio structure than on its sidewalls. It accomplishes this by directing charged dielectric precursor species downward, to the bottom of the gap. Thus, HDP CVD is not an entirely diffusion-based (isotropic) process.

[0004] An etch-enhanced (deposition-etch-deposition) gap fill technique which involves a sequence of deposition, etch and deposition steps using an HDP reactor has been developed to maintain the opening at the top of the gap wide enough for a subsequent deposition(s) to completely fill the gap. Such processes are described, for example, in U.S. Pat. Nos. 6,335,261 and 6,030,881, the disclosures of which are incorporated herein by reference for all purposes. A typical 3-step etch-enhanced process can be described as follows: First step—Deposition 1: a partial deposition of SiO2 thin film is conducted to obtain maximum bottom-up gap fill with the gap remaining unclosed; second step—Etch: in-situ etch back is carried out to remove depositions on the top and sidewall of the trench lines and keep the mouth of the gap open enough for the next deposition step with minimum bottom-up deposition loss; and, third step—Deposition 2: deposition of SiO₂film is carried out to further fill the partially filled gap to completion. In some cases it may be necessary to conduct additional etch and deposition steps to completely fill the gap.

[0005] The etch component of these etch-enhanced gap fill processes typically uses a fluorine-based etchant, such as NF₃, CF₄or C₂F₆, etc., to achieve a fast etch rate. However, the application of those etchants may contaminate the dielectric (e.g., STI) film with foreign atoms, e.g., C, N and F, causing issues in the subsequent integration processes and device degradation.

[0006] Therefore, an etch-enhanced gap fill process that avoided the use of etchants which tend to contaminate the deposited dielectric film would be desirable.

Summary of the Invention

[0007] The present invention addresses this need by providing chemical vapor deposition and biased etch back processes that replace fluorine-based etchants with a helium-based etch chemistry. He is the major or only component of the etch process chemistry and primary or only etchant. The etch process chemistry may also include an inert carrier gas, such as Ar or N₂, and/or an etch process modulator, such as a minor component of H₂or O₂. The process modulating gases may alter the character of the etch, such as by stabilizing the plasma or reducing the etch rate.

[0008] In one aspect, the invention pertains to a method of filling gaps on a semiconductor substrate in accordance with the present invention involves:

[0009] (a) partially filling a gap on a semiconductor substrate with a dielectric using a high density plasma chemical vapor deposition process;

[0010] (b) partially removing dielectric deposited in the gap from the gap opening by an etch back process conducted with a halogen-free etch process chemistry comprising a helium:hydrogen ratio of greater than 1; and

[0011] (c) further filling of the partially filled gap by a high density plasma chemical vapor deposition process.

[0012] The invention provides a high density plasma chemical vapor etch-enhanced gap fill process using hydrogen as an etchant that can effectively fill high aspect ratio (typically at least 3:1, for example 6:1, and up to 10:1 or higher), narrow width (typically sub 0.11 micron, for example 0.1 micron or less) gaps while reducing or eliminating dielectric contamination by etchant chemical species.

[0013] Suitable plasma reactors, e.g., Novellus Speed, with inductively coupled plasma (ICP) sources are available to accomplish both deposition and etch steps of the etch-enhanced gap fill process of the present invention in a single plasma reactor chamber. The deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry.

[0014] The process results in the formation of a dielectric film free of contamination by etchant chemical species.

[0015] These and other features and advantages of the present invention are described below where reference to the drawings is made.

Brief Description of the Drawings

[0016] FIGS. 1A-D depict rough schematic cross-sectional diagrams of an etch-enhanced gap fill process in accordance with the present invention.

[0017] FIG. 2 depicts a SIMS analysis plot showing F content in an HDP film deposited using an He-etch enhanced gap fill process in accordance with one embodiment of the present invention.

[0018] FIG. 3 depicts a plot showing He-based plasma SiO₂removal rate profile vs. distance from wafer center for an He-etch enhanced gap fill process in accordance with one embodiment of the present invention.

[0019] FIG. 4 depicts a plot of normalized etch rate vs. the ratio of applied bias (HFRF) to source (LFRF) power for an He-etch enhanced gap fill process in accordance with one embodiment of the present invention.

[0020] FIG. 5 depicts a plot of normalized etch rate vs. the ratio of H₂to He flow rate in the plasma etch process gas for an He-etch enhanced gap fill process in accordance with one embodiment of the present invention.

[0021] FIG. 6A is a vertical cross-sectional block diagram depicting some components of a plasma processing system suitable for conducting a dep-etch-dep gap fill process in accordance with the present invention.

[0022] FIG. 6B is a horizontal cross-section schematic diagram of the plasma processing system of FIG. 6A.

[0023] FIG. 7 is a process flow diagram depicting a process context of the present invention.

Detailed Description of Specific Embodiments

[0024] Reference will now be made in detail to specific embodiments of the invention. Examples of the specific embodiments are illustrated in the accompanying drawings. While the invention will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to such specific embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.

Introduction

[0025] The present invention addresses this need by providing chemical vapor deposition and biased etch back processes that replace fluorine-based etchants with a helium-based etch chemistry. He is the major or only component of the etch process chemistry and primary or only etchant. A method of filling gaps on a semiconductor substrate in accordance with the present invention involves:

[0026] (a) partially filling a gap on a semiconductor substrate with a dielectric using a high density plasma chemical vapor deposition process;

[0027] (b) partially removing dielectric deposited in the gap from the gap opening by an etch back process conducted with a halogen-free etch process chemistry comprising a helium:hydrogen ratio of greater than 1; and

[0028] (c) further filling of the partially filled gap by a high density plasma chemical vapor deposition process.

[0029] Previously, helium (He) was thought to be an inert gas in etch chemistries. However, it has now been found that helium gas (He) has the ability to serve as sputter source and to be an effective etchant in its own right. With sufficiently high source power, helium gas provides He atoms to be ionized and therefore create high ion energy and high flux density. Ionized He can be used to remove deposited dielectric (e.g., SiO₂) film on all surfaces of a patterned structure (e.g., a semiconductor substrate). The dielectric removal rate is enhanced by a biasing the substrate. Biasing increases sputtering efficiency and the removal rate is increased.

[0030] The invention provides a high density plasma chemical vapor etch-enhanced gap fill process using helium (helium ions) as the etchant that can effectively fill high aspect ratio (typically at least 3:1, for example 6:1, and up to 10:1 or higher), narrow width (typically sub 0.11 micron, for example 0.1 micron or less) gaps while reducing or eliminating dielectric contamination by etchant chemical species.

[0031] Suitable plasma reactors, e.g., Novellus Speed, with inductively coupled plasma (ICP) sources are available to accomplish both deposition and etch steps of the etch-enhanced gap fill process of the present invention in a single plasma reactor chamber. The gap fill process of the present invention may also be accomplished in a plurality of processing chambers. The deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry.

[0032] The process results in the formation of a dielectric film free of contamination by etchant chemical species.

[0033] Etch-Enhanced Gap Fill Process

[0034] FIGS. 1A-D depict rough schematic cross-sectional diagrams of a multi-step, etch-enhanced gap fill process in accordance with the present invention. FIG. 1A depicts a trench (gap) 100 on a semiconductor substrate 102 requiring filling with a dielectric. The gap may be defined by its features, namely its bottom 104, sidewalls 106 and entry region (top) 108. The gap 100 is generally lined with a barrier layer, such as thermal silicon dioxide (SiO₂) and (Si₃N₄) silicon nitride. As such, a thin layer (e.g., 10-200 Å, for example 100 Å) of silicon dioxide is formed on the gap bottom 104 and sidewalls 106 prior to being filled with bulk dielectric. A pad nitride also generally exists at the entry region 108, on the substrate surface surrounding the gap 100.

[0035] The present invention, while applicable to the filling of any gap requiring dielectric fill, is particularly suited to gap fill of high aspect ratio, narrow width gaps. For example, the gap 100 may have a high aspect ratio, for example about 6:1 and a narrow width, for example about 1000 Å.

[0036] In an initial step in a multi-step gap fill process in accordance with the present invention, the gap 100 is partially filled with a dielectric 110 deposited by high density plasma (HDP) chemical vapor deposition (CVD) process, as shown in FIG. 1B. The dielectric may be composed of any suitable material including doped (e.g., with fluorine, phosphine or phosphine and borine) or un-doped SiO₂or Si₃N₄, PSG BPSG or FSG. The present invention may be particularly useful in applications where undoped dielectrics (e.g., SiO₂) are desirable, for example, in some FLASH memory devices. Generally, a high density plasma is any plasma having electron density of at least about 1×10¹²electrons per cubic centimeter. Typically, though not necessarily, high density plasma reactors operate at relatively low pressures, in the range of 100 mTorr or lower, and generally below 30 mTorr.

[0037] The deposition process gas will have a particular composition represented by flow rates of the constituent gases in units of standard cubic centimeter per minute (sccm). The process gas will include a precursor for the deposition layer. If the dielectric is a silicon-containing dielectric, like silicon dioxide (SiO₂), then the process gas will include a silicon-bearing compound. Examples of silicon-containing dielectric precursors are well known in the art and include SiH₄, SiF₄, Si₂H₆, TEOS (tetraethyl orthosilicate), TMCTS (tetramethyl-cyclotetrasiloxane), OMCTS (octamethyl-cyclotetrasiloxane), methyl-silane, dimethyl-silane, 3MS (trimethylsilane), 4MS (tetramethylsilane), TMDSO (tetramethyl-disiloxane), TMDDSO (tetramethyl-diethoxyl-disiloxane), DMDMS (dimethyl-dimethoxyl-silane) and mixtures thereof. Where the purity of the dielectric is an issue, inorganic, non-fluorine-containing precursors for SiO₂, such as SiH₄and Si₂H₆, are preferred. During deposition, the process decomposes the silicon-containing reactant to form a silicon-containing gas and plasma phase species, which can react on the surface of the substrate.

[0038] The process gas will also generally include a carrier gas. The carrier gas may be an inert gas, such as He, Ar and/or other noble gases. Or the carrier gas may be or include elemental or molecular hydrogen.

[0039] Oxygen to form the silicon dioxide or other dielectric material may be provided by the silicon-containing precursor itself or from another process gas such as oxygen (O₂), nitric oxide (NO), and/or nitrous oxide (N₂O). Again, where the purity of the dielectric is an issue, oxygen (O₂) is the preferred oxygen source.

[0040] Typical flow rate ranges for deposition process gases of the present invention are listed below.

[0041]


	Gas	Flow Rate (sccm)

	SiH₄	10-300
	O₂	20-1000
	He	0-500
	H₂	0-2000

[0042] Generally, other oxygen and silicon-containing compounds can be substituted for those listed in this table. Depending upon the atom counts in the precursor gases, the flow rate ranges may have to be changed. While there are no precise rules for modifying flow rates as a function of molecular structure, generally the flow rate of the silicon-containing precursor may be reduced by a factor corresponding to the number of silicon atoms in the molecule. So, for example, if the molecule contains two silicon atoms, one may expect to reduce the flow rate of the silicon-containing precursor to a level of between about 5 and 150 sccm.

[0043] Reactor pressure is held at a value necessary to sustain the high-density plasma. Preferably the process vessel is maintained at a pressure of at most about 100 mTorr. In some cases, the process chamber pressure is maintained below 1 mTorr. For many applications, however, the pressure is maintained between about 1 and 100 mTorr; most preferably between about 1 and 30 mTorr.

[0044] The temperature within the process vessel should be maintained sufficiently high to ensure that the dielectric deposition reaction proceeds efficiently. Hence, the temperature preferably resides at values between about 30 and 1000° C. This temperature will vary depending upon the types of precursors employed in the reaction. Further, the temperature may be limited by process constraints, such as thermal budget limitations that preclude temperatures above 700-750° C. Such constraints become increasingly common with advanced technologies and corresponding smaller feature sizes. For such applications, the process temperature is preferably maintained between about 30 and 750° C. In particularly preferred embodiments, the substrate temperature is maintained between about 300 and 700° C., even more preferably between about 350 and 650° C.

[0045] As indicated, to control the substrate temperature, the reactor may supply a heat transfer gas between a surface of the substrate and a surface of the substrate holder on which the substrate is supported during film deposition. The heat transfer gas may include at least one of helium and argon. The back-side helium pressure is set by the temperature requirements of the process (a typical range being between 0-15 Torr).

[0046] For some applications, it may be desirable to preheat the wafer to a pre-specified relatively low temperature and then gradually raise the temperature. This allows for isothermal operation. The goal is to start the deposition and then maintain the wafer temperature within a narrow range during the entire deposition process.

[0047] The low frequency power applied to the induction coil typically varies from 1 kW to 20 kW, and the high frequency power (for biasing the wafer) typically varies from 0.5 kW to 10 kW depending on the substrate size (e.g., 200 or 300 mm diameter) and the requirements of the specific process being used.

[0048] The power source applied to the induction coil and substrate electrode is typically a radio frequency source. Applying radio frequency bias to the substrate involves supporting the substrate on a substrate holder having an electrode supplying a radio frequency bias to the substrate. For many embodiments, the radio frequency bias applied to the substrate is at the frequency range of between about 100 kHz and 27 MHz. The power source applied to the induction coil typically has a frequency range between about 300 kHz and 1 MHz. In a preferred embodiment, the deposition process chemistry is as follows:

[0049]


	Gas	Flow Rate (sccm)


	SiH₄	80
	He	200
	H₂	100
	O₂	110

The low frequency coil is powered at 3000 W and the high frequency substrate electrode is powered at 800 W. Further details of suitable HDP CVD deposition process gas chemistries are provided below.

[0050] The HDP CVD deposition results in beneficial filling of the trench from the bottom 104 up. However, there is still some problematic top and sidewall deposition resulting in narrowing of the entry region 108 of the gap 100 by the formation of an overhang 109 and the formation of a dielectric peak (the so-called “top-hat” feature) 109 on either side of the gap opening. This results from the non-directional deposition reactions of neutral species in the plasma reactor and from sputtering/redeposition processes. The overhang 109 and top-hat 111 features exacerbate the difficulties of filling the high aspect ratio gap.

[0051] To address these problems, following this initial deposition stage of the process, the detrimental overhang 109 is removed and the top-hat 111 substantially reduced in an etch back stage of the process to facilitate further void free filling of the trench in a subsequent deposition stage. In a preferred embodiment, the etch back process is carried out in the same reactor chamber as the deposition.

[0052] He as Etchant

[0053] According to the present invention, helium is used as an etching agent to replace conventional F-containing etchants in a biased etch back stage of the gap fill process. He is introduced into the deposition chamber and ionized by source plasma power in the chamber. The ionized helium acts as an etchant for deposited dielectric film on all exposed surfaces of the substrate 102 on which the gap 100 is being filled. In accordance with the present invention, He is the major or only component of the etch process chemistry and primary or only etchant. The etch process chemistry may also include an inert carrier gas, such as Ar or N₂, and/or an etch process modulator, such as a minor component of H₂or O₂, but no other etchant (e.g., F-based etchant) is used.

[0054] In the biased etch back stage, the wafer is biased and exposed to a plasma, for example, a radio frequency based inductively coupled plasma, containing He-based etchant chemistry. As shown in FIG. 1C, there is partial removal of deposited dielectric film, primarily in the overhang and top-hat areas at the top of the gap, by the He etch. The efficiency of the etch may be increased by biasing the substrate and the etch rate increases with the bias power. This He-based etching leads to efficient removal of unnecessary deposition at and adjacent to the gap opening in order to maintain the gap open enough for a complete gap fill in a subsequent HDP CVD deposition stage(s) of the multi-step process.

[0055] The chuck may be biased with a power range of about 1000 to 7000 W. Biasing the chuck imparts some directionality to the etch plasma towards the wafer on the biased chuck. Thus, while the etch process of the present invention has a dominant isotropic character, it does favor the biased wafer/chuck. Increase in bias power enhances etch rate, but does not significantly alter the isotropic characteristic of He etch. This is observed by the conservation of bottom-up deposition even with high bias power He etch processing. This process advantage shows that He ions are small enough to cause negligible bombardment/sputtering of the dielectric material that is normal to the incoming ions, while efficient in removing the “top-hat” area that is about 45-60° to the incoming ions. The biased etch process is referred to herein as substantially isotropic.

[0056] He is the major or only component of the etch process chemistry and primary or only etchant. The etch process chemistry may also include an inert carrier gas, such as Ar or N₂, and/or an etch process modulator, such as a minor component of H₂or O₂. The process modulating gases may alter the character of the etch, such as by stabilizing the plasma or reducing the etch rate. O₂should only be used to the extent necessary to achieve plasma stability since its addition enhances the redeposition effect.

[0057] In some specific embodiments, a He-only etch chemistry is used. In other embodiments, a He/H₂etch process chemistry is used. When hydrogen (H₂) is present as an etch process gas, the etch process chemistry has a helium:hydrogen ratio of greater than 1. In many cases, the helium:hydrogen ratio will be greater than 2 or greater than 3.

[0058] Typical process parameter ranges for a suitable inductively coupled He-based etch chemistry plasma process gas mixture in accordance with one embodiment of the present invention, and associated reactor conditions, are listed as follows:

[0059]


	Wafer temp	250-700
	(° C.)
	He (sccm)	500-1500
	H₂(sccm)	0-500
	O₂(sccm)	0-500
	Pressure	0.2-10
	(mTorr)
	Bias (HF RF)	1000-7000
	Power (W)
	Source (LF)	4000-10,000
	Power (W)

[0060] When a 200 mm wafer is being etched, the source power is preferably at least about 4000 KW. When a 300 mm wafer is being etched, the source power is preferably at least about 6000 KW.

[0061] An example of suitable etch plasma process chemistry and reactor conditions for a 200 mm wafer is as follows:

[0062]


	Wafer temp	600
	(° C.)
	He (sccm)	1000
	H₂(sccm)	0
	Pressure (mTorr)	3
	Bias (HF RF)	3000
	Power (W)
	Source (LF)	7000
	Power (W)

[0063] An example of suitable etch plasma process chemistry and reactor conditions for a 300 mm wafer is as follows:

[0064]


	Wafer temp	600
	(° C.)
	He (sccm)	1500
	H₂(sccm)	0
	Pressure (mTorr)	4
	Bias (HF RF)	5000
	Power (W)
	Source (LF)	9500
	Power (W)

[0065] The conditions are preferably set so that the etch is selective for the HDP CVD deposited dielectric (e.g., SiO₂) relative to the silicon nitride barrier layer lining the trench and the hard mask (the pad nitride on the substrate surface surrounding the gap opening) so that neither is exposed and clipped by the etch. Adjustment of the process selectivity is within the skill in the art given the process parameters and description provided herein.

[0066] Following the He-based etch back stage, an additional HDP CVD deposition is performed in order to further fill the gap 100 with dielectric 110, as shown in FIG. 1D. The etch back and deposition steps depicted in FIGS. 1C and 1D may be repeated, as necessary, until the gap is filled. For a gap with about a 6:1 aspect ratio and about a 1000 Å width, three to five, for example four, iterations of the etch back and deposition steps are typical to obtain void free filling of the gap.

[0067] Without limiting the invention described and claimed herein, some beneficial effects of the use of helium as an etchant in accordance with the present invention are illustrated with reference to FIGS. 2-5.

[0068] FIG. 2 provides a plot of the secondary ion mass spectroscopy (SIMS) analysis result of an HDP film formed using an He-based etch-enhanced gap fill process in accordance with the invention showing that there is only trace amount of F (0.001%) contained in the dielectric film SiO₂. This illustrates that the etch may be accomplished without any substantial contamination of the deposited dielectric as may be the case when fluorine based etchants are used.

[0069] FIG. 3 illustrates the within wafer (WIW) uniformity of the He-based etch technique of the present invention. The etch rate was measured at forty nine points across a 200 mm wafer from the center of the wafer (0) to the edge of the wafer (3) for a process conducted using an He only etch chemistry at source/bias ratio of 4.5. The measurement points were averaged and plotted in FIG. 3 As can be seen in the plot, the WIW uniformity of the process is very high. The helium-based plasma etch helps reduce or avoid clipping at the wafer center when the desired removal amount on the edge is reached on a structure wafer.

[0070] FIGS. 4 and 5 illustrate etch rate changes with adjustments to the etch conditions. From FIG. 4, it can be seen that the etch rate increases substantially linearly with increasing bias power (increased LF/HF ratio). From FIG. 5, it can be seen that the addition of hydrogen (H₂) to the etch process gas mixture modulates the process, slowing the etch rate. While the invention is not limited to any particular theory of operation, it is believed that H₂provides a chemical etch component and a passivating component; the chemical etch capability of H₂ions leads to more isotropic removal of deposited film, while the passivating capability of H ions to any dangling bonds of the deposited surface leads to minimization of redeposition. These effects can be used to adjust the etch performance as desired by a particular user for a particular application.

[0071] Thus, this invention provides an etch-enhanced HDP gap fill (e.g., STI) process with an in situ high throughput He-based etch step without dielectric contamination.

[0072] Implementation: Plasma Processing Reactor

[0073] Various plasma reactor designs are suitable for use with this invention. The particular design is not critical to this invention. It merely needs to support HDP CVD dielectric layer formation and etch back on appropriate substrates. Examples of suitable reactors include the Novellus SPEED reactor, available from Novellus Systems, Inc. of San Jose, Calif., and the Ultima reactor, available from Applied Materials, Inc. of Santa Clara, Calif.

[0074] The principal components of most suitable reactors include a reaction chamber, a process gas delivery system, a support for the substrate, one or more electrodes or radio frequency power source coupled to an induction coil to generate an inductively coupled plasma, and a bias source for the substrate. A temperature control system is typically used to heat the substrate. Suitable plasma processing reactors and described, for example, in U.S. Pat. Nos. 5,346,578, 5,405,480 and 5,605,599, the disclosures of which are incorporated by reference herein in their entirety and for all purposes.

[0075] FIG. 6A is a vertical cross-section block diagram depicting some components of a suitable plasma processing reactor suitable for conducting an H₂etch-enhanced gap fill process in accordance with the present invention on semiconductor wafers. As shown, the reactor 601 includes a process chamber 603 which encloses other components of the reactor and serves to contain the plasma generated by the radio frequency power source coupled to the induction coil 605 which surrounds the chamber on or embedded in the chamber walls. In one example, the process chamber walls are made from aluminum, aluminum oxide, and/or other suitable material. The coil 605 is powered by a “low frequency” radio frequency (RF) source 606. The power and frequency supplied by source 606 is sufficient to generate high-density plasma from the process gas.

[0076] Within the reactor, a wafer pedestal 607 supports a substrate 609. The pedestal typically includes a chuck 608 to hold the substrate in place during the deposition reaction. The chuck may be an electrostatic chuck, a mechanical chuck or various other types of chuck as are available for use in the industry and/or research.

[0077] A heat transfer subsystem including a line 611 for supplying a heat transfer gas controls the temperature of substrate 609. In some embodiments, the heat transfer fluid comprises at least one of helium and argon gas. The heat transfer fluid is supplied to a space 613 between the surface of the substrate and a surface of the chuck.

[0078] A “high frequency” RF source 615 serves to electrically bias substrate 609 and draw charged precursor species onto the substrate for the deposition or etch reactions. Electrical energy from source 615 is coupled to substrate 609 via an electrode or capacitive coupling, for example. Note that the bias applied to the substrate need not be an RF bias. Other frequencies and DC bias may be used as well. In a specific embodiment, source 615 supplies a radio frequency bias to the substrate with a power ranges from 0.5 kW to 10 kW.

[0079] The process gases are introduced via one or more chamber inlets 617. The gases may be premixed or not. A source of hydrogen gas provides hydrogen for the deposition and etch process gas. Other sources of dielectric precursor gases and carrier gases are also provided. Preferably, the process gas is introduced through a gas supply inlet mechanism including orifices. The gas or gas mixture may be introduced from a primary gas ring, which may or may not direct the gas toward the substrate surface. In this embodiment, a ring inlet(s) 618 is connected to the primary gas ring 619 to supply gas or gas mixture into the chamber via the chamber inlets 617. This arrangement is further illustrated in the horizontal cross-section of FIG. 6B which depicts a ring inlet and eight chamber inlets for process gas. Note that inlets, gas rings or other mechanisms for supplying process gas to the reactor process chamber are not critical to this invention. The sonic front caused by the gas entering the chamber will itself cause the gas to rapidly disperse in all directions—including toward the substrate.

[0080] The process gas exits the chamber 603 via an outlet or outlets 620. A vacuum pump (e.g., a turbomolecular pump) or pumps 622 typically draws the gas out and maintains a suitably low pressure within the reactor.

[0081] As noted above, the gap fill process of the present invention is preferably accomplished in a single reactor process chamber, but it may also be accomplished in a plurality of processing chambers. When more than one processing chamber is used, a pressure controlled transfer module should be used to transfer the wafers from one chamber to another. Such transfer modules and procedures are known to those of skill in the art.

[0082] Process Parameters

[0083] FIG. 7 is a process flow diagram (700) depicting a process context of the present invention. Reference is made to the system depicted in FIG. 6A throughout the description of this process flow as a sample context for implementation of the invention. A substrate requiring gap filling, such as a semiconductor wafer, is situated in an HDP CVD reactor (701).

[0084] A deposition process begins with an electrical subsystem applying electrical energy of appropriate power and frequency to one or more electrodes of a process chamber of the reactor. The power and frequency are chosen to generate a high density plasma in the chamber, given the process gas concentration, pressure, and other process parameters. Providing the substrate to the reactor may involve clamping the substrate to a pedestal or other support in the chamber. For this purpose, an electrostatic or mechanical chuck may be employed.

[0085] After the wafer is appropriately situated in the chamber, a gap on the substrate is partially filled by HDP CVD deposition of dielectric (703). The process adjusts the substrate temperature to a level promoting the deposition of the dielectric layer. Typically, this temperature is between about 30-1000° C. (more preferably about 300 to 680° C., for example 450-550° C.). The temperature control mechanism may gradually raise the temperature during deposition or it may preheat the wafer to first drive out certain interfering species. During deposition, the temperature may be maintained by supplying a heat transfer gas between a back surface of the substrate and a surface of the substrate holder on which the substrate is supported during the film growth operation.

[0086] The reactor system introduces a process gas to the reaction chamber via an inlet. The process gas includes dielectric precursor species such as high vapor pressure silicon-containing compounds. Molecular oxygen or another oxygenated compound will often be present. A carrier gas is also generally present. The carrier gas may be an inert carrier gas such as helium. However, in high aspect ratio gap fill applications the carrier gas preferably is or includes molecular or elemental hydrogen which inhibits precursor dissociation and promotes bottom-up gap fill. All the process gas components are introduced at specified flow rates.

[0087] An electrical subsystem applies a bias to the substrate, to thereby direct charged precursor species from the plasma onto the substrate and grow a dielectric film. Note that the substrate itself serves as an electrode here. Its bias accelerates charged species to it. Typically, the substrate electrode is powered by a high frequency RF bias and the induction coil is powered by a lower frequency RF source.

[0088] Dielectric is deposited in the gap or gaps on the substrate to a desired thickness, generally at the point where the overhang that forms at the gap entry point prevents further effective filling of the gap (703).

[0089] After finishing the deposition step, the flow of deposition chemistry is turned off and the helium-based etchant chemistry is introduced to the reaction chamber via an inlet to begin the plasma etch (705). The He etchant gas should dissociate at a controlled rate consistent with isotropic etching. Molecular hydrogen or oxygen may also be present in the etchant chemistry, but should be minimized. All the process gas components are introduced at specified flow rates within the parameters noted above. In a specific embodiment, the isotropic etch is conducted using an inductively coupled plasma source in the reactor. The RF bias and source powers in the reactor are adjusted to between about 1000 and 7000 W and 4000 and 10,000 W, respectively. It should be noted that the inductively coupled plasma (ICP) etch may alternatively be accomplished by a downstream microwave plasma etch. The etch back process preferentially removes dielectric overhang and top-hat features at the gap opening thereby decreasing the gap's aspect ratio and facilitating further filling in subsequent deposition processing.

[0090] Following the etch, etch process chemistry flows are turned off and further deposition process for filling the remaining gap is performed (707) by introducing the deposition process gases into the reactor. The etch back and deposition process (705-707) is then repeated until the gap is filled (709). For a gap with about a 6:1 aspect ratio and about a 1000 Å width, three to five, for example four, iterations of the etch back and deposition steps are typical to obtain void free filling of the gap.

[0091] Substrates and Dielectric Materials

[0092] The above-described processes and apparatuses may deposit dielectric on any type of substrate that requires thin dielectric layers. Often, the substrate will be a semiconductor wafer having gaps in need of dielectric filling. The invention is not, however, limited to such applications. It may be employed in a myriad of other fabrication processes such as for fabricating flat panel displays.

[0093] As indicated above, this invention finds particular value in integrated circuit fabrication. The gap filling processes are performed on partially fabricated integrated circuits employing semiconductor substrates. In specific examples, the gap filling processes of this invention are employed to form shallow trench isolation (STI), pre-metal dielectric (PMD), inter-metal layer dielectric (ILD) layers, passivation layers, etc.

[0094] As indicated, the invention can effectively fill gaps having widths of 0.15 microns or less, for example 0.1 micron or less, and aspect ratios of 3:1 or greater, for example 5:1, 6:1, or even 10:1 or greater. More aggressive structures having, e.g., greater aspect ratios and smaller widths may also be used. In one example the gap width is 0.15 micrometers or less, e.g., between 0.11 micrometer and 0.08 micrometer.

[0095] The dielectrics employed to fill those gaps will often be a silicon oxide such as silicon dioxide, silicon oxynitride, silicon oxyfluoride, and doped variants of each of these. Therefore, the scope of the invention includes at least phosphorus-doped, boron/phosphorus-doped oxides and fluorine/phosphorus-doped oxides. As indicated, the dielectric may also be a phosphorus- and boron-doped silicon oxide glass (BPSG).

Alternative Embodiments

[0096] While the invention is primarily described herein with reference to an etch-enhanced multi-step gap fill process, it should be understood that the He-based etch may also be conducted independent of the other steps of the gap fill process. For example, the He-based etch may be applied to etch a silicon-based dielectric in any appropriate context.

Conclusion

[0097] While this invention has been described in terms of a few preferred embodiments, it should not be limited to the specifics presented above. Many variations on the above-described preferred embodiments, may be employed. Therefore, the invention should be broadly interpreted with reference to the following claims.

Claims

What is claimed is:

1. A method of filling gaps on a semiconductor substrate, the method comprising:

(a) partially filling a gap on a semiconductor substrate with a dielectric using a high density plasma chemical vapor deposition process;

(b) partially removing dielectric deposited in the gap from the gap opening by a net etch back process conducted with a halogen-free etch process chemistry comprising helium as the major component of the etch process chemistry, wherein the etch chemistry further comprises hydrogen at a helium:hydrogen ratio of greater than 1; and

2. The method of claim 1, wherein the etch process chemistry comprises a helium:hydrogen ratio of greater than 2.

3. The method of claim 1, wherein the etch process chemistry comprises a helium:hydrogen ratio of greater than 3.

4. The method of claim 1, wherein the deposited dielectric is silicon dioxide (Sio₂).

5. The method of claim 1, wherein the substrate is biased during the etch back process and the etch rate is determined by the substrate bias power.

6. The method of claim 5, wherein the etch rate increases with increasing substrate bias power.

7. The method of claim 1, wherein (b) and (c) are repeated until the gap is filled.

8. The method of claim 1, wherein the etch process chemistry further comprises an inert gas selected from the group consisting of Ar and N₂.

9. The method of claim 1, wherein the deposition and etch steps are conducted in a single plasma reactor process chamber.

10. The method of claim 9, wherein the plasma generated for deposition and etch is a radio frequency based inductively coupled plasma.

Patent Citations (112)

Patent	Date	Inventor	Cited By
US4361461(A)	1982-11-01	Chang	Applicant
US5129958(A)	1992-07-01	Nagashima et al.	Applicant
US5227191(A)	1993-07-01	Nagashima	Applicant
US5246885(A)	1993-09-01	Braren et al.	Applicant
US5252178(A)	1993-10-01	Moslehi	Applicant
US5270264(A)	1993-12-01	Andideh et al.	Applicant
US5282925(A)	1994-02-01	Jeng et al.	Applicant
US5342801(A)	1994-08-01	Perry et al.	Applicant
US5385857(A)	1995-01-01	Solo de Zaldivar	Applicant
US5494854(A)	1996-02-01	Jain	Applicant
US5516729(A)	1996-05-01	Dawson et al.	Applicant
US5532516(A)	1996-07-01	Pasch et al.	Applicant
US5621241(A)	1997-04-01	Jain	Applicant
US5622894(A)	1997-04-01	Jang et al.	Applicant
US5636320(A)	1997-06-01	Yu et al.	Applicant
US5641545(A)	1997-06-01	Sandhu	Applicant
US5702982(A)	1997-12-01	Lee et al.	Applicant
US5705419(A)	1998-01-01	Perry et al.	Applicant
US5711998(A)	1998-01-01	Shufflebotham	Applicant
US5789818(A)	1998-08-01	Havermann	Applicant
US5834068(A)	1998-11-01	Chern et al.	Applicant
US5851344(A)	1998-12-01	Xu et al.	Applicant
US5858876(A)	1999-01-01	Chew	Applicant
US5869902(A)	1999-02-01	Lee et al.	Applicant
US5872058(A)	1999-02-01	Van Cleemput et al.	Applicant
US5897370(A)	1999-04-01	Joshi et al.	Applicant
US5910020(A)	1999-06-01	Yamada	Applicant
US5911133(A)	1999-06-01	Soble	Applicant
US5913140(A)	1999-06-01	Roche et al.	Applicant
US5920792(A)	1999-07-01	Lin	Applicant
US5937323(A)	1999-08-01	Orczyk et al.	Applicant
US5953635(A)	1999-09-01	Andideh	Applicant
US5962923(A)	1999-10-01	Xu et al.	Applicant
US5963840(A)	1999-10-01	Xia et al.	Applicant
US5968610(A)	1999-10-01	Liu et al.	Applicant
US5972192(A)	1999-10-01	Dubin et al.	Applicant
US6027663(A)	2000-02-01	Martin et al.	Applicant
US6030881(A)	2000-02-01	Papasouliotis et al.	Applicant
US6037018(A)	2000-03-01	Jang et al.	Applicant
US6077451(A)	2000-06-01	Takenaka et al.	Applicant
US6077574(A)	2000-06-01	Usami	Applicant
US6100205(A)	2000-08-01	Liu et al.	Applicant
US6106678(A)	2000-08-01	Shufflebotham et al.	Applicant
US6124211(A)	2000-09-01	Butterbaugh et al.	Applicant
US6136703(A)	2000-10-01	Vaartstra	Applicant
US6149779(A)	2000-11-01	Van Cleemput	Applicant
US6184158(B1)	2001-02-01	Shufflebotham et al.	Applicant
US6200412(B1)	2001-03-01	Kilgore et al.	Applicant
US6211065(B1)	2001-04-01	Xi et al.	Applicant
US6232196(B1)	2001-05-01	Raaijmakers et al.	Applicant
US6265269(B1)	2001-07-01	Chen et al.	Applicant
US6277764(B1)	2001-08-01	Shin et al.	Applicant
US6331494(B1)	2001-12-01	Olson et al.	Applicant
US6335261(B1)	2002-01-01	Natzle et al.	Applicant
US6395150(B1)	2002-05-01	Van Cleemput et al.	Applicant
US6400023(B2)	2002-06-01	Huang	Applicant
US6410446(B1)	2002-06-01	Tsai et al.	Applicant
US6451705(B1)	2002-09-01	Trapp et al.	Applicant
US6479361(B1)	2002-11-01	Park	Applicant
US6479396(B1)	2002-11-01	Xu et al.	Applicant
US6486081(B1)	2002-11-01	Ishikawa et al.	Applicant
US6500728(B1)	2002-12-01	Wang	Applicant
US6531377(B2)	2003-03-01	Knorr et al.	Applicant
US6566229(B2)	2003-05-01	Hong et al.	Applicant
US6569777(B1)	2003-05-01	Hsu et al.	Applicant
US6596653(B2)	2003-07-01	Tan et al.	Applicant
US6596654(B1)	2003-07-01	Bayman et al.	Applicant
US6599829(B2)	2003-07-01	Smith et al.	Applicant
US6617207(B1)	2003-09-01	Kiryu et al.	Applicant
US6642105(B2)	2003-11-01	Kim et al.	Applicant
US6706541(B1)	2004-03-01	Toprac et al.	Applicant
US6737334(B2)	2004-05-01	Ho et al.	Applicant
US6787483(B1)	2004-09-01	Bayman et al.	Applicant
US6794290(B1)	2004-09-01	Papasouliotis et al.	Applicant
US6808748(B2)	2004-10-01	Kapoor et al.	Applicant
US6812043(B2)	2004-11-01	Bao et al.	Applicant
US6821905(B2)	2004-11-01	Pan et al.	Applicant
US6846391(B1)	2005-01-01	Papasouliotis et al.	Applicant
US6846745(B1)	2005-01-01	Papasouliotis et al.	Applicant
US6852639(B2)	2005-02-01	Rudolph et al.	Applicant
US6867086(B1)	2005-03-01	Chen et al.	Examiner
US6958112(B2)	2005-10-01	Karim et al.	Examiner
US7001854(B1)	2006-02-01	Papasouliotis et al.	Applicant
US7067440(B1)	2006-06-01	Bayman et al.	Applicant
US7078312(B1)	2006-07-01	Sutanto et al.	Applicant
US7122485(B1)	2006-10-01	Papasouliotis et al.	Applicant
US7135409(B2)	2006-11-01	Komagata	Examiner
US7148155(B1)	2006-12-01	Tarafdar et al.	Applicant
US7163896(B1)	2007-01-01	Zhu et al.	Examiner
US2001/0019903(A1)	2001-09-01	Shufflebotham et al.	Applicant
US2001/0044203(A1)	2001-11-01	Huang et al.	Applicant
US2002/0052119(A1)	2002-05-01	Van Cleemput	Applicant
US2002/0084257(A1)	2002-07-01	Bjorkman et al.	Applicant
US2002/0179570(A1)	2002-12-01	Mathad et al.	Applicant
US2002/0187657(A1)	2002-12-01	Morozumi	Applicant
US2003/0003244(A1)	2003-01-01	Rossman	Applicant
US2003/0003682(A1)	2003-01-01	Moll et al.	Applicant
US2003/0087506(A1)	2003-05-01	Kirchhoff	Applicant
US2003/0165632(A1)	2003-09-01	Lin et al.	Applicant
US2003/0203652(A1)	2003-10-01	Bao et al.	Applicant
US2003/0207580(A1)	2003-11-01	Li et al.	Applicant
US2004/0020894(A1)	2004-02-01	Williams et al.	Applicant
US2004/0058549(A1)	2004-03-01	Ho et al.	Applicant
US2004/0082181(A1)	2004-04-01	Doan et al.	Applicant
US2004/0110390(A1)	2004-06-01	Takagi et al.	Applicant
US2004/0241342(A1)	2004-12-01	Karim et al.	Applicant
US2005/0074946(A1)	2005-04-01	Chu et al.	Examiner
US2005/0130411(A1)	2005-06-01	Bao et al.	Applicant
US2005/0136576(A1)	2005-06-01	Ishihara et al.	Applicant
US2005/0136686(A1)	2005-06-01	Kim et al.	Applicant
US2005/0250346(A1)	2005-11-01	Schmitt	Applicant
JP2003-031649	2003-01-01		Applicant

Non-Patent Literature (14)

Papasouliotis et al., “Hydrogen-Based Phosphosilicate Glass Process for Gap Fill of High Aspect Ratio Structures”, Novellus Systems, Inc., filed Oct. 11, 2002, U.S. Appl. No. 10/271,333, pp. 1-28.Applicant
Guari et al., “Method of Preventing Structures Erosion During Multi-Step Gap Fill”, Novellus Systems, Inc., filed Dec. 4, 2003, U.S. Appl. No. 10/728,569, pp. 1-29.Applicant
Bayman et al., “Gap Fill For High Aspect Ratio Structures”, Novellus Systems, Inc., filed Jul. 13, 2004, U.S. Appl. No. 10/890,655, pp. 1-24.Applicant
Sutanto et al., “Method For Controlling Etch Process Repeatability”, Novellus Systems, Inc., filed Sep. 2, 2003, U.S. Appl. No. 10/654,113, pp. 1-31.Applicant
Bayman et al., “Process Modulation to Prevent Structure Erosion During Gap Fill”, Novellus Systems, Inc., filed Sep. 7, 2004, U.S. Appl. No. 10/935,909, pp. 1-30.Applicant
Papasouliotis et al., “Dynamic Modification of Gap-Fill Process Characteristics”, Novellus Systems, Inc., filed Sep. 21, 2004, U.S. Appl. No. 10/947,424, pp. 1-25.Applicant
Hook et al., “The Effects of Fluorine on Parametrics and Reliability in a 0.18-μm 3.5/6.8 nm Dual Gate Oxide CMOS Technology”, IEEE Transactions on Electron Devices, vol. 48, No. 7., Jul. 2001, pp. 1346-1353.Applicant
Shanker et al., “Hydrogen Treatment Enhanced Gap Fill”, Novellus Systems, Inc., filed Mar. 16, 2005, U.S. Appl. No. 11/082,369, pp. 1-33.Applicant
Papasoulitotis et al., “Deposition Profile Modification Through Process Chemistry”, Novellus Systems, Inc., filed Dec. 9, 2002, U.S. Appl. No. 10/316,987, pp. 1-35.Applicant
Zhu et al., “Biased H2 Etch Process In Deposition-Etch-Deeposition Gap Fill”, Novellus Systems, Inc., filed Dec. 10, 2003, U.S. Appl. No. 10/733,858, pp. 1-28.Applicant
Lang et al., “Strain Engineering—HDP Thin Film With Tensile Stress For FEOL and Other Applications”, Novellus Systems, Inc., filed Nov. 17, 2004, U.S. Appl. No. 10/991,890, pp. 1-35.Applicant
Lang et al., “Using Water (H20) To Replace Oxygen (02) In A Silicon Dioxide (Si02) Thin Film Deposition Process for HDP STI Technology”, Novellus Systems, Inc., filed Nov. 9, 2005, U.S. Appl. No. 11/272,487, pp. 1-25.Applicant
Nguyen et al., “Halogen-Free Noble Gas Assisted H2 Plasma Etch Process in Deposition-Etch-Deposition Gap Fill”, Novellus Systems, Inc., filed Mar. 1, 2006, U.S. Appl. No. 11/366,220.Applicant
Yu et al., “Stress Profile Modulation in STI Gap Fill,” Novellus Systems, Inc., U.S. Appl. No. 11/471,958, filed Jun. 20, 2006, pp. 1-27.Applicant