Method of pitch dimension shrinkage

[0001] The present invention relates to integrated circuit fabrication methods, and more particularly to a method of fabricating integrated circuit with a reduced pitch.

[0002] Integrated circuits are commonly used to make a wide variety of electronic devices, such as memory chips. There is a strong desire to reduce the size of integrated circuits, so as to increase the density of the individual components and consequently enhance the functionality of an integrated circuit. The minimum pitch on an integrated circuit (the minimum distance between the same points of two adjacent structures of the same type, e.g., two adjacent gate conductors) is often used as a representative measure of the circuit's density. The feature width is sometimes referred to herein as F, and the width of the space between features is sometimes referred to herein as S.

[0003] Increases in circuit density often are limited by the resolution of the available photolithographic equipment. The minimum size of features and spaces that a given piece of photolithographic equipment can produce is related to its resolution capability. If one tries to define features in a photoresist which are smaller than the machine's minimum feature size, then the photoresist regions exposed to radiation may fail to correspond to the mask plate pattern, resulting in the photoresist features being skewed.

[0004] The sum of minimum feature width and minimum space width producible with a given piece of photolithographic equipment is the minimum pitch that the piece of equipment can produce. Since for practical purposes, the minimum feature width can be considered to be approximately equal to the minimum space width, the minimum pitch that can be produced with a given piece of photolithographic equipment is approximately equal to double the minimum feature width that it can produce. Using contemporary photolithography techniques, one line (feature) and one space may be defined for a given minimum pitch.

[0005] Some attempts have been made to try to reduce the pitch of an integrated circuit device below that of the minimum pitch produced lithographically, but these methods are difficult to control and show varying results.

[0006] In view of the drawbacks of the prior methods, it is necessary to provide a method that can reduce the pitch in a device below that producible by the lithographic process.

[0007] According to an aspect of the invention, roughly described, a method of manufacturing an integrated circuit includes several steps. A patterned first layer is provided, patterned with features having top surfaces and sidewalls. Typically but not necessarily, the patterning in the first layer is formed lithographically. The patterned first layer is formed over a second layer which is formed over a substrate. In a conversion process, first layer material is consumed at the feature sidewalls (and optionally at the top surfaces of the features as well), to form third layer material at the feature sidewalls. The width of third layer material at each of the sidewalls is greater than the width of first layer material consumed at the respective sidewall in the conversion process. The second layer is patterned using the third layer material as mask. A fourth layer of material is formed over the substrate, and fourth layer material is planarized or otherwise partially removed so as to expose the top surfaces of the features in the first layer material through the fourth layer. The exposed first layer material is removed to expose portions of the second layer through the fourth layer, and the second layer is further patterned using the fourth layer material as a mask. The process can be designed such that the resulting pattern in the second layer has features that are narrower than those of the initial patterned first layer.

[0008] In various embodiments, the first layer material may be polysilicon or amorphous silicon, for example, and the conversion process can be a thermal process, a chemical reaction, or an interdiffusion process, for example. The thermal process may include a thermal oxidation process, for example, or a silicide process.

[0009] The above process steps can be repeated, either before or after the instance described above, to result in features that are even further narrowed relative to the initial lithographically-produced features. If the repetition is thought of as occurring before the instance described above, then it can take the form of a predecessor instance that produces the initial patterning in the first layer for the instance described above. In this formulation, the step of providing a patterned first layer includes the steps of providing a fifth layer patterned with features having top surfaces and sidewalls, the patterned fifth layer being formed over an unpatterned first layer of the first layer material; consuming fifth layer material at the feature sidewalls in a preliminary conversion process to form sixth layer material at the feature sidewalls, the width of sixth layer material at each of the sidewalls being greater than the width of fifth layer material consumed at the respective sidewall in the preliminary conversion process; patterning the first layer using the sixth layer material as mask, forming a seventh layer of seventh layer material over the substrate; exposing the top surfaces of the features in the fifth layer material through the seventh layer; removing the exposed fifth layer material to expose portions of the first layer through the seventh layer; and further patterning the first layer using the seventh layer material as a mask.

[0010] Pitch dimensions can be narrowed even further by recycling the process flow yet again, and so on. Some of the drawbacks of lithographic processes in the prior art can be prevented.

[0015] It is to be understood and appreciated that the process steps and structures described herein do not describe a complete process flow for the manufacture of an integrated circuit. The invention may be practiced in conjunction with various integrated circuit fabrication techniques that are conventionally used in the art, or that are hereafter developed, and only so much of the commonly practiced process steps are included herein as are necessary to provide an understanding of the invention.

[0016] Referring to the drawings, FIGS. 1–8 depict a first preferred embodiment of the integrated circuit pitch reduction method of the present invention.

[0017] As shown in FIG. 1, a first layer 105 is provided over a second layer 103, which is in turn provided over a substrate 101. As used herein, one layer is “over” another layer if it is physically above the other layer. The term does not necessarily preclude one or more intervening layers, although process flow may have to be adjusted in ways that will be apparent to the reader. In addition, the layer referred to herein as the substrate may include one or more sublayers as well as impurity implants, all as desired for the ultimately desired circuitry. For example, the substrate layer 101 may include a gate dielectric layer overlying a floating gate structure, in turn overlying bulk silicon within which source and drain regions have been implanted. In this example the ultimately formed narrowed-pitch lines might function as gate conductors in a floating gate memory array.

[0018] A patterned photoresist layer 107 with a first width 109 is formed over the first layer 105. The first layer 105 may be composed of silicon material and is preferably a polysilicon layer. The polysilicon layer is formed using chemical vapor deposition (CVD) from a silane (SiH₄) source. The second layer 103 may be a dielectric layer and is preferably a silicon nitride layer. The Silicon nitride layer is formed using chemical vapor deposition (CVD) from a dichlorosilane (SiCl₂H₂) and ammonia (NH₃).

[0019] Next, as depicted in FIG. 2, a plasma etch is performed to remove the first layer 105 not covered by photoresist layer 107. Photoresist layer 107 acts as an etching mask during the patterning of the first layer 105. Photoresist layer 107 is removed after the etch process.

[0020] FIG. 3 illustrates the formation of a third layer 111 on the top surfaces and sidewalls of the first layer material 105. A thermal process, preferably a thermal oxidation process, is used to form the third layer 111. The process is preferably one unable to react with the underlayer such as silicon nitride layer or the second layer 103. The dimension of the patterned first layer 105, preferably a polysilicon layer, will shrink vertically and horizontally during the thermal process, and in the preferred embodiment, a silicon oxide layer will be formed on the top surfaces and sidewalls of the first layer material 105. The resulting structure has an overall width 123 which is larger than the original size of the patterned first layer 105, and encloses laterally (and vertically as well, though that is less important for purposes of this aspect of the invention) the structure of the first layer 105 having a width 113 that is now narrower than the original size of the patterned first layer 105. (The narrowed first layer 105 is now designated 106 in FIGS. 3–6.) An example suitable thermal oxidation process is to expose the wafer in an oxygen-bearing ambient environment at high temperature, e.g. 800° C. In FIG. 3, the dashed line shows the dimension change before and after this process step.

[0021] Turning to FIG. 4, the third layer 111 serves as an etching mask to pattern the second layer 103, thereby leaving portions of substrate 101 exposed. In the preferred embodiment, an anisotropic etch is used that has a high etch rate to silicon nitride and a relatively low etch rate to silicon oxide. An example of an appropriate etch chemistry is CH₃F/O₂ or CH₂F₂.

[0022] Subsequently, as shown in FIG. 5, a fourth layer 115 is formed across the configuration depicted in FIG. 4 to cover the first layer 106, the second layer 103 and the third layer 111 (not shown explicitly in FIG. 5). In a preferred embodiment, the fourth layer 115 comprises a silicon oxide layer formed by high density plasma chemical vapor deposition (CVD) with SiH₄/O₂/argon (O₂) source. In one embodiment, the third layer material 111 is removed before depositing the fourth layer 115. In another embodiment, if the fourth layer material is one that has good gap filling capability in the third layer material and can be planarized (see next step) together with the third layer material, then the third layer material need not be removed before depositing the fourth layer material.

[0023] FIG. 6 illustrates the fourth layer 115 being planarized until the first layer material 106 is exposed. In the preferred embodiment, the fourth layer 115 may be removed down to the level to the top surface of the first layer 106 using Chemical Mechanical Planarization (CMP). Alternatively, The wafer may be placed within a dry etcher to remove the fourth layer 115.

[0024] As FIG. 7 shows, the first layer 106 is then etched to expose the underlying portions of the second layer 103. The first layer 106, preferably polysilicon, is etched with a plasma process, e.g., chlorine (Cl2)/hydrogen bromide (HBr)/oxygen (O2), having a higher etching rate for the first layer material 106 than for the second layer 103 and the fourth layer 115. The openings to the second layer 103 with width 113 are formed after the etch process.

[0025] Referring to FIG. 8, a conventional etching process is performed to pattern the second layer 103 by using the fourth layer 115 as mask. The fourth layer 115 is then removed. The features patterned in the second layer 103 have a second width 117 which is narrower than the original width of the patterned first layer 105.

[0026] FIGS. 21 and 22 illustrate a variation of the process steps of FIGS. 2–4. As shown in FIG. 21, the first material layer 105 is superposed by an additional mask layer 310, having a pattern matching that of the first material layer 105. The additional mask layer 310 may be made of a material that is not affected by the thermal process used in FIG. 3 to convert material at the sidewalls of the first layer features to the third layer material. Thus as shown in FIG. 22, the thermal process forms third layer material at the sidewalls of the first layer features but not at the top surfaces of the first layer features. The additional mask layer material 310 is then removed in some step prior to the etching of first layer material (discussed above with reference to FIGS. 6 and 7).

[0027] Preferably, the material of the additional mask layer 310 is the essentially the same as the material of the second layer 103, so that the additional mask layer 310 will be removed as part of the same process step in which the second layer 103 is etched. For example, the additional mask layer 310 and the second layer 103 may both consist essentially of silicon nitride, and the step of etching the second layer material 103 using the third layer material 111 as a mask also etches away the additional mask layer 310.

[0028] FIGS. 9–19 depict another preferred embodiment of the present invention.

[0029] As shown in FIG. 9, a first layer 205 and a second layer 203 are formed on a substrate 201. A patterned photoresist layer 207 with a first width 209 is formed on the surface of the first layer 205. The first layer 205 maybe composed of silicon material and is preferably a polysilicon layer. Polysilicon layer is formed using chemical vapor deposition (CVD) from a silane (SiH₄) source. The second layer 203 maybe composed of dielectric layer and is preferably a silicon nitride layer. Silicon nitride layer is formed using chemical vapor deposition (CVD) from silane (SiH₄) and NH₃.

[0030] Next, as depicted in FIG. 10, a plasma etch is performed to remove the first layer 205 not covered by photoresist layer 207. Photoresist layer 207 acts as an etching mask during the patterning of the first layer 205. Photoresist layer 207 is removed after etch process.

[0031] FIGS. 11–13 illustrate the formation of a third layer 213 at the top surfaces and sidewalls of the first layer material 205. A thermal process, preferably a silicide process, is used to form the third layer 213.

[0032] In order to accomplish this, referring to FIG. 11, a metal layer 211 is formed across the configuration depicted in FIG. 10. The metal layer 211 maybe composed of refractory metal formed by a sputtering process under high vacuum conditions. The refractory metal can be, for example, Platinum, Nickel, Cobalt, Titanium, Tantalum or Molybdenum.

[0033] FIG. 12 shows the growth of the third layer 213 at the top surfaces and sidewalls of the first layer 205 by a sintering process. The sintering process is preferably a rapid thermal process (RTP) in the temperature range from 400° C. to 800° C. The process used for growing the third layer 213 is preferably one unable to react with the underlayer such as silicon nitride layer or the second layer 203. The dimensions of the patterned first layer 205, preferably a polysilicon layer, will shrink vertically and horizontally during the sintering process, and in the preferred embodiment, the third layer will be formed on the top surfaces and sidewalls of the now-narrowed first layer material 205. (The narrowed first layer material is now designated 206 in FIGS. 12–17.) The third layer is preferably composed of compounds of refractory metals including PtSi₂, NiSi, Co₂Si, CoSi, TiSi₂, TaSi₂ and MoSi₂. After the sintering process, the residual metal film 211 is removed by a wet etch process. The structure in FIG. 13 is shown after the wet etch process. The resulting structure has an overall width 223 which is larger than the original size of the patterned first layer 205, and encloses the structure of the first layer 206 having a width 215 that is now narrower than the original size of the patterned first layer 205.

[0034] Turning to FIG. 14, the third layer 213 serves as an etching mask to pattern the second layer 203, thereby leaving portions of substrate 201 exposed. In the preferred embodiment, an anisotropic etch is used that has a high etch rate to silicon nitride and a relatively low etch rate to TiSi₂. An example of an appropriate etch chemistry is tetrafluoride (CF₄)/Hydrogen (H₂) gas.

[0035] As shown in FIG. 15, the third layer 213 is removed from the configuration depicted in FIG. 14. The third layer 213 is etched with a dry etch process, having higher etching rate for the third layer 213 than for the first layer material 206 and the second layer 203.

[0036] Subsequently, as shown in FIG. 16, a fourth layer 217 is formed across the configuration depicted in FIG. 15 to cover the first layer 206 and the second layer 203 on the substrate 201. In a preferred embodiment, the fourth layer 217 comprise a silicon oxide layer formed by high density plasma chemical vapor deposition (CVD) with a SiH₄/O₂/Ar source.

[0037] FIG. 17 illustrates the fourth layer 217 being planarized until the first layer 206 is exposed. In the preferred embodiment, the fourth layer 217 may be removed down to the level to the upper surface of the first layer 206 using CUT. Alternatively, The wafer may be placed within a dry etcher to remove the fourth layer 217.

[0038] As FIG. 18 shows, the first layer 206 is etched and portions of the second layer 203 are exposed. The first layer 206, preferably polysilicon, is etched with a plasma process, e.g., chlorine (Cl₂)/hydrogen bromide (HBr)/oxygen (O₂), having a higher etching rate for the first layer material 206 than for the second layer material 203 and the fourth layer material 217. The openings to the second layer 203 with the width 215 are formed after the etch process.

[0039] Referring to FIG. 19, a conventional etching process is performed to pattern the second layer 203 by using the fourth layer 217 as mask. The fourth layer 217 is removed after etching process. The features patterned in the second layer 203 now have a second width 219, which as mentioned, is narrower than the feature width 209 as originally patterned lithographically into the first layer 205.

[0040] Note that in all of the above embodiments, the feature narrowing process described herein can be repeated if desired, assuming appropriate materials are used in the starting structure of FIGS. 1 and 9, and substrates 101 and 201 include appropriate sublayers superposing the bulk support material. The repeated feature narrowing process can be thought of as being constructed by adding a second instance of the process steps described above either before or after the first instance described above.

[0041] In the above embodiments, the third layer material is formed at the sidewalls of the first layer material by means of processes which convert a portion of the first layer material into the third layer material. These processes can be thermal processes, as in the above-described embodiments, or can be another form of chemical reaction or interdiffusion reaction in other embodiments. Any process that converts a portion of the first layer material into the third layer material will suffice, so long as the impact of the process on other materials in the structure is insignificant or otherwise accommodated.

[0042] In addition, it will be appreciated that the process forming the third layer material has the effect of reducing the width of the first layer features, and replacing the volume of first layer material with a volume of third layer material at the sidewalls and top of the first layer features. The resulting structure has an overall width that is greater than the starting width of the first layer features, since the width of third layer material produced in the conversion process exceeds the width of first layer material consumed. The width of first layer sidewall material that is consumed in the conversion, and the width of third layer material created in the conversion, both bear on the width and regularity of the sub-lithographic features produced by the remaining steps of the process.

[0043] To illustrate this concept, FIG. 20 sets forth dimensions for the views of FIGS. 3 and 13. As shown in FIG. 20, A indicates the width of an original first layer line, B indicates the width of the first layer line remaining after the conversion process, C indicates the total third layer material width on one sidewall, and D indicates the width of first layer material on one sidewall consumed during the conversion process.

[0044] In one embodiment, if the original first layer lines are formed in a regular pattern of equal width lines and spaces, the process can be used to form a new regular pattern of equal width lines and spaces at substantially one-half the pitch of the original lines. (As used herein, the term “substantially” is intended to accommodate manufacturing tolerances.) This can be accomplished by using a material conversion process in which C=2D=B (i.e. the third layer material width produced by the material conversion process on one sidewall is equal to twice the width of first layer material that is consumed from that sidewall during the conversion process, and is also equal to the width of the first layer material remaining after the conversion process). In other embodiments, however, C can be greater or less than 2D, and/or C can be greater or less than B, A can be greater or less than 2B, and/or the original first layer lines may not be formed in regular patterns of equal width lines and spaces. Variations such as these and others can be used to produce various different sub-lithographic feature patterns as desired in the resulting integrated structure.

[0045] As used herein, a particular patterned layer is “used as a mask” for a particular process step if it is the top layer present when the particular process step is performed, and also if it is only an intermediate layer present when the particular process step is performed, as long as any superposing layers are patterned the same as or more narrowly than the particular layer. In other words, as used herein, if the structure includes two patterned layers, then each of them individually, as well as both of them together, are all considered herein to act as a “mask” for the particular process step. The presence of a superposing layer having the same or narrower pattern as the particular layer does not prevent the particular layer from being “used as a mask” for the particular process step.

[0046] The above-described embodiments have been provided by way of example, and the present invention is not limited to these examples. Multiple variations and modification to the disclosed embodiments will occur, to the extent not mutually exclusive, to those skilled in the art upon consideration of the foregoing description. For example, although the method may be used in the context of a semiconductor fabrication process, actually it can apply to any integrated circuit fabrication process in which lines or other features are to be fabricated with narrow pitch. As another example, although the original features patterned lithographically into the photoresist layer 102 (FIGS. 1 and 9) are preferably created using the minimum feature size available from the employed photolithographic process, it will be appreciated that in another embodiment the primary mask may be created with a feature size larger than the minimum. Of course, as the lithographically produced feature size increases, correspondingly less benefit is gained by employing the process. All these variations and others fall well within the scope of the present invention as set forth in the following claims.