Method to produce small space pattern using plasma polymerization layer

[0002] The present invention generally relates to semiconductor processing, and in particular to a method for producing small space patterns via employment of a plasma polymerization layer.

[0003] In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.

[0004] The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photo mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through the photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.

[0005] The spacing between adjacent lines of an integrated circuit is an important dimension, and ever continuing efforts are made toward reducing such spacing dimension. The wavelength of light used in the photolithographic process along with the lithographic tool set employed in the process generally dictate the spacing dimension. For example, a tool set designed to provide lines and/or spaces at 0.18 μm does not achieve consistent lines and/or spacing at its minimum range of 0.18 μm but rather is employed to generate lines and/or spacing above the minimum range (e.g., 0.20 μm) with fairly consistent results.

[0006] In view of the above, it would be desirable for a technique which allows for a particular lithographic tool set to be employed and achieve consistent lines and/or spacing between lines at the minimum range of the tool set and even below the minimum range.

[0007] The present invention relates to a method for employing a photolithographic tool set and achieving substantially consistent spacing dimensions below the minimum range of the tool set. A given photolithographic tool set is employed to pattern a photoresist layer in a desired fashion. The tool set is capable of achieving a smallest spacing dimension between adjacent lines of d₁. After the photoresist layer is patterned, a plasma polymerization layer is conformably deposited over the patterned photoresist layer. Thereafter, a directional etch is performed to remove a particular amount of the polymerization layer (preferably a thickness equivalent to the thickness of the polymerization layer residing over a photoresist portion). The directional etch leaves polymer sidewalls along the patterned photoresist portions which result in a reduction in dimension size of exposed areas interposed between adjacent photoresist portions. Thus a spacing dimension size (d₂) of exposed areas is substantially less than the spacing dimension size (d₁) of exposed areas prior to the depositing the polymerization layer. An etch step is performed to etch layers underlying the photoresist. Adjacent lines etched from one of the underlayers will have a smallest spacing design dimension of d₂as compared to d₁. Thus, the present invention provides for achieving spacing dimensions between lines at and below a minimum patterning range for a particular lithographic tool set.

[0008] One aspect of the invention relates to a method for forming an etch mask. A photoresist layer is patterned, wherein d₁is a smallest space dimension of an exposed area of a layer underlying the photoresist layer. A polymer layer is formed to be conformal to the patterned photoresist layer and exposed portions of the underlayer. The polymer layer is etched to form polymer sidewalls, the polymer sidewalls reducing the smallest space dimension of the exposed underlayer area to d₂, wherein d₂<d₁.

[0009] Another aspect of the invention relates to a method for producing a small space pattern in a semiconductor layer. A photoresist layer of a semiconductor structure is patterned with a photolithographic tool set, a minimum printed space dimension of the patterned photoresist being d₁, wherein d₁is the smallest space dimension consistently printable by the photolithographic tool set. A polymer layer is formed to be conformal to the patterned photoresist layer and exposed portions of a first layer underlying the photoresist layer, d₁being the smallest dimension of the exposed portions. The polymer layer is etched an amount substantially equivalent to a minimum thickness parameter (γ) of the polymer to leave polymer sidewalls such that the smallest dimension of the exposed portions is now d₂, wherein d₂<d₁.

[0010] Another aspect of the invention relates to method of forming closely spaced lines from a polysilicon layer. A semiconductor structure is used, the semiconductor structure including: the polysilicon layer; an anti-reflective coating (ARC) layer over the polysilicon layer; and a patterned photoresist layer over the ARC layer, wherein a smallest dimension of at least one exposed portion of the ARC layer equals d₁. A polymer layer is formed to conform to an exposed surface of the semiconductor structure. The polymer layer is etched so as to leave polymer portions along sidewalls of the photoresist layer, the polymer portions reducing the smallest dimension of the at least one exposed portion of the ARC layer to d₂, wherein d₂<d₁.

[0011] Still another aspect of the invention relates to a method of forming closely spaced lines from a polysilicon layer. A photolithographic tool set is used to pattern a photoresist layer of a semiconductor structure wherein d₁is a smallest space dimension consistently printable by the photolithographic tool set, the semiconductor structure including: the polysilicon layer; an anti-reflective coating (ARC) layer over the polysilicon layer; and the patterned photoresist layer over the ARC layer, wherein a smallest dimension of at least one exposed portion of the ARC layer equals d₁. The ARC layer is etched. The photoresist layer is removed. A polymer layer is formed to conform to remaining portions of the ARC layer and exposed portions of a polysilicon layer underlying the ARC layer. The polymer layer is etched so as to leave polymer sidewalls, the polymer sidewalls reducing the smallest dimension of the at least one exposed portion of the polysilicon layer to d₂, wherein d₂<d₁. The polysilicon layer is etched, wherein a smallest space dimension between at least two adjacent lines is substantially equal to d₂.

[0012] To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.

[0013] FIG. 1ais a schematic cross-sectional illustration of lines formed in accordance with the present invention;

[0014] FIG. 1bis a schematic cross-sectional illustration of a ratio of line width to space width in accordance with the present invention;

[0015] FIG. 2 is schematic cross-sectional illustration of a semiconductor structure including a polysilicon layer, an anti-reflective coating layer and a photoresist layer patterned with a particular tool set;

[0016] FIG. 3 is a schematic illustration of the semiconductor structure of FIG. 2 undergoing a deposition process to conformably deposit a polymer layer on the structure in accordance with the present invention;

[0017] FIG. 4 is a schematic cross-sectional illustration of the structure of FIG. 3 after the polymer layer has been conformably formed on the structure;

[0018] FIG. 5 is a schematic cross-sectional illustration of the structure of FIG. 4 undergoing a directional etch of the polymer layer in accordance with the present invention;

[0019] FIG. 6 is a schematic cross-sectional illustration of the structure of FIG. 5 after the directional etch is complete in accordance with the present invention;

[0020] FIG. 7 is a schematic cross-sectional illustration of the structure of FIG. 6 undergoing an etch process to remove exposed portions of the anti-reflective layer and polysilicon layer in accordance with the present invention;

[0021] FIG. 8 is a schematic cross-sectional illustration of the structure of FIG. 7 after the etch process is complete in accordance with the present invention;

[0022] FIG. 9 is a schematic cross-sectional illustration of the structure of FIG. 8 undergoing a stripping process to remove remaining polymer and photoresist portions from the structure in accordance with the present invention;

[0023] FIG. 10 is a schematic cross-sectional illustration of the structure of FIG. 9 after the stripping process is complete in accordance with the present invention.

[0024] FIG. 11 is a schematic cross-sectional illustration of the structure of FIG. 8 undergoing an optional ion implant step;

[0025] FIG. 12 is schematic cross-sectional illustration of a semiconductor structure including a polysilicon layer, an anti-reflective coating layer and a photoresist layer patterned with a tool set;

[0026] FIG. 13 is a schematic illustration of the semiconductor structure of FIG. 12 undergoing an etch step to etch a layer underlying the patterned photoresist layer in accordance with the present invention;

[0027] FIG. 14 is a schematic cross-sectional illustration of the structure of FIG. 13 after the underlayer etch step is complete, and illustrating the structure undergoing a photoresist stripping process in accordance with the present invention;

[0028] FIG. 15 is a schematic cross-sectional illustration of the structure of FIG. 14 after the photoresist has been removed in accordance with the present invention;

[0029] FIG. 16 is a schematic cross-sectional illustration of the structure of FIG. 15 undergoing a deposition process to conformably deposit a polymer layer on the structure in accordance with the present invention;

[0030] FIG. 17 is a schematic cross-sectional illustration of the structure of FIG. 16 after the polymer deposition step is substantially complete in accordance with the present invention;

[0031] FIG. 18 is a schematic cross-sectional illustration of the structure of FIG. 17 undergoing a directional etch step in accordance with the present invention;

[0032] FIG. 19 is a schematic cross-sectional illustration of the structure of FIG. 18 after the directional etch step is substantially complete in accordance with the present invention;

[0033] FIG. 20 is a schematic cross-sectional illustration of the structure of FIG. 19 undergoing a poly etch step to form lines in accordance with the present invention;

[0034] FIG. 21 is a schematic cross-sectional illustration of the structure of FIG. 20 after the poly etch step is substantially complete in accordance with the present invention;

[0035] FIG. 22 is a schematic cross-sectional illustration of the structure of FIG. 21 undergoing a stripping process to remove remaining portions of the polymer layer and ARC layer in accordance with the present invention;

[0036] FIG. 23 is a schematic cross-sectional illustration of the structure of FIG. 22 substantially complete in relevant part in accordance with the present invention; and

[0037] FIG. 24 is a schematic cross-sectional illustration of floating gates formed in accordance with the present invention.

[0038] The present invention will now be described with reference to the drawings.

[0039] FIG. 1aillustrates a set of lines 50_A, 50_Band 50_C(collectively referred to by reference numeral 50) formed in accordance with the present invention. The lines 50 are formed employing a photolithographic tool set (not shown) having a minimum feature printing dimension of d_M. More particularly, the smallest spacing between lines printable by the tool set has a dimension of d_M. However, consistent printing at the minimum spacing dimension d_Mis typically not possible. The tool set is capable of printing consistently at a spacing dimension of d₁(which is larger than d_M). As can be seen from FIG. 1, the present invention provides for employing the particular tool set to form the lines 50 such that a spacing dimension (d₂) between adjacent lines, respectively, is achieved. The dimension d₂is substantially less than dimensions d_Mand d₁.

[0040] FIG. 1billustrates a ratio of line width to space width in accordance with the present invention. As is known, small spacing between adjacent lines having relatively large width is very difficult to achieve. The present invention provides for achieving a ratio of line width to space width of up to about 20:1. Lines 50_Dand 50_Ehave widths, respectively, about twenty times greater than the space between the lines 50_Dand 50_E.

[0041] FIGS. 2-11 illustrate in greater detail how the present invention provides for forming the lines 50 having a spacing dimension there between, respectively, of d₂using the tool set which has a minimum print feature dimension of d_M(which is substantially greater than d₂).

[0042] FIG. 2 illustrates a structure 60 which includes an oxide layer 52, a polysilicon layer 54, an anti-reflective coating layer 62 and a patterned photoresist layer 64. Formation of the structure 60 is well known in the art, and further detail regarding such is omitted for sake of brevity. The photoresist layer 64 has been patterned via a photolithographic tool set (e.g., deep ultra-violet (DUV)) tool set capable of patterning lines separated by distances equal to or greater than 0.18 μm). The patterned photoresist layer 64 will serve as a mask for the underlying layers during etch steps to form the lines 50. The distance d₁is representative of the smallest space parameter consistently achievable by the photolithographic tool set.

[0043] FIG. 3 illustrates a polymer deposition step 70 performed on the structure 60 to form a carbon/oxygen based polymer conformal to the exposed surface of the structure 60. More particularly, the patterned photoresist layer 64 is exposed to at least one of a CHF₃chemistry, an HBr chemistry, a CH₃F chemistry, and a CH₂F₂chemistry to form a conformal polymer coating 80 (FIG. 4) on the patterned photoresist 64. Oxygen based reactive gases are reduced as compared to a typical etch chemistry so that the conformal polymer coating 80 is formed over the photoresist layer 64.

[0044] One specific example of a suitable chemistry to form the polymer layer 80 includes using a relatively high pressure of 50-100 mT, relatively low power of less than or equal to 500 W, and a temperature of below 80° C. It is to be appreciated that one skilled in the art could readily tailor without undue experimentation a suitable chemistry to form the conformal polymer coating 80. As discussed in greater detail below, the etch chemistry and duration thereof may be suitably tailored to form the polymer coating at substantially any desired thickness (e.g., between about the range of 10-1000 Å).

[0045] Below are some specific examples of chemistries that may be employed in forming the polymer layer 80.

[0046] A MERIE method is used with CHF₃(50 to 200 sccm) with reactant gases of: Ar (100 to 500 sccm) and O₂(10 to 50 sccm) at a power level within the range of about 100 to 500 W and pressure within the range of about 60 to 100 mT.

[0047] A MERIE method is used with HBr (100 to 250 sccm) with reactant gases of: Ar (100 to 500 sccm) at a power level within the range of about 100 to 500 W, and pressure within the range of about 500 to 100 mT.

[0048] A MERIE method is used with CH₃F (50 to 250 sccm) with reactant gases of: Ar (50 to 200 sccm) and N₂(10 to 50 sccm) at a power level within the range of about 100 to 500 W, and pressure within the range of about 50 to 100 mT.

[0049] A MERIE method is used with CH₂F₂(100 to 200 sccm) with reactant gases of: Ar (50 to 200 sccm) and N₂(10 to 50 sccm) at a power level within the range of about 100 to 500 W, and pressure within the range of about 50 to 100 mT.

[0050] FIG. 4 illustrates the structure 60 after the polymer deposition step 70 is substantially complete. The polymer layer 80 is conformal to the exposed surface of the structure 60 with a substantially uniform thickness.

[0051] FIG. 5 illustrates a directional etch step 90 being performed to remove a predetermined thickness of the polymer layer 80. An etch chemistry including CHF₃, O₂, Ar and CF₄, for example, is employed to perform a dry directional etch of the polymer layer 80. Preferably, the directional etch 90 is performed to remove an amount of the polymer layer 80 equivalent to the conformal thickness of the polymer layer 80. The directional dry etch 90 is next adjusted to be selective to the ARC layer 62 so as to etch exposed portions of the ARC layer 62.

[0052] Substantial completion of the etch step 90 results in a structure 100 shown in FIG. 6. The structure 100 includes polymer sidewalls 120 which result in exposed portions of the polysilicon layer 54 having a dimension of d₂. The dimension d₂is less than the dimension d₁(FIG. 1). The dimension d₂may be controlled via the controlling the thickness (γ) of the polymer layer 80. For example, the dimension d₂may be controlled according to the following relationship:

[0053] d₂=d₁−2γ

[0054] Since there are two polymer sidewalls 120 within a particular dimension d₁the value of d₂equals d₁less twice the polymer layer thickness (γ).

[0055] Next, referring to FIG. 7, a poly etch 130 is performed to etch exposed portions of the polysilicon layer 54 so as to form the lines 50 (FIG. 1) having a spacing there between, respectively, of d₂. The poly etch 130 chemistry may include, for example: (1) HBr, Cl₂and He—O₂; or (2) Cl₂and He—O₂; or (3) HBr and He—O₂. The etch chemistry may be suitably tailored in accordance with the thickness of the oxide layer 52, desired etch speed, and desired selectivity.

[0056] FIG. 8 illustrates a structure 140 resulting after the poly etch 130 is substantially complete. The structure 140 includes lines 50 having a spacing dimension between adjacent lines, respectively, equal to d₂.

[0057] FIG. 9 illustrates an etch step 150 which removes remaining portions of the photoresist 64, remaining portions of the ARC layer 62 and the polymer sidewalls 120 from the structure 140.

[0058] FIG. 10 illustrates the lines 50 after the stripping step 150 is substantially complete. The spacing dimension between adjacent lines (e.g., 50_Aand 50_B) substantially equals d₂. Thus, for example, if a 0.18 μm tool set were employed to pattern the photoresist 64 with a spacing dimension d₁=0.20 μm and the polymer layer 80 was formed to have a thickness of 0.03 μm, the resulting spacing dimension between adjacent lines 50_Aand 50_Bwould be approximately 0.14 μm=(0.20 μm−2(0.03 μm)). The minimum space dimension (d_M) for the 0.18 μm tool set employed is 0.18 μm, and such minimum space dimension typically would be difficult to achieve consistently in accordance with conventional techniques. However, by employing the present invention the same 0.18 μm tool set can be employed to achieve with substantial consistency minimum space dimensions between lines at and below the minimum space dimension parameter of the tool set.

[0059] Thus, the present invention provides for a method for employing a conventional tool set to obtain minimum space dimensions well below the minimum space parameter typically achievable by the tool set. As a result, the present invention provides for a relatively low cost alternative to purchasing new photolithographic tool sets for achieving reduced spacing between lines.

[0060] FIG. 11 illustrates an optional ion implant step 160 (e.g., boron implant) which may be performed on the structure 140 of FIG. 8 so as to isolate active regions below the oxide layer 52. The patterned photoresist layer 64 and the polymer sidewalls 120 will serve as masks during the implant step 160.

[0061] FIGS. 12-23 illustrate another embodiment of the present invention.

[0062] FIG. 12 illustrates a structure 200 which includes an oxide layer 252, a polysilicon layer 254, an anti-reflective coating layer 262 and a patterned photoresist layer 264.

[0063] FIG. 13 illustrates an etch step 266 to etch exposed portions of the ARC layer 262.

[0064] FIG. 14 illustrates a photoresist stripping step 268 to remove remaining portions of the photoresist layer 264.

[0065] FIG. 15 illustrates a structure 269 formed after the etch step 266 and the stripping step 268 are substantially complete.

[0066] FIG. 16 illustrates a polymer deposition step 270 performed on the structure 269 to form a carbon/oxygen based polymer conformal to the exposed surface of the structure 269. More particularly, the etched ARC layer 254 is exposed to a CHF₃chemistry or an HBr chemistry or a CH₃F or a CH₂F₂chemistry to form a conformal polymer coating 280 (FIG. 17) on the ARC layer 262. Oxygen based reactive gases are reduced as compared to a typical etch chemistry so that the conformal polymer coating 280 is formed over the ARC layer 262.

[0067] FIG. 18 illustrates a directional etch step 290 being performed to remove a predetermined thickness of the polymer layer 280. An etch chemistry including CHF₃, O₂, Ar and CF₄, for example, is employed to perform a dry directional etch of the polymer layer 280. Preferably, the directional etch 290 is performed to remove an amount of the polymer layer 280 equivalent to the conformal thickness of the polymer layer 280.

[0068] Substantial completion of the etch step 290 results in a structure 300 shown in FIG. 19. The structure 300 includes polymer sidewalls 320 which result in exposed portions of the polysilicon layer 254 having a dimension of d₂. The dimension d₂is less than the dimension d₁(FIG. 12). The dimension d₂may be controlled via the controlling the thickness (γ) of the polymer layer 280. For example, the dimension d₂may be controlled according to the following relationship:

[0069] d₂=d₁−2γ

[0070] Since there are two polymer sidewalls 320 within a particular dimension d₁, the value of d₂equals d₁less twice the polymer layer thickness (γ).

[0071] Next, referring to FIG. 20, a poly etch 330 is performed to etch exposed portions of the polysilicon layer 254 so as to form lines 350 (FIG. 21) having a spacing there between, respectively, of d₂.

[0072] FIG. 22 illustrates a stripping step 360 to remove remaining portions of the ARC layer 262 and polymer sidewalls 330.

[0073] FIG. 23 illustrates a structure 400 including the lines 350 having a spacing dimension between adjacent lines (e.g., 350_Aand 350_B) substantially equal to d₂. The optional ion implant step 160 (e.g., boron implant) of FIG. 11 may also be employed in this embodiment on the structure of FIG. 21 so as to isolate active regions below the oxide layer 252.

[0074] Employing the present invention achieves with substantial consistency minimum space dimensions between lines at and below the minimum space dimension parameter of a particular tool set employed.

[0075] Although the present invention has been described primarily in the context of forming lines, it is to be appreciated that the present invention may be applied to forming other features (e.g., floating gates of flash memory devices and/or embedded flash memory devices) where achieving small space dimension between adjacent features is desired. For example, as shown in FIG. 24 the principles of the present invention may be employed in the formation of closely spaces floating gates 450_A, 450_Band 450_Cof a memory device 460.

[0076] The present invention provides for a method for employing a particular photolithographic tool set to obtain minimum space dimensions well below the minimum space parameters typically obtainable by the tool set.

[0077] What has been described above are preferred embodiments of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.