Fabrication method of sub-resolution pitch for integrated circuits

[00002] 1. Field of the Invention

[00003] This invention is in general related to a method of fabricating integrated-circuits and, more particularly, to a method of fabricating integrated circuits with a sub-resolution pitch.

[00004] 2. Background of the Invention

[00005] Although modern integrated circuits already have very high device densities, for example, up to millions of devices per single chip, many applications still require even higher densities. Lithography is one, and probably the most important, manufacturing process that may be improved to obtain a high device density or a small feature size. However, the device density becomes more and more difficult to increase as the scale of devices approaches the limit of the lithography process.

[00006] With conventional photolithography methods using a 248 nm scanner, pitches smaller than 0.24 μm, the resolution of the scanner, are difficult to generate. A pitch is defined as a minimum center-to-center distance between two features, such as interconnect lines, pads, or pins. To realize a pitch of 90 nm or 65 nm, conventional methods would require a 193 nm or a 157 nm scanner, respectively. However, these scanners are not matured yet for industrial production.

[00007] Alternatively, to scale down device dimensions, resolution enhancement techniques (RET) such as phase shifting masks or off-axis illumination may be implemented. However, these conventional solutions are generally complicated and very expensive to implement in product manufacturing.

[00008] It is therefore an object of the present invention to provide a cost-effective approach to reducing a pitch of the lithography process.

[00009] In accordance with the present invention, there is provided a method of manufacturing a semiconductor device using a scanner, wherein the scanner is capable of realizing a minimum pitch, wherein the minimum pitch is the smallest possible pitch for the scanner, the method including providing a semiconductor substrate, forming a first layer over the semiconductor substrate, forming a second layer over the first layer, patterning the second layer to form a plurality of second layer patterns, patterning the first layer to form a plurality of first layer patterns, wherein a line width of the first layer patterns is greater than a line width of the second layer patterns, and each second layer pattern is located approximately over the center of a corresponding first layer pattern, performing a tone reversal to form a reversed tone for the second layer patterns, and etching the first layer patterns using the reversed tone as a mask, wherein the etched first layer patterns have a final pitch size, and wherein the final pitch is smaller than the minimum pitch.

[00010] Also in accordance with the present invention, there is provided a method of manufacturing a semiconductor device using a scanner, wherein the scanner is capable of realizing a minimum pitch, wherein the minimum pitch is the smallest possible pitch for the scanner, the method including providing a first layer, depositing a layer of photoresist over the first layer, patterning the photoresist to form a plurality of photoresist patterns, wherein the photoresist patterns have a line width approximately one fourth of the minimum pitch, and etching a portion of the first layer using the trimmed photoresist patterns as mask, wherein the etched first layer includes a flat layer with a plurality of protrusions thereon, and wherein the protrusions have a line width approximately one fourth of the minimum pitch, etching the flat layer to form a plurality of flat layer patterns, wherein a line width of the flat layer patterns is approximately three fourths of the minimum pitch, and wherein each protrusion is located approximately on top of the center of a corresponding flat layer pattern, performing a tone reversal to form a reversed tone for the protrusions, and etching the flat layer patterns, wherein the etched flat layer patterns have a final pitch size, and wherein the final pitch is approximately equal to a half of the minimum pitch.

[00011] Further in accordance with the present invention, there is provided a method of manufacturing a semiconductor device using a scanner, wherein the scanner is capable of realizing a minimum pitch, wherein the minimum pitch is the smallest possible pitch for the scanner, the method including providing a semiconductor substrate, forming a first layer over the semiconductor substrate, depositing a layer of photoresist over the first layer, patterning the photoresist to form a plurality of photoresist patterns using the scanner, wherein a line width of the photoresist patterns is approximately equal to a half of the minimum pitch, trimming the photoresist patterns, wherein the trimmed photoresist patterns have a line width approximately one fourth of the minimum pitch, etching a portion of the first layer using the trimmed photoresist patterns as mask, wherein the etched first layer includes a flat layer with a plurality of protrusions thereon, and wherein the protrusions have a line width approximately one fourth of the minimum pitch, etching the flat layer to form a plurality of flat layer patterns, wherein a line width of the flat layer patterns is approximately three fourths of the minimum pitch, and wherein each protrusion is located approximately on top of the center of a corresponding flat layer pattern, performing a tone reversal to form a reversed tone for the protrusions, and etching the flat layer patterns, wherein the etched flat layer patterns have a final pitch size, and wherein the final pitch is approximately equal to a half of the minimum pitch.

[00012] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

[00018] Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

[00019] For illustration purposes, in the following descriptions of embodiments of the present invention, a 248 nm scanner is used and a minimum, or smallest possible, initial pitch size of 260 nm is realized. However, it is to be understood that any suitable scanner may be used in connection with the methods of the present invention to obtain a reduced pitch.

[00020] In accordance with the present invention, there is provided a novel method of reducing a pitch of the lithography process, as described below with reference to FIGS. 1A-1K. FIGS. 1A-1K show a fabrication method consistent with a first embodiment of the present invention.

[00021] Referring to FIG. 1A, there is provided a semiconductor substrate 100, which may comprise any conventional semiconductor material, such as silicon or germanium. A gate dielectric layer 102 is formed over substrate 100. A gate contact layer 104 is formed over gate dielectric 102. Gate dielectric 102 may comprise oxide or other suitable gate dielectric materials. Gate contact 104 may comprise a layer of polysilicon, metal, or a combination therefor. A first dielectric layer 106 is deposited over gate contact 104, followed by depositing a second dielectric layer 108 over first dielectric layer 106. In one aspect, first dielectric layer 106 comprises silicon nitride. In another aspect, second dielectric layer 108 comprises polysilicon, and serves as a sacrificial layer. Gate dielectric 102 may be deposited using thermal growth or chemical vapor deposition (CVD) Gate contact 104, first dielectric layer 106, and second dielectric layer 108 may be deposited using chemical vapor deposition (CVD) or sputtering.

[00022] A photoresist layer (not numbered) is deposited over second dielectric layer 108 and patterned to form a plurality of first photoresist patterns 110. In the following description of the embodiment, without limiting the scope of the present invention, patterns 110 have the same line width and are equally spaced-apart, and the line width of each pattern 110 is equal to the space between two consecutive patterns 110. Therefore, the initial pitch is equal to the sum of the line width of photoresist patterns 110 and the space therebetween. With the assumption that an initial pitch size of 260 nm is realized using a 248 nm scanner, both the line width of patterns 110 and the space therebetween are 130 nm, as shown in FIG. 1A.

[00023] Referring to FIG. 1B, a step of photoresist trimming is performed to trim, or reduce, first photoresist patterns 110 to form second photoresist patterns 110a. Photoresist trimming is well-known to one skilled in the art and therefore is not described in detail herein. In one aspect, the line width of first photoresist patterns 110 is reduced by half by the photoresist trimming, i.e., the line width of second photoresist patterns 110a as shown in FIG. 1B is approximately 65 nm, about a fourth of the initial pitch of 260 nm, while the space therebetween is about 195 nm.

[00024] Second dielectric 108 is etched using second photoresist patterns 110a as an etch mask, forming a plurality of second dielectric patterns 108a. After etching second dielectric 108, first dielectric 106 is partially exposed, as shown in FIG. 1C. Second dielectric patterns 108a also have a line width of approximately 65 nm.

[00025] In one aspect, second photoresist patterns 110a are stripped off after the etching of second dielectric 108. In another aspect, second photoresist patterns 110a are not stripped off after the etching of second dielectric 108. It is to be understood that the removal of second photoresist patterns 110a is not critical to, the present invention. For illustration purposes, it is assumed that second photoresist patterns 110a are not stripped off after the etching of second dielectric 108.

[00026] After etching second dielectric 108, a layer of polymer 112 is deposited over the tops of second photoresist patterns 110a, on the sidewalls of second photoresist patterns 110a and second dielectric patterns 108a, and over the exposed surface of first dielectric 106, as shown in FIG. 1D. Polymer 112 has a structure with a plurality of openings 112a. In one aspect, the thickness of polymer 112 is approximately 65 nm over the tops of second photoresist patterns 110a, on the sidewalls of second photoresist patterns 110a and second dielectric patterns 108a, and over the exposed surface of first dielectric 106. Therefore, the width of openings 112a is also approximately 65 nm. Polymer 112 may be deposited by chemical vapor deposition (CVD) or any other conventional deposition methods.

[00027] Polymer 112 is then etched to expose parts of first dielectric 106 at the bottom of openings 112a, followed by an etching step to etch through first dielectric 106. After the etching of polymer 112 and first dielectric 106, a plurality of first dielectric patterns 106a are formed, and parts of gate contact 104 are exposed. As shown in FIG. 1E, first dielectric patterns 106a have a line width of approximately 195 nm, three fourths of the initial pitch and greater than that of second dielectric patterns 108a. Also, second dielectric patterns 108a are located approximately over the center of first dielectric patterns 106a. Remaining polymer 112 and second photoresist patterns 110a are then removed, exposing first dielectric patterns 106a and second dielectric patterns 108a.

[00028] From the above description, one skilled in the art would appreciate the advantages of using polymer 112, which include a wider process window in providing an anisotropic coating than conventional plasma enhanced CVD (PECVD) oxide or nitride. Polymer may be processed at low temperatures, which is compatible with photoresist, and therefore can be removed together with the photoresist, resulting in a reduction in the number of manufacturing steps.

[00029] A third dielectric layer (not numbered) is deposited over the resultant structure including second dielectric patterns 108a, first dielectric patterns 106a, and gate contact layer 104. In one aspect, the third dielectric layer comprises oxide, deposited by high density plasma (HDP) method. In another aspect, the third dielectric layer comprises polymer. The third dielectric layer is then polished or etched, using a conventional chemical-mechanical-polishing (CMP) or etching method, to expose the surface of second dielectric layer 108a. After the polishing or etching a step, a plurality of third dielectric patterns 114 are formed, as FIG. 1F.

[00030] Referring to FIG. 1G, selective etching is performed to remove second dielectric patterns 108a, exposing parts of the surface of first dielectric patterns 106a. As shown in FIG. 1G, the width of the upper portion of third dielectric patterns 114 is approximately 195 nm. The steps of depositing the third dielectric and etching second dielectric patterns 108a are similar in function to a tone reversal of second dielectric patterns 108a. The term “tone reversal” used herein conveys the same meaning as “mask tone reversal” except the term is used to describe a non-photoresist or non-mask structure. Since the term “mask tone reversal” is well known to one skilled in the art, no additional description is required. As shown in FIG. 1G, third dielectric patterns 114 represent the reversed tone of second dielectric patterns 108a.

[00031] Referring to FIG. 1H, using third dielectric patterns 114, or the reversed tone of second dielectric patterns 108a, as a hard mask, another step of etching is performed to etch first dielectric patterns 106a to expose gate contact 104 that results in a plurality of first dielectric patterns 106b.

[00032] Third dielectric patterns 114 are removed afterwards, resulting in the structure shown in FIG. 11. Conventional steps then follow to form patterned gate contacts 104a and to remove first dielectric patters 106b, as shown in FIGS. 1J and 1K, respectively, resulting in a final pitch of about 130 nm, approximately half of the initial pitch size.

[00033] A second embodiment of the present invention is described with reference to FIGS. 2A-2I. As shown in FIG. 2A, there is provided a substrate 200 which may comprise any conventional semiconductor material such as silicon or germanium. A layer of gate dielectric 202 is formed over substrate 200. A layer of gate contact 204 is formed over gate dielectric 202. A first dielectric layer 206 is formed over gate contact 204. Gate dielectric 202 may comprise oxide. Gate contact 204 may comprise polysilicon, metal, or a combination thereof. First dielectric 206 may comprise silicon nitride (SiN).

[00034] After the formation of gate dielectric 202, gate contact 204, and first dielectric 206, a photoresist film is formed over first dielectric 206 and patterned to form a plurality of first photoresist patterns 208. An initial pitch as indicated in FIG. 2A is approximately 260 nm, assuming a 248 nm scanner is used. Therefore, the line width of first photoresist patterns 208 and the space therebetween are both approximately 130 nm.

[00035] Photoresist trimming is then performed to trim first photoresist patterns 208 to form a plurality of second photoresist patterns 208a, as shown in FIG. 2B. After photoresist trimming, the line width of the photoresist patterns is reduced by half, i.e., the line width of second photoresist patterns 208a is approximately 65 nm, while the space therebetween is about 195 nm.

[00036] As shown in FIG. 2C, using second photoresist patterns 208a as mask, first dielectric 206 is etched to form a plurality of first dielectric patterns 206a, exposing parts of gate contact 204. First dielectric patterns 206a also have a line width of about 65 nm.

[00037] After the etching of first dielectric 206, a layer of polymer 210 is deposited over the tops of second photoresist patterns 208a, on the sidewalls of second photoresist patterns 208a and first patterns 206a, and over the exposed surfaces of gate contact 204, as shown in FIG. 2D. Polymer 210 has a structure with a plurality of openings 210a. In one aspect, the thickness of polymer 210 is approximately 65 nm over the tops of second photoresist patterns 208a, on the sidewalls of second photoresist patterns 208a and first dielectric patterns 206a, and over the exposed surfaces of gate contact 204. Therefore, the width of openings 210a is also approximately 65 nm. Polymer 210 may be deposited by chemical vapor deposition or any other conventional deposition methods.

[00038] Polymer 210 is then etched to expose parts of gate contact 204 at the bottom of openings 210a, followed by a step of etching to etch through gate contact 204. After the etching of polymer 210 and gate contact 204, a plurality of gate contact patterns 204a are formed. As shown in FIG. 2E, gate contact patterns 204a have a line width of approximately 195 nm, which is about three fourths of the initial pitch and greater than that of first dielectric patterns 206a. Also, first dielectric patterns 206a are located approximately over the center of gate contact patterns 204a. Remaining polymer 210 and second photoresist patterns 208a are then removed, exposing gate contact patterns 204a and first dielectric patterns 206a.

[00039] After polymer 210 and second photoresist patterns 208a are removed, a tone reversal is performed for first dielectric patterns 206a. First, a second dielectric layer (not numbered) is deposited over the resultant structure including first dielectric patterns 206a, gate contact patters 204a, and gate dielectric 202. In one aspect, the second dielectric layer comprises oxide deposited by high density plasma (HDP) method. In another aspect, the second dielectric layer comprises polymer. Then the second dielectric layer is polished or etched, using a conventional chemical-mechanical-polishing (CMP) or etching method, to expose the surface of first dielectric patterns 206a. After the polishing or etching step, a plurality of second dielectric patterns 212 are formed, as shown in FIG. 2F. Referring to FIG. 2G, selective etching is performed to remove first dielectric patterns 206a, exposing parts of the surface of gate contact patterns 204a. The step of selective etching does not etch away second dielectric patterns 212. As a result, second dielectric patterns 212 are the reversed tone of first dielectric patterns 206a.

[00040] Also as shown in FIG. 2G, the width of the upper portion of second dielectric patterns 212 is approximately 195 nm. Then, using second dielectric structures 212, or the reversed tone of first dielectric patterns 206a, as hard mask, another step of etching is performed to etch through gate contact patterns 204a, exposing gate dielectric 202 and resulting in a plurality of gate contact patterns 204b, as shown in FIG. 2H.

[00041] Second dielectric structures 212 are removed afterwards, resulting in the structure shown in FIG. 21, wherein a pitch defined as the sum of the line width of gate contact patterns 204b and the space therebetween Is approximately 130 nm. Comparing FIG. 21 with FIG. 2A, a smaller pitch has been realized through the above processing steps.

[00042] Next, a third embodiment of the present invention is described with reference to FIGS. 3A-3J. Referring to FIG. 3A, there is provided a substrate 300 which may comprise any conventional semiconductor material such as silicon or germanium. A layer of gate dielectric 302 is formed over substrate 300. A layer of gate contact 304 is formed over gate dielectric 302. A first dielectric layer 306 is formed over gate contact 304. Gate dielectric 302 may comprise oxide. Gate contact 304 may comprise polysilicon, metal, or a combination thereof. First dielectric 306 may comprise silicon nitride (SiN).

[00043] A photoresist film is formed over first dielectric 306 and patterned to form a plurality of first photoresist patterns 308. An initial pitch as indicated in FIG. 3A is approximately 260 nm. The line width of first photoresist patterns 308 and the space therebetween are both approximately 130 nm.

[00044] Photoresist trimming is performed to trim first photoresist structures 308 to form a plurality of second photoresist patterns 308a, as shown in FIG. 3B. The line width of patterns 308a is approximately 65 nm, and the space therebetween is about 195 nm.

[00045] Using second photoresist patterns 308a as mask, first dielectric 306 is partially etched. As shown in FIG. 3C, the remaining part of first dielectric layer 306 has a structure including a flat layer 306a and a plurality of protrusions 306b. Protrusions 306b also have a line width of about 65 nm.

[00046] A layer of polymer 310 is then deposited over the tops of second photoresist patterns 308a, on the sidewalls of second photoresist patterns 308a and protrusions 306b, and over flat layer 306a, as shown in FIG. 3D. Polymer 310 has a structure with a plurality of openings 310a. In one aspect, the film thickness of polymer 310 is approximately 65 nm. Therefore, the width of openings 310a is also approximately 65 nm. Polymer 310 may be deposited by chemical vapor deposition or any other conventional deposition methods.

[00047] Polymer 310 is etched to expose parts of flat layer 306a at the bottom of openings 310a, followed by a step of etching to etch through flat layer 306a. After the etching of polymer 310 and flat layer 306a, a plurality of flat layer patterns 306c are formed, as shown in FIG. 3E. Remaining polymer 310 and second photoresist patterns 308a are then removed, exposing protrusions 306b and flat layer patterns 306c.

[00048] After polymer 310 and second photoresist patterns 308a are removed, a tone reversal is performed for protrusions 306b. First, a second dielectric layer (not numbered) is deposited over the resultant structure including protrusions 306b, flat layer patterns 306c, and gate contact 304. In one aspect, the second dielectric layer may comprise oxide deposited by high density plasma (HDP) method. In another aspect, the second dielectric layer may comprise polymer. The second dielectric layer is then polished or etched, using a conventional chemical-mechanical-polishing (CMP) or etching method, to expose the surface of protrusions 306b. After the polishing or etching step, a plurality of second dielectric patterns 312 are formed, as shown in FIG. 3F.

[00049] Referring to FIG. 3G, selective etching is performed to remove protrusions 306b and to etch through flat layer patterns 306c, exposing parts of gate contact 304. After the etching of protrusions 306b and flat layer patterns 306c, first dielectric patterns 306d as shown in FIG. 3G are formed. The step of selective etching does not etch away second dielectric structures 312. As shown in FIG. 3G, the width of the upper portion of second dielectric structure 312 is approximately 195 nm.

[00050] Second dielectric structures 312 are removed afterwards, resulting in the structure as shown in FIG. 3H, including first dielectric patterns 306d. Then, as shown in FIG. 31, a step of etching is performed to etch gate contact 304 using first dielectric patterns 306d as a hard mask, forming a plurality of gate contact patterns 304a.

[00051] Finally, first dielectric patterns 306d are removed using any conventional method. As shown in FIG. 3J, contact patterns 304a have a final pitch of approximately 130 nm, about half of the initial pitch.

[00052] Although the gate dielectric and gate contact layers are formed over the substrate in the above descriptions of the embodiments, it is to be understood that the gate dielectric and gate contact layers are not required for the present invention. Methods of the present invention are not limited to the manufacturing of devices having a MOS structure. The methods consistent with embodiments of the present invention may also be applied to realize a smaller pitch on any other device that requires a lithography step in the manufacturing process thereof.

[00053] It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed process without departing from the scope or spirit of the invention. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.