Switching power converter

[0002] This invention relates to switching power supplies or converters. In particular, this invention relates to a simple, robust switching power supply which is capable of providing power to a number of different regulated power sources within a given circuit.

[0003] Switching power supplies are used to provide power in numerous products such as cell phones, camera, PDAs (Personal Digital Assistants), calculators, portable computers and similar types of electronic equipment. Such switching power supplies are quite complex and use numerous components to provide a number of precisely regulated output voltages to power the various integrated circuits and other components contained within the product being powered. Relative to the cost and the quality of the products in which they are used, such power supplies are expensive, bulky and inefficient. Efficiency is important to provide the equipment a long battery life. FIG. 1 shows a typical prior art power supply used in portable equipment powered by a battery 10. The signal from battery 10 is transmitted on lead 10ato a level translation circuit 12, which is controlled by a control signal from analog pulse width modulated controller 11. The control signal from analog pulse width modulator is responsive to the voltage drop across resistor 16 as detected by signals on conductive leads 17aand 17bconnecting, respectively, the two terminals of resistor 16 into analog PWM controller 11. N-channel MOS transistors 13aand 13bare connected to operate in a complementary fashion. Level translation circuit 12 provides a high level voltage to the gate of N-channel transistor 13ato apply a pulse from battery 10 to one input terminal of coil 15. The other input terminal of coil 15 is connected to one terminal of resistor 16. The other terminal of resistor 16 is connected to load capacitor 18, which contains a charge at the voltage necessary to supply the particular circuitry being powered by this portion of the power supply. The analog PWM controller 11 measures the current through resistor 16 and controls the ON time of N-channel MOS transistor 13a. N-channel MOS transistor 13bis driven by the complement of the signal driving the gate of N-channel MOS transistor 13aand turns on to pull the input lead of coil 15 to ground and to shut off the current required to be supplied through resistor 16 to the power supply. Internal circuitry of analog pulse width controller 11 is shown schematically in FIG. 2.

[0004] As shown in FIG. 2, current source 20 provides a charging current to capacitor 21 to generate a ramp voltage across this capacitor. This ramp voltage is provided to the positive input lead of differential amplifier 22a, the negative input lead of which receives the output signal from differential amplifier 22bThe positive input lead of amplifier 22bis connected to the load capacitor 18 and carries a signal representing the voltage across the load capacitor 18. The negative input lead of differential amplifier 22bis connected to the node between resistors 23aand 23bmaking up a voltage divider (one terminal of which is connected to a reference voltage VRef and the other terminal of which is connected to the output lead of differential amplifier 22b). Thus when the output voltage across capacitor 18 is less than the voltage at node A between resistor 23aand resistor 23b, the output voltage from differential amplifier 22bgoes to a low level. This low level output voltage is provided to the negative input lead of amplifier 22a, causing amplifier 22ato produce a positive output pulse. This positive output pulse is transferred to coil to provide a charging current to capacitor 18. With time, the charge on capacitor 18 increases until the voltage across capacitor 18 exceeds the voltage on node A. At this point the output voltage from differential amplifier 22bgoes to a high level, so that the voltage at the negative input lead of differential amplifier 22aexceeds the voltage on the positive input lead of differential amplifier 22a, causing the output voltage from amplifier 22ato go a low level, and thus preventing further charging of capacitor 18. The voltage across coil 15 is negative, reflecting the negative rate of change in current in response to the trailing edge of the pulse from amplifier 22agoing from a high level to a low level. The current through coil 15 does not change instantaneously due to the magnetic field of the coil but rather gradually changes with time. This type of power supply, which is characterized by a current source driving a capacitor, is known as an analog buck converter. Each MOSFET modulation cycle is formed by the precision comparator and the error amplifier. Such a power supply is difficult to scale and integrate into an integrated circuit and is typically fabricated using dedicated analog process technologies at captive semiconductor foundries.

[0005] Accordingly, what is needed is a power supply which provides different level precision voltages and at the same time and is simple to implement with a smaller number of components than in the prior art. Such a power supply must also be relatively inexpensive, robust and reliable.

[0006] In accordance with one embodiment of the present invention, a switching power converter is provided which comprises a ring oscillator made up of a plurality of series-connected inverters, a feedback loop from the output lead of the last inverter in the series to the input lead of the first inverter of the series, a selection circuit capable of selecting at least one output signal from an inverter in the string of series-connected inverters, and an exclusive OR gate receiving the selected output signal on one lead and a reference output signal from an output lead of an inverter in the string of inverters on the other input lead.

[0007] In accordance with another embodiment of the present invention, a switching power converter as described above is structured wherein the exclusive OR gate produces an output signal having a time duration proportional to the number of inverters between the inverters providing the output signals to the exclusive OR gate.

[0008] In a further embodiment, the duty cycle of the output signal from the exclusive OR gate can vary from 0 to close to 100%.

[0009] In a further embodiment of the present invention the frequency of oscillation of the ring oscillator is equal to the number 1/(2nΔ), where n is a number of inverters in the string of series-connected inverters and Δ is the time delay of a signal passing through each of the inverters.

[0010] According to another embodiment of the present invention, the period of the oscillations of the ring oscillator is 2nΔ.

[0011] This invention will be more fully understood in conjunction with the drawings taken together with the following detailed description.

[0012] FIG. 1 shows the basic construction of a prior art analog buck converter.

[0013] FIG. 2 shows the details of the analog PWM controller 11 in FIG. 1.

[0014] FIG. 3 shows the basic structure of a pulse width modulation controller utilizing a ring oscillator in accordance with this invention.

[0015] FIG. 4 shows an alternative implementation of a pulse width modulated controller in accordance with this invention.

[0016] FIG. 5 shows an example of waveforms of the type generated using the structure of FIG. 3.

[0017] FIG. 6 shows a ring oscillator used in accordance with this invention together with a switching matrix used to select the particular output signals from the ring oscillator to be provided to the two input leads of an exclusive OR gate 63 to generate a pulse width modulated signal.

[0018] FIG. 7 shows the waveform of signals generated using the structure of FIG. 6.

[0019] FIG. 8 shows the waveforms generated using the structure of FIG. 6 with an inverter connected between the output lead from each even-numbered inverter in the ring oscillator and the pass-transistors driven by the signals G, H, I, J and K.

[0020] FIG. 9 shows the relative delay times obtained when signals are selected from different combinations of pairs of inverters in the ring oscillator of FIG. 6.

[0021] FIG. 10 shows one circuit for controlling the selection of the particular gates to transfer a selected pair of signals to the exclusive OR gate 63 in FIG. 6 to generate a pulse width modulated signal.

[0022] FIG. 11 shows another circuit used to generate the pulse width modulated signal from exclusive OR gate 63 in FIG. 6 in accordance with the principles of this invention

[0023] FIG. 12 is a block diagram of switching power supply controller 1200, in accordance with one embodiment of the present invention.

[0024] FIG. 13 is a block diagram showing interface signals of digital pulse converter wrapper 1201, according to one implementation

[0025] FIG. 14 is a block diagram showing interface signals of analog to digital converter 1206, according to one implementation.

[0026] FIG. 15 is a block diagram showing the interface signals of Kelvin temperature sensor (KTS) 1500.

[0027] FIG. 15A is an exemplary circuit for KTS 1500 in accordance with one implementation.

[0028] FIG. 16 is a timing diagram illustrating the quad-slope (i.e., dual conversion) analog to digital conversion (ADC) operations carried out in the QSADC module 1211a, which is contained within touch screen interface 1211.

[0029] FIG. 17 is a block diagram showing the interface signals of QSADC module 1211ain one implementation.

[0030] FIG. 17A is a block diagram showing the interface signals of QSADC 1211awith touch screen interface 1211 in one implementation.

[0031] FIG. 18 is a top-level block diagram of QSADC module 1211a, including analog block ANLG 1801, control block CNTRL 1802 and DOWN/UP COUNTER block 1803, according to one embodiment of the present invention.

[0032] FIG. 18A shows one implementation of analog block 1801 of QSAD module 1211ashown in FIG. 18.

[0033] FIG. 18B shows one arrangement of a four-contact touch-screen application.

[0034] FIG. 18C shows one arrangement of a five-contact touch-screen application.

[0035] FIG. 19 is a block diagram summarizing the modules in switching power supply controller 1200, providing a control loop for a battery or power supply management application.

[0036] FIG. 20 illustrates regulation of output voltage Vout using inductor current IL and sensing output voltage Vout, according to one embodiment of the present invention.

[0037] FIG. 21 illustrates the approximation of a weighted average inductor current by duty cycle.

[0038] FIG. 22 illustrates a method under the present invention for estimating the parasitic resistance of an MOS switch.

[0039] FIG. 23 shows flow diagram 2300, illustrating a control method according to one embodiment of the present invention.

[0040] FIG. 24 illustrates a low-frequency closed loop and high-frequency open loop control method, according to one embodiment of the present invention.

[0041] FIG. 25 is a diagram showing switching power supply controller 1200 being used in a battery and power supply management application in, for example, a personal digital assistant (PDA).

[0042] FIG. 26 illustrates the operation of a control loop in accordance of the present invention.

[0043] FIG. 27 illustrates the low-frequency closed loop and high-frequency open loop control method of FIG. 24, showing the signature input values of controlled variables and an open-loop response, according to one embodiment of the present invention.

[0044] FIG. 28 illustrates a sequential transient recovery control method, in accordance with one embodiment of the present invention.

[0045] FIG. 29 illustrates a buck converter.

[0046] FIG. 30 through FIG. 33 show curves of current with respect to time for a supply circuit such as circuit 49, based on the application of different gate drive voltages to the transistors.

[0047] FIG. 34 is a block diagram showing the interface signals of clock generator 12223.

[0048] FIG. 35 shows the port table for the clock generator block shown in FIG. 34 and FIG. 12.

[0049] FIG. 36 shows an exemplary pulse width modulation implementation, which includes a pulse width generator and a sequencer, for digital pulse converter 1201.

[0050] FIG. 36A is an exemplary implementation of the pulse width generator of FIG. 36.

[0051] FIG. 36B is an exemplary implementation of the sequencer of FIG. 36.

[0052] FIG. 36C shows an exemplary feedback control system.

[0053] FIG. 36D shows another exemplary feedback control system.

[0054] FIG. 37 shows a timing diagram for one digital to pulse converter frame for DPC 1201 in accordance with one implementation.

[0055] FIG. 37A shows exemplary interface signals for digital pulse converter 1201 for one implementation.

[0056] FIG. 37B illustrates an exemplary circuit implementation for DPC 1201, which includes a CAM.

[0057] FIG. 37C illustrates one exemplary implementation for the CAM of FIG. 37B.

[0058] FIG. 37D illustrates an exemplary circuit implementation for output logic of the CAM of FIG. 37C.

[0059] FIG. 37E illustrates an exemplary timing diagram for the CAM of FIG. 37C.

[0060] FIG. 38 shows an exemplary implementation of a Grey counter.

[0061] FIG. 38A shows another exemplary implementation of a Grey counter.

[0062] FIG. 38B shows an exemplary implementation for a flip flop of FIG. 38 or FIG. 3BA.

[0063] FIG. 38C shows an exemplary implementation for another flip flop of FIG. 38 or FIG. 38A.

[0064] FIG. 38D shows an exemplary circuit implementation for a logic gate.

[0065] FIG. 38E shows an exemplary circuit implementation for another logic gate.

[0066] FIG. 38F shows an exemplary circuit implementation for a multiplexer.

[0067] FIG. 38G shows an exemplary circuit implementation for binary to Grey and Grey to binary conversion.

[0068] FIG. 38H illustrates an exemplary implementation for a digital pulse converter.

[0069] FIG. 38I illustrates another exemplary implementation for a digital pulse converter.

[0070] FIG. 39 shows a plot of typical gate drive waveforms which may be applied to, for example, the gates of the transistors of circuit 49 and the resulting voltage at terminal S.

[0071] FIG. 40 is a block diagram of SHM 1207 in one implementation.

[0072] FIG. 40A is a functional schematic illustrating voltage and current sampling for one implementation.

[0073] FIG. 40B is a circuit schematic illustrating voltage and current selection for one implementation.

[0074] FIG. 40C is an exemplary interface signal block for SHM 1207 in accordance with another implementation.

[0075] FIG. 40D is a block diagram of SHM 1207 in another implementation.

[0076] FIG. 40E is a functional schematic illustrating voltage and current sampling for another implementation.

[0077] FIG. 40F is a circuit schematic illustrating voltage and current selection for another implementation.

[0078] FIG. 40G is a clock generation circuit in accordance with another implementation.

[0079] FIG. 40H is a voltage divider in accordance with another implementation.

[0080] FIG. 40I is a voltage multiplier in accordance with another implementation.

[0081] FIG. 40J is an exemplary interface signal block for an I/O circuit in accordance with another implementation.

[0082] FIG. 40K is a multiplexer scheme in accordance with another implementation.

[0083] FIG. 41 is a block diagram of the regulation control module (REG) of FIG. 12 according to one embodiment of the invention.

[0084] FIG. 42 shows a gate drive waveform with respect to time.

[0085] FIG. 42A shows a boost converter circuit.

[0086] FIG. 42B shows two switching waveform in time off-set relationship.

[0087] FIG. 43 shows waveform A, B and C illustrating the current which is output for three gate drive scenarios of a switching power supply.

[0088] FIG. 43A shows a plot of the voltage with respect to time at a terminal S intermediate the upper and lower transistors in buck converter 49 of FIG. 29.

[0089] FIG. 43B and FIG. 43C show plots of the voltage at terminal S for two different duty cycles of FET 50 in circuit 49.

[0090] FIG. 44 shows a circuit for generating a high voltage to drive a cold cathode fluorescent light bulb.

[0091] FIG. 44A shows two exemplary sets of gate drive waveforms of the type which could be applied to the gates of the transistors of circuit 1.2.2.12.

[0092] FIG. 45 shows a buck converter circuit.

[0093] FIG. 45A shows gate drive waveforms for the transistors in FIG. 45 and corresponding current and output voltage waveforms.

[0094] FIG. 45B shows a boost circuit.

[0095] FIG. 45C shows gate drive waveforms for the circuit of FIG. 45B and corresponding current and output voltage waveforms.

[0096] FIG. 46 shows switching power supply controller 1200 connected to regulate the operation of two switching power supplies.

[0097] FIG. 46A shows a plot of current with respect to time for one cycle of a switching power supply.

[0098] FIG. 46B shows a buck power supply circuit.

[0099] FIG. 46C shows a plot of current with respect to time for one cycle of a switching power supply circuit.

[0100] FIG. 46D shows a plot of current with respect to time for one cycle of a switching power supply.

[0101] FIG. 46E shows a plot of current with respect to time for a switching power supply circuit.

[0102] FIG. 47 shows switching power supply controller 1200 connected to a plurality of power supplies.

[0103] FIG. 48 shows in block diagram form a processor coupled to two switching supplies, a nonvolatile memory and a Kelvin temperature sensor, with a battery connected to one of the switching power supplies.

[0104] FIG. 48A shows a curve of battery capacity with respect to temperature for a typical battery.

[0105] FIG. 49 shows a block diagram of a power supply system for use in conjunction with a cellular telephone.

[0106] FIG. 49A shows a block diagram for a solar cell array coupled to a power supply being controlled by switching power supply controller 1200 of the present invention.

[0107] FIG. 50 is a block diagram of a spreader divider unit 2482.4 according to one embodiment of the invention.

[0108] FIG. 50A is a circuit diagram of a spectral spreader 210.1 for the spreader divider unit 2482.4 of FIG. 50 according to one embodiment of the invention.

[0109] FIG. 51 is a block diagram showing the interface signals of QSADC module 1211bin another implementation.

[0110] FIG. 51A is a top-level block diagram of QSADC module 1211b, including analog block 2001.4, control block 2002.4, and up/down counter block 2003.4, according to another embodiment of the present invention.

[0111] FIG. 51B shows one implementation of analog block 2001.4 of FIG. 51A.

[0112] FIG. 51C illustrates a block diagram showing exemplary interface signals between touch screen interface 1211 and the other blocks of switching power supply controller 1200.

[0113] FIG. 51D shows a flowchart for performing diagnostics of QSADC module 1211a.

[0114] FIG. 51E shows a functional block diagram corresponding to the implementation of FIG. 51B.

[0115] FIG. 51F illustrates the circuit connections of analog block 1801 for an initial measurement state.

[0116] FIG. 51G illustrates the circuit connections of analog block 1801 to integrate the voltage due to contact with the Y coordinate sheet in a four-contact implementation.

[0117] FIG. 51H illustrates the circuit connections of analog block 1801 to digitally convert the voltage due to contact with the Y coordinate sheet in a four-contact implementation.

[0118] FIG. 51I illustrates the circuit connections of analog block 1801 to integrate the voltage due to contact with the X coordinate sheet in a four-contact implementation.

[0119] FIG. 51J illustrates the circuit connections of analog block 1801 to digitally convert the voltage due to contact with the X coordinate sheet in a four-contact implementation.

[0120] FIG. 51K illustrates the circuit connections of analog block 1801 to integrate the voltage due to contact with the X-Y coordinate sheet in a five-contact implementation due to horizontal position.

[0121] FIG. 51L illustrates the circuit connections of analog block 1801 to digitally convert the voltage due to contact with the X-Y coordinate sheet in a five-contact implementation due to vertical position.

[0122] FIG. 51M illustrates the circuit connections of analog block 1801 to integrate the voltage due to contact with the X-Y coordinate sheet in a five-contact implementation due to horizontal position.

[0123] FIG. 51N illustrates the circuit connections of analog block 1801 to digitally convert the voltage due to contact with the X-Y coordinate sheet in a five-contact implementation due to horizontal position.

[0124] FIG. 51O illustrates the circuit connections of analog block 1801 to detect continuity between the resistive sheets in a four-contact implementation.

[0125] FIG. 51P illustrates the detection of contact for a five-contact implementation.

[0126] FIG. 52 illustrates a block diagram of LED control block 1214.

[0127] FIG. 53 is a block diagram for the watchdog module of FIG. 12 according to one embodiment of the invention.

[0128] FIG. 54 is an exemplary functional diagram of Internal Voltage Supply (IVS) 1209 in accordance with one implementation.

[0129] FIG. 54A is an exemplary interface block diagram for IVS 1209 in accordance with another implementation.

[0130] FIG. 54B is another exemplary functional diagram of IVS 1209 in accordance with another implementation.

[0131] FIG. 54C is an exemplary flowchart for a power-up sequence for IVS 1209 in accordance with another implementation.

[0132] FIG. 55 is an exemplary functional diagram of NFET driver module 1202 in accordance with one implementation.

[0133] FIG. 55A illustrates exemplary interface signals of NFET driver module 1202 in accordance with another implementation.

[0134] FIG. 55B illustrates exemplary interface signals of NFET driver module 1202 in accordance with another implementation.

[0135] FIG. 55C shows an exemplary functional diagram for the implementation of FIG. 55B.

[0136] FIG. 55D illustrates an application,employing internal buffers to directly drive an external coil for the implementation of FIG. 55B.

[0137] FIG. 55E illustrates an application employing internal buffers to drive external FETs for the implementation of FIG. 55B.

[0138] FIG. 55F shows an exemplary on-chip configuration block diagram for the implementation of FIG. 55B.

[0139] FIG. 56 is a block diagram of central processing module (SYS) 1205 of FIG. 12 according to one embodiment of the invention.

[0140] FIG. 57 shows a circuit model of converter 2570 of FIG. 25.

[0141] FIG. 58 is a flow chart illustrating the steps of control algorithm 5800, in accordance to with one embodiment of the present invention.

[0142] FIG. 59 illustrates the operation of control algorithm 5800 of FIG. 58.

[0143] The following detailed description is intended to illustrate the embodiments discussed herein and is not intended to be limiting of the scope of the present invention. Other embodiments of this invention will be apparent to those skilled in the art in view of this disclosure.

[0144] The present invention is applicable to a power converter and power management peripheral that integrates a set of power-management related functions. Switching power supply controller 1200, shown in FIG. 12 in block diagram form, illustrates an implementation of a switching power converter controller product, according to one embodiment of the present invention. The system implements substantially all of a power converter's expected functions, such as maintaining a steady output voltage (constant voltage power supply) that is substantially independent of the current drawn from the power supply or maintaining a steady output current (constant current power supply) that is substantially independent on the load applied to the power supply, deciding when to shed loads, and measuring the state of charge in a battery, charging the battery, and performing battery sequencing. In addition, the system performs a number of other peripheral management functions, such as digitizing a touch panel, scanning a keyboard, and conditioning reset signals received from the rest of the system. In one embodiment, watch dog timer functions are provided to allow power-cycling and to provide reset signals to different subsystems of the product, in response to an exception condition, such as a software lock up or even a hardware lock up (e.g., an SCR latch up or a disruption due to an IO transient). The system of the present invention also controls LEDs that indicates the statuses of various subsystems. Thus, a system according to the present invention can handle a large number of functions that a portable electronic device (e.g., a PDA) performs when the processor of that PDA is powered down, such as between pen strokes (while the user is writing a note on the PDA), or when the PDA is displaying information, but no input or output is expected. In this implementation, the product includes a digital control subsystem that controls various digital interfaces, including reset signals, watch dog timers, enable signals, status signals for indicating individual status of internal power supplies. Communication among elements of the system is provided through a communication interface. In one embodiment, the present invention includes a time base generation circuit and a digitizer interface to a keyboard.

[0145] Referring to FIG. 12, substantially all of the digital interface functions are performed by an internal 8051 or a comparable microprocessor which is included in central processing module (SYS) 1205 and which communicates with the outside system with a number of interfaces through a number of general purpose input/output (GPIO) signals that can be defined in software in the microprocessor and mapped flexibly to individual input or output pins or terminals of the integrated circuit. For example, each pin can be defined to carry a high true or a low true signal, and can be defined to be an input signal or an output signal. In addition, each pin can be assigned to any of the individual power supply elements and can be shared so that more than one power supply can receive the same control signal from a single pin. In this manner, for example, a single enable signal may be shared amongst multiple power supplies. The GPIO signals can be used to implement input and output signals of some of the peripheral devices. For example, the keyboard scanner functions interact with an external keyboard through the GPIO signal interface. The watch-dog timer may receive input signals and status information from circuits external to the integrated circuit. Also, interrupt signals can share pins with the GPIO signals. This implementation thus provides a rich set of functionality to allow the product to be capable of being made “plug-compatible” with prior art solutions that were based on separate discrete devices. Central processing module (SYS) 1205 handles serial communication on and off the chip. Every signal which can be implemented as a GPIO signal, except an interrupt signal, can also be implemented as a serial communication signal. In an application designed for prior art devices, serial communication can be used to access a keyboard and coulombmetric measurement capabilities. The GPIO signals can be used to turn on and off individual power supplies and to monitor their statuses.

[0146] A computation circuit, which may be provided as a very long instruction word processor (“VLIW engine”) to simplify decoding logic, is included in regulation control module (REG) 1204 (labelled in FIG. 12 as “REG”). The VLIW engine executes low level commands from central processing module (SYS) 1205 (labeled in FIG. 12 as “SYS”). Regulation control module (REG) 1204 receives and interprets the measurements of voltages and currents from the various circuits supplied by the regulated power supply pins. Using a number of different types of control loops, regulation control module (REG) 1204 provides to digital pulse converter (DPC) 1201 commands in the form of precisely modulated signals, which then are used to operate external components through NFET driver module 1202. Together with the external components, switching power supply controller 1200 forms one or more power converters of various designated topologies.

[0147] One unique feature of the system according to the present invention is that the system is programmable. In addition to allowing every function, mode and regulation parameters to be preset, the specifications of external components can be stored internally in the integrated circuit and used to perform the regulator functions. Thus, regulation control module (REG) 1204 operates with a large amount of information about the characteristics of the power converter components external to switching power supply controller 1200. Unlike a prior art switching power supply controller circuit implemented in analog technology, a power supply controller circuit of the present invention “knows” the output voltage it's trying to attain (“target voltage”) and the error(i.e., the difference between the current output voltage and the target voltage). Typically, prior art analog converters correct the error using algorithms that are independent of the current switching duty cycle or the value of the input voltage. Such prior art converters also do not internally store information about the external components. An engineer attempting to design with such a prior art power supply controller circuit can only provide “hints” to the power supply controller circuit in the form of compensation networks. In contrast, a power supply controller circuit according to the present invention has many advantages and benefits over the prior. For example, having information regarding the current output voltage and duty cycle, the target voltage and the internally stored parameter values of the external circuit allows the power supply controller to calculate the potential duty cycles that would result in the correct output voltage to high precision and to select a realistic response that observes the constraints of the external circuit (e.g., the saturation current of an inductor). Proper response to external circuit anomaly limits the amount of noise that's reflected to the power supply controller circuit. For example, by controlling the transient noise currents through the power controller circuit, a battery or a long wire that provide the supply voltage to the power controller circuit could experience and possibly radiate less electromagnetic interference (EMI).

[0148] A programmable keyboard scan function is implemented in central processing module (SYS) 1205, and allows individual keys to be scanned or detected after a key has been pressed to awake the keyboard scanning circuit from a stand-by state. A watch dog function is performed with software in central processing module (SYS) 1205, and provides full-featured watch-dog timer functions. Watch dog timer functions may be used to handle software faults in a system. For example an external processor running a complex operating system (e.g., Win CE) may periodically briefly assert (“toggle”) a signal on a specified pin. The watch dog timer resets its timer whenever the signal on the specified pin is toggled. When a malfunction occurs in the software of the host microprocessor, such that the signal on the specified pin is not toggled within the scheduled time, then a set of pre-programmed actions are taken to recover operation of the external system processor. These actions range from simply resetting the processor or another circuit element, or cycling the processor's power off and on. Power-cycling removes current from parasitic SCRs that may be present in the processor or other integrated circuits, thereby affecting a recovery from a semiconductor latch-up state. Other anomalies that would normally not be recoverable using logic or reset signals may also be corrected through power cycling.

[0149] Central processing module (SYS) 1205 controls external status LEDs, or a single multi-color LED. Internal reset logic which is included in internal voltage supply 1209, provides a power-on reset to allow internal clocks and internally generated voltages to stabilize prior to operation. This is a different and distinct concept from the host reset conditioning feature described below, which is implemented in software and runs on the internal microcontroller. The host reset conditioning software conditions the external system's reset signal with the status signals of the power supplies, and external signals at the product's input pins.

[0150] Touch screen interface 1211 uses a dual-slope technique to read the X and Y coordinates of a resistive touch panel display. In a PDA, this digitization operation, because of the large area of the display, is quite subject to noise induced by the back light. In the prior art, a typical back light is implemented by cold cathode fluorescent light (CCFL), which is essentially a fluorescent light bulb that does not have a cathode heater to raise the energy of the internal gas for ionization at a low voltage. In CCFL, for a typical device, initial ionization (“ignition”) is brought about using an AC voltage of 700 volts or more, and an AC voltage of over 300 volts, is used thereafter to maintain the ignition. The high voltage AC waveform that is driving the CCFL is a potentially serious source of noise to the touch panel, which is made up of panels of resistive material and is located only a few millimeters away directly in front of the display. Touch screen interface 1211 uses a quad-slope analog-to-digital converter circuit which operates synchronously with the back light voltages generated by the power supply controller. By operating synchronously with the back light, the noise from the back light is integrated over an even number of cycles, thereby effectively removing it without a of complex filtering or an algorithmic approach.

[0151] Internal voltage supply 1209 is the power supply for switching power supply controller 1200, deriving from either one of two external supply pins, or one of two external battery pins the internal voltages required for the operations of the various blocks, including central processing module (SYS) 1205 and regulation control module (REG) 1204. In addition to providing the various voltages required for the various subsystems, internal voltage supply 1209 also provides the crystal oscillator function (other than the crystal, which is off-chip) various charge pumps for creating internal supplies, and comparators to indicate when the supplies are stable for use by internal processing elements.

[0152] Sample and hold module 1207 includes an array of sample and hold circuits and scaling circuits. Sample and hold module 1207 monitors the various points within the output sections of the power supplies, measuring voltages and currents, input voltages, and temperatures at various points. Sample and hold module 1207 provides its data, one sample at a time, to analog to digital converter 1206 (a system shared resource), which converts the external analog samples into digital samples. The digital samples are used by regulation control module (REG) 1204, or passed upstream to central processing module (SYS) 1205. In this embodiment of the present invention, the analog to digital converter and the sample and hold structures are based on either ratios of capacitors or unity gain. Thus, calibration can be achieved using a single calibration.

[0153] NFET drivers module 1202 include a set of output drivers which operate in one of two modes. The first mode is to drive external power MOSFET devices. In this mode, each output voltage is associated with two sets of driver circuits; one for driving the control FET and the other one for driving the sync FET. For modest currents, the two driver circuits may be used in another mode of operation where they are driven together, and their output signals may be connected together, to drive an external coil directly in a power switching function.

[0154] A power supply utilizing the present invention can be completely programmable, i.e., no external discrete components have to be chosen to set voltages and currents and a single chip can perform many different functions across many different products. Such programmability has the benefit of reducing the component count on a circuit board. It also has the benefit of reducing the number of parts that an individual manufacturer of an end product would have to stock since this same device can be used across many different applications. All of these features can be preset, either at the time the chip is manufactured, at the time that it is delivered, i.e., through a distributor, using programming techniques similar to those used with programmable logic array devices. Alternatively, the system of the present invention can be programmed by a customer even on the circuit board during the in-circuit test phase or final test for their product. Further, even though all these functions can be programmed, the values programmed during manufacturing and test are used merely as initial conditions and may be changed dynamically (i.e., during operation) by the system containing the power supply controller. For example, the system can reprogram the internal voltages and currents dynamically, as is often required in complex microprocessors which require different voltages for different modes of operation. Reprogramming activity can also be done for the purposes of dimming displays and controlling motors. Digital-to-analog conversion functions can be implemented by rapidly changing the output voltages of the regulators. Switching power supply controller 1200 features a completely programmable start-up and shut-down sequence, so as to allow a system using power supply controller 1200 to be started in a sequence that would avoid a latch-up conditions. For example, the I/O structure of a microprocessor is often required be powered before the microprocessor core. To reverse the order could result in damage or destruction of the microprocessor or cause a malfunction. A specific power sequence is also required for powering down these devices. In prior art solutions, this timing is set rather crudely by resistors and capacitors or not at all.

[0155] The individual power supplies controlled by switching power supply controller. 1200 can be programmed for a wide variety of topologies, so that if a voltage which is higher than the input source, lower than the input source, or sometimes the same as the input source can be accommodated. For example, a boost converter topology is used for a power supply having an output voltage that is higher than the input voltage, a buck converter topology is used for a power supply having an output voltage that is lower case than the input voltage, and a sepic topology is used for a power supply having the same input and output voltages. When very high voltages are required (i.e., a cold cathode fluorescent light bulb or even a photographic strobe in a digital camera), topologies such as half-bridge may be used. All of these can be programmed and any number of them can be present in the design at any time, and any combination of these topologies may be supported simultaneously.

[0156] Switching power supply controller 1200 of the present invention can also perform dimming using pulse width modulation. This ability is important for cold cathode fluorescent lights because, typically, a simple reduction of current provides insufficient energy to ionize the entire display, resulting in the so called “thermometer effect” where only part of the back light is actually illuminated. Another application where PWM dimming is desirable is in white LEDs. White LEDs suffer an esthetically unacceptable shift in hue or color, as a function of current. Using pulse-width modulation for dimming white LEDs maintains a constant current during “on” time, so that a constant color is maintained over a large dimming range. Switching power supply controller 1200 also has input pins for use in temperature compensation: an internal temperature sensor is included, as well as external pins for reading an external temperature sensor. Temperature compensation is used in battery-charging to tailor a rate of charge, to respond to unsafe environmental conditions, to detect fault conditions and to prevent the destruction of external batteries or damage due to excessive heat build-up. The internal battery charger algorithms accommodate a number of different chemistries (e.g., lithium ion). Any chemistry can be accommodated since battery charging algorithms are provided in software to be executed in central processing module (SYS) 1205.

[0157] Switching power supply controller 1200 also allows selection between different batteries as its power supply. Central processing module (SYS) 1205 can be programmed to use an external battery first, thus preserving its internal battery for emergency situations or while the external battery is being changed. It can also automatically choose to charge the internal battery first, and then external accessory batteries second. Central processing module (SYS) 1205 computes how much energy is available and charge both batteries at the same time or use them in parallel. Another function provided by a product using the present invention is the ability to provide the voltage, current and coulombmetric data to the outside system. This permits independent direct control over the voltage regulator functions and intermediate readings of the amount of energy available in a battery before an individual threshold. A system encompassing the present invention also maintains a charge acceptance history. This is useful in determining whether the battery may be fully charged. It's also an early indicator of battery wear out and provides a basis for limiting overcharge events where the battery may be indefinitely charged because of some sort of malfunction.

[0158] In accordance with one aspect of the present invention, the individual switching waveforms of the product are carefully staggered so that the amount of energy that is derived from an external power source, for example, a battery, is made as uniform as possible around all of the different outputs that require power. This effectively raises the frequency of the current required from the external source and may reduce the peak current demanded from an external source, which reduces the amount of noise on that external source and also reduces the noise radiated from the interconnecting wires to the external source and makes the noise easier to filter. Additionally, a spread spectrum approach is applied to internal frequencies. This reduces the net energy at a given frequency from external switching power supply functions. That is to say that instead of always operating at a constant frequency, the spread spectrum feature allows the switching frequency to be varied rapidly and that frequency modulated using industry standard patterns so that the energy at any particular frequency is reduced. The spread spectrum feature effectively reduces noise that would be experienced by an associated radio either within a product using the present invention,.within the end product that this chip is implemented within or other products that are nearby. The frequency of operation can also be determined by external sources. In one embodiment, a 32 kilohertz crystal oscillator generates all the internal clocks and provides a 32 kilohertz time based output for use by other elements within the system. According to another feature, the system provides an external clock which is guaranteed to be 20 nanoseconds away from the nearest switching edge. This unique feature allows the external system to conduct sampling synchronously with the switching power supply functions in the same way the system synchronously samples to reduce switching noise internally. Normal switching prior art switching power supplies, since they have no knowledge of what duty cycle they're going to provide in any given cycle, have no way to provide this information ahead of time. Since all of the pulse width modulators used in the present invention are digital, this is achieved by another control signal that is scheduled within the array of control signals that make up all the pulse width modulators.

[0159] Referring to FIG. 12, clock generator macro 1223 (CLKGEN) generates clock signals required by the modules illustrated in FIG. 12. The clock generator module 1223 is illustrated in greater detail in the high level block diagram of FIG. 34 which shows the interface signals. The clock generator generates the clocks based on a source clock signals provided by digital pulse control module 1201. These source clock pulses are received by clock generator module 1223 over CST[9:0] output bus 1223.2 and the output ports PLOCK and PLLCK from DPC 1201 which are provided on interfaces 1223.4 and 1223.1, respectively. In the table below, the frequencies of the signals on the CST bus 1223.2 are illustrated.

[0160] Referring to the various interfaces to clock generator 1223, the CST interface from DPC module 1201 is comprised of a 10-bit bus indicated by reference character 1223.2 and FIG. 34. The bus is connected to the output of the GREY counter in DPC 1201 and provides the majority of the source clocks for clock generator 1223. Table 102A shows the frequency of the signals on each of the bus lines CST[0] to CST[9].

[0161] The 2-bit bus PD_OUT[1:0] indicated by reference character 1223.3 controls the mode of operation of the generated clock signals. Power modes of operation are designated as Standard, Low Power and Shut Down. Table 102B below shows the modes as function of the signals on the 2-bit bus.

[0162] The clock signal to analog to digital-converter 1206 is provided over line 1223.7 and the frequencies at the various modes are indicated as set forth below in Table 102C. The Low Power and Standard mode frequencies are derived from the 538,870.921 khz DPLL clock through a division by 5.

[0163] The clock signal to the sample and hold block 1207 is provided over line 1223.9. The frequency which is needed for the various modes of operation is shown in Table 102D below.

[0164] The Standard mode frequency is derived from bit CST[4] bit, and the Low Power mode frequency is derived from a division of the CST[8] bit by 2.

[0165] The clock signal to the internal voltage supply 1209 is provided over line 1223.8 and the frequencies needed for the various modes of operation are illustrated in Table 102E below. The Standard mode frequency is derived from the CST[4] that, in the Low Power mode frequency is derived by the division of the CST[8] bit by 2.

[0166] The clock signals for touch screen interface 1211 are provided by the QSADC_CLK. The frequencies for the various modes of operations are shown in Table 102F below. The Low Power and Standard mode frequencies are derived from the CST[8] bit through a division by 2.

[0167] Regulation control module (REG) 1204 is provided clock signals for the Standard, Low Power and Shut Down modes by the clock generator 1223, and the frequency for each is indicated in Table 102G below. The frequencies for the various modes are derived, for example the Standard mode by using CST[0] bit and the low power operating frequency is derived from bit CST[8] through a division by 4. In addition, CLKGEN 1223 provides the SHM CLK and SYS CLK clock signals to regulation control module (REG) 1204.

[0168] Table 102H illustrates the modes and frequencies for those modes for the clock signal provided to central processing module (SYS) 1205. As illustrated in Table 102H, in the Shut Down mode the frequency is 0. For the Low Power and Standard modes, the frequencies are identical and they are derived from CST[2].

[0169] The LED_CLK is a clock used for the LED block which is associated with central processing module (SYS) 1205. The frequencies for the various modes of operation are indicated in Table 102I below. The Standard Mode frequency is derived from the CST[8] through a division by 2.

[0170] A digital supply voltage of 3.3 V+300 mV is provided to clock generator block 1223 via VDD which is connected to the core digital power supply. Similarly, VSS is provided over line 1223.6 and is the core digital ground.

[0171] Turning to FIG. 35, the port table is illustrated showing the port names, whether it is an input or an output, the description as well as the source and destination of the signals for those ports.

[0172] Referring to FIG. 12, reset circuit 1221 generates the resets for switching power supply controller 1200. The signals received by this circuit and produced by the circuit are indicated within the block. As with the other circuits shown in FIG. 12, the arrow adjacent to the signal name indicates whether the signal is generated by or received by reset circuit 1221.

[0173] Digital Pulse Converter wrapper 1201 can be implemented as a combination of a custom mixed-signal circuit (DPC) and an interface wrapper of digital glue logic synthesized from a logic circuit description expressed in a hardware description language (HDL). In this implementation, digital pulse converter wrapper 1201 converts 10-bit digital values to pulses with edges resolved to about 2 ns. As explained in further detail below, dual-port memory block with a single write port and a single read port is provided to store 10-bit values that express pulse start and width control, cycle skipping and bypass circuitry control (for direct output control).

[0174] FIG. 13 is a block diagram showing interface signals of digital pulse converter wrapper 1201, according to one implementation. As shown in FIG. 13, digital pulse converter wrapper 1201 has five interfaces: (a) timing control interface 1301, (b) regulation control interface 1302, (c) power regulation interface 1303, (d) sample and hold control interface 1304, and (e) power supply interface 1305.

[0175] Timing control interface 1301 includes 32 KHz, 50% duty cycle reference clock signal 1301a(FREF), reference clock bypass control signal 1301b(BYPASS), digital phase-locked status signal 1301c(PLOCK), count time state bus 1301d(CS[9:0]), and output state bus 1301e(STATE[15:0]), which are used to provide clocks and control states for the circuitry external digital pulse converter wrapper 1201. In this implementation, reference clock signal 1301a(i.e., signal FREF) is a reference clock provided to a digital phase-locked loop (DPLL) in digital pulse converter wrapper 1201 for frequency synthesis, and bypass controls signal 1301b(i.e., the BYPASS signal) is a test control signal used for bypassing the DPLL. PLOCK is a status signal indicating a phase-locked condition of reference clock signal 1301ain the DPLL. Count time state bus 1301d(i.e., bus CS[9:0]) is a 10-bit clock state bus which provides the clocks and control states to synchronize the DPC, the interface and other core circuits of switching power supply controller 1200. While count time state bus 1301dcollectively displays the time state of the DPC, individual bits of count time state bus 1301dcan be used as 50% duty cycle clocks. For example, if a 31.25 KHz reference clock is used, bit CS[9] corresponds to a 256 KHz clock with a 50% duty cycle, bit CS[8] corresponds to a 512 KHz clock with a 50% duty cycle. In general CS[n] corresponds to a 50% duty cycle clock with frequency f(n,m)=2^−(n+m)f₀, where n ∈ {0, 1, . . . , 9} and m ∈ {0, 1, . . . , 6}. Output state bus 1301e(i.e., bus STATE[15:0]) is a 16-bit state bus which displays the internal state of switch control buses 1303aand 1303b(described below) prior to passing through the direct control logic used by regulation control interface 1303 to force the output signals of switch control bus 1303a(i.e., HIGHFET) and switch control bus (i.e., LOWFET) to specific states. Bus 1301esignals when write operations can occur to the DPC core circuit.

[0176] Regulation control interface 1302, which provides access to the dual-port memory in digital pulse converter wrapper 1201, includes memory write data bus 1302a(DWI[9:0]), memory address bus 1302b(ADW[7:0]), memory read data bus 1302c(DWO[9:0]), write-enable signal 1302d(WE) and read-enable signal 1302e(RE). Regulation control interface 1302 controls the offsets and pulse widths for the various pulses in power regulation interface 1303.

[0177] Power regulation interface 1303 includes switch control bus 1303a(HIGHFET[6:0]) and switch control bus 1303b(LOWFET[6:0]). Sample and hold control interface 1304, which controls the sampling and holding of analog voltages for digital conversion by the ADC used in the system control loop, includes a first sample control bus 1304a(SMPA[6:0]), a second sample control bus 1304b(SMPB[6:0]), and an auxiliary control bus 1304c(SMPAX[3:0]). The timing for each bit in the sample buses 1304aand 1304bis associated with each bit of the corresponding switch bus 1303aor switch bus 1303b. Each of sample buses 1304aand 1034bcontrols the sampling and holding of analog voltages associated with either the HIGHFET or LOWFET control buses for digital conversion. Sampling control bus 1304c(i.e., auxiliary sample SMPAX[3:0]) controls the sampling of other analog signals needed for system monitoring and control.

[0178] Power supply interface 1305 includes digital power reference 1305c(VDD), analog power reference 1305d(AVD), digital ground reference 1305a(VSS) and analog ground reference 1305b(AVS). Digital power and ground reference signals (i.e., VDD and VSS references) are global signals. In this implementation, VDD is the digital high voltage supply (3.3V±10%) connected to the core digital power supply. AVD is the analog high voltage supply (3.3V±10%) connected to the core analog power supply. VSS and AVS are, respectively, the digital ground and analog ground references (0V) connected to the core digital ground reference.

[0179] FIG. 3 shows a supply management controller of a type in accordance with this invention. As shown in FIG. 3, a ring oscillator includes inverters 301-1 through 301-15 connected in series. In an actual embodiment of this invention, the ring oscillator may include a larger number of series-connected inverters. For example, a thousand inverters can be connected in series, with the result that the duty cycle achieved by the controller of this invention can be almost 100%. However, to simplify explanation, only 15 inverters will be illustrated in this detailed description. The inverters each have inherently a delay “Δ,” which is the elapsed time between the time a signal is applied to the input lead to the inverter and the time the resulting output signal is obtained on the output lead of each inverter. This time “Δ” is a function of the voltage applied to the components contained within the inverter. By varying the voltage applied to the inverter's components, the actual delay time Δ associated with an inverter can be varied. A typical inverter in CMOS technology will contain a P-channel MOS device series connected with an N-channel MOS device between a voltage source and a reference voltage, typically system ground. Should buffers be used with an inverter an additional four transistors may be used giving each inverter six transistors. The delay associated with the transmission of a signal through the inverter is a function of the voltage applied to the inverter. The higher the supply voltage applied to the inverter, the slower the transmission of the signal from the input to the output lead and the larger the delay Δ.

[0180] In the structure of FIG. 3 a crystal 302 capable of oscillating at 32.768 KHz is connected by leads 303aand 303bto an inverting amplifier 304. Amplifier 304 provides a voltage across the crystal to cause the crystal to oscillate at 32.768 KHz, thereby causing the output signal from inverting amplifier 304 to oscillate at the frequency of crystal 302. The output signal of the ring oscillator is divided by eight in divided-by-eight circuit 305 and then sent to phase comparator 306, which receives also the output signal from oscillator 302. Thus the control frequency of the ring oscillator is 262.144 KHz, eight times the normal frequency of crystal 302.

[0181] The normal operating frequency of the ring oscillator is generally selected to be approximately the 262 Khz. The phase comparator 306 senses the phase difference between the phase of the divided-by-eight output signal from the ring oscillator and the phase of the signal from crystal oscillator 302. Phase comparator 306 provides this phase difference in an output signal on lead 306ato Vcc control circuit 307 to correct any deviation in the frequency of the ring oscillator's divided-by-eight output signal from the control frequency 32.768 Khz associated with crystal oscillator 302. Should the ring oscillator be at too low a frequency, then Vcc control circuit 307 is driven to provide a higher voltage on lead 307ato the inverter 301-15, thereby decreasing the delay time associated with this inverter and thus increasing the oscillating frequency of the ring oscillator. Alternatively, if the operating frequency of the ring oscillator is too high, then Vcc control circuit 307 provides a lower output voltage on output lead 307a, thereby increasing the delay time through inverter 301-15 and thus lowering the voltage associated with this inverter.

[0182] Phase selector 308 controls the width of a pulse width modulated (PWM) output signal on output lead 310 from exclusive OR gate 309. Each of the two input leads to exclusive OR gate 309 is coupled by phase selector 308 to a tap associated with one output lead from an inverter 301-i in the ring oscillator. The output leads from the even-numbered inverters 301 are connectable one at a time to input lead 309aof exclusive OR gate 309. The output leads from the odd-numbered inverters 301 are connectable one at a time to input lead 309bof exclusive OR gate 309. The particular output leads from inverters 301-1 through 301-15 to be connected to input leads 309aand 309bof inverter 309 are selected depending upon the requirements of the power supply being driven by the PWM signal on output lead 310 from exclusive OR gate 309.

[0183] Exclusive OR gate 309 will have a high output whenever its inputs are different. This happens each time a high edge or a low edge propagates through the ring oscillator past the inverters that the exclusive OR gate is attached to. Since one cycle of the ring oscillator contains both a rising edge and a falling edge, the PWM signal observed at output lead 310 of exclusive OR gate 309 will be twice the frequency of the ring oscillator.

[0184] The normal frequency “f” of the ring oscillator (made-up of inverters 301-1 through 301-15) is given by the delay time “Δ” associated with each of the inverters. Thus if all inverters have equal delays, then the normal frequency f=1/(2nΔ) where n is the number of inverters and Δ is the delay time associated with each inverter. Thus the frequency is inversely proportional to the number of inverters. The period of the ring oscillator is given by 1/f. Thus if the number of inverters equals 1,000 and the delay associated with each inverter is 10⁻⁹seconds, then the frequency is 500 Khz and the period is 2 microseconds.

[0185] The various pulse widths which the system is capable of achieving are determined by the taps on the output leads of the inverters which are connected to the input leads 309aand 309bof exclusive OR gate 309.

[0186] Section 1.1.2 Second Embodiment of the PWM Timing Generator

[0187] FIG. 4 shows an alternative embodiment of the invention employing counters and comparators to generate a pulse width modulated signal. A five bit counter 41 (although a different number of bits can be used if desired) counts from 0 to 31 driven by a 16.7772 MHz signal. The instantaneous count from 5 bit counter 41 is sent on 5-bit bus 42 to comparators 43aand 43b, each of which compares the count to a reference count stored in it. Digital comparator 43awill store one count determined by the signals on phase select bus 44aand digital comparator 43bwill store a second count determined by the signals on phase select bus 44b. The signals on phase select bus 44aand phase select bus 44bare determined by external circuitry which measures the voltage on the load capacitor and the current into the load capacitor and compares the voltage and current to reference values to determine the extent to which the charge on the load capacitor must be replenished. This is accomplished by switching power supply controller 1200, using in particular sample and hold circuit 1207, analog to digital converter 1206 and regulation control module (REG) 1204. These circuits, as well as their operation and the operation of the system are described in detail below. The output signal from digital comparator 43atoggles a D flip-flop 45aand the output signal from digital comparator 43btoggles a D flip-flop 45b. The inverting output signal from D flip-flop 45ais transferred on lead 47ato the input lead of a delay line 48a. The delay line has a length determined by bits 4-0 so as to correspond to the time taken to drive the 5-bit counter to the particular value which causes digital comparator 43ato toggle flip-flop 45a. The output signal from the delay line is transferred on lead 49ato one input lead of exclusive OR gate 49.

[0188] 5-bit counter 41 continues counting after finding a match in digital comparator 43auntil another match is found in digital comparator 43b. The particular value of the count in digital comparator 43bis set by bits 9-5 derived from phase select-red bus 44bas described below. The match results in input signal being sent from digital comparator 43bto D flip-flop 45b. D flip-flop 45bthen produces an output signal on lead 47b, which is transmitted to the input lead of delay line 48b. Delay line 48bthen produces a high level output signal on lead 49bto exclusive OR gate 49. During the time that the output signal from delay line 48ais high and the output signal from delay line 48bis low, a pulse width modulated signal will be produced by exclusive OR gate 49 on output lead 49c. When however, the output signals on output leads 49aand 49bare the same level, exclusive OR gate 49 will produce a low level output signal on output lead 49c. Thus the output signal from exclusive OR gate 49 is phase-modulated in response to the signals on phase select-green and phase select-red buses 44aand 44b, respectively.

[0189] Selecting 16.7772 MHz to drive 5-bit counter 41 causes it to cycle through its complete count 524,287 1/2 times per second. In other words, the output frequency of the signal on lead 49cfrom circuitry FIG. 4 is 262,144 KHz. FIG. 5 illustrates waveforms of a string of 13-series connected inverters. The top curve represents the input signal to the first inverter. The second curve represents the output signal from the second inverter. The third curve represents the output signal from the fourth inverter and the fifth, sixth, seventh and eighth curves represent the output signals from the sixth, eighth, tenth and twelfth inverters, respectively. The bottom curve represents the pulse width modulated output signal from the circuit as shown in FIG. 3 or FIG. 4. Note that, in this example, the output signal is controlled by the signals input to the series-connected inverters and the signal output from the tenth inverter. Note that the output signal is off when the signal input to the series-connected inverters and the signal output from the tenth inverter are the same amplitude and is on when these two signals are of complementary amplitudes. In one embodiment, discussed below, where the PWM signal drives a main switch of a DC/DC converter, the output current is sampled when the switch is on as shown by the dashed line and the output voltage is sampled when the switch is off as shown by the dashed line at the left hand portion of the curves. The output frequency of the pulse width modulated signal is 524;288 Hz while the frequency of change of the signals from the series-connected inverters is half this frequency over 262,144 Hz

[0190] Section 1.1.3 Discussion of Counter+Comparators Approach—Without Delay Lines—Optimization Techniques in the Implementation

[0191] Digital Pulse Converter wrapper 1201 may have various implementations and include various types of interfaces to perform its functions (e.g., pulse width modulation), as described herein. For example, pulse width modulation may be performed utilizing 1) a low frequency digital phase locked loop (DPLL) voltage controlled oscillator (VCO) with inverter stages and taps (e.g., as described in reference to FIG. 3), 2) a high frequency DPLL with a counter combined with a digital comparator, or 3) a DPLL combined with a content addressable memory (CAM) to generate the required pulse width modulated signals.

[0192] FIG. 36 shows an exemplary pulse width modulation implementation, which includes a pulse width generator (PWG) 2300.4 and a sequencer 2302.4, for digital pulse converter 1201. As illustrated herein, this exemplary pulse width modulation implementation is directed to a high frequency DPLL with a counter combined with a digital comparator (i.e., example 2 as listed above), with one DPLL/counter/comparator combination for each power supply to be regulated.

[0193] PWG 2300.4 receives a 10-bit trigger (TRG[9:0]) signal and an 8-bit tag (TAG[7:0]) signal from sequencer 2302.4, along with a reference clock (FREF) and a reset (RST) signal. PWG 2300.4 generates a lock (PLOCK) signal, a sequencer clock (SCLK) signal, a pulse width modulation (PWM[7:0]) signal, and a clock (CLK[m:n]) signal. Sequencer 2302.4 generates the trigger (TRG[9:0]) signal and the tag (TAG[7:0]) signal and receives the global reset RST signal and a data (DATA[p:0]) signals from a control logic block such as regulation control module (REG) 1204. Sequencer 2302.4 also receives or provides control (CNTL[q:0]) signals.

[0194] The tag signal allows the start and stop times of different PWM signal outputs to occur at the same trigger value (i.e., time). This allows the PWN start and stop times to slide through each other (i.e., vary independently in time relative to each other) during normal operation. As an example of a sequence control, the trigger signal values (n0, n1, n2, . . . , n15) correspond to the tag signal values (t0, t1, t2, . . . , t15), where 1023≧n15> . . . >n2>n1>n0≧0 (where 1023 represents a time duration from 0 to 1023 from a counter). If t1 corresponds to the start of the PWM[3] signal and t8 corresponds to the stop of the PWM[3] signal, then the pulse width of the PWM[3] signal is PWM[3]=(n8-n1)τ, where τ≅2 ns.

[0195] FIG. 36A is an exemplary implementation of pulse width generator 2300.4 of FIG. 36. FIG. 36A includes a DPLL 2304.4 that generates the lock signal and an output frequency (F_OUT) signal that is provided to a divider counter 2308.4 that generates the clock signal. The most significant bit of the clock signal is divided by 16 (by divider 2306.4) to provide a feedback signal for comparison to the reference clock. Divider counter 2308.4 also generates a 10-bit count (CNT[9:0]) signal that is compared to the trigger signal by a comparator 2310.4, whose output is clocked out to a PWM circuit 2314.4 via a flip flop 2312.4.

[0196] PWM circuit 2314.4 also receives the tag signal and generates the PWM signal and the sequencer clock signal. An exemplary circuit implementation for PWM circuit 2314.4 is illustrated by a circuit 2316.4.

[0197] FIG. 36B is an exemplary implementation of sequencer 2302.4 of FIG. 36. FIG. 36B includes a series of registers 2330.4 (which are separately referenced as 2330.4athrough 2330.4p) and multiplexers 2332.4 (which are separately referenced as 2332.4athrough 2332.4n) that are clocked by the sequencer clock (SCLK) signal and generate the trigger signal and the tag signal. Registers 2330.4 and multiplexers 2332.4 are controlled by a controller 2334.4, which receives the data signal and receives or provides the control signals. Controller 2334.4 operations may be performed by regulation control module (REG) 1204 or by a separate controller, such as a processor or a microcontroller, to provide the control and data sequencing logic.

[0198] FIG. 36C shows an exemplary feedback control system for a PWM switching voltage regulator without a dead zone. For example, the feedback control system monitors a voltage of interest (V_M) and compares it to a target voltage (V_T) to generate an estimated PWM stop target (i.e., stop time) for use by controller 2334.4. FIG. 36C includes an analog-to-digital converter (ADC) 2340.4, a subtractor 2342.4, a summer 2344.4, and a register 2346.4.

[0199] The voltage (V_M) is digitized by ADC 2340.4 and subtracted from the voltage (V_Tor digital DVT) by subtractor 2342.4 and summed with an output of register 2346.4 by summer 2344.4. Register 2346.4 provides a PWM stop target (PWMST) signal.

[0200] If the voltage (V_T) is greater than the voltage (V_M), then the PWM stop target signal is incremented until the voltage (V_T) is less than the voltage (V_M), which results in the PWM stop target (PWM_ST) signal to decrement. Once steady state is achieved, the control loop will continue incrementing and decrementing the PWM stop target PWM_ST) signal to minimize the difference between the voltage (V_T) and the voltage (V_M). This negative feedback control system relies on the fact that an increase in the PWM stop target PWM_ST) signal will cause an increase in the voltage (V_M). The transient response of the control loop is small because the change in the PWM stop target (PWM_ST) signal will be, for example, only one unit (e.g., ±2 ns) from cycle to cycle.

[0201] FIG. 36D shows an exemplary feedback control system for a PWM switching voltage regulator with a dead zone. For example, the feedback control system monitors a voltage of interest (V_M) and compares it to a target voltage (V_T) to generate an estimated PWM stop target (i.e., stop time) for use by controller 2334.4. FIG. 36D includes converter (ADC) 2340.4, subtractor 2342.4, summer 2344.4, register 2346.4, comparators 2348.4, and a logic gate (OR) 2352.4.

[0202] The voltage (V_M) is digitized by ADC 2340.4 and subtracted from the voltage (V_Tor digital DVT) by subtractor 2342.4, with the result compared to a positive and negative dead zone target by comparators 2348.4 and 2350.4. The output of comparators 2348.4 and 2350.4 is provided to logic gate 2352.4, whose output along with comparator 2350.4 is summed by summer 2344.4 with an output of register 2346.4. Register 2346.4 provides a PWM stop target PWM_ST) signal.

[0203] If the difference (i.e., the voltage (V_T) minus the voltage (V_M)) is less than the positive dead zone target and greater than the negative dead zone target, the PWM stop target PWM_ST) signal remains constant. Otherwise, the PWM stop target PWM_ST) signal is incremented or decremented, as required.

[0204] Section 1.1.4 Discussion of PLL/RO using CAM, Optimization Techniques in CAM Implementation

[0205] FIG. 7 shows the output waveforms from the eleventh series-connected inverters shown in FIG. 6. In FIG. 6 the series-connected inverters are shown having pass transistors connected from the output of each of the inverters. For the pass transistors-connecting the output signals from the odd numbered inverters to input lead 63aof exclusive OR-gate 63, each pass transistor is driven by a signal labeled as A, B, C, D, E, or F. Similarly, for pass transistors connecting the output signals from the even-numbered inverters to leads 63bto exclusive OR gate 63, each pass transistor is driven by a signal labeled G, H, I, J, or K. The pulse width modulated output signal from exclusive OR gate 63 is transmitted on output lead 63cto the load capacitor of the particular circuit being powered by the structure shown in FIG. 6. The particular combination of pass transistors to be turned on determines the width of the pulse width modulated signal output on lead 53cfrom exclusive OR gate 63. Turning to FIG. 7, one can see the waveform from the inverters 1 through 11. The waveform from inverter 11 is, of course, fed back in FIG. 6 to the input lead of inverter 1.

[0206] FIG. 7 and FIG. 8 show waveforms for the output signals from each of the inverters 1 through 11 in FIG. 6. FIG. 7 shows the output signals for these inverters as taken straight from each inverter. FIG. 8 shows the output signals from inverters 1, 3, 5, 7, 9 and 11 taken straight from the output lead of each inverter while curves 2, 4, 6, 8 and 10 show the complement of the output signal taken from inverters 2, 4, 6, 8 and 10. FIG. 9 shows the pulse width for the various combinations of signals applied to input leads 63aand 63bof exclusive OR gate 63, respectively, throughout the pulse width of the pulse on output lead 63cfrom exclusive OR gate 63 is shown in the columns labeled pulse width. As can be seen from FIG. 9, only one combination of output signals from the various inverters is required to yield the five possible different pulse widths obtainable using the signals directly from the inverters. Thus the pulse widths 10, 8, 6, 4 and 2 are obtained from using on input lead 63aof exclusive OR gate 63 the output signal from inverter 1 activated by pass transistor A together with one of the output signals from inverters 2, 4, 6, 8 and 10 activated by pass transistors G, H, I, J or K. Thus pulse widths of 10 delays, 8 delays, 6 delays, 4 delays and 2 delays are obtained using these combinations. The only other combination of output signals is that which uses the output signal for inverter 11 together with the output signals from inverters 2, 4, 6, 8 and 10, which again yields pulse widths of 2, 4, 6, 8 and 10 delays.

[0207] If output signals from the even-numbered inverters are inverted, then pulse widths of 1, 3, 5, 7, and 9 delays can be obtained by combining an exclusive OR gate 63 the output signal from inverter 1 with the output signal from inverters 2, 4, 6, 8 and 10, each inverted. Again, this set of pulse widths represent all possible pulse widths obtainable using inverted output signals from the even-numbered inverters together with the output signal from any one of the odd-numbered inverters.

[0208] An alternative implementation for performing pulse width modulation by digital pulse converter 1201 includes a DPLL combined with a content addressable memory (CAM) to generate the required pulse width modulated signals (i.e., example 3 as listed above).

[0209] Digital Pulse Converter (DPC) 1201 is a low power custom mixed-signal macro. In general, the input and output signals of DPC 1201 are digital, however separate analog power and ground signals are provided to supply an internal digital phase lock loop (DPLL) circuit used for frequency synthesis.

[0210] DPC 1201 synthesizes a reference clock (32.768 khz) to produce a variety of pulses with pulse widths based on a DPC frame which starts with a count of 0 and ends with a terminal count of 1023, as illustrated in the timing diagram shown in FIG. 37. In one implementation the DPLL generates a frame clock of 524.288 KHz, yielding a frame time of 1.907 μSec. The minimum pulse width is represented by a count difference of 0 (i.e., 0% duty cycle) and the maximum pulse width by a count difference of 1024 (i.e., 100% duty cycle).

[0211] The rising and falling pulse edges have a minimum resolution of 1 count, which corresponds to a real time difference of ˜1.863 ns. The pulses are used to control chip I/O output drivers within NFET driver module 1202 for external power regulation. The pulses are also used to control chip I/O input drivers within sample and hold module (SHM) 1207, with sample and hold circuits for analog to digital conversion using an on chip analog to digital converter (ADC) found within analog to digital converter 1206.

[0212] DPC 1201 also generates other output signals used by other chip circuitry, for example real time clock states and synchronization pulses for regulation control module (REG) 1204, and source clocks for a Clock Generation and Enable (CKGEN) macro 1223. DPC 1201 generates pulses as shown in FIG. 37, where one DPC frame corresponds to ˜1.907 us in the timing diagram.

[0213] Each pulse (i.e., a PFET pulse 2410.4, a SFET pulse 2412.4, a SMPA pulse 2414.4, and a SMPB pulse 2416.4 associated respectively with a PFET signal 2402.4, a SFET signal 2404.4, a SMPA signal 2406.4, and a SMPB signal 2408.4) generated by DPC 1201 is represented as a pair of 10-bit Grey coded numbers, which are presented to DPC 1201 through the interface of Regulation control module (REG). The Grey coded numbers are designated as Primitive numbers or simply Primitives, with a pair of Primitives associated with each pulse.

[0214] The first Primitive number (i.e., a PFTS, a SFTS, a SPAS, and a SPBS in FIG. 37) in each pair indicates the offset of the leading edge of the pulse from a count of 0 and can be any integer from 0 to 1023. The second Primitive number (i.e., a PFTR, a SFTR, a SPAR, and a SPBR in FIG. 37) in each pair indicates the offset of the trailing edge of the pulse from a count of 0 and can also be any integer from 0 to 1023. The letter “S” on the end of signal parameters for the first Primitive numbers (PFTS, SFTS, SPAS, and SPBS) stands for SET and the letter “R” on the end of signal parameters for the second Primitive numbers (PFTR, SFTR, SPAR, and SPBR) stands for RESET.

[0215] PFET pulse 2410.4 and SFET pulse 2412.4, shown along the ordinate of the timing diagram in FIG. 37, control Primary and Secondary NFET drivers in NFET driver module 1202 and SMPA pulse 2406.4 and SMPB pulse 2416.4 control the input sample and hold circuits in SHM 1207. The pulses shown in the diagram can be represented by 8 independent 10-bit Primitives.

[0216] The eight independent Primitives are designated as follows: PFTS, PFTR, SFTS, SFTR, SPAS, SPAR, SPBS and SPBR.

[0217] These primitive numbers (i.e., PFTS, PFTR, SFTS, SFTR, SPAS, SPAR, SPAS and SPBR) are stored in a special purpose, dual port content addressable memory (CAM) device in DPC 1201 and the notation for these numbers are described in detail for port descriptions below. The timing diagram in FIG. 37 shows the Primitive number set for a single pulse channel controlled by DPC 1201, however DPC 1201 can provide a number of independent pulse channels (e.g., seven independent pulse channels for external PWM-switching power conversion and an eighth independent auxiliary pulse channel which can be used for synchronization of internal or external circuitry).

[0218] If DPC 1201 provides eight independent pulse channels, then a bus notation for PFET signal 2402.4, SFET signal 2404.4, SMPA signal 2406.4, and SMPB signal 2408.4 may be used to designate these independent channels as a PFET[7:0] signals 2454.4, a SFET[7:0]) signals 2452.4, a SMPA[7:0]0 signals 2450.4, and a SMPB[7:0] signals 2448.4, respectively, as discussed below in reference to FIG. 37A. PFET[7], SFET[7], SMPA[7] and SMPB[7] refer to the auxiliary pulse channel, and the PFET[6:0] signals 2454.4 and SFET[6.0] signals 2452.4 refer to pulses which control drivers in NFET driver module 1202 to turn on and off external power FETs used for power regulation. The SMPA[6:0] signals 2450.4 and SMPB[6:09 signals 2448.4 refer to pulses which control the input sample and hold circuits in SHM 1207 for digitizing external analog voltages. It should be noted that the timing diagram shown in FIG. 37 illustrates a break before make switching algorithm between PFET signal 2402 and SFET signal 2404.4 (i.e., between the Primitive number PFTR and the Primitive number SFTS), which is generally needed for efficient power regulation.

[0219] DPC 1201 for this implementation has five interfaces to communicate with five corresponding portions of switching power supply controller 1200 (i.e., IVS 1209, CKGEN 1223, regulation control module (REG) 1204, NFET driver module 1202, and SHM 1207). FIG. 37A illustrates this exemplary interface implementation for DPC 1201. The interface with IVS 1209 includes the FREF signal 2420.4.

[0220] Additionally, the interface with IVS 1209 includes power and ground signals, including a VDD signal 2464.4, an AVD signal 2466.4, a VSS signal 2442.4, and an AVS signal 2444.4. The digital power and ground, VDD signal 2464.4 (e.g., 3.3 V) and VSS signal 2442.4, respectively, can be treated as global signals, whereas the analog power and ground, AVD signal 2466.4 (e.g., 3.3 V) and AVS signal 2444.4, respectively, are generally not treated as global signals.

[0221] FREF signal 2420.4 is a reference clock provided to the DPLL in DPC 1201 and has a frequency and a duty cycle of about 32.768 kHz and 50%, respectively. PLOCK signal 2462.4 is a signal which is asserted (i.e., transitions to a logical high or HIGH state) and remains asserted (i.e., remains at a logical high) after the DPLL achieves and remains in a phase lock condition. Otherwise PLOCK is not asserted (i.e., a logical low or LOW state). AUX signal 2446.4 is an auxiliary signal port that is used for synchronizing circuitry external to switching power supply controller 1200.

[0222] The interface with Clock Generator and Enable (CKGEN) 1223 includes various signals, including a CST[9:0] signal 2458.4, a PLLCK signal 2460.4, and a PLOCK signal 2462.4. CST[9:0] signal 2458.4 is a 10-bit Grey coded clock state bus which provides the clocks and control states to synchronize DPC 1201, regulation control module (REG) 1204, and the CKGEN macro 1223. In a standard operating mode, with SSC signal 2424.4 set LOW and FREF signal 2420.4 set to 32.768 kHz, exemplary frequencies for the CST[9:0] signals 2458.4 are given in Table 1. PLLCK signal 2460.4 is the DPLL output clock which has a frequency and a duty cycle of 524.288 kHz and 50% respectively, assuming a reference frequency for FREF signal 2420.4 of 32.768 kHz. The same frequency for the last two most significant bits of CST[9:0] signals 2458.4 is an artifact of a 10-bit Grey counter generating these frequencies. The MSB (most significant bit) and NMSB (next most significant bit), (CST[9] and CST[8], respectively, of CST[9:0] signal 2458.4) have a quadrature phase relationship to each other.

[0223] The interface with regulation control module (REG) 1204 includes various signals, including PD_OUT[1:0] signals 2426.4, SET[28:0] signals 2438.4, RST[28:0] signals 2440.4, ENBL[21:0] signals 2436.4, DWI[19:0] signals 2428.4, DRO[19:0] signals 2456.4, and ADW[4:0] signals 2430.4, which are input buses, and the CST[9:0] signals 2458.4, which is an output bus. Additionally, the interface includes an input signal WE 2432.4, an input signal RE 2434.4, and an output signal PLOCK 2462.4.

[0224] The interface with the regulation control module (REG) 1204 is used to generate the various pulses, such as PFET pulse 2410.4 and SFET pulse 2412.4. The DWI[19:0] signals 2428.4, ADW[4:0] signals 2430.4, DRO[19:0] signals 2456.4, and input signal WE 2432.4 and input signal RE 2434.4 transfer data and control the read/write ports of the dual port CAM, discussed in further detail herein. The read port for the CAM is within DPC 1201.

[0225] More specifically, the PD_OUT[1:0] signals 2426.4 are a 2-bit bus which controls the mode of operation for DPC 1201. The modes of operation are designated as Standard mode, Low Power mode, and Shut Down mode, as summarized in Table 2.

[0226] When PD_OUT[1:0] signals 2426.4 are asserting the Shut Down mode, the DPLL is powered down, the CAM is in standby mode, and the rest of the digital blocks in DPC 1201 are in low power states. When PD_OUT[1:0] signals 2426.4 are asserting the Low Power mode, the DPLL is powered up and phase locked at its normal operating frequency (536,870.912 kHz), the DPLL output is divided by 16 to produce the LSB of CST[9:0] signal 2458.4 (i.e., the frequency of the CST LSB is 33,554.432 kHz), the CAM is in standby mode, and the remaining blocks of DPC 1201 are in low power states. When PD_OUT[1:0] signals 2426.4 are asserting the Standard mode, the DPLL is operating normally, the DPLL output is divided by 4 to produce the LSB of CST[9:0] signals 2458.4 (i.e., the frequency of the CST LSB is 134,217.728 kHz), the CAM is powered up and operating normally and the rest of the DPC blocks are also powered up and are operating normally.

[0227] The SET[31:0] signals 2438.4 are a 32-bit control bus which is used to independently set each output bit of DPC 1201. For example, when SET[0] of the SET[31:0] signals 2438.4 is HIGH, SMPA[0] of the SMPA[7:0] signals 2450.4 is set HIGH, and when SET[1] of the SET[31:0] signals 2438.4 is HIGH, PFET[6] of the PFET[7:0] signals 2454.4 is set HIGH. Table 3 illustrates exemplary associations between SET[31:0] signal 2438.4, the

[0228] Primitive numbers, and output signals from DPC 1201.

[0229] The RST[31:0] signals 2440.4 are a 32-bit control bus which is used to independently reset each output bit of DPC 1201. For example, when RST[0] of the RST[31:0] signals 2440.4 is HIGH, the SMPA[0] output of the SMPA[7;0] signals 2450.4 is reset LOW, and when RST[1] of the RST[31:0] signals 2440.4 is HIGH, the PFET[0] output of the PFET [6:0] signals 2454.4 is reset LOW. Table 4 illustrates exemplary associations between RST[31:0] signal 2440.4, the Primitive numbers, and output signals from DPC 1201.

[0230] The ENBL[23:0] signals 2436.4 are a 24-bit CAM enable bus used to independently enable the CAM match ports. The ENBL[3n] bits of ENBL[23:0] signal 2436.4 enable the SMPA[n] bits of the SMPA[7:0] signals 2450.4 and the SMPB[n] bits of the SMPB[7.0] signals 2448.4 for CAM match outputs, where n ∈ {0, 1, 2, . . . , 7}. The ENBL[3n+1] bits of the ENBL[23:0] signals 2436.4 enable the PFET[n] bits of the PFET[7:0] signals 2454.4 for the CAM match outputs and the ENBL[3n+2] bits of the ENBL[23:0] signals 2436.4 enable the SFET[n] bits of the SFET[7:0] signals 2452.4 for the CAM match outputs, where n ∈ {0, 1, 2, . . . , 7}. The CAM ENBL bus (i.e., the ENBL[23:0] signals 2436.4) and output correspondence for an exemplary implementation is given in Table 5.

[0231] The ENBL bits of the ENBL[23:0] signals 2436.4 are active HIGH. To enable specific CAM match ports, the corresponding enable bit is set HIGH. The ENBL[23:0] signals 2436.4 affects only the read port of the CAM and the Primitive numbers can be read from and written to the CAM through the read/write port, as described in further detail below. This feature allows the CAM to be safely updated without causing an inadvertent match during a CAM update. In addition, the ENBL[23:0] signals 2436.4 allow the capability for pulse skipping during the normal operation of the CAM.

[0232] The DWI[19:0] signals 2428.4 are a 20-bit write data bus for the read/write CAM port and it is used for writing Grey coded words to the CAM. The DWI[19:0] bus 2428.4 writes to the CAM are controlled by the ADW address bus (i.e., the ADW[4:0] signals 2430.4) and the WE signal 2432.4. The DWI[9:0] bits of DWI[19:0] signal 2428.4 are allocated for the bank zero of the CAM and the DWI[19:10] bits of DWI[19:0] signal 2428.4 are allocated for bank one of the CAM.

[0233] The ADW[4:0] signals 2430.4 are a 5-bit address bus used to address a single (20-bit) word in the CAM for reading or writing. For ease of implementation and in accordance with one embodiment, the CAM is split into two banks, as described in Table 6. The ADW[4:0] signals 2430.4 simultaneously addresses one 10-bit word out of 22 words in each CAM bank. For example, ADW[0] of the ADW[4:0] signals 2430.4 corresponds to the Primitive SPBS[0] in the CAM bank zero and the Primitive SPBR[0] in the CAM bank one.

[0234] The DRO[19:0] signals 2456.4 are a 20-bit read data bus for the read/write CAM port and it is used for reading Grey coded words from the CAM. The DRO[19:0] bus 2456.4 reads from the CAM are controlled by the ADW address bus (i.e., the ADW[4:0] signals 2430.4) and the RE signal 2434.4. The DRO[9:0] bits of DRO[19:0] signal 2456.4 are allocated for the bank zero of the CAM and the DRO[19:10] bits of DRO[190] signal 2456.4 are allocated for bank one of the CAM.

[0235] The PFET[6:0] signals 2454.4 are a 7-bit bus which provides the primary power FET pulses (i.e., pulses, such as PFET pulse 2410.4) to NFET driver module 1202. The SFET[6:0] signals 2452.4 are a 7-bit bus which provides the secondary power FET pulses (i.e., pulses, such as SFET pulse 2412.4) to NFET driver module 1202.

[0236] The WE signal 2432.4 is the write enable control signal for the read/write CAM port. When WE signal 2432.4 toggles HIGH, a 10-bit word is written to each bank of the CAM at the address specified by the ADW[4:0] signals 2430.4. The RE signal 2434.4 is the read enable control signal for the read/write CAM port. When the RE signal 2434.4 toggles HIGH, a 10-bit word is read from each bank of the CAM at the address specified by the ADW[4:0] signals 2430.4.

[0237] The interface for NFET driver module 1202 includes various signals, including the PFET[6:0] signals 2454.4 and SFET[6:0] signals 2452.4. As discussed above, a single PFET (primary FET) and SFET (secondary FET) pulse channel is shown in the above timing diagram (FIG. 37).

[0238] The interface for SHM 1207 includes various signals, including the SMPA[6:0] signals 2450.4 and the SMPB[6:0] signals 2448.4. This interface is used to control the sampling and holding of analog voltages for digital conversion by analog to digital converter 1206. As described above in accordance with one embodiment, the sample pulses SMPA (e.g., SMPA pulse 2414.4) and SMPB (e.g., SMPB pulse 2416.4) are independent from the PFET (Primary FET) and SFET (Secondary FET) pulses. Either of the SMPA[6:0] signals 2450.4 or the SMPB[6:0] signals 2448.4 can be used to control the sampling (and holding) of analog voltages in SHM 1207 for analog to digital converter 1206. The remaining signals shown in FIG. 37A and described in Table 8 include a bypass signal 2422.4 and the SSC signal 2424.4. Bypass signal 2422.4 is a test control signal used for bypassing the DPLL. When bypass signal 2422.4 is held HIGH, FREF signal 2420.4 bypasses the DPLL, but when bypass signal 2422.4 is held LOW, FREF signal 2420.4 is used for frequency synthesis. SSC signal 2424.4 is a control signal that activates spread spectrum clocking. Spread spectrum clocking is activated when SSC signal 2424.4 is HIGH; otherwise spread spectrum clocking is disabled. The spread spectrum clocking scheme implemented in DPC 1201 can be either up or down frequency spreading where the DPC frame frequency (e.g., 524.288 kHz without spread spectrum clocking) deviates from its fundamental frequency by approximately 0.5% with a modulation period of approximately 22 us.

[0239] FIG. 37B illustrates one circuit implementation for DPC 1201 and includes a DPLL 2480.4, a spreader divider 2482.4, a Grey counter 2484.4, and a CAM module 2486.4. CAM module 2486.4 includes a modified CAM for generating PFET[6:0] signal 2454.4, SFET[6:0] signal 2452.4, SMPA[6:0] signal 2450.4, SMPB[6:0] signal 2448.4, and AUX signal 2446.4. FIG. 37C illustrates one exemplary implementation for CAM module 2486.4.

[0240] CAM module 2486.4 stores, for example, 64 words (i.e., Primitives, which were discussed above), with 10-bits per word and with an address read port 2502.4 (labeled ADR[63:0]) of CAM module 2486.4 not encoded. Address read port 2502.4 provides 64 address signals, referenced collectively as ADR[63:0] signals 2508.4. The even ADR bits (ADR[0], ADR[2], . . . , ADR[62]) of ADR[63:0] signals 2508.4 are associated with CAM bank zero and the odd ADR bits (ADR[1], ADR[3], . . . , ADR[63] of ADR[63:0] signals 2508.4 are associated with the CAM bank one, as previously discussed (e.g., in reference to ADW[4:0] signal 2430.4) ADR[63:0] signals 2508.4 are connected to 32 RS latches, which are represented by an RS latch 2504.4 (FIG. 37C), through control logic 2506.4, shown in a representative fashion in FIG. 37C. A more detailed exemplary implementation for control logic 2506.4 and RS latch 2504.4, associated with a single pulse channel at the output of CAM module 2486.4, is shown in FIG. 37D and discussed below.

[0241] DPLL 2480.4 (FIG. 37B) is shown coupled to Grey counter 2484.4 (e.g., a free running 10-bit Grey Counter), with spreader divider 2482.4 situated between DPLL 2480.4 and Grey counter 2484.4. When SSC signal 2424.4 is enabled, spreader divider 2482.4 produces spread spectrum clocking, as described above, by employing a uniform pulse swallowing technique which varies in frequency. Spread spectrum mode of operation is described below.

[0242] Additionally, spreader divider 2482.4 provides the variable divide ratio for toggling between the standard and low power modes, described above for PD_OUT[1:0] signal 2426.4. The extra division provided by spreader divider 2482.4 reduces the current drawn by Grey counter 2484.4 in the low power mode. For example, as compared to a binary counter, Grey counter 2484.4 produces glitch free read operations for CAM module 2486.4.

[0243] An example of operation for the implementation shown in FIG. 37B for DPC 1201 starts with DPLL 2480.4, which increments Grey counter 2484.4 (i.e., through spreader divider 2482.4) to produce the read data, identified by a DRI signal 2488.4, for CAM Module 2486.4. If the read data of DRI signal 2488.4 generates a CAM match in CAM Module 2486.4, one or more of the CAM output read address lines (i.e., ADR[63:0] signals 2508.4) of CAM Module 2486.4 becomes active, which sets or resets one or more of the 32 RS latches (i.e., RS latch 2504.4) to produce the output pulses on the PFET[7:0] signals 2454.4, SFET[7:0] signals 2452.4, SMPA[7:0] signals 2450.4 and SMPB[7:0] signals The 32 RS latches (represented by RS latch 2504.4) are organized into eight pulse channels. The 4 pulses within a pulse channel are completely independent as described earlier And the eight independent Primitive numbers (one set of eight numbers for each pulse channel) are Grey coded and written to specific address locations in the CAM of CAM module 2486.4 regulation control module (REG) 1204. The address locations for the Primitive numbers are given above in reference to ADW[4:0] signal 2430.4.

[0244] CAM Module's 2486.4 logic that is associated with one pulse channel (e.g., given by a PFET[n] signal 2512.4, an SFET[n] signal 2516.4, an SMPA[n] signal 2510.4, and an SMPB[n] signal 2514.4, where n ∈ {0, 1, 2, . . . , 7}) is shown in detail in FIG. 37D. Eight independent CAM ADR lines (e.g., ADR[8n], ADR(8n+1], ADR[8n+2], ADR[8n+3], ADR[8n+4], ADR[8n+5], ADR[8n+6] and ADR[Bn+7]) from the ADR[63:0] signals 2508.4 are shown controlling four RS latches (separately referenced as RS latches 2504.4(1) through 2504.4(4)) of RS latch 2504.4.

[0245] The control circuitry for the ENBL[23:0] signals 2436.4, which are separately referenced as enable control logic 2506.4(1) of control logic 2506.4, is also shown in detail in FIG. 37D. The ENBL[3n+1] signals and ENBL[3n+2] signals, of the ENBL[23:0] signals 2436.4, control RS latches 2504.4(2) and 2504.4(4) for the PFET[n] signals 2512.4 and SFET[n] signals 2516.4, respectively, and the ENBL[3n] signals of the ENBL[23:0] signals 2436.4 controls RS latches 2504.4(1) and 2504.4(3) for the SMPA[n] signals 2510.4 and SMPB[n] signals 2514.4, respectively. Table 5, discussed above, provides additional details regarding the ENBL[23:0] signals 2436.4.

[0246] The control circuitry for the SET[31:0] signals 2438.4 and the RST[31:0] signals 2440.4, which are separately referenced as set/reset control logic 2506.4(2) of control logic 2506.4, is also shown in detail in FIG. 37D. The SET[31:0] signals 2438.4 and RST[31:0] signals 2440.4 allow direct control of RS latch 2504.4 (e.g., RS latches 2504.4(1) through 2504.4(4)) at the output of CAM Module 2486.4). In the low power mode, this interface is used in conjunction with the ENBL[23:0] signals 2436.4 by logic in regulation control module (REG) 1204 to generate the ADC samples and power regulation pulses needed for operation in this mode. Using these control signals, regulation control module (REG) 1204 can take direct control of RS latch 2504.4 to avoid hazard conditions (e.g., preventing the set (S) and reset (R) inputs to each latch from being active simultaneously).

[0247] As shown in FIG. 37C, a CAM 2494.4 is a dual-port memory device with one read/write port 2496.4 (associated with the DWI[19:0] signals 2428.4, ADW[4:0] signals 2430.4, WE signal 2432.4, RE signal 2434.4, and DRO[19:0] signals 2456.4) and one read port 2498.4 (associated with the DRI signals 2488.4 and ADR[63:0] signals 2508.4). The same Primitive number can be written to two or more address locations in CAM 2494.4, which will cause multiple matches on the ADR[63:0] signals 2508.4 (i.e., the CAM read address lines) when the matching data is presented to read port 2498.4 (through the DRI signals 2488.4) of CAM 2494.4 by Grey Counter 2484.4. The multiple matches allow two or more output edges to coincide.

[0248] Regulation control module (REG) 1204 synchronizes the writes to CAM 2494.4 to avoid the generation of inadvertent glitches on the various pulse channels. When key independent pulse edges (i.e., master edges) change from one DPC frame of DPC 1201 to the next, regulation control module (REG) 1204 re-computes the dependent pulse edges (i.e., slave edges) and updates CAM 2494.4 accordingly. The master edges correspond to the Primitives PFTS[n], PFTR[n], SFTS[n], and SFTR[n], where n ∈{0, 1, . . . , 7}. All other edges are either slave edges or auxiliary edges.

[0249] If a master edge is moved from its position (Grey coded count) in the current DPC frame of DPC 1201 to a different position in the next frame, the slave edges related to the specific master edge are re-computed and written to CAM 2494.4 by regulation control module (REG) 1204 for use in the next frame. Regulation control module (REG) 1204 provides the computations, Grey coding, and CAM write coordination required to perform these tasks efficiently and without hazards.

[0250] The information necessary to compute the slave edges from the master edge information is contained within regulation control module (REG) 1204, and this information does not generally change from one DPC frame of DPC 1201 to the next. For example, the slave edge information necessary to calculate the Primitive data SPAS and SPBS edges for each channel can be provided as a single 10-bit binary constant (or pulse width), which is used by regulation control module (REG) 1204 to compute and Grey encode a new Primitive SPAS value if a Primitive PFTS value changes or (more likely) to compute and Grey encode a new Primitive SPBS value if a given Primitive PFTR value changes.

[0251] The master edge information provided by regulation control module (REG) 1204 can change from one DPC frame of DPC 1201 to the next. Regulation control module (REG) 1204 provides this information as pairs of 10-bit Grey coded numbers comprised of two offsets from a DPC 1201 frame initial count of zero. One offset corresponds to the SET input of one of the RS latches (i.e., RS latch 2504.4) at the output of CAM module 2486.4 and the other offset corresponds to the RESET input of the RS latch.

[0252] As mentioned above, read port 2498.4 of CAM 2494.4 (associated with DRI signal 2488.4) is buried within DPC 1201, as illustrated in FIG. 37B and FIG. 37C. The ENBL[23:0] signals 2436.4 affects only the read port of CAM 2494.4 and is used for the multiple functions described above. If a specific ENBL bus bit of the ENBL[23:0] signals 2436.4 is held LOW, for example ENBL[0] bit, the read address section corresponding to the ENBL[0] bit is disabled and any data match occurring in the corresponding disabled section (e.g., the Primitives SPAS[0], SPAR[0], SPBS[0] and SPBR[0]) will not produce a match. However, if the same data occurs in another read address section of CAM 2494.4, which is not disabled, the match will occur.

[0253] Because the ENBL[23:0] signals 2436.4 only affects the read port of CAM 2494.4, read/write port 2496.4 is not affected. Therefore, reads and writes to CAM 2494.4 through read/write port 2496.4 can take place unimpeded. This capability can be used in conjunction with the PFET[7:0] signals 2454.4 or SFET[7:0] signals 2452.4 to safely update the Primitive numbers in CAM 2494.4 and avoid the inadvertent generation of pulse glitches. One,possible update sequence is shown in the timing diagram of FIG. 37E for updating the Primitive SFTR[0] in CAM 2494.4.

[0254] The Primitive SFTR[0] update to CAM 2494.4 starts with the rising edge of an SFET[0] bit of the SFET[7:0] signals 2452.4. At the rising edge of the SFET[0] bit, the SFTS[0] Primitive match has already occurred. Regulation control module (REG) 1204 detects the rising edge of the SFET[0] bit and disables the required CAM section of CAM 2494.4 one regulation control module (REG) 1204 clock cycle later by setting an ENBL[2] signal LOW. Note that this does not present a problem for a PFET[0] pulse of the PFET[7:0] signals 2454.4, because the rising and falling edges of that pulse have already occurred.

[0255] After the CAM section of CAM 2494.4 is disabled, regulation control module (REG) 1204 enables a CAM write by toggling WE signal 2432.4 HIGH. Because the ADW[4:0] signals 2430.4 (i.e., the read/write address port ADW) has been set to address location 2, which corresponds to the Primitive SFTR[0] as shown in Table 6, the new Primitive for SFTR[0] is written to the CAM address location 2 of CAM 2494.4. Regulation control module (REG) 1204 then re-activates the section by setting the ENBL[2] bit HIGH and the new falling edge of the SFET[0] pulse of the SFET[7:0] signals 2452.4 occurs at the new SFTR[0] Primitive value when the CAM match occurs as indicated by the falling edge of the SFET[0] pulse.

[0256] Changing some Primitives has more of an effect on other Primitives than the example given in reference to FIG. 37E. Because of the dependencies discussed herein, if the Primitive PFTR is changed, the Primitives SPBS, SFTS, and SFTR may need to be recomputed, Grey coded, and updated to CAM 2494.4 by regulation control module (REG) 1204. As another example, if the Primitive PFTS is changed all of the Primitives SPAS, SPBS, PFTR, SFTS, and SFTR may need to be recomputed, Grey coded, and updated to CAM 2494.4 by regulation control module (REG) 1204.

[0257] Because the worst case write cycle time for CAM 2494.4 is, for example, 7.5 ns, the updates described in the previous sentence can be completed in 22.5 ns (i.e., 3 times 7.5 ns). To update the entire 64 words in CAM 2494.4 would take approximately 240 ns. In FIG. 37, as an example, a break before make switching algorithm for PFET signal 2402.4 and SFET signal 2404.4 was presented. If the break time between PFET signal 2402.4 and SFET'signal 2404.4 were always greater than 30 ns, all of the Primitives (eight numbers) necessary to update a pulse channel can be written to CAM 2494.4 during this period.

[0258] Section 1.1.5 Discussion of Combinations and Permutations of PLL/RO, DLL and Counters for Optimization of Standby Power and Die Size.

[0259] FIG. 38 shows a circuit 2600.4, which is an exemplary implementation for Grey counter 2484.4 (FIG. 37B). Circuit 2600.4 represents a 10-bit Grey counter, but could be implemented as any number of bits based upon the techniques discussed herein. Furthermore, circuit 2600.4 can be implemented as a low power circuit utilizing circuit techniques discussed below (e.g., in reference to FIG. 38B through FIG. 38F).

[0260] Circuit 2600.4 includes a number of flip flops 2602.4, which are separately referenced as flip flop 2602.4(1) through 2602.4(10), along with a number of AND gates 2604.4 and a number of exclusive OR (XOR) gates 2606.4. Circuit 2600.4 generates a 10-bit Grey count (i.e., bits C0 through C9 in FIG. 38) that is provided to CAM module 24B6.4 (FIG. 37B).

[0261] FIG. 38A shows a circuit 2610.4, which is another exemplary implementation for Grey counter 2484.4. Circuit 2610.4 is similar to Circuit 2600.4, but utilizes NAND gates 2612.4 and NOR gates 2614.4 rather than AND gates 2604.4. As shown in FIG. 38 and FIG. 38A, flip flop 2602.4(1) receives a clock (CLK) signal 2603.4 while flip flops 2602.4(2) through 2602.4(10) receive a clock signal (CLK bar) 2605.4, which is the complement of clock signal 2603.4. Circuits 2600.4 and 2610.4 may be implemented using low power circuit techniques discussed in the following figures.

[0262] FIG. 38B and FIG. 38C illustrate circuit implementations that may require less power than conventional flip flop circuits by utilizing fewer circuit elements. FIG. 38B shows an exemplary implementation for flip flop 2602.4(1) of FIG. 38 or FIG. 38A. FIG. 38B includes transistors 2620.4 and 2624.4 (i.e., a p-type and an n-type transistor, respectively) along with inverters 2622.4, 2626.4, and 2628.4. Transistor 2620.4 receives a D input signal 2630.4 and transistors 2620.4 and 2624.4 receive a clock (CLK) signal 2632.4, with inverters 2626.4 and 2628.4 providing a Q signal 2634.4 and a QN (Q NOT or Q bar) signal 2636.4, respectively.

[0263] In a similar fashion, FIG. 38C shows an exemplary implementation for flip flops 2602.4(2) through 2602.4(10) of FIG. 38 or FIG. 38A. FIG. 38C includes transistors 2640.4 and 2642.4 (i.e., an n-type and a p-type transistor, respectively) along with inverters 2644.4, 2646.4, and 2648.4. Transistor 2640.4 receives a D input signal 2650.4 and transistors 2640.4 and 2642.4 receive a clock (CLK bar) signal 2652.4, with inverters 2646.4 and 2648.4 providing a Q signal 2654.4 and a QN (Q NOT) signal 2656.4, respectively.

[0264] FIG. 38D shows an exemplary circuit implementation for an XOR logic gate (e.g., XOR gate 2606.4 of FIG. 38 and FIG. 38A or an XOR gate 2717.4 as shown in FIG. 38D), which requires less power than a conventional XOR gate. FIG. 38D includes inverters 2700.4 and 2702.4 and transistors 2704.4 and 2706.4. An input signal (A) 2708.4 and an input signal (B) 2710.4 are provided, as shown, to transistors 2704.4 and 2706.4, respectively, with inverter 2702.4 providing an output signal (Z) 2712.4 in accordance with the equation

[0265] Z=A·{overscore (B)}+Ā·B.

[0266] Likewise, FIG. 38E shows an exemplary circuit implementation for an exclusive NOR (XNOR) logic gate 2720.4, which may require less power than a conventional XNOR gate. FIG. 38E includes inverters 2722.4 and 2724.4 and transistors 2726.4 and 2728.4. An input signal (A) 2730.4 and an input signal (B) 2732.4 are provided, as shown, to transistors 2726.4 and 2728.4, respectively, with inverter 2724.4 providing an output signal (Z) 2734.4 in accordance with the equation

[0267] Z={overscore (A·{overscore (B)})}+{overscore (A)}·B.

[0268] Additionally, FIG. 38F shows an exemplary circuit implementation for an inverting multiplexer 2740.4, which includes transistors 2742.4 and 2744.4 and an inverter 2746.4. Inverting multiplexer 2740.4 receives input signals (A) 2748.4, (B) 2750.4, and (C) 2752.4 and provides an output signal (Z) 2754.4, in accordance with the equation

[0269] Z={overscore (C·B+{overscore (C)})}·A.

[0270] FIG. 38G shows an exemplary circuit implementation for a binary to Grey conversion (BGC) 2770.4 and a Grey to binary conversion (GBC) 2780.4. BGC 2770.4 shows an exemplary 4-bit conversion from binary to Grey code utilizing XOR gates 2772.4, while GBC 2780.4 shows an exemplary 4-bit conversion from Grey to binary code utilizing XOR gates 2772.4. XOR gates 2772.4 may be implemented as discussed above in reference to FIG. 38D to minimize the amount of power utilized.

[0271] Another alternative implementation, in accordance with an embodiment of the present invention, for performing pulse width modulation includes a low frequency digital phase locked loop (DPLL) voltage controlled oscillator (VCO) with inverter stages and taps (i.e., example 1 as listed above). FIG. 38H illustrates an exemplary implementation in accordance with this embodiment, which includes a phase frequency detector (PFD or phase detector) 2802.4, a charge pump 2804.4, a loop filter 2806.4, a VCO 2808.4, and a frequency divider 2810.4.

[0272] PFD 2802.4 receives a reference frequency (e.g., 32 kHz) on a line 2814.4 and a feedback signal from frequency divider 2810.4 on a line 2812.4 and determines whether to provide a pump up or a pump down signal to charge pump 2804.4. Charge pump 2804.4 provides a signal, based on the pump up or the pump down signal to loop filter 2806.4 and VCO 2808.4. VCO 2808.4 is comprised of a ring oscillator having inverter stages and taps, as discussed similarly above in reference to FIG. 3, and therefore the description will not be repeated. An output signal from VCO 2808.4 is received by frequency divider 2810.4, which divides down a frequency of the output signal to a desired frequency to provide as the feedback signal.

[0273] Another alternative implementation for performing pulse width modulation may be viewed as a hybrid of a high frequency DPLL with a counter combined with a digital comparator (i.e., example 2 as listed above) and a DPLL combined with a content addressable memory (i.e., example 3 as listed above) to generate the required pulse width modulated signals.

[0274] More specifically, FIG. 38I illustrates a circuit 2900.4 to assist in generating pulse width modulation signals. Circuit 2900.4 includes a decoder 2902.4 which controls logic gates 2904.4 for writing to memory 2906.4 (e.g., random access memory) having address lines (ADR) and data lines (D1). Memory 2906.4 stores data that determines start and stop times for desired pulse width modulated-signals.

[0275] Memory 2906.4 provides data (at a DO terminal) under control of a controller 2924.4 (through a read address (RA)) to multiplexers 2912.4, exclusive OR (XOR) gates 2910.4, and multiplexers 2918.4 via multiplexers 2908.4. Under direction of controller 2924.4, XOR gates 2910.4, multiplexers 2912.4 and 2918.4, registers 2914.4 and 292.0.4, and adder/subtractor 2916.4 determine the data to provide to a comparator 2922.4 to compare with a reference count 2926.4. Comparator 2922.4, which is similar to comparator 2310.4 of FIG. 36A, provides an output signal to a pulse width modulation circuit (i.e., PWM circuit 2314.4 as described in reference to FIG. 36A). Consequently, by using memory and a comparator, pulse width modulated signals can be generated.

[0276] Section 1.1.6 Discussion of Phase Offset Tuning of Synchronous Drive to Optimize Conduction Losses vs. Dead Time

[0277] One of the efficiency optimizations in switching power supplies is to attempt to minimize the power dissipated by the Schottky diode that will typically either be inserted in the circuit across the-lower transistor (QB₁in circuit 1301.2 of FIG. 46), or as is well known is intrinsic to a FET. In FIG. 46, the Schottky diode is indicated by reference character S1. In order to minimize the voltage drop across diode S1, transistor QB₁is inserted between terminal S and ground, and is turned on in some instances to reduce the voltage drop across diode S1, therefore substantially reducing the power dissipated by this diode of course, any of this power dissipated will not be delivered to the load and so is therefore a source of inefficiency. The challenge becomes minimizing the amount of time that diode Si conducts. It is desirable that diode S1 conduct only a very small amount of time, however, if the switching signals to QB₁and QT₁become too close in time, because of the time delay required to switch on and off, it's possible that both transistors might be on simultaneously which would not only be a huge efficiency loss, but could potentially result in catastrophic circuit failure due to the unlimited currents flowing directly from the input supply through QT₁to QB₁to ground. So the optimization then is to move the gate signal for QB₁as close as possible to the gate signal of QT₁, but without causing an overlap in conduction.

[0278] FIG. 39. illustrates the expected voltage at terminal S in FIG. 46 for the switching timing diagrams immediately above it in the figures. It will be appreciated that the voltage at terminal S falls as the gate drive to QT₁is turned off and drops to the point where it is caught by the Schottky diode S1, then in the subsequent time QB₁is turned on pulling the voltage back up to the supply rail. This process happens in reverse order at the other end of the pulse where the gate for QB₁is turned off. Current is again allowed to flow into diode S1, and the voltage at terminal S falls below ground which results in wasted power dissipated until QT₁is turned on and the voltage at terminal S switches up to the positive supply rail and the cycle repeats.

[0279] In prior art solutions, a guard band must be constructed between the timing of these two gate signals. This guard band has to be long enough to accommodate the slowest transistor that might be used in the application. In the present invention, in one embodiment we use data provided by the designer of the power supply being regulated by switching power supply controller 1200 and program that data into internal memory of switching power supply controller 1200, stating what the characteristics of the external transistors are. Accordingly, a fixed guard band and time are not required. In a first embodiment, we use the minimum number that could be used based on the published data for the individual devices, and store the phase offset values in REGhw. In another embodiment of the present invention, we dynamically optimize this further. This can be done by observing the efficiency of the given output stage. For example, we know that for a buck power supply, the output voltage is equal to the duty cycle multiplied by the input supply voltage. Any deviation of the actual output voltage from that calculated output voltage will be due to parasitic effects of inductors, resistors, capacitors, and the transistors themselves. It is therefore possible to carefully, and at a slow rate over many cycles, tune the timing between QT₁and QB₁until this efficiency peaks and begins to degrade. It will degrade rapidly as the transistors overlap, but this permits dynamic adaptation of the timing of the gate drive signals to the transistors to the actual devices in the circuit being regulated. Switching power supply controller 1200 can have a number of guard bands on a circuit to circuit basis because the switching times of these transistors are also somewhat dependent on the load current that they are supplying and the temperatures at which they are operating. The required amount of phase offset between the time QT₁turns off and QB₁turns on and the phase offset between when QB₁turns off and QT₁turns on may be different. Accordingly, fine tuning on both can be made. Temperature data is available to the controller from the Kelvin temperature sensor located in internal voltage supply 1209. In the first embodiment described above, providing the rise and fall time parameters for the transistors to the controller can achieve a significant improvement over the prior art worst case tolerance scheme which does not take into account the specifications of the actual transistors being used. In the second embodiment, efficiency can be further improved by dynamically adapting to the devices that are used, and thus achieving the highest efficiency possible for the given set of transistors and discrete output components.

[0280] Section 1.1.7 Synchronous Sampling Multiple Output

[0281] Sample and Hold Module (SHM) 1207 samples various voltages and currents and holds them until analog to digital converter 1206 is ready to receive them. As noted herein, analog input signals used in the control loops are provided by Digital Pulse Converter 1201 via SHM 1207, and are converted to digital signals by analog to digital converter 1206. As an example, SHM 1207 samples and holds thirteen voltages and seven currents, with seven voltages associated with external power supplies being controlled or driven, two voltages associated with SUPPLYA and SUPPLYB and four auxiliary voltages: VOUT from Kelvin Temperature Sensor 3516.4, and three pads TEMPEXT, AUX0 and AUX1

[0282] FIG. 40 is a functional block diagram of SM 1207 in one implementation. The functional block diagram includes an input/output (I/O) circuit 3008.4, a voltage divider (scalar) 3010.4, a multiplexer 3012.4, and a multiplexer 3016.4. An external voltage is sampled by I/O circuit 3008.4 via a pad 3000.4, with an output signal (OUTV) provided to voltage divider 3010.4. Voltage divider 3010.4 divides down or scales the output signal (OUTV) to an acceptable level under control of a scale[3:0] signal received from regulation control module (REG) 1204. For example, an external voltage (e.g., 15 V or less) is scaled to an appropriate value for analog to digital converter 1206 (e.g., input range of 0 to 3.3. V).

[0283] I/O circuit 3008.4 receives a SSUP signal and a SELVX signal from regulation control module (REG) 1204 and an AUX signal and a SCLKVX signal from DPC 1201. The AUX signal provides a sample clock for sampling one or more external supply voltages. The SSUP signal provides a select clock for selecting which external supply voltage to sample. The SCLKVX signal corresponds to SMPA[6:0] signal 2450.4 and SMPB[6.0] signal 2448.4, which control the sampling (and holding) of analog voltages in SHM 1207 for analog to digital converter 1206. The SELVX signal provides a select clock for selecting which external voltage to sample. An IDDO signal provided to I/O circuits 3008.4 and 3016.4 indicates a test control signal for these circuits.

[0284] An external current is sampled by I/O circuit 3016.4 via pads 3002.4 and 3006.4 and utilizing a resistor 3004.4 connected between pads 3002.4 and 3006.4, with-an output signal (OUTC) provided. I/O circuit 3016.4 receives an SWCAP[2:0] signal and an SELIX signal from regulation control module (REG) 1204 and an SCLKIX signal from DPC 1201. The SWCAP[2:0] provides input control for a switched capacitive network, discussed further below. The SCLKIX signal corresponds to SMPA[6:0] signal 2450.4 and SMPB[6:0] signal 2448.4, which control the sampling (and holding) of analog voltages (and currents) in SHM 1207 for analog to digital converter 1206. The SELIX signal provides a select clock for selecting which external current to sample.

[0285] Multiplexer 3012.4, under control of a MXSEL[4:0] signal from regulation control module (REG) 1204, selects which input is presented to analog to digital converter 1206 as an output signal VINADC. Besides the input signals discussed above, multiplexer 3012.4 also receives a VOUT signal from a Kelvin temperature sensor and a COUL0 and a COUL1 signals, which are Coulombmetric measurements from available battery supplies (e.g., battery zero and battery one, discussed further herein).

[0286] FIG. 40A is a functional schematic illustrating an exemplary implementation for I/O circuits 3008.4 and 3016.4. An external voltage or current is sampled via a pad 3030.4 and electrostatic discharge protection (ESD) circuitry 3032.4, with the sampled signal passing through a pass gate 3034.4 to a logic circuit 3036.4. Logic circuit 3036.4 buffers or scales the sampled signal, for example, prior to providing it to a capacitor 3038.4, which acts as a holding capacitor until a pass gate 3040.4 is opened and the sampled signal is provided to analog to digital converter 1206 via a lead 3042.4 (labeled OUTV or OUTC for output voltage or output signal from switched capacitor network).

[0287] In terms of general operation, the select clocks (i.e., the SCLKIX, SCLKVX, and AUX signals from DPC 1201) control pass gate 3034.4 for allowing an input voltage to charge capacitor 3038.4. The select lines (i.e., the SELIX, SELVX, and SSUP signals from regulation control module (REG) 1204) present the value stored on capacitor 3038.4 to be scaled (e.g., by voltage divider 3010.4) and passed to analog to digital converter 1206. If current is being measured, capacitor 3038.4 becomes part of a switched capacitor network to multiply a sampled input voltage (i.e., across resistor 3004.4) to a desired value for conversion by analog to digital converter 1206.

[0288] FIG. 40B is a circuit schematic illustrating exemplary voltage and current selection. An SHWIREI signal, an SHWIREV signal, and an SNHREF signal is provided via pads 3060.4, 3062.4, and 3064.4 respectively. The SHWIREI signal, SHWIREV signal, and SNHREF signal represent signals to be measured by I/O circuits 3008.4 and 3016.4 (FIG. 40) for corresponding current, voltage, and ground reference. As illustrated, the SCLKIX and SCLKVX signals control corresponding pass gates 3066.4, 3072.4, 3076.4, and 3080.4 to allow an input voltage to charge a corresponding capacitor 3084.4 or 3086.4. The SELIX and SELVX signals control corresponding pass gates 3068.4, 3074.4, 3078.4, and 3082.4 to allow the charge on corresponding capacitors 3084.4 or 3086.4 to pass as an output signal (labeled VOUTV or VOUTC for sampled voltage or current, respectively).

[0289] FIG. 40C is an exemplary interface signal block diagram for SHM 1207 in accordance with another implementation. The interface signals include an IDDQ signal 3700.4, an AUX0 signal 3702.4, an AUX1 signal 3704.4, a TEMPEXT signal 3706.4, a VOUT signal 3708.4, a SUPPASENSE signal 3710.4, a SUPPBSENSE signal 3712.4, a SHWIREI[6:0] signal 3714.4, a SHWIREV[6:0] signal 3716.4, an SMPA[6:0] signal 3720.4, an SMPB[6:0] signal 3722.4, an SHNREF[9:0] signal 3724.4, a SELA[12:0] signal 3726.4, a SELB[6:0] signal 3728.4, a DIV[2:0] signal 3730.4, a SHM_CLK signal 3732.4, a MUXSEL[1:0] signal 3734.4, a DONE signal 3738.4, a VSEL_SMPA[8:0] signal. 3740.4, a ISEL_SMPA[6:0] signal 3742.4, a VREF_HALF signal 3748.4, a VSSIOA/B signal 3750.4, a VSS signal 3752.4, an AVS signal 3754.4, a VINADC signal 3758.4, an AVD signal 3760.4, a VDD signal 3762.4, and a VDDIOA/B signal 3764.4. Pads 3718.4 indicate signals received external to switching power supply controller 1200.

[0290] IDDQ signal 3700.4 is a test signal, while AUX0 signal 3702.4 and AUX1 signal 3704.4 are external signals for auxiliary applications. TEMPEXT signal 3706.4 is received from a temperature sensor circuit attached to the external battery. VOUT signal 3708.4 represents the voltage from the Kelvin temperature sensor (e.g., Kelvin temperature sensor 2232.4 in FIG. 54) that will be sampled and held to isolate its ground from the ground of analog to digital converter 1206 when this voltage gets converted.

[0291] SUPPASENSE signal 3710.4 and SUPPBSENSE signal 3712.4 are used to sense the voltage on the external Supply A and Supply B power supplies. SHWIREI[6:0] signal 3714.4 is used for sensing the voltage drop across a sense resistor for each of the 7 external power supplies. SHWIREV[6:0] signal 3716.4 is used for sensing the voltage for each of the 7 external power supplies. SHNREF[9:0] signals 3724.4 are ground references for both the voltage and the current of each external power supply, plus there are three additional references for Supply A, Supply B, AUX0 signal 3702.4, AUX1 signal 3704.4, and TEMPEXT signal 3706.4.

[0292] SMPA[6:0] signal 3720.4 is received from DPC 1201 and is used for sampling voltages at the load of the seven power supplies. SMPB [6:0] signal 3722.4 is received from DPC 1201 and is used for sampling the voltage drop across the sense resistor for the seven supplies (described in further detail below). SELA [12;0] signal 3726.4 is received from regulation control module (REG) 1204 and determines which channel voltage needs to be presented to a divider 3804.4 (FIG. 40D). SELB [6:0] signal 3728.4 is received from regulation control module (REG) 1204 and determines which channel current measurement.

[0293] VSEL_SMPA[8:0] signal 3740.4 is received from regulation control module (REG) 1204 and determines the swapping of the sample pulses for the leading edge. ISEL_SMPA[6:0] signal 3742.4 is received from regulation control module (REG) 1204 and determines the swapping of the sample pulses for the falling edge.

[0294] DONE signal 3738.4 is received from analog to digital converter 1206 when it is done with a conversion. DIV[2:0] signal 3730.4 is received from regulation control module (REG) 1204 and determines the divider value of divider 3804.4 for the voltage.

[0295] SHM CLK signal 3732.4 is received from CLKGEN 1223, with a frequency that is 16 times the frame frequency and is the value generated in CTS[4] within DPC 1201 as explained elsewhere herein. MUX_SEL [1:0] signal 3734.4 is used for selecting an output signal for a multiplexer 3806.4 (FIG. 40D, e.g., an analog mux) that will be presented to analog to digital converter 1206. VDDIOA/B signals 3764.4 are the highest voltages needed for substrate connection when using high voltage switches. VSSIOA/B signals 3750.4 are the lowest voltages needed for substrate connection when using high voltage switches.

[0296] VDD signal 3762.4 (e.g., 3.3 V) is a digital voltage required for some control logic. VSS signal 3752.4 is a digital ground required for some control logic. AVD signal 3760.4 (e.g., 3.3 V) is an analog voltage required for some control logic. AVS signal 3754.4 is an analog ground to be tied to a ground of analog to digital converter 1206 when converting values into analog to digital converter 1206. VINADC signal 3758.4 is provided to analog to digital converter 1206, for example, with a range between 0 and 3.0 V. VREF_HALF signal 3748.4 is a voltage offset needed for a multiplier (discussed in detail below) to measure either positive or negative voltage differences across analog to digital converter 1206. The value of VREF_HALF signal 3748.4 is one-half that of VREF signal 3440.4 (FIG. 54A) and is received from IVS 1209. The interface signals are summarized in Table 1.1.7a.

[0297] FIG. 40D is a functional block diagram 3788.4 of SHM 1207 in another implementation. FIG. 40D is similar to FIG. 40 and therefore a discussion regarding general operation will not be repeated. Block diagram 3788.4 of FIG. 40D includes an I/O circuit 3800.4, a multiplexer 3802.4, a divider 3804.4, a multiplexer 3806.4, an I/O circuit 3810.4, and multiplexers 3808.4, 3820.4, and 3822.4.

[0298] The general function of block diagram 3788.4 is to sample nine voltages, seven of them being the external output voltage supplies and two of them being the Supply A and the Supply B, and also to sample the voltage difference across a sense resistor (represented by a sense resistor 3814.4 in FIG. 40D) for measuring current in each of the seven “regulated” output voltage supplies. Additionally, there are a few signals that are sampled on an as needed basis, for example, the voltage entering switching power supply controller 1200 as a result of a temperature sensor system that is connected to the battery (i.e., the voltage of VOUT SIGNAL 3708.4), an internal voltage coming from Kelvin temperature sensor 2232.4 (FIG. 54) and the voltages of TEMPEXT signal 3706.4, AUX0 signal 3702.4 and AUX1 signal 3704.4.

[0299] In general, block diagram 3788.4 interfaces with DPC 1201, regulation control module (REG) 1204, and analog to digital converter 1206 and receives from external sources three analog inputs (via pads 3818.4, 3816.4, and 3812.4) that can be up to 15 V (e.g., for PDAs) or 16 V (e.g., for digital cameras). As shown in FIG. 40D, I/O circuits 3800.4 and 3810.4 are coupled together to sample both voltage and current at the same time, and convert these measurements at different times as needed.

[0300] Multiplexer 3820.4 under control of ISEL_SMPA[6:0] signal 3742.4 selects a signal from SMPA[6:0] signal 3720.4 and SMPB[6:0] signal 3722.4 and generates an SMPI signal 3821.4 for I/O circuit 3810.4. Multiplexer 3822.4 under control of VSEL_SMPA[8:0] signal 3740.4 selects a signal from SMPA(6:01 signal 3720.4 and SMPB[6:0] signal 3722.4 and generates an SMPV signal 3823.4 for I/O circuit 3800.4.

[0301] FIG. 40E illustrates an exemplary block diagram for I/O circuits 3800.4 and 3810.4 in one implementation, which includes a number of transmission gates 3824.4 and 3830.4, ESD protection 3825.4.4, one or more capacitors 3828.4, along with a logic circuit 3826.4 having a test mechanism (via IDDQ signal 3700.4). FIG. 40E is similar to FIG. 40A and therefore the general operation will not be repeated.

[0302] As shown in FIG. 40E, SHWIREI signal 3716.4 represents a voltage signal to be measured across sense resistor 3814.4 (FIG. 40D). As an example for sampling a current, a switched capacitor network will be utilized for the multiplication to be done for each of the seven currents explicitly (discussed in further detail below). SHWIREV signal 3714.4 represents a voltage signal to be measured, and SHNREF signal 3724.4 represents a voltage signal for a ground reference. The Supply A and the Supply B, along with TEMPEXT signal 3706.4 and VOUT signal 3708.4, will be measured using a combination of SHWIREV signal 3714.4 and SHNREF signal 3724.4 to sample and measure the voltages.

[0303] FIG. 40F is an exemplary circuit schematic illustrating voltage and current selection for another implementation and may be viewed as an expanded view of a portion of FIG. 40E. In terms of general operation (in reference to FIG. 40D and1.1.7 g), the three basic analog input signals is as follows. When there is a sample pulse for SMPV signal 3823.4, a measured voltage between pads 3816.4 and 3818.4 is stored in a holding capacitor 3858.4 as the voltage measurement at the load.

[0304] When there is a sample pulse for SMPI signal 3821.4, a measured voltage between pads 3812.4 and 3816.4 is stored across capacitors 3856.4, arranged in a parallel fashion by appropriate switching of pass gates 3840.4, which represents the voltage measured across sense resistor 3814.4. Note that the voltage difference across sense resistor 3814.4 can be positive or negative depending on the external power supply topology.

[0305] When a SELA signal corresponding to SELA[12:0] signal 3726.4 is asserted, the voltage in holding capacitor 3858.4 gets transferred into voltage divider 3804.4 as a VOUTV signal 3912.4. When there is a SELB signal corresponding to SELB[6:0] signal 3728.4, capacitors 3856.4 are stacked serially, by appropriate switching of pass gates 3840.4, to perform voltage multiplication (e.g., multiplication of 4) and provide a VOUTC signal 3859.4. The reference for the voltage multiplication is done with respect to VREF_HALF signal 3748.4.

[0306] Divider 3804.4 divides the voltage down to a range of 0 to 3 V so that it is within desired limits and analog to digital converter 1206 can read the value. Divider circuitry for divider 3804.4 will be implemented, for example, using capacitor ratios with switches, two non-overlapping clocks, and control logic. The non-overlapping clocks discharge the capacitance of the divider network and prepare the divider network for the next voltage sample.

[0307] FIG. 40G is an exemplary clock generation circuit in accordance with another implementation. The two non-overlapping clocks, a DCLKH signal 3884.4 and a DCLKL signal 3886.4, will be implemented by employing two RS latches 3876.4 and 3878.4 and control logic, such as with an AND gate 3880.4 and an OR gate 3882.4. The clock generation circuit receives DONE signal 3738.4, SHM_CLK signal 3732.4, and DIV[2:0] signal 3730.4, as shown, to produce DCLKH signal 3884.4 and DCLKL signal 3886.4. Table 1.1.7b provides exemplary divide or scalar values for given input voltages to produce representative values from analog to digital converter 1206.

[0308] As an example, the maximum input voltage stored in holding capacitor 3856.4 is 16 V. Depending upon the type of capacitor used (e.g., PiP capacitors can only withstand 13.5 V), two or more capacitors may be stacked in accordance with an implementation of divider 3804.4.

[0309] FIG. 40H is an exemplary voltage divider 3898.4 in accordance with another implementation for voltage divider 3808.4. VOUTV signal 3912.4 is a selected channel voltage and switches 3900.4, 3902.4, 3904.4, 3908.4, 3910.4, and 3912.4 are controlled by the non-overlapping clocks (DCLKH signal 3884.4 and DCLKL signal 3886.4) as shown. For example, because there are four values for division (i.e., divide values in Table 1.1.7b), the default will be a divide by 1 which will allow VOUTV signal 3912.4 to pass through directly, with DIV[2:0] signal 3730.4 set to logic 0. Voltage division is accomplished by charge sharing across capacitors. Different effective capacitor values can be selected by transfer gates 3900.4,3902.4 and 3904.4 and their associated capacitors 3914.4,3916.4 and 3918.4. The DIV[2:0] determines which transfer gates are selected to achieve the divide ratios. Table 1.1.7c provides exemplary divide values based on DIV[2:0] signal 3730.4.

[0310] I/O circuit 3810.4 (FIG. 40D) includes a switched capacitor network to provide voltage multiplication for a measured voltage difference across sense resistor 3814.4 for a corresponding current measurement. For example, in a continuous mode of operation at 2A and using a 0.1 ohm resistor for sense resistor 3814.4, the voltage difference across sense resistor 3814.4 is 200 mV. Thus, voltage multiplication based on the desired voltage parameters is desirable. Furthermore, because the external battery may be charging itself from another power supply configuration, the current sense may be negative with respect to the ground of analog to digital converter 1206 and the multiplier circuit, illustrated below in reference to FIG. 40I, has the capability of reversing polarities to always present a positive voltage difference to the ADC.

[0311] Table 1.1.7d provides exemplary current measurements for a 2A power supply system with a 0.1 ohm resistance for sense resistor 3814.4 (where D.C.S. and C.S. stand for Deep Cycle Skipping and Cycle Skipping, respectively).

[0312] FIG. 40I is an exemplary voltage multiplier 3928.4 in accordance with another implementation for I/O circuit 3810.4. Voltage multiplier 3928.4 includes pass gates 3930.4 and capacitors 39344. In terms of general operation, when a sampling pulse from SMPI signal 3821.4 is received, capacitors 3930.4 are arranged in parallel by pass gates 3930.4. When a SELB signal of SELB[6:0] signal 3728.4 is asserted, capacitors 3934.4are stacked in series via pass gates 3930.4 and connected between either positive or negative with respect to VREF_HALF signal 3748.4. It should be noted that no matter what the polarity is for the voltage drop, it will not affect the measurements since the reference is not ground but an offset voltage provided by VREF_HALF signal 3748.4.

[0313] Because there is a 4x multiplication done at once for each current measurement channel (i.e., for the different current measurements for each power supply), there will be 7 multipliers, with one for each external power supply. FIG. 40J illustrates an exemplary block diagram of I/O circuit 3810.4 with various interface signals shown.

[0314] Multiplexer 3806.4 (FIG. 40D) employs high voltage switches and care needs to be taken so that divider 3804.4 does not present a high voltage via multiplexer 3806.4 to analog to digital converter 1206. FIG. 40K is a multiplexer scheme in accordance with another implementation that mitigates the threat of a high voltage being presented to analog to digital converter 1206. As shown, SHM_CLK signal 3732.4 is gated with DIV[2:0] signal 3730.4, by an AND gate 4002.4, to properly present a DIVOUT signal 4010.4 from divider 3898.4 or VOUTC signal 3859.4 to analog to digital converter 1206 (not shown) via a multiplexer 4008.4 and VINADC signal 3758.4.

[0315] FIG. 11 shows an alternative structure for implementing the principles of this invention. In FIG. 11, controller 111 detects the current through resistor R and the voltage across load capacitor CL. The charge on load capacitor CL is used to drive a load on lead 112. The controller 111 produces an error signal proportional to the voltage difference between the voltage across capacitor CL and a reference voltage, shown as system ground, but which could be any other desired reference voltage. The output signal from controller 11l is supplied to an A to D converter 113 having ten output bits. This allows 1,024 levels to be identified and quantized. The ten output bits from the A to D converter are sent on 10-bit bus 114 to comparator 115 where these bits are compared to a reference number driven from programmable reference 116. Reference 116 is programmed by the user to contain the desired reference voltage to be held by load capacitor CL. The output signal from comparator 115 is a binary difference signal D0 through D9 which is transmitted on 10-bit bus 117 to phase select circuit 118. Phase select circuit 118 is of the type, for example, shown above in FIG. 6. The signals DO through D9 from comparator 115 are decoded using a circuitry of a type shown, for example, in FIG. 10 and are used to generate a signal which controls a pass transistor which allows a selected output signal from an inverter in the ring oscillator to be applied to the red input lead 119aof exclusive OR gate 119. The green input lead 119b, as described above, will typically be the output signal pulled from the first inverter in the ring oscillator string. The result is a pulse width modulated output signal on lead 119cfrom exclusive OR gate 119, which is then used to charge capacitor CL through resistor R (FIG. 11). The current through resistor R is measured by a signal detected on leads 111aand 111band used in controller 111 to provide a measure of the charge being provided to load capacitor CL.

[0316] Analog to digital converter 1206 (FIG. 12), which measures and digitizes the voltage of an analog signal to 10-bits of resolution, can be implemented by a combination of a custom low-power mixed-signal circuit (ADC) and a digital logic circuit for interfacing the ADC to external logic circuits. Inputs and output signals to analog to digital converter 1206 include both analog and digital signals. In one implementation, the analog to digital conversion can operate at 10 Msps (i.e., Mega-samples per second).

[0317] FIG. 14 is a block diagram showing interface signals of analog to digital converter 1206, according to one implementation. As shown in FIG. 14, analog to digital converter 1206 includes: (a) analog measurement interface (AMI) 1401, digital interface (DI) 1402, and power supply interface 1403. Analog measurement interface 1401 includes analog input signal 1401a(VIN), which is sampled for analog to digital conversion, and an analog voltage reference input signal 1401b(VREF).

[0318] Digital interface 1402 comprises data output bus 1402a(DOUT[9:0]), analog to digital conversion completion or “done” signal 1402b(DONE), analog to digital conversion initiation plus reset signal 1402c(START/RSTN), and clock signal 1402d(CLK). In this implementation, data output bus 1402ais a 10-bit bus which provides the result of the analog to digital conversion. In this implementation, clock signal 1402dhas a frequency of about 128 MHz and a duty cycle of about 50%. When the asynchronous reset signal 1402eis held at a low logic value, circuits in analog to digital converter 1206 are held in a reset state. Similarly, when power down signal 1402f is held at a low logic value, the analog circuits in analog to digital converter 1206 are powered down, and the digital logic circuits are placed in a low-power state.

[0319] Power supply interface 1403 includes analog power and ground references 1403aand 1403b(AVD and AVS), and digital power and ground references 1403cand 1403d(VDD and VSS), respectively. In one implementation, both the analog and the digital power references (i.e., AVD and VDD) are provided at 3.3V±10%.

[0320] FIG. 15 is a block diagram showing the interface signals of kelvin temperature sensor (KTS) 1500, which is an absolute temperature sensor circuit that produces an output voltage linearly related to the CIRCUIT'S absolute temperature. As shown in FIG. 15, Kelvin temperature sensor 1500 receives analog power and ground reference voltages at terminals 1501 and 1502 and asynchronous power-down control signal (PDN) at terminal 1503, and provides output voltage VOUT at terminal 1504, which is linearly related to the temperature of the circuit between 0.0V and 3.0V.

[0321] Section 1.2.1 Hardware Description Regulation Control Module (REG) 1204

[0322] Combined Section 1.2.1.1 detailed description of the REG module and Section 1.2.1.2 voltage/current feedback SPS—hardware portion

[0323] Referring now to FIG. 41 and FIG. 12, Regulation control module (REG) includes a microcontroller 500.1 configured to generate pulse width modulation (PWM) information for a plurality of switching power converters under the control of switching power supply controller 1200. This PWM information may include the switching times for power switches within the PWM switching power converters as well as voltage and current sampling times for each switching power converter. Regulation control module (REG) provides the PWM and sample information to Digital Signal to Pulse Converter (DPC) 1201, which in turn generates signals controlling pulse rising and falling edges to implement the PWM information, as well as generating the sample pulses for voltage and current sampling.

[0324] As described further herein, DPC 1201 may be implemented in a number of ways, e.g., it may be CAM-based, ring-oscillator-based, comparator-based, or RAM-based. The following description will assume that DPC 1201 is in the CAM-based embodiment. However, it will be appreciated that regulation control module (REG) 1204 would operate analogously should DPC 1201 have a non-CAM-based embodiment.

[0325] The frame rate implemented by DPC 1201 affects the required processing speed of microcontroller 500.1. A DPC frame is illustrated in FIG. 37. For example, it seven switching power supplies are being controlled by switching power supply controller 1200 and the DPC frame rate is 524 KHz, the PWM information for each switching power converter may be updated approximately every 2 microseconds, which is the corresponding DPC frame period. Accordingly, a regulation scheduler module 521.1 may divide each DPC frame period into calculation periods corresponding to the various switching power supplies being regulated so as to implement a pipelined timeslot-based approach to the calculations for the PWM updates and voltage and current feedback conversion scheduling for each switching power supply under control. In addition, another calculation period may be required for each DPC frame for related calculations with respect to “book-keeping” tasks, and the monitoring of the various power supplies for the switching power supplies being regulated. Thus, should there be seven switching power supplies under control at a DPC frame rate of 524 KHz, there would be eight 250 ns timeslots (7 power supplies+1 slot for bookkeeping). Thus, the microcontroller 500.1 would have only 250 nanoseconds to calculate the PWM information (pulse width) for each of the seven switching power supplies. Regulation scheduler module 521.1 receives switching power supply controller 1200 clock signal 522.1 and CST signals 2458.4 and coordinates the timing of the various modules within regulation control module (REG) 1204 accordingly. If each calculation period may be completed in 32 arithmetic steps (corresponding to 32 cycles of internal clock 522.1), microcontroller 500.1 would require an instruction execution rate of 128 MHz. The arithmetic functions implemented in each instruction may include, for example, any of add, subtract, multiply, magnitude comparison, and absolute value. Microcontroller 500.1 may be implemented using any of a number of architectures to achieve the required operation speed, including a RISC-based or a VLIW-based architecture (i.e., “reduced instruction set computer”-based architecture or “very-long-instruction word”-based architecture). For example, in a VLIW-based embodiment, microcontroller 500.1 may include a VLIW computing engine 517.1 that interfaces with a decode ROM (i.e., read-only memory, not illustrated) for decoding the VLIW instructions. In addition, microcontroller 500.1 may include a RAM 516.1 for storing data and parameter values. Register files 518.1 store the regulation parameter values for the various switching power supplies under regulation and provides run-time register resources for calculations taking place in VLIW engine 517.1. In one embodiment, VLIW engine 517.1 includes a topology register which points to the beginning of a 32-instruction segment in memory (corresponding to the number of instructions that can be executed within a time slot). The topology register is so-named as the regulation algorithm for each topology (e.g., buck, boost, SEPIC) can be stored at different 32-instruction segments in memory. In addition, a 5-bit program counter can be provided for sequencing VLIW engine 517.1 through the 32-instruction segment in memory.

[0326] Referring again to FIG. 37, for a given switching power converter, regulation control module (REG) 1204 computes the timings for the rising and falling edges for a PFET pulse 2410.4 and an SFET pulse 2412.4. The rising edge and falling edge of PFET pulse 2410.4 control the on and off times, respectively, of a given switching power converter's primary FET switch as driven by NFET driver module 1202. Similarly, the rising edge and falling edge of SFET pulse 2412.4 control the on and off times, respectively, of the given switching power converter's secondary FET switch as driven by NFET driver module 1202. The rising edge and falling edge of SMPA pulse 2414.4 may control the voltage sampling period used by sample and hold module (SHM) 1207 to obtain voltage feedback information from the corresponding switching power converter. Similarly, the rising edge and falling edge of SMPB pulse 2416.4 may control the current sampling period used by SHM 1207 to obtain current feedback information from the corresponding switching power converter. However, either pulse SMPA 2414.4 or SMPB 2416.4 may be used for voltage or current feedback purposes.

[0327] The four pulses illustrated in FIG. 37 thus correspond to eight independent rising and falling edge times. For example, the falling edge of SMPA pulse 2414.4 may be programmed to coincide with the rising edge of PFET pulse 2410.4 (PFTS), because SMPA pulse 2414.4 can be required to be completed no less than 150 nano-seconds prior to the rising edge of PFET 2410.4. (This relationship allows sufficient time for microprocessor 500.1 to calculate the required duration of PFET pulse 2410.4 using the data sampled by SHM 1207 using SMPA pulse 2414.4 and converted by analog to digital converter 1206.) Similarly, the falling edge of SMPB pulse 2416.4 may be programmed to coincide with the falling edge of PFET pulse 2410.4 (PFTR), thereby allowing sampling of the peak current in external inductor that occurs immediately prior the falling edge of PFET pulse 2410.4. The widths of sampling pulses (i.e., SMPA pulse 2414.4 and 2416.4) can be programmed, for example, at 2 or 4 nanoseconds. Because at least 50 nanoseconds are to be provided between sampling a pulse and a transition in the PFET and SFET pulses, the effective duty cycle range computed by microprocessor 500.1 is 10% to 90%. Duty cycles of 0% or 100% can be achieved in the DPC by masking the edge transitions of the PFET or SFET pulses, as needed.

[0328] Regardless of the number of independent pulse edges regulation control module (REC) 1204 must control, other objectives besides power regulation may affect the scheduling of the various pulse rising and falling edges for each controlled switching power converter within a DPC frame. For example, having two switching power supplies switch simultaneously may generate electromagnetic interference (EMI) or other undesirable effects. In addition, simultaneous switching output (SSO) requirements may limit the number of FETS that may be switched at any given time. Accordingly, regulation control module (REG) 1204 may schedule the various pulse rising and falling edges to satisfy such objectives using an edge scheduler 510.1. As described above, microcontroller 500.1 may implement a pipelined regulation approach such that each DPC frame is divided into calculation periods to calculate pulse width information 505.1 for each switching power supply controlled by switching power supply controller 1200. In a given DPC frame, the necessary calculations to update PWM and schedule the digitization of the related analog voltage and current feedback signals are performed with respect to the preceding DPC frame. If SHM clock signal 3732.4 has a frequency {fraction (1/16)}^ththat of SPS clock 522.1, two feedback signal analog-to-digital conversions may be accomplished per calculation period. Thus, a given DPC frame may be divided as follows:

[0329] Thus, during slot (or calculation period) 0, the conversions for the voltage and current feedback signals for the zeroth switching power supply occur. Then, VLIW engine 517.1 may perform the necessary PWM updates to a register file 518.1 using the converted feedback signals for the zeroth switching power supply during calculation period 1. Then, DPC I/F 590.1 may perform the necessary PWM update using the converted feedback signals from the zeroth slot of the previous DPC frame. In addition, the conversions for the first switching power supply feedback signals may occur in calculation period 1. Then, VLIW engine 517.1 may perform the necessary PWM updates to a register file 518.1 using the converted feedback signals in the second calculation period, the DPC I/F may perform the PWM updates using the converted feedback signals from the first time slot of the previous DPC frame, and so on for the remaining switching power supplies. Note that in calculation period 7, an analog-to-digital conversion is made for the voltages of powers supplies A and B. No corresponding calculation period need be scheduled (switching power supply controller 1200 does not regulate these supply voltages). Because these conversions occur in the seventh timeslot, the zeroth timeslot of the next DPC frame may be used by regulation scheduler 521.1 to schedule any required inter-process communication and bookkeeping. A separate state machine may be used to implement edge scheduler 510.1. Having received the pulse width information and sample commands from microcontroller 500.1, edge scheduler 510.1 may then schedule the various pulse rising and falling edges. For example, referring again to FIG. 37, each DPC frame may be divided into a plurality of counts, e.g., 1024 counts (from 0 to 1023). The time between these counts determines the maximum PWM resolution that may be implemented. The various pulse edges may be scheduled according to the counts a DPC frame is divided into. Thus, edge scheduling would comprise assigning each edge to a DPC frame count. A number of algorithms may be used to provide the appropriate edge scheduling. For example, should a pulse edge from two switching power converters be scheduled for the same count, edge scheduler 510.1 could delay one of the conflicting pulse edges by one or more counts. Sample pulses SPAS 2414.4 and SPBS 2416.4 may be scheduled to have a rising edge one or more counts before the rising edge and falling edges of PFET pulse 2410.4, respectively. A special cycle skipping mode is enabled by the edge scheduler through a programmable register. This provides the ability to skip the generation of a PFET pulse during a specified cycle. This is accomplished by writing the same value to DPC 1201 for rising and falling edges of PWM pulses thereby generating a 0% DC output for those pulses.

[0330] To minimize the need for edge scheduling, central processing module (SYS) 1205 initializes regulation control module (REG) 1204 with appropriate rising and falling edge schedules prior to normal operation. For example, central processing module (SYS) 1205 stores in memory the desired voltage levels provided by the various switching power converters, the expected power drawn by the loads, and the associated operating characteristics such as inductances and capacitances used in the switching power converters. From this information, central processing module (SYS) 1205 may calculate an expected pulse width for each switching power converter. In turn, central processing module (SYS) 1205 may then assign pulse edges corresponding to these pulse widths distributed across a DPC frame to help reduce the need for edge scheduling. For example, assuming a pipelined approach has been implemented, the rising edge of PFET pulse 2410.4 for each switching power supply has been calculated by central processing module (SYS) 1205. Central processing module (SYS) 1205 then provides these initial edge schedules and other information to regulation control module (REG) 1204 through an internal bus 520.1, which in turn may comprise buses for SFR-mapped data as well as buses for memory-mapped data. A bus interface 525.1 may be used to coordinate the flow of data between regulation control module (REG) 1204 and central processing module (SYS) 1205 on internal bus 520.1 and provide the coordinated data to microcontroller 500.1. For example, internal bus 520.1 may comprise an SFR enable signal REG_SFR_EN 700.1 to indicate an SFR transaction is set to occur; an SFR address signal SFR_ADDR[7:0] 701.1; an SFR data out signal SFR_DATA_OUT[7:0] 702.1 from central processing module (SYS) 1205; an SFR write enable SFR_WR 703.1; an SFR read enable SFR_RD 704.1; an SFR data out signal SFR_DATA_IN[7:0] 705.1 from central processing module (SYS) 1205; a memory-mapped enable signal REG_MEM_EN 706.1 to indicate a memory-mapped transaction is set to occur; a memory-mapped address signal MEM_ADDR[15:0] 707.1; a memory-mapped data out signal MEM_DATA_OUT[7:0] 708.1 from central processing module (SYS) 1205; a memory-mapped data write enable signal MEM_WR_N 709.1; a memory-mapped data read enable signal MEM_RD_N 710.1; a memory-mapped data out signal MEM_DATA_IN[7:0] 711.1 from regulation control module (REG) 1204; a mode signal PD[1:0] 712.1, a REG-generated interrupt signal REG_INT 713.1; and the central processing module clock signal SYS_CLK 714.1. By coordinating the flow of these signals on internal bus 520.1, interface module 525.1 allows central processing module (SYS) 1205 to configure regulation control module (REG) 1204 and monitor its operation.

[0331] Referring again to FIG. 12, regulation control module (REG) 1204 receives digitized feedback information (representing voltage and current samples) from each switching power converter from analog to digital converter 1206 as signal DOUT[9:0] 715. The analog voltage and current samples digitized by analog to digital converter 1206 are provided by SHM module 1207 based upon the rising and falling edge times corresponding to pulses SPAS 2414.4 and SPBS 2416.4. Referring now to FIG. 40D, a multiplexer 3806.4 within SHM 1207 may select between the sampled-and-held voltages and provide the selected voltage to analog to digital converter 1206. To keep analog to digital converter 1206 operating efficiently, a conversion scheduler 540.1 receives the timing information from signals SMPA 2406.4 and SMPB 2408.4 and commands multiplexer 3806.4 accordingly using MUX_SEL[1:0] signal 3734.4. As discussed above, if a pipelined approach is implemented, two conversions may be accomplished for each calculation period in a DPC frame. Conversion scheduler 540.1 drives SHM module 1207 to perform the required scaling of the analog feedback signals and properly schedule the digitization of the converted values in analog to digital converter 1206.

[0332] Analog to digital converter 1206 may respond to a START/RSTN signal 586.1 from conversion scheduler 540.1 toggling LOW to HIGH to begin the analog-to-digital conversion process for a given analog feedback signal. During times of no active ADC activity, REG may pull START/RSTN signal 586.1 LOW to put analog to digital converter 1206 into a low power mode. To keep the sampled voltages within the dynamic range of analog to digital converter 1206, conversion scheduler 540.1 provides a scalar variable, DIV[1:0] 3730.4, to SHM 1207 to provide the appropriate scaling. Conversion scheduler 540.1 may drive SHM 1207 to select the appropriate voltage feedback signal for conversion through selection signal SELA[12:0] 3726.4. Similarly, selection signal SELB[8:0] 3728.4 drives the appropriate selection of current feedback signals. Because each pulse SMPA 2406.4 or SMPB 2408.4 may be used for either voltage or current feedback, conversion scheduler 540.1 indicates which pulse has been used for voltage or current feedback by signals VSEL_SMPA[8;0] 3728.4 and ISEL_SMPA[6:0] 3742.2, respectively.

[0333] During a given DPC frame, multiplexer 3806.4 will begin to receive the various sampled-and-held voltage and current feedback signals. Conversion scheduler 540.1 may simply cause multiplexer 3806.4 to select the sampled-and-held feedback voltages as received in real time. Alternatively, conversion scheduler 540.1 may delay the scheduling according to whether or not all the feedback information has been received from a given switching power converter. For example, suppose the voltage feedback from a given switching power converter has been sampled-and-held and received by multiplexer 3734.4. Conversion scheduler 540.1 would not cause multiplexer 3734.4 to select this voltage feedback signal, however, until the corresponding current feedback signal has also been received at multiplexer 3734.4.

[0334] To allow sufficient setup time for SHM 1207 to properly latch data, conversion scheduler 540.1 may switch the various SHM 1207 control signals described above one SPS clock cycle 522.1 before calculation period boundaries within a given DPC frame. In addition, conversion scheduler 540.1 may switch MUX_SEL[1:0] signal 3734.4 one-half SPS clock cycle 522.1 after values for SHM 1207 control signals SELA[12:0] 3726.4, SELB[6:0] 3728.4, and DIV[1:0] 3730.4 have been switched to protect analog to digital converter 1206 from receiving any dangerous voltage fluctuations. In response to START signal 586.1, SHM module 1207 will generate the actual START pulse 3768.4, as shown in FIG. 40C, to analog to digital converter 1206 to begin the conversion. Analog to digital converter 1206 signals the completion of the conversion to regulation control module (REG) 1204 using signal DONE 3738.4.

[0335] In addition to managing the scheduling of the feedback signals from the switching power supplies, conversion scheduler 540.1 may also manage the sampling and conversion of the external supply A and B voltages, and the voltages representing external and internal temperatures. Upon request from central processing module (SYS) 1205, regulation control module (REG) 1204 schedules a conversion of the external and internal temperature voltages (TEMPEXT signal 3706.4 and VOUT signal 3708.4, respectively, as illustrated in FIG. 1.1.7d).When the conversion is complete regulation control module (REG) 1204 writes the data to a status register which is read by central processing module (SYS) 1205 so that the converted temperature values may be used in couloumbmetric measurements.

[0336] Conversion scheduler 540.1 controls the conversion of feedback samples as well as source identification of the ADC data—i.e, whether or not it is a voltage or current sample and to which switching power supply it corresponds as sample data DOUT[9:0] 715.1. However, in one embodiment, pulse widths are not adjusted if the voltage and current samples for a given switching power supply are within a desired operating range. This condition does not require VLIW engine 517.1 to do computations, thus saving power. Thus, regulation control module (REG) 1204 may include limit comparison module 560.1 to test whether or not a given feedback signal is within the desired operating range (which may be denoted as the deadband limits). If DOUT[9:0] 715.1 is within limits, conversion scheduler 540.1 may indicate this condition to microcontroller 500.1 so that no PWM adjustment calculations need be performed for the associated switching power converter, and no DPC 1201 writes are required. In addition, limit comparison module 560.1 may also test whether DOUT[9:0] 715.1 is within acceptable high and low regulation limits. If DOUT[9:0] 715.1 is within these limits, limit comparison module 560.1 directs VLIW engine 517.1 to calculate new PWM values as described above, and values calculated for DOUT[9:0] 715.1 being within limits, are written to DPC 1201. If DOUT[9:0] 715.1 is outside these limits, limit comparison module 560.1 directs VLIW engine 517.1 to calculate new PWM values as described above, and values calculated for DOUT[9:0] 715.1 being outside limits, are written to DPC 1201.

[0337] In response to assertion of DONE signal 3738.4, limit comparison module latches in DOUT[9:0] 715.1. Although conversion scheduler 540.1 and limit comparison module 560.1 are illustrated as functionally separate from microcontroller 500.1, these functions may be performed by microcontroller 500.1 or by separate state machines.

[0338] Having received sample data DOUT[9:0] 715.1 from limit conversion module 560.1, microcontroller 500.1 performs the pulse width calculations as described above. As explained in greater detail with respect to DPC 1201, sample scheduler 510.1 schedules the corresponding pulse edges through data words DWI[19:0] 2428.4, their addresses ADW[4.0] 2430.4, and control signal WE 2432.4 that will be written into memory in DPC 1201 through a DPC interface 590.1. DPC 1201 stored data may be read by regulation control module (REG) 1204 for testing or other purposes via DRO[19:0] 2442.4, address ADW[4:0] 2430.4, and control signal RE 2434.4 through DPC interface 590.1 As controlled by mode signal PD[1:0] 712.1 from central processing module (SYS) 1205, regulation control module (REG) 1204 may be configured to implement a low-power mode as well as the normal operation described herein. In this low-power mode, microcontroller 500.1 and edge scheduler 510.1 are powered down by, e.g., gating off the relevant clock signals such that regulation control module (REG) 1204 controls only a subset of the possible switching power converters. Regulation control module (REG) 1204 subsequently passes on the PD signal to DPC 1201 and CLKGEN 1223 as signal PD_OUT[9:0], which may be delayed from the time of receipt of PD[9:0] from central processing module (SYS) 1205 via bus 520.1. A low power engine 585.1 performs the necessary pulse width and sampling calculations. For example, low power engine 585.1 may issue a conversion request to conversion scheduler 540.1 to receive feedback data (voltage and/or current) for a given switching power converter. To calculate the required pulse widths based upon the received feedback information, low power engine 585.1 may perform a limit comparison as discussed with respect to limit comparison module 560.1. If the sample is within a desired operating range, low power engine 585.1 may skip a number of DPC frames, e.g., four frames before again sampling feedback from the particular switching power converter. If the sample is outside the desired operating range, sleep engine will command DPC 1201 to change the SFET 2404.4 and PFET 2402.4 pulse edges accordingly. To save power, the change may be based upon predetermined values stored in registers (not illustrated) associated with sleep engine 540.1 such that the implemented PWM adjustment algorithm is a table look-up function.

[0339] In this low-power mode, CAM function in DPC 1201 is also disabled as described further herein with respect to DPC 1201 operation. Thus, low power engine 585.1 directly causes the desired pulse edge times through SET[28:0] and RESET[28:0] signals 2438.4 and 2440.4. Low power engine 585.1 may be implemented through a configured state machine or other suitable means.

[0340] x.2 LED Controller

[0341] Because switching power supply controller 1200 may be used in LED-containing devices such as PDAS, it may include LED control block, contained in central processing module (SYS) 1205 as shown in FIG. 12. FIG. 52 is a block diagram of LED control block 1214.

[0342] An interface module 30.1 receives LED control commands from central processing module (SYS) 1205 (FIG. 12). In turn, interface module 30.1 controls one or more LEDs using, e.g., first LED driver module 35.1 and a second LED driver module 40.1. Each driver module 35.1 and 40.1 provides a PWM-modulated drive signal to its external LED (not illustrated).

[0343] The PWM modulation in each driver module 35.1 and 40.1 is under the control of values written into registers within interface module 30.1. The greater the pulse width specified in each PWM period, the greater the amount of brightness shown by the corresponding LED. In addition, other registers within interface module 30.1 may control LED blinking, or ramp modes wherein a selected driver module gradually changes its PWM so that its corresponding LED gradually changes from one brightness level to another.

[0344] x.4 internal Power Supply Structure (GM)

[0345] Internal voltage supply (IVS) 1209 (FIG. 12) provides the operating voltages and power for internal operations in switching power supply controller 1200. IVS 1209 receives and provides various interface signals, including a reset (RSTn) signal, a power on reset (POR) signal, a clock output (CLK_OUT) signal, a clock input (CLK_IN) signal, a supply A signal, a supply B signal, a battery 0 (batt0) signal, a battery 1 (batt1) signal, and various supply or reference voltages (i.e., AVD, AVS, VDD, VSS, VDDIO[A,B], and VSSIO[A,B]).

[0346] The reset signal and the power on reset signal are received from reset module 1215 to reinitialize or reset operations of IVS 1209, in accordance with one embodiment, or the power on reset signal may be provided by IVS 1209 to other circuits within switching power supply controller 1200, in accordance with another embodiment. The clock input signal is received from external circuitry and a clock output signal is provided to external circuitry to synchronize and enable various clocking operations.

[0347] The supply signals (supplyA and supplyB) and the battery signals (batt0 and batt1) are various external power supplies that may be received by IVS 1209. These external power supply sources, such as the exemplary ones listed below in Table x.4a, are coupled to switching power supply controller 1200 (and consequently to IVS 1209) and are used to power up and generate internal voltages (e.g., 3.3 V) and are used as power supplies for various circuitry, such as the core logic and to supply or drive external power NFETs (e.g., with up to 15 V).

[0348] IVS 1209 also includes a Kelvin temperature sensor (discussed below in reference to FIG. 54) to monitor the temperature of switching power supply controller 1200 or external ICs. IVS 1209 also provides a voltage reference (VREF) that is used for various circuits, such as analog to digital converter 1206, and may also generate a power on reset signal for distribution within switching power supply controller 1200, as explained in further detail below.

[0349] FIG. 54 is an exemplary functional diagram of IVS 1209 in accordance with one implementation. FIG. 54 shows the four external power supplies 2202.4 through 2208.4 (i.e., BATT0, BATT1, SUPPLYA, and SUPPLYB, respectively) that are received via pads 2210.4 (with diodes 2212.4 serving as protection devices, such as to guard against a reverse polarity condition). The BATT0, BATT1, SUPPLYA, and SUPPLYB labels represent external battery source 0, external battery source 1, external car adapter or wall adapter source A, and external car adapter or wall adapter source B, respectively.

[0350] IVS 1209 determines which of power supplies 2202.4 through 2208.4 to use, if more than one is available, to generate the core voltage and the I/O voltages for switching power supply controller 1200. For example, there may be two core voltages required (e.g., digital 3.3 V and analog 3.3 V).

[0351] Switching power supply controller 1200 in accordance with one implementation has three modes of operation: 1) shut-down mode, 2) low-power mode, and 3) standard mode. In the shut-down mode, nothing on switching power supply controller 1200 is powered on except what monitors the external sources of energy (e.g., power supplies 2202.4 through 2208.4) and no current is flowing except leakage current in switching power supply controller 1200.

[0352] In the low-power mode, internal and I/O voltages are maintained, DPCW 1201 and two external loads (i.e., regulated power supplies) are operating, and switching power supply controller 1200 is performing cycle skipping (discussed further herein). The amount of current required is generally less than in the standard mode. The low-power mode is the default mode of operation once switching power supply controller 1200 is powered-up from any other mode or when neither the clocks nor the registers are running or set. In the standard mode, all of switching power supply controller 1200 is operating and all of the external loads (e.g., seven) are being supplied with regulated power. IVS 1209 receive commands from central processing module (SYS) 1205 which will command IVS 1209 to the appropriate mode.

[0353] As illustrated in FIG. 54, if power is being supplied by power supply 2202.4 or 2204.4, then this external voltage is routed to and supplies power to a crystal oscillator 2216.4, which generates a clock for a voltage multiplier 2214.4 (e.g., either a doubler or a tripler). Crystal oscillator 2216.4 has two pins, for input signals (XTALIN) and output signals (XTALOUT), via pads 2210.4.

[0354] An output of voltage multiplier 2214.4, which may be implemented using well known circuitry, is used as an input voltage for voltage regulators 2226.4, 2228.4, and 2230.4, which supply voltages VDD, AVD, and VREF which can be of conventional circuitry. Additionally, voltage VREFH and VREFL are generated by circuits 2236 and 2238, respectively, and provided to touch screen interface 1211. As will be appreciated from the figures, to simplify the illustration, line have not been included to show each connection. Instead, triangles are utilized within each block indicating the signal and the direction of travel of the signal. The supply voltage VDD provides an output digital core voltage (e.g., 3.3 V) and is treated as global within switching power supply controller 1200. The supply voltage AVD provides an output analog core voltage (e.g., 3.3 V) and is utilized by analog blocks that require a quieter power supply voltage than the supply voltage VDD. The supply voltage VREF shown on IVS 1209 and analog to digital converter 1206 in FIG. 12 also provides an output reference voltage for analog to digital converter 1206. Additionally, the supply voltages VDDIOA and VDDIOB are external I/O power (A and B) used by internal NFET I/O buffers to drive the external power NFET. An external capacitor (labeled generically as EXT CAP) will be generally connected to each of the corresponding bond pads (not shown). The supply voltage VDDIO3 is an external I/O power supply (e.g., of 3.3 V) required for the general purpose I/O digital pads.

[0355] Once the supply voltages VDD and AVD are generated, a phase locked loop (PLL) 2218.4 operates and the supply voltages VDD and AVD are distributed. A DONEMU signal is used to cause voltage multiplier 2214.4 to cease its operations. A MODE[1:0] block 2224.4 informs voltage regulators 2226.4 and 2228.4 of the proper mode of operation and is required for setting the appropriate current.

[0356] The input voltage to voltage regulators 2226.4 and 2228.4 is also provided to power on reset (POR) block 2234.4, for resetting or releasing switching power supply controller 1200 via a RSTN_INT signal, and also to a charge pump block 2220.4 which may be implemented by any well known charge pump circuit. Charge pump block 2220.4 stores the amount of charge (e.g., in external capacitors) required for an instantaneous current needed to drive the external power NFET for setting one or two regulated power supplies. A PUMPCLK signal and a DONEIO signal are control signals that cause charge pump block 2220.4 when to start and when to stop operations, respectively.

[0357] If power is being received from power supply 2206.4 or 2208.4, crystal oscillator 2216.4 and voltage multiplier 2214.4 are bypassed and the supply voltage is routed directly to voltage regulators 2226.4 through 2230.4.

[0358] A band gap reference (BGR) block 2222.4 provides reference signals to voltage regulators 2226.4 through 2230.4 and to a Kelvin temperature sensor 2232.4. As noted above, voltage regulator 2230.4 generates the supply voltage VREF. Kelvin temperature sensor 2232.4 generates a VOUT signal.

[0359] FIG. 15 is a block diagram showing the interface signals of kelvin temperature sensor (KTS) 1500, which is an exemplary implementation of Kelvin temperature sensor 2232.4. Kelvin temperature sensor 1500 is an absolute temperature sensor circuit that produces an output voltage (VOUT) linearly related to the circuit's absolute temperature. As shown in FIG. 15, Kelvin temperature sensor 1500 receives analog power and ground reference voltages at terminals 1501 and 1502 and asynchronous power-down control signal (PDN) at terminal 1503, and provides output voltage VOUT at terminal 1504, which is linearly related to the temperature of the circuit between 0.0V and 3.0V.

[0360] FIG. 15A is an exemplary circuit for KTS 1500 in accordance with one implementation and highlights the basic equations that illustrate how the output voltage VOUT corresponds to temperature. For example, all of the components in FIG. 15A can be integrated on the same chip and, thus, the matching of the components can be better than 0.1%. Without calibration, approximately ±5% accuracy may be obtained over the temperature range 0° C. to 125° C. With calibration, by measuring the output voltage VOUT at a known temperature (e.g., 25° C.), greater than ±1% accuracy may be obtained.

[0361] FIG. 54A is an exemplary interface block diagram illustrating interface signals for IVS 1209 in accordance with another implementation and FIG. 54B is a corresponding functional block diagram. As shown in FIG. 54A and x.4c, the interface signals include a battery (BATT) signal 3400 .4, a switch (SWT) signal 3402.4, power supplies A and B (SUPPLYA and SUPPLYB, respectively) 3404.4 and 3406.4, respectively, an XIN signal 3408.4, an XOUT signal 3410.4, a VM1 signal 3412.4, a VM2 signal 3414.4, a VM3 signal 3416.4, an IVS_CLK signal 3418.4, a DONEPUMP signal 3420.4, a DONEBOOT signal 3422.4, a VOUT signal 3424.4, a RESETN signal 3426.4, a VSSIOA signal 3428.4, a VSSIOB signal 3430.4, a VDDIOA signal 3432.4, a VDDIOB signal 3434.4, a VREF_HALF signal 3436.4, a COLDBOOT signal, a SWT_ADAPT a FREF signal 3438.4, a VREF signal 3440.4, an AVS signal 3442.4, a VSS signal 3444.4, an AVD signal 3446.4, and a VDD signal 3448.4. Some of the signals employ pads 3550.4, as shown in FIG. 54A.

[0362] Battery (BATT) signal 3400.4 is the signal provided if an external battery is available. Switch (SWT) signal 3402.4 is used to cause switching power supply controller 1200 to go from the shutdown mode into the low power mode, or the standard mode. Power supply A 3404.4 and power supply B 3406.4 are pads connected to the external power source (A or B, respectively). XIN signal 3408.4 is an input signal for a crystal oscillator 3500.4, while XOUT signal 3410.4 is an output signal from crystal oscillator 3500.4, both for communication with an external crystal oscillator (e.g., of 32.768 kHz).

[0363] VM1 signal 3412.4, VM2 signal 3414.4, and VM3 signal 3416.4 are signals provided to and from external capacitors (labeled EXT CAP in FIG. 54B) coupled to a voltage multiplier 3504.4. IVS_CLK signal 3418.4 is a clock signal from CLKGEN 1223 that is used by a charge pump 3518.4, while DONEPUMP signal 3420.4 is a signal from central processing module (SYS) 1205 to cause charge pump 3518.4 to stop. DONEBOOT signal 3422.4 is a signal from central processing module (SYS) 1205 to cause a power detection circuit 3502.4 to stop voltage multipler 3504.4 and voltage regulators 3510.4 and 3514.4.

[0364] VOUT signal 3424.4 is an output signal from a Kelvin temperature sensor 3516.4, which is provided to SHM 1207. RESETN signal 3426.4 is a reset signal from a power on reset (POR) circuit 3512.4 and is provided to reset module 1215. VSSIOA signal 3428.4 and VSSIOB signal 3430.4 are two ground signals, while VDDIOA signal 3432.4 and VDDIOB signal 3434.4 are two power supply signals generated in charge pump IO 3518.4, all provided to various blocks in switching power supply controller 1200, including to NFET driver module 1202.

[0365] VREF signal 3440.4 is a reference voltage signal (e.g., 3.0 V) provided to analog to digital converter 1206, while VREF_HALF signal 3436.4 is one-half the voltage level of VREF signal 3440.4, which is provided to SHM 1207. FREF signal 3438.4 is a reference frequency provided by crystal oscillator 3500.4. AVS signal 3442.4 is an analog ground signal, VSS signal 3444.4 is a digital ground signal, AVD signal 3446.4 is an analog voltage signal (e.g., 3.3 V), and VDD signal 3448.4 is a digital voltage signal (e.g., 3.3 V).

[0366] As a functional example of operation (referring to FIG. 54B), if an external battery is supplying the power, battery signal 3400.4 will provide a voltage (e.g., at least 1.8 V) to run power detection circuit 3502.4 (which detects the voltage) and crystal Oscillator (XTAL OSC1) 3500.4 to generate a clock for voltage multiplier 3504.4. Power detection circuit 3502.4 provides a voltage (e.g., 1.8 V) to crystal oscillator 3500.4 and detects when to exit the shutdown mode. The output of voltage multiplier 3504.4 (e.g., twice the input voltage) is used as an input voltage for voltage regulators (VRAVD) 3514.4 and (VRVDD) 3510.4, which generate a VRAVD voltage and a VRVDD voltage, respectively. A separate internal voltage doubler 3508.4 provides a voltage (e.g., 6.6 V or twice VDD signal 3448.4) to a VREF block 3506.4, which provides a stable reference voltage (i.e., VREF signal 3440.4) by employing, for example, band gap reference circuits.

[0367] Once core logic VDD signal 3448.4 and AVD signal 3446.4 are generated, a phase-locked loop (PLL) circuit (not shown) along with other circuitry shown in FIG. 54B can begin operating using the voltage (e.g., 3.3 V) from VDD signal 3448.4 and/or AVD signal 3446.4. When the VRVDD voltage reaches a minimal level, a POR circuit 3512.4 exits a reset state (during,reset, POR circuit 3512.4 functions to asynchronously set or reset registers used in switching power supply controller 1200). The 8051 contained within central processing module (SYS) 1205 will then bring up the rest of the system, which enables regulation control module (REG) 1204 to regulate an external supply (e.g., 3.3. V).

[0368] After regulation control module (REG) 1204 is regulating the external voltage supply (e.g., 3.3V), central processing module (SYS) 1205 will assert DONEBOOT signal 3422.4. Once DONEBOOT signal 3422.4 is asserted (e.g., logical high level), IVS 1209 will turn off voltage multiplier 3504.4 and internal voltage regulators 3510.4 and 3514.4. The voltage from voltage regulator 3510.4 should also go to POR block 3512.4 so that the asynchronous registers (not shown) can exit their reset condition.

[0369] Additionally, charge pump 3518.4 will receive the output of voltage multiplier 3504.4 and store in an external capacitor (EXT CAP) the charge needed in NFET driver module 1202 during the power-up sequence (e.g., 3 V above the power supply to drive a gate of the external NFET). Charge pump 3518.4 will start once IVS_CLK signal 3418.4 is generated and continue pumping until DONEPUMP signal 3420.4 from central processing module (SYS) 1205.

[0370] If no battery is available and an external power source is provided by power supply A 3404.4 or power supply b 3406.4 (e.g., either supply providing between 4.5 V and 14.4 V), this voltage will be detected by and run power detection circuit 3502.4 and also crystal oscillator 3500.4. VREF block 3506.4 and voltage regulators 3510.4 and 3514.4 will receive as their input voltage, either power supply A 3404.4 or power supply B 3406.4 to generate the analog and digital voltages (i.e., AVD signal 3446.4 and VDD signal 3448.4, respectively). Once AVD signal 3446.4 and VDD signal 3448.4 are generated, the same procedure as described above for a battery supply will take place to provide the external 3.3V connected back into the chip through AVD signal 3446.4 and VDD signal 3448.4.

[0371] If the chip has entered shutdown mode , and it still has power from either battery 3400.4, SUPPLYA 3404.4 or SUPPLYB 3406.4, it will remain in that state with just the Xtal Osc 3500.4 and Power Detection Circuit 3502.4 running. It will remain in this state until one of two conditions occur: Pad SWT is pulled low or a supply is provided. Upon either or these conditions will initiate the power up sequences described above and provide signal COLDBOOT and SWT_ADAPT to central processing module (SYS) 1205.

[0372] FIG. 54C is an exemplary flowchart for a power-up sequence for IVS 1209 in accordance with another implementation. Step 3600.4 begins the power-up sequence when an external voltage is applied. If the external voltage is greater than a required threshold (e.g., 1.8 V) at step 3602.4, then the shutdown mode is held to allow circuits to power up (step 3604.4). If the external voltage is greater than expected battery voltages, then the external voltage is routed to VREF block 3506.4 and voltage regulators (LDOs) 3510.4 and 3514.4 (as discussed in reference to FIG. 54B).

[0373] If the external voltage is around the expected battery voltages, step 3608.4 determines if a switch (SWT 3402.4) is pressed, if not then the shutdown mode (step 3604.4) is entered. If the power switch is pressed, step 3612.4 starts voltage multiplier 3504.4, VREF block 3506.4, and voltage regulators 3510.4 and 3514.4. RESETN signal 3426.4 is asserted (step 3614.4) and charge pump 3518.4 operation begins.

[0374] Step 3618.4 determines if a low battery condition exists if so IVS returns to step 3604.4. IVS remains in state 3618.4 until central processing module (SYS) 1205 (referred to as 8051 in flowchart) has completed its coldboot operations. Once central processing module (SYS) 1205 is done with these operations step 3620.4 switches off all redundant systems and the external voltage (i.e., VDD signal 3448.4) is fed back into switching power supply controller 1200. Step 3622.4 begins operation of voltage doubler 3508.4 and, when DONEBOOT signal 3422.4 is asserted, the standard mode or the low power mode (step 3626.4) is initiated. When the shutdown mode command is received, step 3624.4 switches off VREF block 3506.4 and voltage doubler 3508.4 and step 3606.4 is repeated.

[0375] Section x.5 Converter Structure (ADC)

[0376] Referring to FIG. 12, analog to digital converter 1206 may be constructed as a successive approximation converter (SAR) or in other suitable architectures such a flash analog-to-digital converter. Due to the use of sample and holds in combination with capacitor ratio based voltage division and multiplication; several unusual simplifications may be made to the input of the analog-to-digital converter. A standard implementation of a SAR converter requires an input buffer amplifier to condition and scale the input voltage and a sample and hold circuit to prevent the input voltage from changing at the input to the SAR comparator as successive SAR DAC values are compared to the input voltage. In a SAR analog-to-digital converter, the conversion may be corrupted if the input voltage is allowed to change during the conversion process. The additional input stages normally required in a SAR analog-to-digital converter require that voltages to be measured be made available and settled a significant time before the conversion starts. This “set up time” is a particular issue in a multiplexed system such as the present invention since it reduces the rate at which new inputs can be presented or demands much higher speed from the analog-to-digital converter. Since the present invention utilizes sample and holds at its inputs and capacitor ratio based scaling, both the input amplifier and sample and hold sections may be eliminated from the SAR analog-to-digital converter implemented in an embodiment thus eliminating much of the set up time and several sources of error while reducing the speed requirements and power consumption of the SAR analog-to-digital converter. The required processing speed of analog to digital converter 1206 is driven by the DPC frame rate and the number of switching power supplies under control by switching power supply controller 1200 and the desired A/D resolution. For example, if switching power supply controller 1200 uses a cycle rate of 524 KHz and controls seven switching power supplies, analog to digital converter 1206 must convert 14 feedback signals plus two input signals in a DPC frame period of approximately 2 micro-seconds. If 10 bits of resolution are desired, the resulting A/D logic clock frequency is approximately 110 MHz.

[0377] x.7 Output Structure NFET (GM)

[0378] FIG. 55 is an exemplary functional diagram of NFET driver module 1202 in accordance with one implementation. FIG. 55 includes input/output (I/O) buffers 2102.4 and 2104.4, which drive corresponding external power MOSFETs 2112.4 and 2114.4 via pads 2106.4 and 2110.4 (corresponding to UPPER_FET and LOWER_FET terminals, respectively, on NFET driver module 1202 of FIG. 12).

[0379] As shown in FIG. 55, power MOSFET 2112.4 is referred to as an “UPPER FET” and power MOSFET 2114.4 is referred to as a “LOWER FET,” with both employed to provide a regulated DC supply to a load. NFET driver-module 1202 receives via switch control bus 1303a(i.e., HIGHFET) and switch control bus 1303b(i.e., LOWFET) signals shown adjacent to the bus, which contain information utilized by NFET driver module 1202 to control I/O buffers 2102.4 and 2104.4. A pad 2108.4 is coupled to power MOSFETs 2112.4 and 2114.4 to provide feedback (fb) to NFET driver module 1202 regarding external load parameters (e.g., voltage).

[0380] NFET driver module 1202 (FIG. 12) further includes interface signals VDDIO[A,B], VSSIO[A,B], UPFET_Source, LOWFET_Source, and IDDQ. The VDDIO[A,B] signals are supply voltages A and B, while the VSSIO[A,B] signals are corresponding A and B ground references. The UPFET_Source and LOWFET_Source signals monitor and provide feedback regarding power MOSFETs 2112.4 and 2114.4, respectively, and correspond symbolically to the feedback (fb) illustrated in FIG. 55. The IDDQ signal is provided for test purposes.

[0381] FIG. 55A illustrates exemplary interface signals of NFET driver module 1202 in accordance with another implementation. The interface signals include a PFET[6:0] signal 3200.4, an SFET[6:0] signal 3202.4, an IDDQ signal 3204.4, a SELMODE signal 3206.4, a CNTL[1:0] signal 3208.4, a VSSIOA signal 3210.4, a VSSIOB signal 3212.4, a SUPPLYB signal 3214.4, a SUPPLYA signal 3216.4, an UPSENSE[6:0] signal 3218.4, a LOWFET[6:0] signal 3220.4, an UPFET[6:0] signal 3222.4, a VDDIOB signal 3224.4, a VDDIOA signal 3226.4, a VSS signal 3228.4, and a VDD signal 3230.4.

[0382] PFET[6.0] signal 3200.4 and SFET[6:0] signal 3202.4 are the pulses received from DPC 1201 to drive the primary and secondary external NFETS, respectively. IDDQ signal 3204.4 is a test signal, while SELMODE signal 3206.4 selects a mode of operation and CNTL[1:0] signal 3208.4 provides control information.

[0383] VSSIOA signal 3210.4 and VSSIOB signal 3212.4 are return ground paths for the external power supplies (i.e., SUPPLYA signal 3216.4 and SUPPLYB signal 3214.4, respectively). VDDIOA signal 3226.4 and VDDIOB signal 3224.4 are high voltage sources derived from supply A 3216.4 or supply B 3214.4, which may be controlled by DPC 1201 to regulate the load voltage as needed. VSS signal 3228.4 and VDD signal 3230.4 are digital ground and digital supply voltage (e.g., 3.3 V), respectively.

[0384] UPFET[6:0] signal 3222.4 and LOWFET[6:0] signal 3220.4 are signals that drive the primary and secondary external NFETs, while UPSENSE[6:0] signal 3218.4 is a reference source voltage for the primary external NFETs of switching power converters being controlled by switching power supply controller 1200.

[0385] FIG. 55B illustrates exemplary interface signals of switch driver module also referred to as NFET driver module 1202 in accordance with another implementation. NFET driver module 1202 contains I/O drivers, as explained below, that can be used to drive external power FETs as well as an external coil (e.g., for digital camera applications). The interface signals include PFET[6:0] signal 3200.4, SFET[6:0] signal 3202.4, a PFET_SEL[6:0] signal 4402.4, a FET_SWAP[6:0] signal 4404.4, an EN_EXT33 signal 4406.4, IDDQ signal 3204.4, a PFETSENSE[6:0] signal 4408.4, a SUPPLY_SEL[6:0] signal 4410.4, VDDIOA signal 3226.4, VSSIOA signal 3210.4, VDDIOB signal 3224.4, VSSIOB signal 3212.4, a PADIO[6:0] signal 4418.4, a PFETDRIVE[6:0] signal 4416.4, an SFETDRIVE[6:0] signal 4414.4, and an EXTDRIVE signal 4412.4.

[0386] PFET[6:0] signal 3200.4 and SFET[6:0] signal 3202.4 are the pulses received from DPC 1201 used to drive the external primary NFETs and external secondary NFETs, respectively. PFET_SEL[6:0] signal 4402.4, received from regulation control module (REG) 1204, commands whether to drive external FETs or external coils. If driving external coils, VDDIOA signal 3226.4 or VDDIOB signal 3224.4 will be connected to the Supply A or the Supply B. If driving external FETs, VDDIOA signal 3226.4 or VDDIOB signal 3224.4 will be boosted to voltage levels equivalent to 3 V above the voltage level of the Supply A or the Supply B.

[0387] FET_SWAP[6:0] signal 4404.4, received from regulation control module (REG) 1204, signals NFET driver module 1202 to swap the pulses from PFET[6:0] signal 3200.4 and SFET[6:0] signal 3202.4, depending upon whether a boost or a buck is the external power topology. EN_EXT33 signal 4406.4 drives EXTDRIVE signal 4412.4, which drives the external switch to isolate the external voltage supply (e.g., 3.3 V) from the rest of the system IDDQ signal 3204.4 is a test signal.

[0388] PFETSENSE[6:0] signal 4408.4 is the source of the primary external NFET and is connected back into switching power supply controller 1200 to monitor the source voltage of PFETDRIVE[6:0] signal 4416.4 SUPPLY_SEL[6:0] signal 4410.4 selects between the Supply A and the Supply B for generation of VDDIOA signal 3226.4 or VDDIOB signal 3224.4. VDDIOA signal 3226.4 is connected externally to PADIO[6:0] signal 4418.4 and provides a voltage level above the voltage of the Supply A (e.g., 3.0 V above) as a main power supply for PFETDRIVE[6:0] signal 4416.4 or SFETDRIVE[6:0] signal 4414.4 (if driving an external NFET) or as a pre-driver voltage (if driving an external coil). VSSIOA signal 3210.4 is a ground signal for VDDIOA signal 3226.4 or PADIO[6:0] signal 4418.4. Similarly, VDDIOB signal 3224.4 is connected externally to PADIO[6:0] signal 4418.4 and provides a voltage level above the voltage of the Supply B (e.g., 3.0 V above) as a main power supply for PFETDRIVE[6:0] signal 4416.4 or SFETDRIVE[6:0] signal 4414.4 (if driving an external NFET) or as a pre-driver voltage (if driving an external coil).

[0389] VSSIOB signal 3212.4 is a ground signal for VDDIOB signal 3224.4 or PADIO[6:0] signal 4418.4. PADIO[6:0] signal 4418.4 is a main source of input/output power for the final stage in PFETDRIVE[6:0] signal 4416.4 or SFETDRIVE[6:0] signal 4414.4 and may utilize VDDIOA signal 3226.4 or VDDIOB signal 3224.4 as well as the Supply A or the Supply B, depending upon the configuration (discussed further below). PFETDRIVE[6:0] signal 4416.4 drives the external primary FET. SFETDRIVE[6:0] signal 4414.4 drives the external secondary FET. EXTDRIVE signal 4412.4 switches on or off the external FET switch used for isolating the external power supply (e.g., 3.3 V) that will be connected back to switching power supply controller 1200.

[0390] FIG. 55C shows an exemplary functional diagram for the implementation of FIG. 55B. In terms of general operation, two pulses, PFET signal 3200.4 and SFET signal 3202.4 are received from DPC 1201. If these pulses overlap, a fail safe mode logic 4430.4 (FIG. 55D) sets the output signal to LOW to PFETDRIVE signal 4416.4 and SFETDRIVE signal 4414.4 until the next frame. Pre-driver logic 4432.4 and 4434.4 (FIG. 55D) checks for swapping between external primary and secondary output terminals. PFET_SEL signal 4402.4 will also configure the driver either as driving external FETs or driving directly the external coil PFETDRIVE signal 4416.4 needs to be, for example, 3 V higher than PFETSENSE signal 4408.4 when driving external FETs. Hence, PFETSENSE signal 4408.4 is connected back into the pre-driver logic to monitor the source voltage for the external FET.

[0391] VDDIOA signal 3226.4 and VDDIOB signal 3224.4 (FIG X.7d) are connected external to NFET driver module 1202 and each of the channels (e.g., seven) of NFET driver module 1202 will be connected to either VDDIOA signal 3226.4 or VDDIOB signal 3224.4, depending on the value of SUPPLY_SEL signal 3202.4. Each of the seven channels utilize PADIO signal 4418.4, PFETDRIVE signal 4416.4, PFETSENSE signal 4408.4, SFETDRIVE signal 4414.4, and its corresponding VSSIOA signal 3210.4 or VSSIOB signal 3212.4. During the power-up sequence an external NFET will be driven by EXTDRIVE signal 4412.4, which is an I/O buffer similar to the buffers used for PFETDRIVE signal 4416.4. EN_EXT33 signal 4406.4, received from central processing module (SYS) 1205, controls EXTDRIVE signal 4412.4.

[0392] FIG. 55D illustrates an application employing internal buffers, represented by transistors 4440.4 and 4442.4, to directly drive an external coil 4444.4 for the implementation of FIG. 55B. As discussed above for this configuration, PADIO signal 4418.4 is connected externally (i.e., at the board level) to Supply A or the Supply B. As shown, PFETDRIVE signal 4416.4 and SFETDRIVE signal 4414.4 may be arranged to drive in parallel external coil 4444.4 and a capacitive load 4446.4, which may result in lower source impedance.

[0393] Fail safe mode logic 4430.4 verifies that PFET signal 3200.4 and SFET signal 3202.4 do not overlap. Supply_SEL 4410.4 selects VDDIOA signal 3226.4 or VDDIOB signal 3224.4 via a multiplexer 4448.4 to route to control logic 4432.4 and 4434.4, which control transistor pairs 4440.4 and 4442.4.

[0394] FIG. 55E illustrates an application employing internal buffers, represented by transistor pairs 4440.4 and 4442.4, to drive external FETs 4450.4 and 4452.4 for the implementation of FIG. 55B. As discussed above for this configuration, PADIO signal 4418.4 is connected externally (i.e., at the board level) with VDDIOA signal 3226.4 or VDDIOB signal 3224.4. The application shown in FIG. 55E is similar to FIG. 55D and therefore will not be repeated. However, as shown in FIG. 55E, external FETs 4450.4 and 4452.4 are driven by PFETDRIVE signal 4416.4 and SFETDRIVE signal 4414.4, respectively, to drive external coil 4444.4 and capacitive load 4446.4. When PFET 3200.4 is high, its control logic 4432.4 maintains PFETDRIVE at a constant 3V above PFETSENSE 4408.4

[0395] Table x.7a summarizes in a truth table format the state of various signals for the exemplary configurations. For PFET_SEL signal 4402.4, a zero and a one indicate internal and external, respectively. For FET_SWAP signal 4404.4, a zero and a one indicate no swap and swap, respectively.

[0396] FIG. 55F shows an exemplary on-chip configuration block diagram for the implementation of FIG. 55B. As shown, switching power supply controller 1200 receives the Supply A or the Supply B signal via pads 4462.4 or through PADIO signal 4418.4, and generates VDDIOA signal 3226.4 and VDDIOB signal 3224.4.

[0397] Switching power supply controller 1200, through NFET driver module 1202, generates PFETDRIVE signal 4416.4 and SFETDRIVE signal 4414.4 and receives PFETSENSE 4408.4 and optionally SFETSENSE 4460.4.

[0398] x.8 Microcontroller Structure

[0399] Referring to FIG. 56, an exemplary embodiment for central processing module (SYS) 1205 comprises a microprocessor core 400.1 such as an 8051 which interfaces with external hosts through an Advanced General Purpose I/O (AGPIO) module 410.1. ADGPIO module 410.1 provides 31 GPIO ports that may be individually configured to suit a host application's needs, such as the ability to determine power supply status, an 8×8 keyboard interface, and a serial communication bus for communication with a host device.

[0400] Such serial communication with a host device may occur using a number of signaling protocols as selected by a serial multiplexer 420.1. For example, serial data may be received from a universal asynchronous receiver/transmitter (UART) 425.1, an SPI receiver/transmitter 435.1, or a JTAG receiver/transmitter 440.1. Additional serial devices could also be used such as Microwire, I2C, or SSI2 devices.

[0401] Microprocessor core 400.1 communicates with the serial device selected by serial multiplexer 420.1 on an internal bus 450.1.

[0402] A data-path multiplexer 470.1 multiplexes the data on a read data path in internal bus 450.1 to select data from different sources such as LED controller 1214 and watchdog controller 1213. In addition, microprocessor core 400.1 may receive data from and store data to the non-volatile memory module 1216 (FIG. 12) through an external interface 455.1 coupled to internal bus 450.1. As described further herein with respect to watchdog controller 1213 and LED controller 1214, microcontroller 400.1 also interfaces with these modules through internal bus 450.1.

[0403] Data necessary for program execution on microprocessor core 400.1 may be stored in a program memory device 460.1. Program memory device 460.1 may be any technology suitable for program storage and execution, such as masked ROM, Flash memory, EEPROM, or other suitable media. Microprocessor core 400.1 may also store data in a RAM 465.1 or in a non-volatile memory module 1216 (FIG. 12). Microprocessor core 400.1 communicates with other modules such as regulation control module (REG) 1204 in switching power supply controller 1200 through internal bus 520.1, which is also illustrated and discussed with respect to regulation control module (REG) 1204 in FIG. 12. A handshaking protocol or glue logic may be used to coordinate this communication. The outgoing data is addressed to a particular module in a memory-mapped fashion or by SFR-mapped addresses.

[0404] Microprocessor core 400.1 is clocked by clock signal 714.1 received from clock generation module 1223. However, because the regulation from DPC frame to DPC frame during normal operation is under the control of regulation control module (REG) 1204, it would be a waste of power to have microprocessor 400.1 clocked continuously by clock 714.1 during normal operation. Thus, clock 714 is gated off during normal operation by the microprocessor when the microprocessor has completed any processing that is needed. In response to interrupts from other modules such as watchdog controller 1213 or LED controller 1214, the power management module 480.1 allows microprocessor core 400.1 to receive clock 714.1. Once the interrupt has been serviced, clock 714.1 is once again gated off by the microprocessor core 400.1.

[0405] Section 1.2.2 Control Loops/algorithms

[0406] FIG. 25 is a diagram of switching power supply controller 1200 being used in a battery and power supply management application in, for example, a personal digital assistant (PDA). As shown in FIG. 25, switching power supply controller 1200 (a) regulates buck converter 2570 to provide a regulated DC power supply at terminal 2540, (b) regulates DC/AC converter 2571 to provide an AC power supply between terminals 2542 and 2543, (c) to charge battery 2517 through converter 2572, operating either in buck or boost mode, when an external DC supply voltage (e.g., 12-15 volts) is available at terminal 2544, and (d) to draw power from battery 2517, operating in boost mode, when the external DC supply voltage at terminal 2544 is not available. In a PDA application, for example, switching power supply controller 1200 may communicate with a host processor and peripheral devices over data interface 2573. Conventional reference oscillator circuit 2574 provides a 32.768 KHz reference clock signal for switching power supply controller 1200.

[0407] Even though specific converter configurations are shown in FIG. 25 to illustrate the exemplary embodiments described herein, one skilled in the art would appreciate that the present invention is not so limited. Other converter configurations can be implemented within the scope of the present invention based upon this detailed description. In FIG. 25, buck converter 2570 includes inductor 2503, current-sense resistor 2504, output capacitor 2501, and MOS switches 2505 and 2506 (which includes intrinsic diode 2502) receiving at their respective gate terminals the pulse-width modulated drive signals (“upper_FET_gate” and “lower_FET gate”) from switching power supply controller 1200.

[0408] Inductor 2503, current-sense resistor 2504 and output capacitor 2501 are connected in series between sense input terminal 2518 of switching power supply controller 1200 (one of the “upper_FET_source_sense” terminals), which is connected to the source terminal of MOS switch 2505, and a ground reference. Diode 2502 prevents the voltage at sense input terminal 2518 from dropping below a predetermined voltage (e.g., approximately 1 volt) less than the ground reference. The drain terminal of MOS switch 2505 is connected to one of two supply terminals (“Supply A” or “Supply B”) of switching power supply controller 1200. The drain and source terminals of MOS switch 2506 are connected respectively to the sense input terminal 2518 and the ground reference. The regulated output voltage is taken from the ungrounded terminal 2540 of output capacitor 2501. This regulated output voltage is determined by the duty cycle of the pulse-width modulated signals received at the gate terminals of MOS switches 2505 and 2506. In one implementation, the period of the pulse-modulated signals (also referred to as a “cycle”) is two microseconds, as shown in FIG. 22.

[0409] The terminals of current-sense resistor 2504 are connected to sense input terminals 2530 and 2531 (one terminal from each of the “sense_I” and “sense_VI” buses) of switching power supply controller 1200. The voltage (V_out−V_IL) across these sense input terminals is proportional to the current in inductor 2503.

[0410] External DC power can be provided to supply terminal 2508 of the system from terminal 2544. In converter 2572, diodes 2511, 2512 and 2513 are configured to ensure that power flows only from the external power source into the system, and to prevent the voltage at supply terminal 2508 from going below a predetermined voltage (i.e., the forward bias voltage of the diode) less than the ground reference. In converter 2572, inductor 2514, sense-resistor 2515 and capacitor 2516 are connected in series between sense terminal 2519 of switching power supply controller 1200 (one of the “upper FET_source_sense” terminals) and a ground reference. The ungrounded terminal of capacitor 2516 is connected to the positive terminal of battery 2517. MOS switches 2509 and 2510 receive pulse-width modulated drive signals at their gate terminals. The drain and source terminals of MOS switch 2509 are connected respectively to power supply terminal 2508 and sense terminal 2519. The drain and source terminals of MOS switch 2510 are connected respectively to sense terminal 2519 and the ground reference. When an external power source is connected at terminal 2544, the pulse-width modulated drive signals at the gate terminals of MOS switches 2509 and 2510 regulate the voltage and current for charging battery 2517. Alternatively, i.e., when an external power source is not connected at terminal 2544 and the system runs from power supplied by battery 2517, the pulse-width modulated signals at the gate terminals of MOS switches 2509 and 2510 regulate the voltage at power supply terminal 2508. Depending on whether the voltage supplied by battery 2517 is higher than the desired voltage at terminal 2508, converter 2572 is operated as a buck or boost converter.

[0411] The terminals of current-sense resistor 2515 are connected to sense input terminals 2535 and 2536 (one terminal from each of the “sense_I” and “sense_VI” buses) of switching power supply controller 1200. The voltage (V_out−V_IL) across these sense input terminals is proportional to the current in inductor 2514.

[0412] DC/AC converter 2571 provides a high voltage AC power supply (e.g., 700 volts) for cold-cathode fluorescent lighting (CCFL) used as back-lighting in a PDA. In converter 2571, MOS switches 2521 and 2522 alternatively connect inductors 2520 and 2523 to the ground reference. Inductors 2520 and 2523 are each connected between power supply terminal 2508 and the drain terminal of one of MOS switches 2521 and 2522 respectively. The voltages at these drain terminals control piezoelectric transformer 2524 to provide the requisite AC signal across terminals 2542 and 2543 of CCFL 2525. Terminal 2543 is connected to the ground reference through sense-resistor 2526.

[0413] Section 1.2.2.1 Input Voltage/output Current Predictive Control Loop

[0414] The terminals of current-sense resistor 2526 are connected to sense input terminals 2532 and 2533 (one terminal from each of the “sense_I” and “sense_VI” buses) terminals of switching power supply controller 1200. The voltage across these sense input terminals is proportional to the current in CCFL 2525. The pulse-width modulated signals at the gate terminals of MOS switches 2521 and 2522 regulate the power supplied to CCFL 2525.

[0415] As can be seen from the above description, each of converters 2570, 2571 and 2572 is regulated by a pair of pulse-width modulated drive signals (one from each of “upper_FET_gate” and “lower FET gate” groups of signals). These signals are preferably non-overlapping (i.e., these signals are not both at a high voltage at the same time). For each converter, regulation is based on a control loop receiving input signals representing the values of the controlled variables. FIG. 19 is a block diagram summarizing the modules in switching power supply controller 1200 providing a control loop for a battery or power supply management application. As shown in FIG. 19, digital to pulse converter module 1201 receives from regulation control module (REG) 1204 a 10-bit value, representing the duty cycle of a pulse-width modulated drive signal and accordingly provides one of seven pairs of pulse-width modulated drive signals 1901aand 1901b. Pulse-width modulated drive signals 1901aand 1901bare driven by NFET driver module 1202 (not shown in FIG. 19) as the upper_FET_gate and lower_FET_gate signals from switching power supply controller 1200. At the same time, seven pair of voltage signals 1902aand 1902b(i.e., I[0:6], VI[0:6]), each pair representing the voltages across the terminals of a sense-resistor, are received into sample and hold module 1207. In addition, the voltages at the two external power supply terminals 1903 and 1904 (i.e., Supply A and Supply B) are also received into sample and hold module 1207. In turn, each of these analog voltage signals is sampled and held for conversion by analog to digital converter 1206, which provides regulation control module (REG) 1204 a 10-bit digital value for each voltage converted. Regulation control module (REG) 1204, which implements a number of methods applicable to the control loop, provides digital to pulse conversion module 1201 the appropriate 10-bit value on bus 1907. Of course, the number of bits to be used for each voltage converted value is a matter of design choice depending upon, for example, the resolution required in the control loop. In fact, within regulation control module (REG) 1204, computation may be carried out at a higher resolution than 10-bits and residual values less than the 10-bit resolution may be kept for multiple cycles to implement specific, higher accuracy control methods.

[0416] Section 1.2.2.2 stored external component parameters.

[0417] For each battery or power supply management application, regulation control module (REG) 1204 receives the power supply voltage V_A(e.g., voltage at terminal 2508), the regulated output voltage V_outat one terminal of the current-sense resistor (e.g., voltage at terminal 2531), and the voltage V_ILat the other terminal of the current-sense resistor (e.g., terminal 2530). A circuit model of converter 2570 is provided in FIG. 57.

[0418] As shown in FIG. 57, the current I_Lin the inductor of a buck or boost converter can be determined by the voltage drop across the current-sense resistor 2504 (i.e., V_out−V_IL) divided by its resistance R_sense. Regulation is achieved based upon the measured voltage values received and quantities derivable from these received values. For example, the present invention allows regulation using an input voltage at terminal 2508 (e.g., the power supply voltage V_A) and an output current (e.g., current I_Lin resistor 2504) as control parameters.

[0419] FIG. 26 illustrates the operation of a control loop in accordance with the present invention. As shown in FIG. 26, such a control loop includes three phases. At the beginning of a control cycle or cycle, which is a 2 microsecond time period in one implementation, the values of controlled variables (e.g., output voltages) are sampled and digitized in phase 2601. Based on these input values, parametric values and an appropriate response (e.g., an increase or a decrease in the value of a controlled variable) are computed at phase 2602. The response (e.g., an increase or a decrease in the duty cycle of the drive signals to the MOS switches) is then applied to effectuate the changes in the controlled variables.

[0420] Referring back to FIG. 57, if one takes the parasitic resistances or impedances of the converter into account, a voltage drop V_pcan be attributed, for example, to the parasitic resistances R_onand R_L, where R_onis the “on” resistance of one of the MOS switches (e.g., MOS switch 2505 or 2506) and R_Lis the parasitic series resistance in the inductor (e.g., inductor 2503). The parasitic resistor R_onis not shown in FIG. 57, and the parasitic resistor R_Lis shown as resistor 5701 in FIG. 57. As discussed above, the current I_Lin the inductor can be obtained by (V_out−V_IN) divided by R_ON+R_L.

[0421] Voltage V_pcan be approximated using a method discussed below. In addition, a parasitic resistance R_c(represented by resistor 5702 in FIG. 57) can be attributed to the parasitic series resistance in the output capacitor (e.g., output capacitor 2501). Since the actual inductance L of a commercially available coil may be more than 10% different from its nominal inductance value, and may vary significantly over the life of the inductor, a method according to the present invention allows an accurate inductance value of the inductor to be calculated periodically or on power-up. The present invention also provide's a method, described below, for calculating the output capacitance C of capacitor 2501.

[0422] According to one embodiment of the present invention, regulation of the output voltage V_outmay be carried out in the manner illustrated in FIG. 20. The regulation method illustrated in FIG. 20 recognizes that an inductor has a saturation current I_LSAT, beyond which the inductor becomes resistive (i.e., the additional current results in energy dissipated as heat and not additional energy being stored in the inductor). Initially, both output voltage V_outand inductor current I_Lare zero. As shown in FIG. 20, the control method of the present invention initially provides a duty cycle in the pulse-width modulated drive signals to the MOS switches (e.g., close to 100%) that increases the current in the inductor at the highest rate until the inductor current reaches a predetermined value of the saturation current I_LSAT(e.g., 95% of I_LSAT). During this time, the inductor current charges both the magnetic field in the inductor and the electric field of the output capacitor (e.g., capacitor 2501), so that the inductor current and output voltage increase along the current/voltage segment 2001. When the inductor current reaches the predetermined current value, as indicated by point 2003, the method of the present invention reduces the duty cycle of the pulse-width modulated drive signals to the MOS switches sufficiently to maintain the inductor current at that level, so that substantially all of the energy transferred by the inductor current is provided to charge the output capacitor. In this portion of the control method, the inductor current and the output voltage follows current/voltage segment 2002. When the output voltage reaches the control target voltage V_target, the control method further reduces the duty cycle such that the energy transferred by the inductor current is substantially dissipated in the load (R_load) and the parasitic impedances in the converter. Regulation controls the MOS switch drive signals such that the inductor current I_Land output voltage V_outfollows current/voltage segment 2004 to an equilibrium value within zone 2005.

[0423] In some embodiments, when the load is operating in a very low power mode, the duty cycle of the MOS switch drive signals necessary to maintain output voltage V_outwithin a selected range 2005 centered at V_target(“controlled interval”) may fall below a minimum value. In that instance, regulation proceeds to an “intermittent” or “cycle skipping” mode in which a pulse may not be sent in each 2 microsecond cycle. Instead, a pulse of fixed duration is sent in the MOS switch drive signals once every two or more cycles, such that the duty cycle averaged over the two or more cycles achieves the duty cycle necessary to maintain the output voltage within the controlled interval.

[0424] Subsequently, any power requirement change in a load operation (e.g., switching on backlighting), would result in a fluctuation in output voltage V_out. The control method adjusts the duty cycle of the MOS switch drive signals to restore the output voltage V_outto the regulated voltage V_targetalong current/voltage segment 2006.

[0425] Recalling that the voltage across inductor 2503 is given by: $L\frac{di}{dt}\cong L\frac{\Delta I}{\Delta t}\cong V_{\mathrm{IL}}-V_{\mathrm{in}},$

[0426] and because along current/voltage segment 2001 the change in current ΔI in inductor 2503 can be approximated by the change in voltage drop A(V_out−V_IL) across sense-resistor 2504 divided by its resistance R_senseover a 2 microsecond cycle (Δt), a first order approximation of the inductance L of inductor 2503 can be thus calculated. Similarly, since the change in output voltage ΔV_outover a 2 microsecond frame (Δt) is given by $\frac{d{V}_{\mathrm{out}}}{dt}\cong \frac{\Delta V_{\mathrm{out}}}{\Delta t}=\frac{I}{C},$

[0427] and because along current/voltage segment 2002, the voltage drop (V_IL−V_in) across inductor 2503 is approximately zero $\left(i.e,L\frac{di}{dt}\cong L\frac{\Delta I}{\Delta t}\cong 0\right)$

[0428] and the current I is given by the voltage (V_out−V_IL) across sense-resistor 2504 divided by its resistance R_sense, capacitance C can also be calculated under no-load conditions, or the combined capacitance of C and C_LOAD. During the same time interval, the parasitic resistance R_Lof inductor 2503 can be approximated from the current I_Land the small voltage drop (V_IL−V_in) across inductor 2503 by (V_IL−V_in)/I_L.

[0429] Other control parameters can be similarly calculated. For example, in a buck converter, the efficiency E at any given time is given by $E=\frac{V_{\mathrm{out}}}{V_{\mathrm{in}}D},$

[0430] where D is the duty cycle of the MOS switch drive at the current time. Efficiency E can be updated at the beginning of each cycle.

[0431] At operating point 2005, before the load is applied, the ripple voltage at the output and the parasitic series resistance R_cof the output capacitor can be approximated using the ratio of the ripple output voltage divided by the average inductor current, which is determined by calculating a weighted average of the maximum and minimum inductor currents over a 2 microsecond cycle. The maximum and minimum inductor currents are obtained by the difference in the maximum and minimum voltage drop (V_out−V_IL) across current-sense resistor 2504, sampled respectively immediately prior to MOS switch 2505 opening and closing, respectively. The weighted average of the maximum and minimum currents is calculated by weighting the maximum and minimum currents by the duty cycle D. In other words, as illustrated in FIG. 21: ${\stackrel{\_}{I}}_L=\frac{{D\left(V_{\mathrm{out}}-V_{\mathrm{IL}}\right)}_{\max }+\left(1-D\right){\left(V_{\mathrm{out}}-V_{\mathrm{IL}}\right)}_{\min }}{2}$