Multiple phase voltage regulator system

[0002] The invention generally relates to a multiple phase voltage regulator system.

[0003] A DC-to-DC voltage regulator typically is used to convert a DC input voltage to either a higher or a lower DC output voltage. One type of voltage regulator is a switching regulator that is often chosen due to its small size and efficiency. The switching regulator typically includes one or more switches that are rapidly opened and closed to transfer energy between an inductor (a stand-alone inductor or a transformer, as examples) and an input voltage source in a manner that regulates an output voltage.

[0004] As an example, referring to FIG. 1, one type of switching regulator is a Buck switching regulator 10 that receives an input DC voltage (called V_IN) and converts the V_INvoltage to a lower regulated output voltage (called V_OUT) that appears at an output terminal 11. To accomplish this, the regulator 10 includes switches 20 and 21 (a combination of a metal-oxide-semiconductor field-effect-transistor (MOSFET) and a passive diode or twin MOSFETs, for example). Switch 20 is operated (via a voltage called V_SW) in a manner to regulate the V_OUTvoltage, as described below.

[0005] Referring also FIGS. 2 and 3, in particular, the switch 20 opens and closes to control energization/de-energization cycles 19 (each having a constant duration called T_S) of an inductor 14. In each cycle 19, the regulator 10 asserts, or drives high, the V_SWvoltage during an on interval (called T_ON) to close the switch 20 and transfer energy from an input voltage source 9 to the inductor 14. During the T_ONinterval, a current (called I_L) of the inductor 14 has a positive slope. During an off interval (called T_OFF) of the cycle 19, the regulator 10 deasserts, or drives low, the V_SWvoltage to open the switch 20 and isolate the input voltage source 9 from the inductor 14. At this point, the level of the I_Lcurrent is not abruptly halted, but rather, the switch 21 begins conducting to transfer energy from the inductor 14 to a bulk capacitor 16 and a load (not shown) that are coupled to the output terminal 11. The bulk capacitor 16 serves as a stored energy source that is depleted by the load, and additional energy is transferred from the inductor 14 to the bulk capacitor 16 during each T_ONinterval.

[0006] For the Buck switching regulator, the ratio of the T_ONinterval to the total switching period, T_S(summation of T_ON+T_OFF), called a duty cycle, generally governs the ratio of the V_OUTto the V_INvoltages. Thus, to increase the V_OUTvoltage, the duty cycle may be increased, and to decrease the V_OUTvoltage, the duty cycle may be decreased.

[0007] As an example, the regulator 10 may include a controller 15 (see FIG. 1) that regulates the V_OUTvoltage by using a pulse width modulation (PWM) technique to control the duty cycle. In this manner, the controller 15 may include an error amplifier 23 that amplifies the difference between a reference voltage (called V_REF) and a voltage (called V_P(see FIG. 1)) that is proportional to the V_OUTvoltage. Referring also to FIG. 5, the controller 15 may include a comparator 26 that compares the resultant amplified voltage (called V_C) with a sawtooth voltage (called V_SAW) and provides the V_SWsignal that indicates the result of the comparison. The V_SAWvoltage is provided by a sawtooth oscillator 25 and has a constant frequency (i.e., 1/T_S).

[0008] Due to the above-described arrangement, when the V_OUTvoltage increases, the V_Cvoltage decreases and causes the duty cycle to decrease to counteract the increase in V_OUT. Conversely, when the V_OUTvoltage decreases, the V_Cvoltage increases and causes the duty cycle to increase to counteract the decrease in V_OUT.

[0009] The voltage regulator may be made in the form of a voltage regulator module (VRM), a semiconductor package, or chip, that may be inserted into a corresponding connector slot, for example. More particularly, multiple VRMs, such as the VRMs 37 and 38 that are depicted in FIG. 6, may be coupled in parallel to form a multiple phase voltage regulator system 36. In this manner, referring also FIGS. 7 and 8, energization/de-energization cycles 40a(depicted by an internal switching voltage of the VRM 37 called V_SW1) of the VRM 37 is interleaved with respect to the energization cycles 40b(depicted by an internal switching voltage of the VRM 38 called V_SW2) of the VRM 38. As depicted in FIGS. 7 and 8, the effective switching period (called T_S1) of the system 36 is one half as long as the switching period (called T_S2) of either VRM 37 or 38. Thus, the system 36 operates at twice the switching frequency of the VRM 37, 38, an operation that provides better transient response performance than either VRM 37, 38 may provide by itself. More than two VRMs (three or four, for example) may be coupled together in parallel and interleaved accordingly to further increase the overall switching frequency of the system 36.

[0010] For purposes of ensuring that each VRM 37, 38 operates in the appropriate time slot, the energization/de-energization cycles of VRMs 37 and 38 may be controlled by synchronization signals to regulate the phasing of the system 36. In this manner, the VRM 37 may receive a SYNC1 signal that is depicted in FIG. 9, and the VRM 38 may receive a SYNC2 signal that is depicted in FIG. 10. The SYNC1 signal includes pulses 42a, each of which enables a particular energization/de-energization cycle of the VRM 37. The pulses 42aare interleaved with pulses 42bof the SYNC2 signal. Each pulse 42bof the SYNC2 signal enables a particular energization/de-energization cycle of the VRM 38.

[0011] A system of interleaved VRMs (such as the system 36, for example) may supply power to a computer system. In this manner, a motherboard may include several slots, or connectors, to receive VRMs. For purposes of providing flexibility in the number of VRMs that are used and thus, the number of phases of the system, the connectors typically appear in an ordered sequence on the motherboard. This sequence defines the placement of the VRMs to form a particular multiple phase system. If the VRMs are not inserted into the appropriate slots, then the appropriate synchronization signals may not be furnished to the slots, and thus, the power supply system may not function properly.

[0012] For example, a particular motherboard may have four VRM slots: Slot1, Slot2, Slot3 and Slot4. To establish a two phase voltage regulator system, an ordering scheme that is imposed by the motherboard may require that the two VRMs are inserted in Slot1 and Slot2, as Slot1 and Slot2 receive the synchronization signals to implement a two phase interleaved switching regulator system. Thus, if the VRMs are inserted into Slot1 and Slot3, for example, the voltage regulator system may not function properly. Therefore, such an arrangement does not allow flexibility in the insertion and use of the VRMs.

[0013] Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.

[0014] FIG. 1 is a schematic diagram of a switching voltage regulator of the prior art.

[0015] FIGS. 2, 3, 4 and 5 are signal waveforms that illustrate operation of the regulator of FIG. 1.

[0016] FIG. 6 is a schematic diagram of a multiple phase voltage regulator system of the prior art.

[0017] FIGS. 7 and 8 are waveforms depicting different switching signals that control energization/de-energization cycles of different voltage regulator modules of the system of FIG. 6.

[0018] FIGS. 9 and 10 are waveforms depicting synchronization signals used to control the voltage regulator modules of the system of FIG. 6.

[0019] FIG. 11 is a schematic diagram of a multiple phase voltage regulator system according to an embodiment of the invention.

[0020] FIGS. 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 and 22 are waveforms illustrating operation of the system of FIG. 11 according to an embodiment of the invention.

[0021] FIG. 23 is a schematic diagram of a portion of the multiplexing circuitry of the system of FIG. 7 according to an embodiment of the invention.

[0022] FIG. 24 is a schematic diagram of another portion of the multiplexing circuitry of the system of FIG. 11 according to an embodiment of the invention.

[0023] FIGS. 25 and 26 are schematic diagrams of the phased synchronization generator of the system of FIG. 11 according to different embodiments of the invention.

[0024] Referring to FIG. 11, an embodiment 50 of a multiple phase voltage regulator system in accordance with the invention includes connector slots 52 (slots 52a, 52b, 52cand 52dshown as examples), each of which may receive a corresponding switching voltage regulator module (VRM) 51. The actual number of VRMs 51 that are received, or inserted, into the slots 52 establishes the number of phases of the system 50. For example, if two VRMs 51 are inserted into the slots 52, then a two phase voltage regulator system is established. Similarly, if four VRMs 51 are inserted into the slots 52, then a four phase voltage regulator system is established.

[0025] Unlike conventional arrangements, the slots 52 are not ordered for purposes of establishing which slots 52 are to be used to form a particular number of phases. In this manner, multiplexing circuitry 56 of the system 50 routes the appropriate signals to the slots 52 that are connected to the VRMs 51 to establish a number of phases (for the system 50) that is equal to the number of inserted VRMs 51. Thus, the insertion of two VRMs 51 into any two of the slots 52 establishes a two phase system 50, the insertion of three VRMs 51 into any three of the slots 52 establishes a three phase system 50, etc. In some embodiments of the invention, if only one VRM 51 is inserted into one of the slots 52, then a single phase voltage regulator system is established. As an example, the system 50 may reside on a motherboard of a computer system for purposes of providing power to components ( one or more microprocessors 55, for example) of the computer system. Thus, due to the routing of the synchronization signals by the multiplexing circuitry 56, the'slots 52 are interchangeable.

[0026] More specifically, in some embodiments of the invention, the multiplexing circuitry 56 selectively routes synchronization signals to the slots 52. The synchronization signals control the timing of the energization/de-energization cycles of VRMs 51 that are inserted into the slots 52 for purposes of establishing interleaved operation. The synchronization signal that is routed to a particular slot 52 is a function of whether a VRM 51 is inserted into that slot 52 and the total number of VRMs 51 that are inserted into the slots 52. If no VRM 51 is inserted into a particular slot 52, then the multiplexing circuitry 56, in some embodiments of the invention, grounds the synchronization line that is associated with that slot 52. Otherwise if a VRM 51 is inserted into a particular slot 52, the multiplexing circuitry 56 routes a synchronization signal to that slot 52 to establish the appropriate timing for the inserted VRM 51.

[0027] Each slot 52 has a voltage input pin connector contact that receives an input voltage (called V_IN), and each slot 52 has an output pin connector contact that is coupled to an output terminal line 53. The output terminal lines 53 are coupled together to provide an output voltage (called V_OUT) at an output node 58 that furnishes power to the computer system. In some embodiments of the invention, the slots 52 may provide multiple output voltages on multiple output terminals. However, regardless of the types of VRMs 51 that are used, the voltage input terminals of the slots 52 are coupled together in parallel, and the voltage output terminals of the slots 52 are coupled together in parallel.

[0028] The output terminals of the multiplexing circuitry 56 are coupled to synchronization communication lines that communicate the synchronization signals from the multiplexing circuit 56 to the slots 52. For example, a synchronization signal communication line 60 is coupled between an output terminal of the multiplexing circuitry 56 and a conductive contact of the slot 52a; a synchronization signal communication line 62 is coupled between an output terminal of the multiplexing circuitry 56 and a conductive contact of the slot 52b; a synchronization signal communication line 64 is coupled between an output terminal of the multiplexing circuitry 56 and a conductive contact of the slot 52c; and a synchronization signal communication line 66 is coupled between an output terminal of the multiplexing circuitry 56 and a conductive contact of the slot 52d. The input terminals of the multiplexing circuit 56 receive synchronization signals from conductive lines 59 that are coupled to the output terminals of a phase synchronized generator 54. Based on which slots 52 have inserted VRMs 51 and the number of inserted VRMs 51, the multiplexing circuitry 56 selectively routes the synchronization signals from the conductive lines 59 to the slots 52.

[0029] For purposes of determining which slots 52 have inserted VRMs 51, in some embodiments of the invention, each slot 52 provides a presence signal (called PRES1#, PRES2#, PRES3# and PRES4#, as examples). As an example, each presence signal may be formed by a terminal of an associated pullup resistor that has its other terminal coupled to a positive supply voltage and ground. When a VRM 51 is inserted into a particular slot 52, the VRM 51 pulls the presence signal low to indicate that the VRM 51 is present in the slot 52. Otherwise, the presence signal remains in a high logic state to indicate the absence of a VRM in the associated slot 52. Other techniques and arrangements may be used to generate the presence signals.

[0030] Exemplary synchronization signals called PhaseA, PhaseB, PhaseC, PhaseD, PhaseE, PhaseF, PhaseG and PhaseH are depicted in FIGS. 12, 13, 14, 15, 16, 17, 19 and 20, respectively. All of these synchronization signals may be generated by the phased synchronization generator 54 from a master system clock signal (called CLK), as described below. As described below, the phase synchronized generator 54 also generates two synchronization signals called PhaseI (FIG. 21) and PhaseJ (FIG. 22) that the generator 54 uses to generate the other synchronization signals. The multiplexing circuitry 56 selects the appropriate synchronization signals and routes the selected synchronization signals to the appropriate slots 52 based on the particular multiple phase interleaved voltage regulator system to be established. The synchronization signals are synchronized to the rising, or positive, edges of a master clock signal (called CLK), and each cycle of a particular synchronization signal lasts for twelve cycles of the CLK signal, in some embodiments of the invention. As depicted, each synchronization signal has a duty cycle of one half, though the synchronization criteria is established by the relative phase of the rising (or falling) edge of each synchronization signal to any other. This lends itself to edge, as well as level-triggered synchronization. Therefore, a particular synchronization signal enables the energization/de-energization cycle of a particular VRM for six cycles of the CLK signal and disables the energization/de-energization cycle for six cycles of the CLK signal. Therefore, the synchronization signals are distinguishable by their different phases. The multiplexing circuitry 56 selects a particular group of the synchronization signals and routes the synchronization signals from the selected group to the appropriate slot 52 to implement a particular interleaved voltage regulator system, as described below.

[0031] For example, for a two phase interleaved voltage regulator system, the multiplexing circuitry 56 selects the PhaseA and PhaseD synchronization signals from the conductive lines 59 and routes the PhaseA and PhaseD synchronization signals to the two slots 52 that have inserted VRMs 51. As depicted in FIGS. 12 and 15, the PhaseA and PhaseD synchronization signals are 180° out of phase to implement the two phase interleaved operation.

[0032] For a three phase interleaved voltage regulator system, the multiplexing circuitry 56 selects the PhaseA, PhaseC and PhaseE synchronization signals from the conductive lines 59 and routes the PhaseA, PhaseC and PhaseE synchronization signals to the three slots 52 that have inserted VRMs 51. As depicted in FIGS. 12, 14 and 16, the PhaseA synchronization signal is 120° out of phase with the PhaseC synchronization signal, and the PhaseE synchronization signal is 120° out of phase with the PhaseC synchronization signal and 240° out of phase with the PhaseA synchronization signal to implement the three phase interleaved operation.

[0033] The PhaseA (FIG. 12), PhaseB (FIG. 13), PhaseD (FIG. 15) and PhaseF (FIG. 17) synchronization signals may be used for a four way interleaved voltage regulator system. The PhaseB signal is 90° out of phase with the PhaseA signal; the PhaseD signal is 90° out of phase with the PhaseB signal; and the PhaseF signal is 90° out of phase with the PhaseD signal.

[0034] The multiplexing circuitry 56 may select the PhaseA (FIG. 12), PhaseH (FIG. 20), Phase C (FIG. 14), PhaseE (FIG. 16) and PhaseG (FIG. 19) synchronization signals to implement a six way interleaved voltage regulator system. For this implementation, six VRMs 51 are inserted into six (only four slots 52 are depicted in FIG. 11) of the slots 52. The PhaseH signal is 60° out of phase with the PhaseA signal; the PhaseC signal is 60° out of phase with the PhaseH signal; the PhaseD signal is 60° out of phase with the PhaseC signal; the PhaseE signal is 60° out of phase with the PhaseD signal and the PhaseG signal is 60° out of phase with the PhaseE signal.

[0035] If only one VRM 51 is inserted into the slots 52, then the multiplexing circuitry 56 may select any (the PhaseA synchronization signal, for example) of the synchronization signals and route the selected synchronization signal to the slot 52 that has the inserted VRM 51 to establish a single phase voltage regulator system.

[0036] Referring to FIG. 23, a circuit 56A of the multiplexing circuitry 56 includes a 2:1 (two input lines 69 that are selected by one select line 67) multiplexer 100 and a 16:4 (sixteen input lines 70 that are selected by four select lines 80) multiplexer 102 that provide the synchronization signals to the synchronization communication lines 60 and 62, respectively. One input terminal of the multiplexer 100 receives the PhaseA synchronization signal, and the other input terminal 69 is coupled to ground. A select input terminal 67 of the multiplexer 100 receives the PRES1# signal, and the non-inverting output terminal of the multiplexer 100 is coupled to the synchronization signal communication line 60. Thus, due to this arrangement, when the PRES1# signal has a logic one level to indicate that no VRM 51 is inserted into the slot, 51a, the multiplexer 100 furnishes a logic zero to the synchronization signal communication line 60. When the PRES1# signal has a logic zero level to indicate that a VRM 51 is inserted into the slot 51 a, the multiplexer 100 routes the PhaseA synchronization signal to the synchronization signal communication line 60. Because the multiplexing circuitry 56 always selects the PhaseA synchronization signal regardless of the number of phases of the system 30, the multiplexing circuit 56 routes the PhaseA synchronization signal to the slot 51aas long as a VRM 51 has been inserted into the slot 51a. As described above, the PhaseA synchronization signal is used regardless of the number of phases of the system 10.

[0037] The multiplexer 102 of the multiplexing circuitry 56A has its output terminal coupled to the synchronization communication line 62 to route the appropriate synchronization signal (if any) to the corresponding contact of the slot 52b. Select lines 80 of the multiplexer 102 receive, in the order of most significant bit (MSB) to least significant bit (LSB), the PRES1#, PRES2#, PRES3# and PRES4# signals. For purposes of convenience, the sixteen input terminals 70 of the multiplexer 102 are labeled in order from the least significant to the most significant using the following sixteen identifiers: D0, D1, D2, D3, . . . D14 and D15. Thus, using this notation, “D0” refers to the input terminal 70 that is selected when the bits that are indicated by the select lines 80 indicate “0,” “D3” refers to the input terminal 70 that is selected when the bits that are indicated by the select lines 80 indicate “3,” D15 refers to the input terminal 70 that is selected when the bits that are indicated by the select lines 80 indicate “15,” etc.

[0038] The input terminals 70 are basically divided into contiguous groups 70a, 70b, 70cand 70d. The input terminals of the groups 70d(including the D12, D13, D14 and D15 input terminals 70) and 70b(including the D4, D5, D6 and D7 input terminals 70) are selected when the PRES2# signal has a logic one level to indicate that a VRM 51 is not inserted into the slot 52b. Each input terminal of the groups 70band 70dis coupled to ground. Therefore, when no VRM 51 is inserted into the slot 52b, the multiplexer 102 grounds the synchronization signal communication line 62.

[0039] The input terminals of the group 70c(including the D8, D9, D10 and D11 input terminals 70) are selected when the PRES2# signal has a logic zero level to indicate that a VRM 51 is inserted into the slot 52band the PRES1# signal has a logic one level to indicate that a VRM 51 is not inserted into the slot 52a. Each input terminal of the group 70creceives the PhaseA synchronization signal. Therefore, the multiplexer 102 routes the PhaseA synchronization signal to the slot 51bas long as a VRM 51 has been inserted into the slot 52band no VRM 51 is inserted into the slot 52a. As described above, the PhaseA synchronization signal is used regardless of the number of phases of the system 50.

[0040] The input terminals of the group 70a(including the D0, D1, D2 and D3 input terminals 70) are selected when both the PRES2# and PRES#1 signals have a logic zero levels to indicate that VRMs 51 are inserted into both slots 52aand 52b. When this condition occurs, the multiplexer 102 selects the appropriate input terminal from the group 70 to establish the appropriate phase of the system. Because the slots 52aand 52bhave inserted VRMs 51, the number of phases depends on whether VRMs 51 are inserted into the other slots 52cand 52d. In this manner, if VRMs 51 are inserted into both slots 52cand 52d, then the PRES3# and PRES4# signals have logic zero levels to cause the multiplexer 102 to select the DO input terminal 40, a terminal 70 that receives the PhaseB synchronization for purposes of establishing four phases for the regulator system 10. If a VRM 51 is inserted into the slot 52cand not into the slot 52d, then the PRES3# has a logic zero level and the PRES4# signals has a logic one level. This condition causes the multiplexer 102 to select the D1 input terminal 70, a terminal 70 that receives the PhaseC synchronization signal for purposes of establishing three phases for the regulator system 10. Similarly, a three phase system 10 is also established if a VRM 51 is inserted into the slot 52dand not into the slot 52c, a condition that causes the multiplexer 102 to select the D2 input terminal, a terminal that receives the PhaseC synchronization signal. If a VRM 51 is neither inserted into the slot 52cnor the slot 52d, then only two VRMs 51 are inserted into the slots 52, and the multiplexer 102 selects the D3 input terminal, a terminal that receives the PhaseD synchronization signal for purposes of establishing two phases (the first phase being established by the PhaseA signal that is communicated by the multiplexer 100 to the synchronization signal communication line 60 and the second phase being established by the PhaseD signal that is communicated by the multiplexer 100 to the synchronization signal communication line 62).

[0041] Referring to FIG. 24, another circuit 56B of the multiplexing circuitry 56 includes a 16:4 (sixteen input lines 86 (each individually designated by the letters a-p) that are selected by four select lines 82) multiplexer 104 and a 16:4 (sixteen input lines 94 (each individually designated by the letters a-p) that are selected by four select lines 96) multiplexer 106 that provide the synchronization signals to the synchronization signal communication lines 64 and 66, respectively.

[0042] The multiplexer 104 of the circuit 56B has its output terminal coupled to the synchronization communication line 64 to route the appropriate synchronization signal (if any) to the corresponding contact of the slot 52c. The select lines 82 of the multiplexer 104 receive, in the order of most significant bit (MSB) to least significant bit (LSB), the PRES1#, PRES2#, PRES3# and PRES4# signals. For purposes of convenience, the sixteen input terminals 83 of the multiplexer 104 are labeled in order from the least significant to the most significant using the following sixteen identifiers: D0, D1, D2, D3, . . . D14 and D15, as described above for the multiplexer 102.

[0043] The multiplexer 104 selects one of the input terminals 86c, 86d, 86g, 86h, 86k, 86l, 86oor 86p(corresponding to the D2, D3, D6, D7, D10, D11, D14 and D15 input terminals) when the PRES3# signal has a logic one level to indicate that a VRM 51 is not inserted into the slot 52c. Each of the input terminals 86c, 86d, 86g, 86h, 86k, 86l, 86oand 86pis coupled to ground. Therefore, when no VRM 51 is inserted into the slot 52c, the multiplexer 104 grounds the synchronization signal communication line 64.

[0044] The multiplexer 104 selects one of the input terminals 86mand 86n(corresponding to the D12 and D13 input terminals 86) are selected when the PRES3# signal has a logic zero level to indicate that a VRM 51 is inserted into the slot 52cand the PRES1# and PRES2# signals each have a logic one level to indicate that the absence of a VRM 51 in both slots 52aand 52b. Each of the input terminals 86mand 86nreceives the PhaseA synchronization signal. Therefore, the multiplexer 104 routes the PhaseA synchronization signal to the slot 51cas long as a VRM 51 has been inserted into the slot 52cand no VRM 51 is inserted into the slots 52aand 52b. As described above, the PhaseA synchronization signal is used regardless of the number of phases of the system 50.

[0045] The multiplexer 104 selects one of the input terminals 86a, 86for 86jfor purposes of establishing a two or four phase system 50 when a VRM 51 is inserted into the slot 52cand at least one VRM 51 is inserted into the slots 52aand 52b. In this manner, if VRMs 51 are inserted into all four slots 52a, 52b, 52cand 52d, the multiplexer 104 selects the input terminal 86ato route the PhaseD synchronization signal to the synchronization signal communication line 64 to establish one of the phases of a four phase system 50. Otherwise, the multiplexer 104 selects one of the input terminals 86for 86jwhen a VRM 51 is inserted into the slot 52c, no VRM is inserted into the slot 52dand only one VRM 51 is inserted into one of the slots 52aor 52b. The selection of the input terminal 86for 86jroutes the PhaseD synchronization signal to the synchronization signal communication line 64 to establish one of the phases of a two phase system 50.

[0046] The multiplexer 104 selects the input terminal 86bwhen VRMs 51 are inserted into each of the three slots 52a, 52band 52c, and no VRM 51 is inserted into the slot 52d. The selection of the input terminal 86broutes the PhaseE synchronization signal to the synchronization signal communication line 64 to establish one of the phases of a three phase system 50.

[0047] The multiplexer 104 selects either the input terminal 86eor 86iwhen only one VRM 51 is inserted into the slot 52aor 52b; a VRM 51 is inserted into the slot 52c; and a VRM 51 is inserted into the slot 52d. The selection of the input terminal 86eor 86iroutes the PhaseC synchronization signal to the synchronization signal communication line 64 to establish one of the phases of a three phase system 50.

[0048] The multiplexer 106 of the circuit 56B has its output terminal coupled to the synchronization communication line 66 to route the appropriate synchronization signal (if any) to the corresponding contact of the slot 52d. The select lines 96 of the multiplexer 106 receive, in the order of most significant bit (MSB) to least significant bit (LSB), the PRES1#, PRES2#, PRES3# and PRES4# signals. For purposes of convenience, the sixteen input terminals 94 (each individually designated by the letters a-p) of the multiplexer 106 are labeled in order from the least significant to the most significant using the following sixteen identifiers: D0, D1, D2, D3, . . . D14 and D15, as described above for the multiplexer 102.

[0049] The multiplexer 106 selects one of the input terminals 94b, 94d, 94f, 94h, 94j, 94l, 94nor 94p(corresponding to the D1, D3, D5, D7, D9, D11, D13 and D15 input terminals) when the PRES4# signal has a logic one level to indicate that a VRM 51 is not inserted into the slot 52d. Each of the input terminals 94b, 94d, 94f, 94h, 94j, 94l, 94nand 94pis coupled to ground. Therefore, when no VRM 51 is inserted into the slot 52d, the multiplexer 106 grounds the synchronization signal communication line 66.

[0050] The multiplexer 106 selects the input terminal 94o(corresponding to the D14 input terminal 94) when the PRES4# signal has a logic zero level to indicate that a VRM 51 is inserted into the slot 52dand the PRES1#, PRES2# and PRES3# signals each have a logic one level to indicate that only one VRM 51 is present in the system 50. The input terminals 94oreceives the PhaseA synchronization signal. Therefore, the multiplexer 106 routes the PhaseA synchronization signal to the slot 52dto establish a single phase system 50 when the only VRM 51 present in the system 50 is inserted into the slot 52d.

[0051] The multiplexer 106 selects one of the input terminals 94g, 94kor 94mfor purposes of establishing a two phase system 10 when a VRM 51 is inserted into the slot 52dand only one VRM 51 is inserted into the slots 52a, 52bor 52c. The input terminals 94g, 94kand 94meach receive the PhaseD signal for purposes of establishing one of the two phases of the system 50 when only two VRMs are inserted into one of the slots 52a, 52bor 52cand the slot 52d.

[0052] The multiplexer 106 selects the input terminal 94awhen VRMs 51 are inserted into all four slots 52a, 52b, 52cand 52d. The selection of the input terminal 94aroutes the PhaseF synchronization signal to the synchronization signal communication line 66 to establish one of the phases of a four phase system 50.

[0053] The multiplexer 106 selects either the input terminal 94c, 94eor 94iwhen a VRM 51 is inserted into the slot 52d; and only two VRMs 51 are inserted into the slots 52a, 52band 52c. The selection of one of the input terminals 94c, 94eand 94iroutes the PhaseE synchronization signal to the synchronization signal communication line 64 to establish one of the phases of a three phase system 50.

[0054] Referring to FIG. 25, in some embodiments of the invention, the phase synchronization generator 54 includes D-type flip flops 150b, 150c, 150dand 150ethat are each clocked by the CLK signal and provide the PhaseA, PhaseB, PhaseC, PhaseD, PhaseE, PhaseF, PhaseG and PhaseH synchronization signals. In this manner, the non-inverting output terminal of the flip-flop 150bprovides the PhaseA synchronization signal, and the inverting output terminal of the flip-flop 150bprovides the PhaseD synchronization signal. The non-inverting output terminal of the flip-flop 150cprovides the PhaseB synchronization signal, and the inverting output terminal of the flip-flop 150cprovides the PhaseF synchronization signal. The non-inverting output terminal of the flip-flop 150dprovides the PhaseC synchronization signal, and the inverting output terminal of the flip-flop 150dprovides the PhaseG synchronization signal. The non-inverting output terminal of the flip-flop 150eprovides the PhaseE synchronization signal, and the inverting output terminal of the flip-flop 150eprovides the PhaseH synchronization signal.

[0055] The generator 54 also includes a D-type flip-flop 150athat is clocked by the SYS_CLK signal and furnishes two signals (called PhaseI and PhaseJ) that are intermediate signals that are used to generate the synchronization signals, as described below. The non-inverting output terminal of the flip-flop 150aprovides the PhaseI synchronization signal, and the inverting output terminal of the flip-flop 150aprovides the PhaseJ synchronization signal.

[0056] The non-inverting input terminal of the flip-flop 150areceives a signal (called L1) from the output terminal of logic 160 that combines the following synchronization signals in the following manner to produce the L1 signal:

[0057] L1=(PhaseA∩PhaseB∩PhaseC∩PhaseH)∪(PhaseD∩PhaseE∩PhaseF∩PhaseG)  Eq. 1

[0058] The non-inverting input terminal of the flip-flop 150breceives a signal (called L2) from the output terminal of logic 180 that combines the following synchronization signals in the following manner to produce the L2 signal:

[0059] L2=(PhaseI∩PhaseE∩PhaseF∩PhaseG)∪(PhaseJ∩PhaseA∩PhaseB∩PhaseH)∪(PhaseJ∩PhaseA∩PhaseF∩PhaseG)  Eq. 2

[0060] The non-inverting input terminal of the flip-flop 150creceives a signal (called L3) from the output terminal of logic 220 that combines the following synchronization signals in the following manner to produce the L3 signal:

[0061] L3=(PhaseJ∩PhaseA∩PhaseG∩PhaseH)∪(PhaseB∩PhaseC∩PhaseH)  Eq. 3

[0062] The non-inverting input terminal of the flip-flop 150dreceives a signal (called L4) from the output terminal of logic 240 that combines the following synchronization signals in the following manner to produce the L4 signal:

[0063] L4=(PhaseJ∩PhaseA∩PhaseB∩PhaseH)∪(PhaseJ∩PhaseB∩PhaseC∩PhaseD)∪(PhaseB∩PhaseC∩PhaseH)  Eq. 4

[0064] The non-inverting input terminal of the flip-flop 150ereceives a signal (called L5) from the output terminal of logic 260 that combines the following synchronization signals in the following manner to produce the L5 signal:

[0065] L5=(PhaseI∩PhaseG∩)PhaseJ∩PhaseD)∪(PhaseB∩PhaseE∩PhaseC∩PhaseF)  Eq. 5

[0066] The phase synchronized generator may assume numerous different forms. For example, FIG. 26 depicts an embodiment 500 of another phased synchronized generator in accordance with the invention that may be used in place of the generator 54. In some embodiments of the invention, the phase synchronized generator 54 includes SR-type flip flops 300b, 300c, 300dand 300ethat are each clocked by the SYS_CLK signal and provide the PhaseA, PhaseB, PhaseC, PhaseD, PhaseE, PhaseF, PhaseG and PhaseH synchronization signals. In this manner, the non-inverting output terminal of the flip-flop 300bprovides the PhaseA synchronization signal, and the inverting output terminal of the flip-flop 300bprovides the PhaseD synchronization signal. The non-inverting output terminal of the flip-flop 300cprovides the PhaseB synchronization signal, and the inverting output terminal of the flip-flop 300cprovides the PhaseF synchronization signal. The non-inverting output terminal of the flip-flop 300dprovides the PhaseC synchronization signal, and the inverting output terminal of the flip-flop 300dprovides the PhaseG synchronization signal. The non-inverting output terminal of the flip-flop 300eprovides the PhaseE synchronization signal, and the inverting output terminal of the flip-flop 300eprovides the PhaseH synchronization signal.

[0067] The generator 500 also includes an SR-type flip-flop 300athat is clocked by the SYS_CLK signal and furnishes two signals (called PhaseI and PhaseJ) that are intermediate signals that are used to generate the synchronization signals, as described below. The non-inverting output terminal of the flip-flop 300aprovides the PhaseI synchronization signal, and the inverting output terminal of the flip-flop 300aprovides the PhaseJ synchronization signal.

[0068] The S input terminal of the flip-flop 300areceives a signal (called S1) from an output terminal of logic 310 that combines the following synchronization signals in the following manner to produce the S1 signal:

[0069] S1=(PhaseA∩PhaseB∩PhaseC∩PhaseH)∪(PhaseD∩PhaseE∩PhaseF∩PhaseG)  Eq. 6

[0070] The R input terminal of the flip-flop 300areceives a signal (called R1) from another output terminal of the logic 310 that combines the following synchronization signals in the following manner to produce the R1 signal:

[0071] R1=((PhaseA∩PhaseF)∪(PhaseB∩PhaseE))∪((PhaseC∩PhaseD)∪(PhaseG∩PhaseH))  Eq. 7

[0072] The S input terminal of the flip-flop 300breceives a signal (called S2) from an output terminal of logic 340 that combines the following synchronization signals in the following manner to produce the S2 signal:

[0073] S2=PhaseI∩PhaseE∩PhaseF∩PhaseG  Eq. 8

[0074] The R input terminal of the flip-flop 300breceives a signal (called R2) from another output terminal of the logic 310 that combines the following synchronization signals in the following manner to produce the R2 signal:

[0075] R2=(PhaseI∩PhaseH)∪(PhaseB∩PhaseE)∪(PhaseC∩PhaseF)  Eq. 9

[0076] The S input terminal of the flip-flop 300creceives a signal (called S3) from an output terminal of logic 360 that combines the following synchronization signals in the following manner to produce the S3 signal:

[0077] S3=PhaseJ∩PhaseA∩PhaseG∩PhaseH  Eq. 10

[0078] The R input terminal of the flip-flop 300creceives a signal (called R3) from another output terminal of the logic 360 that combines the following synchronization signals in the following manner to produce the R3 signal:

[0079] R3=(PhaseI∩PhaseG)∪PhaseE∪(PhaseD∩PhaseG)  Eq. 11

[0080] The S input terminal of the flip-flop 300dreceives a signal (called S4) from an output terminal of logic 380 that combines the following synchronization signals in the following manner to produce the S4 signal:

[0081] S4=PhaseJ∩PhaseA∩PhaseB∩PhaseH  Eq. 12

[0082] The R input terminal of the flip-flop 300dreceives a signal (called R4) from another output terminal of the logic 360 that combines the following synchronization signals in the following manner to produce the R4 signal:

[0083] R4=(PhaseI∩PhaseE)∪PhaseF∪(PhaseA∩PhaseE)  Eq. 13

[0084] The S input terminal of the flip-flop 300ereceives a signal (called S5) from an output terminal of logic 400 that combines the following synchronization signals in the following manner to produce the S5 signal:

[0085] S5=(PhaseI∩PhaseG)∪(PhaseJ∩PhaseD)∪(PhaseC∩PhaseF)  Eq. 14

[0086] The R input terminal of the flip-flop 300ereceives a signal (called R5) from another output terminal of the logic 400 that combines the following synchronization signals in the following manner to produce the R5 signal:

[0087] R5=PhaseJ∩PhaseA∩PhaseF∩PhaseG  Eq. 15

[0088] While the invention has been disclosed with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the invention.