US 6,798,009 B2Grant

Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

Issue Date:2004-09-28

•28 Claims

•13 Drawing Sheets

Abstract

A circuit and method for a memory cell with a vertical transistor and a trench capacitor. The cell includes an access transistor that is formed in a pillar of a single crystal semiconductor material. The transistor has vertically aligned first and second source/drain regions and a body region. The transistor also includes a gate that is formed along a side of the pillar. A trench capacitor is also included in the cell. A first plate of the trench capacitor is formed integral with the first source/drain region. A second plate is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Metadata

Assignee

Micron Technology, Inc.

Inventors

Leonard Forbes
Wendell P. Noble

Application Information

Application Number:US 10/361,986

Filing Date:2003-02-11

Priority Date:1997-10-06

Art Unit:7

Classifications

IPC:

H01L 27108H01L 2976H01L 2994H01L 31119

Field of Search:

438243438366438242438396

Patent Drawings (13 sheets)

Description

[0002] This application is a Continuation of U.S. Application Ser. No. 08/944,890 filed Oct. 6, 1997 now U.S. Pat. No. 6,528,837 which is incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

[0003] The present invention relates generally to the field of memory devices and, in particular, to a circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

BACKGROUND OF THE INVENTION

[0004] Electronic systems typically store data during operation in a memory device. In recent years, the dynamic random access memory (DRAM) has become a popular data storage device for such systems. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, a high logic level is approximately equal to the power supply voltage and a low logic level is approximately equal to ground.

[0005] The cells of a conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects cells on the row with a common control signal. Similarly, each column includes a bit line that is coupled to at most one cell in each row. Thus, the word and bit lines can be controlled so as to individually access each cell of the array.

[0006] A memory array is typically implemented as an integrated circuit on a semiconductor substrate in one of a number of conventional layouts. One such layout is referred to as an “open digit line” architecture. In this architecture, the array is divided into at least two separate parts or “sub-arrays.” Each sub-array includes a number of rows and columns of memory cells. Each memory cell in a row is coupled to a common word line and each transistor in a column is coupled to a common bit line. Each bit line in the first sub-array is paired with a bit line in the second sub-array so as to feed into a common sense amplifier. The sense amplifier detects and amplifies differences in voltage on a pair of bit lines as described in more detail below.

[0007] To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. A complementary bit line that is paired with the bit line for the selected cell is equilibrated with the voltage on the bit line for the selected cell. The equilibration voltage is typically midway between the high and low logic levels. Thus, conventionally, the bit lines are equilibrated to one-half of the power supply voltage, V_CC/2. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the bit line, thus changing the voltage on the bit line.

[0008] The sense amplifier detects and amplifies the difference in voltage on the pair of bit lines. The sense amplifier typically includes two main components: an n-sense amplifier and a p-sense amplifier. The n-sense amplifier includes a cross-coupled pair of n-channel transistors that drive the low bit line to ground. The p-sense amplifier includes a cross-coupled pair of p-channel transistors and is used to drive the high bit line to the power supply voltage.

[0009] An input/output device for the array, typically an n-channel transistor, passes the voltage on the bit line for the selected cell to an input/output line for communication to, for example, a processor of a computer or other electronic system associated with the DRAM. In a write operation, data is passed from the input/output lines to the bit lines by the input/output device of the array for storage on the capacitor in the selected cell.

[0010] Each of the components of a memory device are conventionally formed as part of an integrated circuit on a “chip” or wafer of semiconductor material. One of the limiting factors in increasing the capacity of a memory device is the amount of surface area of chip used to form each memory cell. In the industry terminology, the surface area required for a memory cell is characterized in terms of the minimum feature size, “F,” that is obtainable by the lithography technology used to form the memory cell. Conventionally, the memory cell is laid out with a transistor that includes first and second source/drain regions separated by a body or gate region that are disposed horizontally along a surface of the chip. When isolation between adjacent transistors is considered, the surface area required for such a transistor is generally 8F²or 6F².

[0011] Some researchers have proposed using a vertical transistor in the memory cell in order to reduce the surface area of the chip required for the cell. Each of these proposed memory cells, although smaller in size from conventional cells, fails to provide adequate operational characteristics when compared to more conventional structures. For example, U.S. Pat. No. 4,673,962 (the '962 patent) issued to Texas Instruments on Jun. 16, 1997. The '962 patent discloses the use of a thin poly-silicon field effect transistor (FET) in a memory cell. The poly-silicon FET is formed along a sidewall of a trench which runs vertically into a substrate. At a minimum, the poly-silicon FET includes a junction between poly-silicon channel (58) and the bit line (20) as shown in FIG. 3 of the '962 patent. Unfortunately, this junction is prone to charge leakage and thus the poly-silicon FET may have inadequate operational qualities to control the charge on the storage capacitor. Other known disadvantages of such thin film poly-silicon devices may also hamper the operation of the proposed cell.

[0012] Other researchers have proposed use of a “surrounding gate transistor” in which a gate or word line completely surrounds a vertical transistor. See, e.g., Impact of a VerticalΦ-shape transistor(VΦT) Cell for1 Gbit DRAM and Beyond, IEEE Trans. On Elec. Devices, Vol 42, No. 12, December, 1995, pp. 2117-2123. Unfortunately, these devices suffer from problems with access speed due to high gate capacitance caused by the increased surface area of the gate which slows down the rise time of the word lines. Other vertical transistor cells include a contact between the pass transistor and a poly-silicon plate in the trench. Such vertical transistor cells are difficult to implement due to the contact and should produce a low yield.

[0013] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for realizable memory cell that uses less surface area than conventional memory cells.

SUMMARY OF THE INVENTION

[0014] The above mentioned problems with memory cells and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory cell is described which includes a vertical transistor and trench capacitor.

[0015] In particular, an illustrative embodiment of the present invention includes a memory cell. The memory cell includes an access transistor formed in the pillar of single crystal semiconductor material. The transistor has first and second source/drain regions and a body region that are vertically aligned. The transistor also includes a gate that is disposed adjacent to a side of the pillar. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. A second plate of the trench capacitor is disposed adjacent to the first plate and separated from the first plate by a gate oxide. In another embodiment, the second plate of the trench capacitor surrounds the second source/drain region. In a further embodiment, the second plate comprises poly-silicon. In another embodiment, an ohmic contact couples the second plate to a layer of semiconductor material.

[0016] In another embodiment, a memory device is provided that includes an array of memory cells. Each cell of the array includes a vertical access transistor formed of a semiconductor pillar that extends outwardly from a substrate with body and first and second source/drain regions. The gate is disposed adjacent to the side of the pillar adjacent to the body region. Each memory cell also includes a trench capacitor wherein a first plate of the trench capacitor is integral with the first source/drain region, the second plate of the trench capacitor is disposed adjacent to the first plate. The memory device also includes a number of bit lines that are each selectively coupled to a number of the memory cells at the second source/drain region of the access transistor so as to form columns of memory cells. A number of word lines are also provided with the memory device. The word lines are orthogonal to the bit lines in a trench between rows of the memory cells. The word lines are used to address gates of the access transistors of the memory cells that are adjacent to the word line. Finally, the memory device includes addressing circuitry that is coupled to the word lines and bit lines so as to selectively access the cells of the array. In another embodiment, the surface area of each memory cell is substantially equal to four square minimum feature size (4F²) wherein F refers to the minimum feature size for the lithographic process used to form the memory cell. In another embodiment, the pillar has a sub-micron width so as to allow substantially full depletion of the body region. In another embodiment, the word lines are sub-lithographic.

[0017] In another embodiment, a memory array is provided. The memory array includes an array of memory cells. Each memory cell includes an access transistor having body and first and second source/drain regions vertically formed outwardly from a substrate and a single crystalline semiconductor pillar. Also, a gate is disposed adjacent to a side of the transistor. The second source/drain region includes an upper semiconductor surface. The memory array also includes a number of word lines that interconnect gates of selected access transistors so as to form a number of rows of memory cells. Further, the array includes a number of first isolation trenches separating adjacent rows of memory cells. Each isolation trench houses a word line. Finally, the memory array includes a number of second isolation trenches that are each substantially orthogonal to the first isolation trenches and interposed between adjacent memory cells so as to form a number of rows of the array.

[0018] In another embodiment, a method of fabricating a memory array is provided. The method begins by forming a number of access transistors. Each access transistor is formed in a pillar of semiconductor material that extends outwardly from a substrate. The access transistor includes a first source/drain region, a body region and a second source/drain region formed vertically thereupon. The method also provides for forming a trench capacitor for each access transistor. The first plate of the trench capacitor is integral with the first source/drain region of the access transistor. A number of word lines are formed that interconnect the gates of a number of access transistors to form a row of the array. The word lines are disposed from the number of trenches that separate adjacent rows of the access transistors. Finally, the method provides for forming a number of bit lines that interconnect second source/drain regions of selected access transistors so as to form a number of columns of the array. In another embodiment, the method provides for forming a trench capacitor by forming a second plate that surrounds the first plate. In another embodiment, the method includes the step of forming a contact that couples a second plate of the trench capacitor to an underlying semiconductor layer. In another embodiment, the method provides forming a second plate that forms a grid pattern in a layer of semiconductor material such that the grid surrounds each of the pillars that forms the access transistors. In another embodiment, the method further provides depositing poly-silicon in crossing row and isolation trenches formed around the pillars that define the access transistors.

[0019] In another embodiment, a method of fabricating a memory array is provided. Initially, a first conductivity type first source/drain region layer is formed on a substrate. Additionally, a second conductivity type body region layer is formed on the first source/drain layer. A first conductivity type second source/drain region layer is formed on the body region layer. A number of substantially parallel column isolation trenches are formed so as to extend through the second source/drain region layer, the body region layer, and the first source/drain region layer so as to form column bars between the column isolation trenches. Additionally, a number of substantially parallel row isolation trenches are formed orthogonal to the column isolation trenches and extending to substantially the same depth as the column isolation trenches. These row isolation trenches form an array of vertical access transistors for the memory array. The row and column isolation trenches are filled with conductive material to a level that does not exceed the lower level of the body region so as to provide a common plate for the capacitors of memory cells of the memory array. Conductive word lines are formed in the row isolation trenches that selectively interconnect access transistors on each row. Finally, bit lines are formed that selectively interconnect the second source/drain regions of the access transistors in each column.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG. 1 is a block/schematic diagram of an illustrative embodiment of the present invention that includes a memory device that is coupled to an electronic system;

[0021] FIG. 2 is a plan view of an illustrative embodiment of a layout for a memory array according to the teachings of the present invention;

[0022] FIG. 3 is a perspective view of the illustrative embodiment of FIG. 2;

[0023] FIG. 4 is a schematic diagram of a memory cell of the embodiment of FIGS. 2 and 3; and

[0024] FIGS. 5A through 5J are perspective and elevational views of an embodiment of an integrated circuit that illustrate processing steps for fabricating the integrated circuit according to the teachings of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0025] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. The embodiments are intended to describe aspects of the invention in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and logical, mechanical and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense.

[0026] In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art.

[0027] The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.

[0028] FIG. 1 is a block/schematic diagram that illustrates generally one embodiment of a memory device 100 incorporating an array of memory cells constructed according to the teachings of the present invention. Memory device 100 is coupled to electronic system 101. Electronic system 101 may comprise, for example, a microprocessor, a memory controller, a chip set or other appropriate electronic system. Memory device 100 illustrates, by way of example but not by way of limitation, a dynamic random access memory (DRAM), in an open bit line configuration. Memory device 100 includes memory arrays 110A and 110B. Each array includes N rows and M columns of memory cells 112-ij, where i refers to the row of the cell and j refers to the column of the cell.

[0029] In the exemplary embodiment of FIG. 1, each of memory cells 112-ijhas a substantially identical structure, and accordingly, only one memory cell is described herein. These memory cells 112-ijinclude a vertical transistor where one plate of a capacitor is integral with the transistor. Memory cell 112-11 includes vertical transistor 130-11. A source/drain region of transistor 130-11 is formed in a deep trench and extends to a sufficient depth to form a storage node of storage capacitor 132-11. The other terminal of storage capacitor 132-11 is part of a mesh or grid of poly-silicon that surrounds the source/drain region of transistor 130-11 and is coupled to ground potential.

[0030] Each of the N rows of memory cells includes one of word lines WL-1 through WL-N that is formed in a trench separating adjacent rows of memory cells 112-ij. Portions of word lines WL-1 through WL-N adjacent to transistors 130-ijact as gate regions for the respective transistors. Each of the M columns includes one of bit lines BL-1 through BL-M.

[0031] Bit lines BL-1 through BL-M are used to write to and read data from memory cells 112-ij. Word lines WL-1 through WL-N are used to access a particular row of memory cells 112-ijthat is to be written or read. Addressing circuitry is also included. For example, address buffer 114 is coupled to control column decoder 118, which also includes sense amplifiers and input/output circuitry that is coupled to bit lines BL-1 through BL-M of arrays 110A and 110B. Address buffer 114 also is coupled to control row decoders 116A and 116B. Row decoders 116A and B and column decoder 118 selectably access memory cells 112-ijin response to address signals that are provided on address lines 120 from electronic system 101 during write and read operations.

[0032] In operation, memory 100 receives an address of a particular memory cell at address buffer 114. For example, electronic system 101 may provide address buffer 114 with the address for cell 112-11 of array 110A. Address buffer 114 identifies word line WL-1 for memory cell 112-11 to row decoder 116A. Row decoder 116A selectively activates word line WL-1 to activate access transistor 130-1jof each memory cell 112-1jthat is connected to word line WL-1. Column decoder 118 selects bit lines BL-1 for memory cell 112-11. For a write operation, data received by input/output circuitry is coupled to bit lines BL-1 and through the access transistor 130-11 to charge or discharge storage capacitor 132-11 of memory cell 112-11 to represent binary data. For a read operation, bit line BL-1 of array 110A is equilibrated with bit line BL-1 of array 110B. Data stored in memory cell 112-11, as represented by the charge on its storage capacitor 132-11, is coupled to bit line BL-1 of array 110A. The difference in charge in bit lines BL-1 of array 110A and bit line BL-1 of array 110B is amplified, and a corresponding voltage level is provided to the input/output circuits.

[0033] FIGS. 2 through 4 illustrate an embodiment of a memory cell with a vertical transistor and trench capacitor for use, for example, in memory device 100 of FIG. 1. Specifically, FIG. 2 is a plan view of a layout of a number of memory cells indicated generally at 202A through 202D in array 200. FIG. 2 depicts only four memory cells. It is understood, however, that array 200 may include a larger number of memory cells even though only four are depicted here.

[0034] Each memory cell is constructed in a similar manner. Thus, only memory cell 202D in FIG. 3 is described herein in detail. Memory cell 202D includes pillar 204 of single crystal semiconductor material, e.g., silicon that is divided into first source/drain region 206, body region 208, and second source/drain region 210 to form access transistor 211. Pillar 204 extends vertically outward from substrate 212, for example, p− silicon. First source/drain region 206 and second source/drain region 210 each comprise, for example, n+ silicon and body region 208 comprises p− silicon.

[0035] Word line 212 passes body region 208 of access transistor 211 in isolation trench 214. Word line 212 is separated from body region 208 of access transistor 204 by gate oxide 216 such that the portion of word line 212 adjacent to body region 208 operates as a gate for access transistor 211. Word line 212 may comprise, for example, n+ poly-silicon material that is deposited in isolation trench 214 using a technique such that word line 212 is less than a minimum feature size, F, for the lithographic technique used to fabricate array 200. Cell 202D is coupled in a column with cell 202A by bit line 218.

[0036] Memory cell 202D also includes storage capacitor 219 for storing data in the cell. A first plate of capacitor 219 for memory cell 202D is integral with second source/drain region 210 of access transistor 211. Thus, memory cell 202D may be more easily realizable when compared to conventional vertical transistors since there is no need for a contact between second source/drain region 210 and capacitor 219. Second plate 220 of capacitor 219 is common to all of the capacitors of array 200. Second plate 220 comprises a mesh or grid of n+ poly-silicon formed in deep trenches that surrounds at least a portion of second source/drain region 210 of each pillar 204A through 204D. Second plate 220 is grounded by contact with substrate 212 underneath the trenches. Second plate 220 is separated from source/drain region 210 by gate oxide 222.

[0037] With this construction for memory cell 202D, access transistor 211 is like a silicon on insulator device. Three sides of the transistor are insulated by thick oxide in the shallow trench. If the doping in pillar 204 is low and the width of the post is sub-micron, then body region 208 can act as a “fully-depleted” silicon on insulator transistor with no body or substrate to contact. This is desirable to avoid floating body effects in silicon on insulated transistors and is achievable due to the use of sub-micron dimensions in access transistor 211.

[0038] FIG. 4 is a schematic diagram that illustrates an effective circuit diagram for the embodiment of FIGS. 2 and 3. It is noted that storage capacitor 219 formed by second source/drain region 210 and second plate 220 is depicted as four separate capacitors. This represents that the second plate 220 surrounds second source/drain region 210 which increases the charge storage capacitance and stored charge for the memory cell. It is also noted that second plate 220 is maintained at a constant potential, e.g., ground potential.

[0039] As shown in FIG. 2, the memory cells of array 200 are four-square feature (4F²) memory cells. Using cell 202D as an example, the surface area of cell 202D is calculated based on linear dimensions in the bit line and word line directions. In the bit line direction, the distance from one edge of cell 202D to a common edge of adjacent cell 202A is approximately 2 minimum feature sizes (2F). In the word line direction, the dimension is taken from the midpoint of isolation trenches on either side of memory cell 202D. Again, this is approximately two minimum feature sizes (2F). Thus, the size of the cell is 4F². This size is much smaller than the current cells with stacked capacitors or trenched capacitors.

[0040] FIGS. 5A through 5J illustrate one embodiment of a process for fabricating an array of memory cells, indicated generally at 299, according to the teachings of the present invention. In this example, dimensions are given that are appropriate to a 0.2 micrometer lithographic image size. For other image sizes, the vertical dimensions can be scaled accordingly.

[0041] As shown in FIG. 5A, the method begins with substrate 300. Substrate 300 comprises, for example, a P-type silicon wafer, layer of P− silicon material, or other appropriate substrate material. Layer 302 is formed, for example, by epitaxial growth outwardly from layer 300. Layer 302 comprises single crystalline N+ silicon that is approximately 3.5 micrometers thick. Layer 304 is formed outwardly from layer 302 by epitaxial growth of single crystalline P− silicon of approximately 0.5 microns. Layer 306 is formed by ion implantation of donor dopant into layer 304 such that layer 306 comprises single crystalline N+ silicon with a depth of approximately 0.1 microns.

[0042] A thin layer of silicon dioxide (SiO₂), referred to as pad oxide 308, is deposited or grown on layer 306. Pad oxide 308 has a thickness of approximately 10 nanometers. A layer of silicon nitride (Si₃N₄), referred to as pad nitride 310, is deposited on pad oxide 308. Pad nitride 310 has a thickness of approximately 200 nanometers.

[0043] Photo resist layer 312 is deposited outwardly from layer 310. Photo resist layer 312 is patterned with a mask to define openings 314 in layer 312 to be used in selective etching. As shown in FIG. 5B, column isolation trenches 316 are etched through openings 314 in photo resist layer 312 in a direction parallel to which the bit lines will be formed. Column isolation trenches 316 extend down through nitride layer 310, oxide layer 308, N+ layer 306, P− layer 304, N+ layer 302, and into substrate 300.

[0044] A thin thermal protective oxide layer 318 is grown on exposed surfaces of substrate 300 and layers 302, 304, and 306. Layer 318 is used to protect substrate 300 and layers 302, 304 and 306 during subsequent process step.

[0045] A layer of intrinsic poly-silicon 320 is deposited by chemical vapor deposition (CVD) to fill column isolation trenches 316. Layer 320 is etched by reactive ion etching (RIE) such that layer 320 is recessed below a top of layer 302. Layer 322 of silicon nitride (Si₃N₄) is deposited by, for example, chemical vapor deposition to fill trenches 316. Layer 322 is planarized back to a level of layer 310 using, for example, chemical mechanical polishing (CMP) or other suitable planarization technique to produce the structure shown in FIG. 5C.

[0046] As shown in FIG. 5D, layer 324 of photo resist material is deposited outwardly from nitride layers 322 and 310. Layer 324 is exposed through a mask to define openings 326 in layer 324. Openings 326 are orthogonal to trenches 316 that were filled by intrinsic poly-silicon layer 320 and nitride layer 322. Next, nitride layers 310 and 322 are etched to a depth sufficient to expose a working surface 328 of layer 306. It is noted that at this point layer 320 of intrinsic poly-silicon is still covered by a portion of nitride layer 322.

[0047] As shown in FIG. 5E, the portion of layers 306, 304, and 302 that are exposed in openings 326 are selectively etched down to a distance approximately equal to column isolation trenches 316. A thin thermal protective oxide is grown on the exposed silicon of layers 302, 304 and 306 as well as an exposed upper surface of layer 300. This oxide layer is labeled 330 in FIG. 5E.

[0048] As shown in FIG. 5F, the remaining nitride layer 322 exposed in openings 326 is directionally etched to expose layer of intrinsic poly-silicon 320. It is noted that nitride layer 322 and nitride layer 310 remain intact under the photo resist layer 324. Layer of intrinsic poly-silicon 320 is next isotropically etched using a silicon etchant which does not attack oxide or nitride layers. Next, an isotropic oxide etch is performed to remove all exposed thin oxide. The photo resist layer 324 is removed. At this point, the method has produced the structure shown in FIG. 5G. This structure includes a nitride bridge formed from nitride layers 310 and 322 that extends orthogonal to column isolation trenches 316 and covers the remaining portions of layers 302, 304, and 306. The structure also includes row isolation trenches 332 that are orthogonal to column isolation trenches 316. The structure of FIG. 5G also includes pillars 334A through 334D of single crystal silicon material. Pillars 334A through 334D form the basis for individual memory cells for the memory array formed by the process.

[0049] An optional metal contact 336 may be formed by, for example, deposition of a collimated refractory metal deposition, e.g., titanium, tungsten, or a similar refractory metal. This provides an ohmic metal contact for a capacitor plate on a surface 335 of substrate 300.

[0050] Dielectric layer 338 is deposited or grown on sidewalls of layer 302 of pillars 334A through 334D. Layer 338 acts as the dielectric for the storage capacitors of array 299 of memory cells. If contact 336 was previously deposited on a surface of substrate 300, dielectric layer 338 should be directionally etched to clear dielectric material from the bottom of row isolation trench 332.

[0051] Next, a common plate for all of the memory cells of array 299 is formed by a chemical vapor deposition of N+ poly-silicon or other appropriate refractory conductor in column isolation trenches 316 and row isolation trenches 322. In this manner, conductor mesh or grid 340 is formed so as to surround each of pillars 334A through 334D. Mesh 340 is planarized and etched back to a level approximately at the bottom of the nitride bridge formed by nitride layers 322 and 310 as shown in FIG. 5H. An additional etch is performed to remove any remaining exposed capacitor dielectric of layer 338 from the sides of semiconductor pillars 334A through 334D.

[0052] Referring to FIG. 5I, row isolation trenches 332 are filled with an oxide material by chemical vapor deposition that fills row isolation trenches 332 with oxide layer 342. Oxide layer 342 is planarized using, for example, a chemical mechanical polishing technique or other appropriate planarization technique to bring oxide layer 342 coplanar with the top surface of nitride layer 310.

[0053] Photo resist layer 344 is deposited and patterned using a mask to define stripes in the direction of row isolation trenches 332 so as to define the location of word lines for array 299. Oxide layer 342 is selectively etched to a depth approximately at the top of layer 302. Gate oxide layer 346 is grown or deposited on sidewalls of pillars 334A through 334D to form a gate oxide for the transistors for each memory cell. A material such as N+ poly-silicon is deposited by, for example, chemical vapor deposition (CVD) into the remaining portion of row isolation trench 332 in order to form word lines 348. Word lines 348 are planarized and recessed to a depth at least to the top of silicon pillars 334A through 334D. It is noted that by so forming word line 348, word line 348 is “sub-lithographic” in that the width of word line 348 in the bit line direction is less than F, the minimum feature size for the lithographic process used to form array 299. Photo resist layer 344 is removed. An oxide cap layer is deposited by chemical vapor deposition and conventional techniques are used to add bit lines (BL) that contact layers 306 of semiconductor pillars 334A through 334D in order to produce array 299 shown in FIG. 5J. Array 299 includes memory cells 350A through 350D formed by pillars 334A through 334D, respectively, and surrounding mesh 340.

Conclusion

[0054] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. For example, the semiconductor materials specified in this application are given by way of example and not by way of limitation. Other appropriate material can be substituted without departing from the spirit and scope of the invention.

Claims

Certificate of Correction present

The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.

What is claimed is:

1. A memory cell, comprising:

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;

a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar; and

a second plate of the trench capacitor.

2. The memory cell of claim 1, wherein the second plate includes poly-silicon.

3. The memory cell of claim 1, and further including an ohmic contact that couples the second plate to a layer of semiconductor material.

4. A memory device, comprising:

an array of memory cells, wherein at least one cell includes:

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor includes a first source/drain region, and a body region;

wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion of the pillar also functions as a first plate of a trench capacitor;

a second plate of the trench capacitor;

a number of bit lines that are each selectively coupled to a number of the memory cells at the first source/drain region of the access transistor so as to form columns of memory cells;

a number of word lines, each word line disposed orthogonally to the bit lines with a single word line in each of a number of trenches between rows of the memory cells; and

wherein each single word line addresses gates of access transistors on a first side of a trench, and is isolated from access transistors on a second side of the trench.

5. The memory device of claim 4, wherein the pillars extend outwardly from a semiconductor portion of the substrate.

6. The memory device of claim 4, wherein the second plate of the trench capacitor is maintained at approximately ground potential.

7. The memory device of claim 4, wherein the second plate of the trench capacitor comprises poly-silicon that is maintained at a constant potential.

8. The memory device of claim 4, wherein the pillar has a sub-micron width allowing substantially full depletion of the body region.

9. The memory device of claim 4, wherein the word lines are sub-lithographic.

10. A memory array comprising:

an array of memory cells, each memory cell including

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion the pillar also functions as a first plate of a trench capacitor;

a second plate of the trench capacitor;

a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells.

11. The memory array of claim 10, wherein the gates of the access transistors are each formed integral with one of the word lines.

12. The memory array of claim 10, wherein the pillars extend outwardly from a semiconductor portion of the substrate.

13. The memory array of claim 10, wherein the second plate of the trench capacitor comprises poly-silicon that is maintained at a constant potential.

14. The memory array of claim 10, wherein the word lines have a width that is less than the minimum feature size, F, of a lithographic process.

15. A memory cell, comprising:

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

a second plate of the trench capacitor substantially surrounding the first plate portion of the lower pillar structure; and

an ohmic contact that couples the second plate to a layer of semiconductor material.

16. The memory cell of claim 15, wherein the second plate includes poly-silicon.

17. The memory cell of claim 15, wherein the ohmic contact includes a refractory metal.

18. A memory device, comprising:

an array of memory cells, wherein at least one cell includes:

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

a second plate of the trench capacitor substantially surrounding the first plate portion of the pillar;

an ohmic contact that couples the second plate to a layer of semiconductor material;

a number of bit lines that are each selectively coupled to a number of the memory cells at the first source/drain region of the access transistor so as to form columns of memory cells;

a number of word lines, each word line disposed orthogonally to the bit lines with a single word line in each of a number of trenches between rows of the memory cells; and

wherein each single word line addresses gates of access transistors on a first side of a trench, and is isolated from access transistors on a second side of the trench.

19. The memory device of claim 18, wherein the pillars extend outwardly from a semiconductor portion of the substrate.

20. The memory device of claim 18, wherein the second plate of the trench capacitor is maintained at approximately ground potential.

21. The memory device of claim 18, wherein the second plate of the trench capacitor includes poly-silicon that is maintained at a constant potential.

22. The memory device of claim 18, wherein the pillar has a sub-micron width allowing substantially full depletion of the body region.

23. The memory device of claim 18, wherein the word lines are sub-lithographic.

24. A memory array comprising:

an array of memory cells, each memory cell including

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

a second plate of the trench capacitor substantially surrounding the first plate portion of the pillar;

an ohmic contact that couples the second plate to a layer of semiconductor material;

a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells.

25. The memory array of claim 24, wherein the gates of the access transistors are each formed integral with one of the word lines.

26. The memory array of claim 24, wherein the pillars extend outwardly from a semiconductor portion of the substrate.

27. A memory cell, comprising:

an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;

a second polysilicon plate of the trench capacitor substantially surrounding the first plate portion of the lower pillar structure; and

an ohmic contact that couples the second plate to a layer of semiconductor material.

28. The memory cell of claim 27, wherein the ohmic contact includes a refractory metal.

Patent Citations (191)

Patent	Date	Inventor	Cited By
US3931617(A)	1976-01-01	Russell	Applicant
US4020364(A)	1977-04-01	Kuijk	Applicant
US4051354(A)	1977-09-01	Choate	Applicant
US4252579(A)	1981-02-01	Ho et al.	Applicant
US4313106(A)	1982-01-01	Hsu	Applicant
US4570176(A)	1986-02-01	Kolwicz	Applicant
US4604162(A)	1986-08-01	Sobczak	Applicant
US4617649(A)	1986-10-01	Kyomasu et al.	Applicant
US4630088(A)	1986-12-01	Ogura et al.	Applicant
US4663831(A)	1987-05-01	Birrittella et al.	Applicant
US4673962(A)	1987-06-01	Chatterjee et al.	Applicant
US4677589(A)	1987-06-01	Haskell et al.	Applicant
US4701423(A)	1987-10-01	Szluk	Applicant
US4716314(A)	1987-12-01	Mulder et al.	Applicant
US4740826(A)	1988-04-01	Chatterjee	Applicant
US4761385(A)	1988-08-01	Pfiester	Applicant
US4761768(A)	1988-08-01	Turner et al.	Applicant
US4766569(A)	1988-08-01	Turner et al.	Applicant
US4845537(A)	1989-07-01	Nishimura et al.	Applicant
US4888735(A)	1989-12-01	Lee et al.	Applicant
US4906590(A)	1990-03-01	Kanetaki et al.	Applicant
US4920065(A)	1990-04-01	Chin et al.	Applicant
US4920389(A)	1990-04-01	Itoh	Applicant
US4920515(A)	1990-04-01	Obata	Applicant
US4929988(A)	1990-05-01	Yoshikawa	Applicant
US4949138(A)	1990-08-01	Nishimura	Applicant
US4958318(A)	1990-09-01	Harari	Applicant
US4965651(A)	1990-10-01	Wagner	Applicant
US4987089(A)	1991-01-01	Roberts	Applicant
US5001526(A)	1991-03-01	Gotou	Applicant
US5006909(A)	1991-04-01	Kosa	Applicant
US5010386(A)	1991-04-01	Groover, III	Applicant
US5017504(A)	1991-05-01	Nishimura et al.	Applicant
US5021355(A)	1991-06-01	Dhong et al.	Applicant
US5028977(A)	1991-07-01	Kenneth et al.	Applicant
US5057896(A)	1991-10-01	Gotou	Applicant
US5072269(A)	1991-12-01	Hieda	Applicant
US5083047(A)	1992-01-01	Horie et al.	Applicant
US5087581(A)	1992-02-01	Rodder	Applicant
US5102817(A)	1992-04-01	Chatterjee et al.	Applicant
US5107459(A)	1992-04-01	Chu et al.	Applicant
US5110752(A)	1992-05-01	Lu	Applicant
US5140388(A)	1992-08-01	Bartelink	Applicant
US5156987(A)	1992-10-01	Sandhu et al.	Applicant
US5177028(A)	1993-01-01	Manning	Applicant
US5177576(A)	1993-01-01	Kimura et al.	Applicant
US5181089(A)	1993-01-01	Matsuo et al.	Applicant
US5191509(A)	1993-03-01	Wen	Applicant
US5202278(A)	1993-04-01	Mathews et al.	Applicant
US5208657(A)	1993-05-01	Chatterjee et al.	Applicant
US5216266(A)	1993-06-01	Ozaki	Applicant
US5220530(A)	1993-06-01	Itoh	Applicant
US5221867(A)	1993-06-01	Mitra et al.	Applicant
US5223081(A)	1993-06-01	Doan	Applicant
US5266514(A)	1993-11-01	Tuan et al.	Applicant
US5276343(A)	1994-01-01	Kumagai et al.	Applicant
US5308782(A)	1994-05-01	Mazure et al.	Applicant
US5316962(A)	1994-05-01	Matsuo et al.	Applicant
US5320880(A)	1994-06-01	Sandhu et al.	Applicant
US5327380(A)	1994-07-01	Kersh, III et al.	Applicant
US5329481(A)	1994-07-01	Seevinck et al.	Applicant
US5341331(A)	1994-08-01	Jeon	Applicant
US5363325(A)	1994-11-01	Sunouchi et al.	Applicant
US5365477(A)	1994-11-01	Cooper, Jr. et al.	Applicant
US5376575(A)	1994-12-01	Kim et al.	Applicant
US5378914(A)	1995-01-01	Ohzu et al.	Applicant
US5379255(A)	1995-01-01	Shah	Applicant
US5382540(A)	1995-01-01	Sharma et al.	Applicant
US5385853(A)	1995-01-01	Mohammad	Applicant
US5391911(A)	1995-02-01	Beyer et al.	Applicant
US5392245(A)	1995-02-01	Manning	Applicant
US5393704(A)	1995-02-01	Huang et al.	Applicant
US5396093(A)	1995-03-01	Lu	Applicant
US5396452(A)	1995-03-01	Wahlstrom	Applicant
US5410169(A)	1995-04-01	Yamamoto et al.	Applicant
US5414287(A)	1995-05-01	Hong	Applicant
US5414288(A)	1995-05-01	Fitch et al.	Applicant
US5416350(A)	1995-05-01	Watanabe	Applicant
US5416736(A)	1995-05-01	Kosa et al.	Applicant
US5422296(A)	1995-06-01	Lage	Applicant
US5422499(A)	1995-06-01	Manning	Applicant
US5427972(A)	1995-06-01	Shimizu et al.	Applicant
US5429955(A)	1995-07-01	Joyner et al.	Applicant
US5432739(A)	1995-07-01	Pein	Applicant
US5438009(A)	1995-08-01	Yang et al.	Applicant
US5440158(A)	1995-08-01	Sung-Mu	Applicant
US5443992(A)	1995-08-01	Risch et al.	Applicant
US5445986(A)	1995-08-01	Hirota	Applicant
US5451538(A)	1995-09-01	Fitch et al.	Applicant
US5460316(A)	1995-10-01	Hefele	Applicant
US5460988(A)	1995-10-01	Hong	Applicant
US5466625(A)	1995-11-01	Hsieh et al.	Applicant
US5483094(A)	1996-01-01	Sharma et al.	Applicant
US5483487(A)	1996-01-01	Sung-Mu	Applicant
US5492853(A)	1996-02-01	Jeng et al.	Applicant
US5495441(A)	1996-02-01	Hong	Applicant
US5497017(A)	1996-03-01	Gonzales	Applicant
US5504357(A)	1996-04-01	Kim et al.	Applicant
US5508219(A)	1996-04-01	Bronner et al.	Applicant
US5508542(A)	1996-04-01	Geiss et al.	Applicant
US5519236(A)	1996-05-01	Ozaki	Applicant
US5528062(A)	1996-06-01	Hsieh et al.	Applicant
US5528173(A)	1996-06-01	Merritt et al.	Applicant
US5563083(A)	1996-10-01	Pein	Applicant
US5574299(A)	1996-11-01	Kim	Applicant
US5576238(A)	1996-11-01	Fu	Applicant
US5581101(A)	1996-12-01	Ning et al.	Applicant
US5593912(A)	1997-01-01	Rajeevakumar	Applicant
US5612559(A)	1997-03-01	Park et al.	Applicant
US5616934(A)	1997-04-01	Dennison et al.	Applicant
US5627097(A)	1997-05-01	Venkatesan et al.	Applicant
US5627390(A)	1997-05-01	Maeda et al.	Applicant
US5637898(A)	1997-06-01	Baliga	Applicant
US5640342(A)	1997-06-01	Gonzalez	Applicant
US5640350(A)	1997-06-01	Iga	Applicant
US5644540(A)	1997-07-01	Manning	Applicant
US5646900(A)	1997-07-01	Tsukude et al.	Applicant
US5674769(A)	1997-10-01	Alsmeier et al.	Applicant
US5691230(A)	1997-11-01	Forbes	Applicant
US5696011(A)	1997-12-01	Yamazaki et al.	Applicant
US5705415(A)	1998-01-01	Orlowski et al.	Applicant
US5707885(A)	1998-01-01	Lim	Applicant
US5714793(A)	1998-02-01	Cartagena et al.	Applicant
US5719409(A)	1998-02-01	Singh et al.	Applicant
US5753947(A)	1998-05-01	Gonzalez	Applicant
US5760434(A)	1998-06-01	Zahurak et al.	Applicant
US5780888(A)	1998-07-01	Maeda et al.	Applicant
US5801413(A)	1998-09-01	Pan	Applicant
US5818084(A)	1998-10-01	Williams et al.	Applicant
US5821578(A)	1998-10-01	Shimoji	Applicant
US5827765(A)	1998-10-01	Stengl et al.	Applicant
US5834814(A)	1998-11-01	Ito	Applicant
US5864158(A)	1999-01-01	Liu et al.	Applicant
US5874760(A)	1999-02-01	Burns, Jr. et al.	Applicant
US5877061(A)	1999-03-01	Halle et al.	Applicant
US5879971(A)	1999-03-01	Witek	Applicant
US5907170(A)	1999-05-01	Forbes et al.	Applicant
US5909400(A)	1999-06-01	Bertin et al.	Applicant
US5909618(A)	1999-06-01	Forbes et al.	Applicant
US5914511(A)	1999-06-01	Noble et al.	Applicant
US5917342(A)	1999-06-01	Okamura	Applicant
US5920088(A)	1999-07-01	Augusto	Applicant
US5926412(A)	1999-07-01	Evans, Jr. et al.	Applicant
US5933717(A)	1999-08-01	Hause et al.	Applicant
US5936274(A)	1999-08-01	Forbes et al.	Applicant
US5943267(A)	1999-08-01	Sekariapuram et al.	Applicant
US5946472(A)	1999-08-01	Graves et al.	Applicant
US5963469(A)	1999-10-01	Forbes	Applicant
US5973352(A)	1999-10-01	Noble	Applicant
US5973356(A)	1999-10-01	Noble et al.	Applicant
US5981995(A)	1999-11-01	Selcuk	Applicant
US5991225(A)	1999-11-01	Forbes et al.	Applicant
US5998820(A)	1999-12-01	Chi et al.	Applicant
US6006166(A)	1999-12-01	Meyer	Applicant
US6016268(A)	2000-01-01	Worley	Applicant
US6025225(A)	2000-02-01	Forbes et al.	Applicant
US6040210(A)	2000-03-01	Burns, Jr. et al.	Applicant
US6040218(A)	2000-03-01	Lam	Applicant
US6043527(A)	2000-03-01	Forbes	Applicant
US6066869(A)	2000-05-01	Noble et al.	Applicant
US6072209(A)	2000-06-01	Noble et al.	Applicant
US6100123(A)	2000-08-01	Bracchitta et al.	Applicant
US6121084(A)	2000-09-01	Coursey	Applicant
US6134175(A)	2000-10-01	Forbes et al.	Applicant
US6143636(A)	2000-11-01	Forbes et al.	Applicant
US6150687(A)	2000-11-01	Noble et al.	Applicant
US6153468(A)	2000-11-01	Forbes et al.	Applicant
US6156604(A)	2000-12-01	Forbes et al.	Applicant
US6156607(A)	2000-12-01	Noble et al.	Applicant
US6165836(A)	2000-12-01	Forbes et al.	Applicant
US6172391(B1)	2001-01-01	Goebel et al.	Applicant
US6172535(B1)	2001-01-01	Hopkins	Applicant
US6181121(B1)	2001-01-01	Kirkland et al.	Applicant
US6181196(B1)	2001-01-01	Nguyen	Applicant
US6208164(B1)	2001-03-01	Noble et al.	Applicant
US6221788(B1)	2001-04-01	Kobayashi et al.	Applicant
US6238976(B1)	2001-05-01	Noble et al.	Applicant
US6242775(B1)	2001-06-01	Noble	Applicant
US6255708(B1)	2001-07-01	Sudharsanan et al.	Applicant
US6323719(B1)	2001-11-01	Chang et al.	Applicant
US6399979(B1)	2002-06-01	Noble et al.	Applicant
US6433382(B1)	2002-08-01	Orlowski et al.	Applicant
US6498065(B1)	2002-12-01	Forbes et al.	Applicant
US6528837(B2)	2003-03-01	Forbes et al.	Examiner
EP198590	1986-10-01		Applicant
JP61-140170	1986-06-01		Applicant
JP63066963	1988-03-01		Applicant
JP63-066963	1988-03-01		Applicant
JP5226661	1993-09-01		Applicant
JP11-135757	1999-05-01		Applicant
JP2000-164883	2000-06-01		Applicant

Non-Patent Literature (82)

Adler, E..,et al.,“The Evolution of IBM CMOS DRAM Technology”, IBM J. Res. Develop., 39(1/2), (1995),167-188.Applicant
Asai, S..,et al.,“Technology Challenges for Integration Near and Below 0.1 micrometer”, Proceedings of the IEEE, 85(4), Special Issue on Nanometer-Scale Science & Technology,(Apr. 1997),505-520.Applicant
Banerjee, S..K.,et al.,“Characterization of Trench Transistors for 3-D Memories”, 1986 Symposium on VLSI Technology, Digest of Technical Papers, San Diego, CA,(May 1986),79-80.Applicant
Blalock, T..N.,et al.,“A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier”, IEEE Journal of Solid-State Circuits, 27(4), (April 1992),pp. 618-624.Applicant
Bomchil, G..,et al.,“Porous Silicon: The Material and its Applications in Silicon-On-Insulator Technologies”, Applied Surface Science, 41/42, (1989),604-613.Applicant
Burnett, D..,et al.,“Implications of Fundamentals Threshold Voltage Variations for High-Density SRAM and Logic Circuits”, 1994 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI,(June 1994),15-16.Applicant
Burnett, D..,et al.,“Statistical Threshold-Voltage Variation and its Impact on Supply-Voltage Scaling”, Proceedings SPIE: Microelectronic Device and Multilevel Interconnection Technology, 2636, (1995),83-90.Applicant
Chen, M..J.,et al.,“Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Circuits”, IEEE Transactions on Electron Devices, 43, (June 1996),904-909.Applicant
Chen, M..J.,et al.,“Optimizing the Match in Weakly Inverted MOSFET's by Gated Lateral Bipolar Action”, IEEE Transactions on Electron Devices, 43, (May 1996),766-773.Applicant
Chung, I..Y.,et al.,“A New SOI Inverter for Low Power Applications”, Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL,(1996),20-21.Applicant
De, V..K.,et al.,“Random MOSFET Parameter Fluctuation Limits to Gigascale Integration (GSI)”, 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI,(June 11-13, 1996),198-199.Applicant
Denton, J..P.,et al.,“Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate”, IEEE Electron Device Letters, 17(11), (November1996),pp. 509-511.Applicant
Fong, Y..,et al.,“Oxides Grown on Textured Single-Crystal Silicon—Dependence on Process and Application in EEPROMs”, IEEE Transactions on Electron Devices, 37(3), (March 1990),pp. 583-590.Applicant
Fuse, T..,et al.,“A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic”, 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, (1997),286-287.Applicant
Gong, S..,et al.,“Techniques for Reducing Switching Noise in High Speed Digital Systems”, Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit, Austin, TX,(1955),21-24.Applicant
Hao, M..Y.,et al.,“Electrical Characteristics of Oxynitrides Grown on Textured Single-Crystal Silicon”, Appl. Phys. Lett., 60, (Jan. 1992),445-447.Applicant
Harada, M..,et al.,“Suppression of Threshold Voltage Variation in MTCMOS/SIMOX Circuit Operating Below 0.5 V”, 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI,(June 11-13, 1996),96-97.Applicant
Hisamoto, D..,et al.,“A New Stacked Cell Structure for Giga-Bit DRAMs using Vertical Ultra-Thin SOI (DELTA) MOSFETs”, 1991 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C.,(Dec. 8-11, 1991),959-961.Applicant
Hodges, David.A.,et al.,“MOS Decoders”, In: Analysis and Design of Digital Integrated Circuits, 2nd Edition, Section: 9.1.3,(1988),354-357.Applicant
Holman, W..T.,et al.,“A Compact Low Noise Operational Amplifier for a 1.2 Micrometer Digital CMOS Technology”, IEEE Journal of Solid-State Circuits, 30, (June 1995),710-714.Applicant
Hu, G..,et al.,“Will Flash Memory Replace Hard Disk Drive?”, 1994 IEEE International Electron Device Meeting, Panel Discussion, Session 24, Outline,(Dec. 1994), 2 pp.Applicant
Huang, W..L.,et al.,“TFSOI Complementary BiCMOS Technology for Low Power Applications”, IEEE Transactions on Electron Devices, 42, (Mar. 1995),506-512.Applicant
Jun, Y..K.,et al.“The Fabrication and Electrical Properties of Modulated Stacked Capacitor for Advanced DRAM Applications”, IEEE Electron Device Letters, 13, (Aug. 1992),430-432.Applicant
Jung, T..S.,et al.,“A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications”, IEEE Journal of Solid-State Circuits, 31, (Nov. 1996), 1575-1583.Applicant
Kang, H..K.,et al.,“Highly Manufacturing Process Technology for Reliable 256 Mbit and 1Gbit DRAMs”, IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA,(Dec. 11-14, 1994),635-638.Applicant
Kim, Y..S.,et al.,“A Study on Pyrolysis DMEAA for Selective Deposition of Aluminum”, In: Advanced Metallization and Interconnect Systems for ULSI Applications in 1995, R.C. Ellwanger, et al., (eds.), Materials Research Society, Pittsburgh, PA,(1996)675-680.Applicant
Kishimoto, T..,et al.,“Well Structure by High-Energy Boron Implantation for Soft-Error Reduction in Dynamic Random Access Memories (DRAMs)”, Japanese Journal of Applied Physics, 34, (Dec. 1995),6899-6902.Applicant
Kohyama, Y..,et al.,“Buried Bit-Line Cell for 64MB DRAMs”, 1990 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI,(Jun. 4-7, 1990),17-18.Applicant
Koshida, N..,et al.,“Efficient Visible Photoluminescence from Porous Silicon”, Japanese Journal of Applied Physics, 30, (July 1991),L1221-L1223.Applicant
Kuge, S..,et al.,“SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories”, IEEE Journal of Solid-State Circuits, 31(4), (April 1996),pp. 586-591.Applicant
Lantz, II, L..,“Soft Errors Induced By Alpha Particles”, IEEE Transactions on Reliability, 45, (June 1996),174-179.Applicant
Lehmann, V..,“The Physics of Macropore Formation in Low Doped n-Type Silicon”, Journal of the Electrochemical Society, 140(10), (Oct. 1993),2836-2843.Applicant
Lu, N..,et al.,“The SPT Cell—A New Substrate-Plate Trench Cell for DRAMs”, 1985 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C.,(Dec. 1-4, 1985),771-772.Applicant
Macsweeney, D..,et al.,“Modelling of Lateral Bipolar Devices in a CMOS Process”, IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN,(Sep. 1996),27-30.Applicant
Maeda, S..,et al.,“A Vertical Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond”, 1994 Symposium of VLSI Technology, Digest of Technical Papers, Honolulu, HI(Jun. 7-9, 1994), 133-134.Applicant
Maeda, S..,et al.,“Impact of a Verticle Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond”, IEEE Transactions on Electron Devices, 42, (Dec. 1995),2117-2123.Applicant
Malaviya, S.., IMB TBD, 15, (July 1972),p. 42.Applicant
Nitayama, A..,et al.,“High Speed and Compact CMOS Circuits with Multipillar Surrounding Gate Transistors”, IEEE Transactions on Electron Devices, 36, (Nov. 1989),2605-2606.Applicant
Ohno, Y..,et al.,“Estimation of the Charge Collection for the Soft-Error Immunity by the 3D-Device Simulation and the Quantitative Investigation”, Simulation of Semiconductor Devices and Processes, 6, (Sep. 1995),302-305.Applicant
Oowaki, Y..,et al.,“New alpha-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell”, IEICE Transactions on Electronics, 78-C, (July 1995),845-851.Applicant
Oshida, S..,et al.,“Minority Carrier Collection in 256 M-bit DRAM Cell on Incidence of Alpha-Particle Analyzed by Three-Dimensional Device Simulation”, IEICE Transactions on Electronics, 76-C, (Nov. 1993), 1604-1610.Applicant
Ozaki, T..,et al.,“A Surrounding Isolation-Merged Plate Electrode (Simple) Cell with Checkered Layout for 256 Mbit DRAMs and Beyond”, 1991 IEEE International Electron Devices Meeting, Washington, D.C.,(Dec. 8-11, 1991),469-472.Applicant
Parke, S..A.,et al.,“A High-Performance Lateral Bipolar Transistor Fabricated on Simox”, IEEE Electron Device Letters, 14, (Jan. 1993),33-35.Applicant
Pein, H..,et al.,“A 3-D Sidewall Flash EEPROM Cell and Memory Array”, IEEE Transactions on Electron Devices, 40, (Nov. 1993),2126-2127.Applicant
Pein, H..,et al.,“Performance of the 3-D Pencil Flash EPROM Cell and Memory Array”, IEEE Transactions on Electron Devices, 42, (November, 1995),1982-1991.Applicant
Pein, H..B.,et al.,“Performance of the 3-D Sidewall Flash EPROM Cell”, IEEE International Electron Devices Meeting, Technical Digest, (1993),11-14.Applicant
Rao, K..V., et al.,“Trench Capacitor Design Issues on VLSI DRAM Cells”, 1986 IEEE International Electron Devices Meeting, Technical Digest, Los Angeles, CA,(Dec. 7-10, 1986),140-143.Applicant
Richardson, W..F.,et al.,“A Trench Transistor Cross-Point DRAM Cell”, IEEE International Electron Devices Meeting, Washington, D.C.,(Dec. 1-4, 1985),714-717.Applicant
Sagara, K..,et al.,“A 0.72 micro-meter2 Recessed STC (RSTC) Technology for 256Mbit DRAMs using Quarter-Micron Phase-Shift Lithography”, 1992 Symposium on VLSI Technology, Digest of Technical Papers, Seattle, WA,(Jun. 2-4, 1992), 10-11.Applicant
Saito, M..,et al.,“Techniques for Controlling Effective Vth in Multi-Gbit DRAM Sense Amplifier”, 1996 Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI,(Jun. 13-15, 1996),106-107.Applicant
Shah, A..H.,et al.,“A 4-Mbit DRAM with Trench-Transistor Cell”,IEEE Journal of Solid-State Circuits, SC-21, (Oct. 1986),618-625.Applicant
Shah, A..H., et al., “A 4Mb DRAM with Cross-Point Trench Transistor Cell”, 1986 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, (Feb. 21, 1986),268-269.Applicant
Sherony, M..J.,et al.,“Reduction of Threshold Voltage Sensitivity in SOI MOSFET's”, IEEE Electron Device Letters, 16, (Mar. 1995),100-102.Applicant
Shimomura, K..,et al.,“A 1V 46ns 16Mb SOI-DRAM with Body Control Technique”, 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, (Feb. 6, 1997),68-69.Applicant
Stellwag, T..B.,et al.,“A Vertically-Integrated GaAs Bipolar DRAM Cell”, IEEE Transactions on Electron Devices, 38, (Dec. 1991),2704-2705.Applicant
Su, D..,et al.,“Experimental Results and Modeling Techniques for Substrate Noise in Mixed Signal Integrated Circuits”, IEEE Journal of Solid State Circuits, 28(4), (1993),pp. 420-430.Applicant
Sumak, K..,et al.,“An SOI-DRAM with Wide Operating Voltage Range by CMOS/SIMOX Technology”, IEEE Journal of Solid-State Circuits, 29(11), (November 1994),pp. 1323-1329.Applicant
Sunouchi, K..,et al.,“A Surrounding Gate Transistor (SGT) Cell for 64/256Mbit DRAMs”, 1989 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C.,(Dec. 3-6, 1989),23-26.Applicant
Sunouchi, K..,et al.,“Process Integration for 64M DRAM Using an Asymmetrical Stacked Trench Capacitor (AST) Cell”, 1990 IEEE International Electron Devices Meeting, San Francisco, CA,(Dec. 9-12, 1990),647-650.Applicant
Takai, M..,et al.,“Direct Measurement and Improvement of Local Soft Error Susceptibility in Dynamic Random Access Memories”, Nuclear Instruments & Methods in Physics Research, B-99, (Nov. 7-10, 1994),562-565.Applicant
Takato, H..,et al.,“High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs”, IEEE International Electron Devices Meeting, Technical Digest, (1988),222-225.Applicant
Takato, H..,et al.,“Impact of Surrounding Gate Transistor (SGT) for Ultra-High Density LSI's”, IEEE Transactions on Electron Devices, 38, (Mar. 1991),573-578.Applicant
Tanabe, N..,et al.,“A Ferroelectric Capacitor Over Bit-Line (F-COB) Cell for High Density Nonvolatile Ferroelectric Memories”, 1995 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan,(Jun. 6-8, 1995),123-124.Applicant
Temmler, D..,“Multilayer Vertical Stacked Capacitors (MVSTC) for 64Mbit and 256Mbit DRAMs”, 1991 Symposium on VLSI Technology, Digest of Technical Papers, Oiso,(May 28-30, 1991),13-14.Applicant
Teruchi, M..,et al.,“A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMs”, 1993 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan,(1993),21-22.Applicant
Tsui, P..G.,et al.,“A Versatile Half-Micron Complementary BiCMOS Technology for Microprocessor-Based Smart Power Applications”, IEEE Transactions on Electron Devices, 42, (Mar. 1995),564-570.Applicant
Verdonckt-Vanderbroek, S..,et al.,“High-Gain Lateral Bipolar Action in a MOSFET Structure”, IEEE Transactions on Electron Devices 38, (Nov. 1991),2487-2496.Applicant
Wang, N.., Digital MOS Integrated Circuits, Prentice Hall, Inc., Englewood Cliffs, NJ,(1989),p. 328-333.Applicant
Wang, P..W.,et al.,“Excellent Emission Characteristics of Tunneling Oxides Formed Using Ultrathin Silicon Films for Flash Memory Devices”, Japanese Journal of Applied Physics, 35, (June 1996),3369-3373.Applicant
Watanabe, H..,et al.,“A New Cylindrical Capacitor Using Hemispherical Grained Si(HSG—S) for 256Mb DRAMs”, IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA,(Dec. 13-16, 1992),259-262.Applicant
Watanabe, S..,et al.,“A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's”, IEEE Journal of Solid-State Circuits, 30, (Sep. 1995),960-971.Applicant
Watanabe, H..,“A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs”, 1993 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan,(1993),17-18.Applicant
Watanabe, H..,et al.,“An Advanced Fabrication Technology of Hemispherical Grained (HSG) Poly-Si for High Capacitance Storage Electrodes”, Extended Abstracts of the 1991 International Conference on Solid State Devices and Materials, Yokohama, Japan,(1991),478-480.Applicant
Watanabe, H..,et al.,“A Device Application and Structure Observation for Hemispherical-Grained Si”, J. Appl. Phys., 71, (Apr. 1992),3538-3543.Applicant
Watanabe, H..,et al.,“Hemispherical Grained Silicon (HSG-Si) Formation on In-Situ Phosphorous Doped Amorphous-Si Using the Seeding Mehtod”, Extended Abstracts on the 1992 International Conference on Solid State Devices and Materials, Tsukuba, Japan,(1992),422-424.Applicant
Yamada, T.,et al.,“A New Cell Structure with a Spread Source/Drain (SSD) MOSFET and a Cylindrical Capacitor for 64-Mb DRAM's”, IEEE Transactions on Electron Devices, 38, (Nov. 1991),2481-2486.Applicant
Yamada, T..,et al., “Spread Source/Drain (SSD) MOSFET Using Selective Silicon Growth for 64Mbit DRAMS”, 1989 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C.,(Dec. 3-6, 1989),35-38.Applicant
Yoshikawa, K..,“Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Mulitlevel Flash Cell Design”, 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI,(Jun. 11-13, 1996),240-241.Applicant
Rhyne, In: Fundamentals of Digital Systems Design, Prenctice Hall, New Jersey,(1973),p. 70-71.Applicant
Sun, J., “CMOS Technology for 1.8V and Beyond”, Int'l Symp. on VLSI Technology, Systems and Applications: Digest of Technical Papers, (1997),293-297.Applicant
Takao, Y., et al., “A 4-um(2) Full-CMOS SRAM Cell Technology for 0.2-um High Performance Logic LSIs”, 1997 Symp. on VLSI Technology: Digest of Technical Papers, Kyoto, Japan,(1997),11-12.Applicant
Wolf, Stanley, “Isolation Technologies for Integrated Circuits”, Silicon Processing for the NLSI Era vol. 2 Process Integration, (1990),66-78.Applicant

Abstract